- X6502_Rebase();
- }
- else switch(A)
- {
- case 0x9000:switch(V&0x3)
- {
- case 0:MIRROR_SET(0);break;
- case 1:MIRROR_SET(1);break;
- case 2:onemir(0);break;
- case 3:onemir(1);break;
- }
- break;
- case 0x9001:if((K4sel&2)!=(V&2))
- {
- uint8 swa;
- swa=PRGBankList[0];
- ROM_BANK8(0x8000,PRGBankList[2]);
- ROM_BANK8(0xc000,swa);
- X6502_Rebase();
- }
- K4sel=V;
- break;
- case 0xf000:IRQLatch&=0xF0;IRQLatch|=V&0xF;break;
- case 0xf002:IRQLatch&=0x0F;IRQLatch|=V<<4;break;
- case 0xf001:IRQCount=IRQLatch;IRQa=V&2;K4IRQ=V&1;break;
- case 0xf003:IRQa=K4IRQ;break;
+ }
+ else switch(A)
+ {
+ case 0x9000:switch(V&0x3)
+ {
+ case 0:MIRROR_SET(0);break;
+ case 1:MIRROR_SET(1);break;
+ case 2:onemir(0);break;
+ case 3:onemir(1);break;
+ }
+ break;
+ case 0x9001:if((K4sel&2)!=(V&2))
+ {
+ uint8 swa;
+ swa=PRGBankList[0];
+ ROM_BANK8(0x8000,PRGBankList[2]);
+ ROM_BANK8(0xc000,swa);
+ }
+ K4sel=V;
+ break;
+ case 0xf000:IRQLatch&=0xF0;IRQLatch|=V&0xF;break;
+ case 0xf002:IRQLatch&=0x0F;IRQLatch|=V<<4;break;
+ case 0xf001:IRQCount=IRQLatch;IRQa=V&2;K4IRQ=V&1;acount=0;X6502_IRQEnd(FCEU_IQEXT);break;
+ case 0xf003:IRQa=K4IRQ;X6502_IRQEnd(FCEU_IQEXT);break;