+// from 0.98.15
+#define FCEU_IQEXT2 0x02
+
+#if defined(DEBUG_ASM_6502)
+#define TriggerIRQ TriggerIRQ_d
+#define TriggerNMI TriggerNMI_d
+#define X6502_Run X6502_Run_d
+#define X6502_Reset X6502_Reset_d
+#define X6502_Power X6502_Power_d
+#define X6502_AddCycles X6502_AddCycles_d
+#define X6502_IRQBegin X6502_IRQBegin_d
+#define X6502_IRQEnd X6502_IRQEnd_d
+#define X6502_Rebase X6502_Rebase_d
+#define X6502_GetCycleCount() g_cnt
+#define X6502_C
+#define X6502_A
+#define X6502_D
+
+#elif defined(ASM_6502)
+#define TriggerIRQ TriggerIRQ_a
+#define TriggerNMI TriggerNMI_a
+#define X6502_Reset X6502_Reset_a
+#define X6502_Power X6502_Power_a
+#define X6502_AddCycles X6502_AddCycles_a
+//#define X6502_IRQBegin X6502_IRQBegin_a
+//#define X6502_IRQEnd X6502_IRQEnd_a
+#define X6502_IRQBegin(w) nes_registers[4]|=w<<8
+#define X6502_IRQEnd(w) nes_registers[4]&=~(w<<8)
+#define X6502_Rebase X6502_Rebase_a
+#define X6502_GetCycleCount() ((int32)nes_registers[7]>>16)
+#define X6502_A
+
+#define X6502_Run(c) \
+{ \
+ int32 cycles = (c) << 4; /* *16 */ \
+ if (PAL) cycles -= (c); /* *15 */ \
+ nes_registers[7]+=cycles<<16; \
+ cycles=(int32)nes_registers[7]>>16; \
+ if (cycles > 0) { \
+ X6502_Run_a(); \
+ cycles -= (int32)nes_registers[7]>>16; \
+ asmcpu_update(cycles); \
+ } \
+}
+
+#else
+#define TriggerIRQ TriggerIRQ_c
+#define TriggerNMI TriggerNMI_c
+#define X6502_Reset X6502_Reset_c
+#define X6502_Power X6502_Power_c
+#define X6502_AddCycles X6502_AddCycles_c
+#define X6502_IRQBegin X6502_IRQBegin_c
+#define X6502_IRQEnd X6502_IRQEnd_c
+#define X6502_Rebase(...)
+#define X6502_GetCycleCount() X.count
+#define X6502_C