--- /dev/null
+\r
+#include "app.h"\r
+\r
+// ---------------------------------------------------------------------------\r
+// Gets the offset of a register for an ea, and puts it in 'r'\r
+// Shifted left by 'shift'\r
+// Doesn't trash anything\r
+static int EaCalcReg(int r,int ea,int mask,int forceor,int shift)\r
+{\r
+ int i=0,low=0,needor=0;\r
+ int lsl=0;\r
+\r
+ for (i=mask|0x8000; (i&1)==0; i>>=1) low++; // Find out how high up the EA mask is\r
+ mask&=0xf<<low; // This is the max we can do\r
+\r
+ if (ea>=8) needor=1; // Need to OR to access A0-7\r
+\r
+ if ((mask>>low)&8) if (ea&8) needor=0; // Ah - no we don't actually need to or, since the bit is high in r8\r
+\r
+ if (forceor) needor=1; // Special case for 0x30-0x38 EAs ;)\r
+\r
+ ot(" and r%d,r8,#0x%.4x\n",r,mask);\r
+\r
+ // Find out amount to shift left:\r
+ lsl=shift-low;\r
+\r
+ if (lsl)\r
+ {\r
+ ot(" mov r%d,r%d,",r,r);\r
+ if (lsl>0) ot("lsl #%d\n", lsl);\r
+ else ot("lsr #%d\n",-lsl);\r
+ }\r
+\r
+ if (needor) ot(" orr r%d,r%d,#0x%x ;@ A0-7\n",r,r,8<<shift);\r
+ return 0;\r
+}\r
+\r
+// EaCalc - ARM Register 'a' = Effective Address\r
+// Trashes r0,r2 and r3\r
+int EaCalc(int a,int mask,int ea,int size)\r
+{\r
+ char text[32]="";\r
+ int func=0;\r
+\r
+ DisaPc=2; DisaGetEa(text,ea,size); // Get text version of the effective address\r
+ func=0x68+(size<<2); // Get correct read handler\r
+\r
+ if (ea<0x10)\r
+ {\r
+ int lsl=2;\r
+ if (size>=2) lsl=0; // Saves one opcode\r
+\r
+ ot(";@ EaCalc : Get register index into r%d:\n",a);\r
+\r
+ EaCalcReg(a,ea,mask,0,lsl);\r
+ return 0;\r
+ }\r
+ \r
+ ot(";@ EaCalc : Get '%s' into r%d:\n",text,a);\r
+ // (An), (An)+, -(An):\r
+ if (ea<0x28)\r
+ {\r
+ int step=1<<size;\r
+\r
+ if ((ea&7)==7 && step<2) step=2; // move.b (a7)+ or -(a7) steps by 2 not 1\r
+\r
+ EaCalcReg(2,ea,mask,0,2);\r
+ ot(" ldr r%d,[r7,r2]\n",a);\r
+\r
+ if ((ea&0x38)==0x18)\r
+ {\r
+ ot(" add r3,r%d,#%d ;@ Post-increment An\n",a,step);\r
+ ot(" str r3,[r7,r2]\n");\r
+ }\r
+\r
+ if ((ea&0x38)==0x20)\r
+ {\r
+ ot(" sub r%d,r%d,#%d ;@ Pre-decrement An\n",a,a,step);\r
+ ot(" str r%d,[r7,r2]\n",a);\r
+ }\r
+\r
+ if ((ea&0x38)==0x20) Cycles+=size<2 ? 6:10; // -(An) Extra cycles\r
+ else Cycles+=size<2 ? 4:8; // (An),(An)+ Extra cycles\r
+ return 0;\r
+ }\r
+\r
+ if (ea<0x30) // ($nn,An)\r
+ {\r
+ EaCalcReg(2,8,mask,0,2);\r
+ ot(" ldr r2,[r7,r2]\n");\r
+ ot(" ldrsh r0,[r4],#2 ;@ Fetch offset\n");\r
+ ot(" add r%d,r0,r2 ;@ Add on offset\n",a);\r
+ Cycles+=size<2 ? 8:12; // Extra cycles\r
+ return 0;\r
+ }\r
+\r
+ if (ea<0x38) // ($nn,An,Rn)\r
+ {\r
+ ot(";@ Get extension word into r3:\n");\r
+ ot(" ldrh r3,[r4],#2 ;@ ($Disp,PC,Rn)\n");\r
+ ot(" mov r2,r3,lsr #10\n");\r
+ ot(" tst r3,#0x0800 ;@ Is Rn Word or Long\n");\r
+ ot(" and r2,r2,#0x3c ;@ r2=Index of Rn\n");\r
+ ot(" mov r0,r3,asl #24 ;@ r0=Get 8-bit signed Disp\n");\r
+ ot(" ldreqsh r2,[r7,r2] ;@ r2=Rn.w\n");\r
+ ot(" ldrne r2,[r7,r2] ;@ r2=Rn.l\n");\r
+ ot(" add r3,r2,r0,asr #24 ;@ r3=Disp+Rn\n");\r
+\r
+ EaCalcReg(2,8,mask,1,2);\r
+ ot(" ldr r2,[r7,r2]\n");\r
+ ot(" add r%d,r2,r3 ;@ r%d=Disp+An+Rn\n",a,a);\r
+ Cycles+=size<2 ? 10:14; // Extra cycles\r
+ return 0;\r
+ }\r
+\r
+ if (ea==0x38)\r
+ {\r
+ ot(" ldrsh r%d,[r4],#2 ;@ Fetch Absolute Short address\n",a);\r
+ Cycles+=size<2 ? 8:12; // Extra cycles\r
+ return 0;\r
+ }\r
+\r
+ if (ea==0x39)\r
+ {\r
+ ot(" ldrh r2,[r4],#2 ;@ Fetch Absolute Long address\n");\r
+ ot(" ldrh r0,[r4],#2\n");\r
+ ot(" orr r%d,r0,r2,lsl #16\n",a);\r
+ Cycles+=size<2 ? 12:16; // Extra cycles\r
+ return 0;\r
+ }\r
+\r
+ if (ea==0x3a)\r
+ {\r
+ ot(" ldr r0,[r7,#0x60] ;@ Get Memory base\n");\r
+ ot(" sub r0,r4,r0 ;@ Real PC\n");\r
+ ot(" ldrsh r2,[r4],#2 ;@ Fetch extension\n");\r
+ ot(" add r%d,r0,r2 ;@ ($nn,PC)\n",a);\r
+ Cycles+=size<2 ? 8:12; // Extra cycles\r
+ return 0;\r
+ }\r
+\r
+ if (ea==0x3b) // ($nn,pc,Rn)\r
+ {\r
+ ot(";@ Get extension word into r3:\n");\r
+ ot(" ldrh r3,[r4]\n");\r
+ ot(" mov r2,r3,lsr #10\n");\r
+ ot(" tst r3,#0x0800 ;@ Is Rn Word or Long\n");\r
+ ot(" and r2,r2,#0x3c ;@ r2=Index of Rn\n");\r
+ ot(" mov r0,r3,asl #24 ;@ r0=Get 8-bit signed Disp\n");\r
+ ot(" ldreqsh r2,[r7,r2] ;@ r2=Rn.w\n");\r
+ ot(" ldrne r2,[r7,r2] ;@ r2=Rn.l\n");\r
+ ot(" add r2,r2,r0,asr #24 ;@ r2=Disp+Rn\n");\r
+ ot(" ldr r0,[r7,#0x60] ;@ Get Memory base\n");\r
+ ot(" add r2,r2,r4 ;@ r2=Disp+Rn + Base+PC\n");\r
+ ot(" add r4,r4,#2 ;@ Increase PC\n");\r
+ ot(" sub r%d,r2,r0 ;@ r%d=Disp+PC+Rn\n",a,a);\r
+ Cycles+=size<2 ? 10:14; // Extra cycles\r
+ return 0;\r
+ }\r
+\r
+ if (ea==0x3c)\r
+ {\r
+ if (size<2)\r
+ {\r
+ ot(" ldr%s r%d,[r4],#2 ;@ Fetch immediate value\n",Sarm[size&3],a);\r
+ Cycles+=4; // Extra cycles\r
+ return 0;\r
+ }\r
+\r
+ ot(" ldrh r2,[r4],#2 ;@ Fetch immediate value\n");\r
+ ot(" ldrh r0,[r4],#2\n");\r
+ ot(" orr r%d,r0,r2,lsl #16\n",a);\r
+ Cycles+=8; // Extra cycles\r
+ return 0;\r
+ }\r
+\r
+ return 1;\r
+}\r
+\r
+// ---------------------------------------------------------------------------\r
+// Read effective address in (ARM Register 'a') to ARM register 'v'\r
+// 'a' and 'v' can be anything but 0 is generally best (for both)\r
+// If (ea<0x10) nothing is trashed, else r0-r3 is trashed\r
+// If 'top' is 1, the ARM register v shifted to the top, e.g. 0xc000 -> 0xc0000000\r
+// Otherwise the ARM register v is sign extended, e.g. 0xc000 -> 0xffffc000\r
+\r
+int EaRead(int a,int v,int ea,int size,int top)\r
+{\r
+ char text[32]="";\r
+ int shift=0;\r
+ \r
+ shift=32-(8<<size);\r
+\r
+ DisaPc=2; DisaGetEa(text,ea,size); // Get text version of the effective address\r
+\r
+ if (ea<0x10)\r
+ {\r
+ int lsl=2;\r
+ if (size>=2) lsl=0; // Having a lsl #2 here saves one opcode\r
+\r
+ ot(";@ EaRead : Read register[r%d] into r%d:\n",a,v);\r
+\r
+ if (lsl==0) ot(" ldr r%d,[r7,r%d,lsl #2]\n",v,a);\r
+ else ot(" ldr%s r%d,[r7,r%d]\n",Sarm[size&3],v,a);\r
+\r
+ if (top && shift) ot(" mov r%d,r%d,asl #%d\n",v,v,shift);\r
+\r
+ ot("\n"); return 0;\r
+ }\r
+\r
+ ot(";@ EaRead : Read '%s' (address in r%d) into r%d:\n",text,a,v);\r
+\r
+ if (ea==0x3c)\r
+ {\r
+ int asl=0;\r
+\r
+ if (top) asl=shift;\r
+\r
+ if (v!=a || asl) ot(" mov r%d,r%d,asl #%d\n",v,a,asl);\r
+ ot("\n"); return 0;\r
+ }\r
+\r
+ if (a!=0) ot(" mov r0,r%d\n",a);\r
+\r
+ if (ea>=0x3a && ea<=0x3b) MemHandler(2,size); // Fetch\r
+ else MemHandler(0,size); // Read\r
+\r
+ if (v!=0 || shift) ot(" mov r%d,r0,asl #%d\n",v,shift);\r
+ if (top==0 && shift) ot(" mov r%d,r%d,asr #%d\n",v,v,shift);\r
+\r
+ ot("\n"); return 0;\r
+}\r
+\r
+// Return 1 if we can read this ea\r
+int EaCanRead(int ea,int size)\r
+{\r
+ if (size<0)\r
+ {\r
+ // LEA:\r
+ // These don't make sense?:\r
+ if (ea<0x10) return 0; // Register\r
+ if (ea==0x3c) return 0; // Immediate\r
+ if (ea>=0x18 && ea<0x28) return 0; // Pre/Post inc/dec An\r
+ }\r
+\r
+ if (ea<=0x3c) return 1;\r
+ return 0;\r
+}\r
+\r
+// ---------------------------------------------------------------------------\r
+// Write effective address (ARM Register 'a') with ARM register 'v'\r
+// Trashes r0-r3, 'a' can be 0 or 2+, 'v' can be 1 or higher\r
+// If a==0 and v==1 it's faster though.\r
+int EaWrite(int a,int v,int ea,int size,int top)\r
+{\r
+ char text[32]="";\r
+ int shift=0;\r
+\r
+ if (top) shift=32-(8<<size);\r
+\r
+ DisaPc=2; DisaGetEa(text,ea,size); // Get text version of the effective address\r
+\r
+ if (ea<0x10)\r
+ {\r
+ int lsl=2;\r
+ if (size>=2) lsl=0; // Having a lsl #2 here saves one opcode\r
+\r
+ ot(";@ EaWrite: r%d into register[r%d]:\n",v,a);\r
+ if (shift) ot(" mov r%d,r%d,asr #%d\n",v,v,shift);\r
+\r
+ if (lsl==0) ot(" str r%d,[r7,r%d,lsl #2]\n",v,a);\r
+ else ot(" str%s r%d,[r7,r%d]\n",Narm[size&3],v,a);\r
+\r
+ ot("\n"); return 0;\r
+ }\r
+\r
+ ot(";@ EaWrite: Write r%d into '%s' (address in r%d):\n",v,text,a);\r
+\r
+ if (ea==0x3c) { ot("Error! Write EA=0x%x\n\n",ea); return 1; }\r
+\r
+ if (a!=0 && v!=0) ot(" mov r0,r%d\n",a);\r
+ if (v!=1 || shift) ot(" mov r1,r%d,asr #%d\n",v,shift);\r
+ if (a!=0 && v==0) ot(" mov r0,r%d\n",a);\r
+\r
+ MemHandler(1,size); // Call write handler\r
+\r
+ ot("\n"); return 0;\r
+}\r
+\r
+// Return 1 if we can write this ea\r
+int EaCanWrite(int ea)\r
+{\r
+ if (ea<=0x3b) return 1;\r
+ return 0;\r
+}\r
+// ---------------------------------------------------------------------------\r
notaz.gp2x.de / cyclone68000.git / blobdiff