static void S74LS374NSynco(void)
{
setprg32(0x8000,latch[0]);
+ X6502_Rebase();
setchr8(latch[1]);
setmirror(latch[2]&1);
// setchr8(6);
A&=0x4101;
if(A==0x4100)
cmd=V&7;
- else
+ else
{
switch(cmd)
{
int x;
setprg32(0x8000,latch[5]&7);
+ X6502_Rebase();
if(!UNIFchrrama) // No CHR RAM? Then BS'ing is ok.
{
{
A&=0x4101;
if(A==0x4100) cmd=V;
- else
+ else
{
latch[cmd&7]=V;
S8259Synco();
static void SA0161MSynco()
{
- setprg32(0x8000,(latch[0]>>3)&1);
+ setprg32(0x8000,(latch[0]>>3)&1);
+ X6502_Rebase();
setchr8(latch[0]&7);
}
static void SA72007Synco()
{
setprg32(0x8000,0);
+ X6502_Rebase();
setchr8(latch[0]>>7);
}
static void SA72008Synco()
{
setprg32(0x8000,(latch[0]>>2)&1);
+ X6502_Rebase();
setchr8(latch[0]&3);
}
static void SA0036Synco()
{
setprg32(0x8000,0);
+ X6502_Rebase();
setchr8(latch[0]>>7);
}
static void SA0037Synco()
{
setprg32(0x8000,(latch[0]>>3)&1);
+ X6502_Rebase();
setchr8(latch[0]&7);
}
static void TCU01Synco()
{
setprg32(0x8000,(latch[0]>>2)&1);
+ X6502_Rebase();
setchr8((latch[0]>>3)&0xF);
}