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-.macro ZP_READ_ADDR
+.macro ZP_READ_ADDR update_db=0
ZP_READ
ldrb REG_ADDR, [REG_ADDR, #1]
orr REG_ADDR, r0, REG_ADDR, lsl #8
+.if \update_db
+ strb r0, [REG_OP_TABLE, #(OTOFFS_X + 0x10)] @ X.DB
+.endif
.endm
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@@@ ($nn), Y
.macro INDY_ADDR
ZERO_ADDR
- ZP_READ_ADDR
+ ZP_READ_ADDR 1 @ SMB3 relies on open bus here
add REG_ADDR, REG_ADDR, REG_Y
bic REG_ADDR, REG_ADDR, #0x10000
and r0,REG_ADDR,#0xff
opAB: @ LXA/ATX/OAL #$nn
IMM_VALUE
- orr REG_A, REG_A, #0xee000000
+ orr REG_A, REG_A, #0xff000000
OP_AND
mov REG_X, REG_A, lsr #24
CYCLE_NEXT 2
ldr r0, [REG_OP_TABLE, #OTOFFS_PC_BASE]
sub r0, REG_PC, r0
PUSH_WORD
- orr REG_P_REST, REG_P_REST, #P_REST_B_FLAG
SAVE_P
+ orr r0, r0, #P_B_FLAG
PUSH_BYTE
orr REG_P_REST, REG_P_REST, #P_REST_I_FLAG
mov REG_ADDR, #0x10000
sub REG_PC, REG_PC, #1
sub r0, REG_PC, r0
PUSH_WORD
- bic REG_P_REST, REG_P_REST, #P_REST_B_FLAG
SAVE_P
+ bic r0, r0, #P_B_FLAG
PUSH_BYTE
tst REG_P_REST, #FCEU_IQNMI<<8
- orreq REG_P_REST, REG_P_REST, #P_REST_I_FLAG
- bic REG_P_REST, REG_P_REST, #((FCEU_IQNMI|FCEU_IQTEMP)<<8)
+ orr REG_P_REST, REG_P_REST, #P_REST_I_FLAG
+ biceq REG_P_REST, REG_P_REST, #FCEU_IQTEMP<<8
+ bicne REG_P_REST, REG_P_REST, #FCEU_IQNMI<<8
mov REG_ADDR, #0x10000
subeq REG_ADDR, REG_ADDR, #IRQ_VECTOR
subne REG_ADDR, REG_ADDR, #NMI_VECTOR
subs REG_CYCLE, REG_CYCLE, #7*48<<16
ble cpu_exec_end
ldrb r0, [REG_PC], #1
- tst REG_P_REST, #0xff<<8
- ldreq pc, [REG_OP_TABLE, r0, lsl #2]
-
- tst REG_P_REST, #P_REST_I_FLAG
- ldrne pc, [REG_OP_TABLE, r0, lsl #2]
- b do_int
+ ldr pc, [REG_OP_TABLE, r0, lsl #2]
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