drc: rm an impossible condition
authornotaz <notasas@gmail.com>
Wed, 15 Apr 2026 00:02:14 +0000 (03:02 +0300)
committernotaz <notasas@gmail.com>
Wed, 15 Apr 2026 00:07:19 +0000 (03:07 +0300)
commit4e484ca077fb6e95fd539ed31889338f31d3c82d
tree7784800f7c7bdf9aa1dfdf4bab9eebbbe62ccb13
parent591b7a04cc64fcf1ef9ef32228b804777b72bb67
drc: rm an impossible condition

First instruction can't be a delay slot since long ago
libpcsxcore/new_dynarec/new_dynarec.c