The hardware registers should be represented in little-endian format.
Therefore, on big-endian systems the values need to be byte-swapped.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
#define PSXGPU_TIMING_BITS (PSXGPU_LCF | PSXGPU_nBUSY)
#define gpuSyncPluginSR() { \
- HW_GPU_STATUS &= PSXGPU_TIMING_BITS; \
- HW_GPU_STATUS |= GPU_readStatus() & ~PSXGPU_TIMING_BITS; \
+ HW_GPU_STATUS &= SWAP32(PSXGPU_TIMING_BITS); \
+ HW_GPU_STATUS |= SWAP32(GPU_readStatus() & ~PSXGPU_TIMING_BITS); \
}
GPU_freeze(0, gpufP);
free(gpufP);
if (HW_GPU_STATUS == 0)
- HW_GPU_STATUS = GPU_readStatus();
+ HW_GPU_STATUS = SWAP32(GPU_readStatus());
// spu
SaveFuncs.read(f, &Size, 4);
// VSync irq.
if( hSyncCount == VBlankStart )
{
- HW_GPU_STATUS &= ~PSXGPU_LCF;
+ HW_GPU_STATUS &= SWAP32(~PSXGPU_LCF);
GPU_vBlank( 1, 0 );
setIrq( 0x01 );
frame_counter++;
gpuSyncPluginSR();
- if( (HW_GPU_STATUS & PSXGPU_ILACE_BITS) == PSXGPU_ILACE_BITS )
- HW_GPU_STATUS |= frame_counter << 31;
- GPU_vBlank( 0, HW_GPU_STATUS >> 31 );
+ if ((HW_GPU_STATUS & SWAP32(PSXGPU_ILACE_BITS)) == SWAP32(PSXGPU_ILACE_BITS))
+ HW_GPU_STATUS |= SWAP32(frame_counter << 31);
+ GPU_vBlank(0, SWAP32(HW_GPU_STATUS) >> 31);
}
// Schedule next call, in hsyncs
size = GPU_dmaChain((u32 *)psxM, madr & 0x1fffff);
if ((int)size <= 0)
size = gpuDmaChainSize(madr);
- HW_GPU_STATUS &= ~PSXGPU_nBUSY;
+ HW_GPU_STATUS &= SWAP32(~PSXGPU_nBUSY);
// we don't emulate progress, just busy flag and end irq,
// so pretend we're already at the last block
HW_DMA2_CHCR &= SWAP32(~0x01000000);
DMA_INTERRUPT(2);
}
- HW_GPU_STATUS |= PSXGPU_nBUSY; // GPU no longer busy
+ HW_GPU_STATUS |= SWAP32(PSXGPU_nBUSY); // GPU no longer busy
}
void psxDma6(u32 madr, u32 bcr, u32 chcr) {
*mem-- = SWAP32((madr - 4) & 0xffffff);
madr -= 4;
}
- mem++; *mem = 0xffffff;
+ *++mem = SWAP32(0xffffff);
//GPUOTCDMA_INT(size);
// halted
mdecInit(); // initialize mdec decoder
cdrReset();
psxRcntInit();
- HW_GPU_STATUS = 0x14802000;
+ HW_GPU_STATUS = SWAP32(0x14802000);
}
u8 psxHwRead8(u32 add) {
return hard;
case 0x1f801814:
gpuSyncPluginSR();
- hard = HW_GPU_STATUS;
- if (hSyncCount < 240 && (HW_GPU_STATUS & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
+ hard = SWAP32(HW_GPU_STATUS);
+ if (hSyncCount < 240 && (hard & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
hard |= PSXGPU_LCF & (psxRegs.cycle << 20);
#ifdef PSXHW_LOG
PSXHW_LOG("GPU STATUS 32bit read %x\n", hard);
PSXHW_LOG("IMASK 16bit write %x\n", value);
#endif
psxHu16ref(0x1074) = SWAPu16(value);
- if (psxHu16ref(0x1070) & value)
+ if (psxHu16ref(0x1070) & SWAPu16(value))
new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
return;
PSXHW_LOG("IMASK 32bit write %x\n", value);
#endif
psxHu32ref(0x1074) = SWAPu32(value);
- if (psxHu32ref(0x1070) & value)
+ if (psxHu32ref(0x1070) & SWAPu32(value))
new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
return;