\r
// Cyclone 68000 Emulator - Header File\r
\r
-// Most code (c) Copyright 2004 Dave, All rights reserved.\r
-// Some coding/bugfixing was done by notaz\r
+// (c) Copyright 2004 Dave, All rights reserved.\r
+// (c) 2005-2007 notaz\r
// Cyclone 68000 is free for non-commercial use.\r
\r
// For commercial use, separate licencing terms must be obtained.\r
\r
+\r
+#ifndef __CYCLONE_H__\r
+#define __CYCLONE_H__\r
+\r
#ifdef __cplusplus\r
extern "C" {\r
#endif\r
{\r
unsigned int d[8]; // [r7,#0x00]\r
unsigned int a[8]; // [r7,#0x20]\r
- unsigned int pc; // [r7,#0x40] Memory Base+PC\r
+ unsigned int pc; // [r7,#0x40] Memory Base (.membase) + 68k PC\r
unsigned char srh; // [r7,#0x44] Status Register high (T_S__III)\r
unsigned char unused; // [r7,#0x45] Unused\r
unsigned char flags; // [r7,#0x46] Flags (ARM order: ____NZCV) [68k order is XNZVC]\r
unsigned char irq; // [r7,#0x47] IRQ level\r
unsigned int osp; // [r7,#0x48] Other Stack Pointer (USP/SSP)\r
unsigned int xc; // [r7,#0x4c] Extend flag (bit29: ??X? _)\r
- unsigned int prev_pc; // [r7,#0x50] set to start address of currently executed opcode + 2 (if enabled in config.h)\r
- unsigned int unused1; // [r7,#0x54] Unused\r
- int stopped; // [r7,#0x58] 1 == processor is in stopped state\r
- int cycles; // [r7,#0x5c]\r
+ unsigned int prev_pc; // [r7,#0x50] Set to start address of currently executed opcode + 2 (if enabled in config.h)\r
+ unsigned int reserved;// [r7,#0x54] Reserved for possible future use\r
+ int state_flags; // [r7,#0x58] bit: 0: stopped state, 1: trace state, 2: activity bit, 3: addr error, 4: fatal halt\r
+ int cycles; // [r7,#0x5c] Number of cycles to execute - 1. Updates to cycles left after CycloneRun()\r
int membase; // [r7,#0x60] Memory Base (ARM address minus 68000 address)\r
- unsigned int (*checkpc)(unsigned int pc); // [r7,#0x64] - Called to recalc Memory Base+pc\r
- unsigned char (*read8 )(unsigned int a); // [r7,#0x68]\r
- unsigned short (*read16 )(unsigned int a); // [r7,#0x6c]\r
- unsigned int (*read32 )(unsigned int a); // [r7,#0x70]\r
+ unsigned int (*checkpc)(unsigned int pc); // [r7,#0x64] called to recalc Memory Base+pc\r
+ unsigned int (*read8 )(unsigned int a); // [r7,#0x68]\r
+ unsigned int (*read16 )(unsigned int a); // [r7,#0x6c]\r
+ unsigned int (*read32 )(unsigned int a); // [r7,#0x70]\r
void (*write8 )(unsigned int a,unsigned char d); // [r7,#0x74]\r
void (*write16)(unsigned int a,unsigned short d); // [r7,#0x78]\r
void (*write32)(unsigned int a,unsigned int d); // [r7,#0x7c]\r
- unsigned char (*fetch8 )(unsigned int a); // [r7,#0x80]\r
- unsigned short (*fetch16)(unsigned int a); // [r7,#0x84]\r
- unsigned int (*fetch32)(unsigned int a); // [r7,#0x88]\r
- void (*IrqCallback)(int int_level); // [r7,#0x8c] - optional irq callback function, see config.h\r
- void (*ResetCallback)(void); // [r7,#0x90] - if enabled in config.h, calls this whenever RESET opcode is encountered.\r
- int (*UnrecognizedCallback)(void); // [r7,#0x94] - if enabled in config.h, calls this whenever unrecognized opcode is encountered.\r
+ unsigned int (*fetch8 )(unsigned int a); // [r7,#0x80]\r
+ unsigned int (*fetch16)(unsigned int a); // [r7,#0x84]\r
+ unsigned int (*fetch32)(unsigned int a); // [r7,#0x88]\r
+ int (*IrqCallback)(int int_level); // [r7,#0x8c] optional irq callback function, see config.h\r
+ void (*ResetCallback)(void); // [r7,#0x90] if enabled in config.h, calls this whenever RESET opcode is encountered.\r
+ int (*UnrecognizedCallback)(void); // [r7,#0x94] if enabled in config.h, calls this whenever unrecognized opcode is encountered.\r
+ unsigned int internal[6]; // [r7,#0x98] reserved for internal use, do not change.\r
};\r
\r
-// used only if Cyclone was compiled with compressed jumptable, see config.h\r
-void CycloneInit();\r
+// Initialize. Used only if Cyclone was compiled with compressed jumptable, see config.h\r
+void CycloneInit(void);\r
\r
-// run cyclone. Cycles should be specified in context (pcy->cycles)\r
+// Run cyclone. Cycles should be specified in context (pcy->cycles)\r
void CycloneRun(struct Cyclone *pcy);\r
\r
-// utility functions to get and set SR\r
-void CycloneSetSr(struct Cyclone *pcy, unsigned int sr); // auto-swaps a7<->osp if detects supervisor change\r
-unsigned int CycloneGetSr(struct Cyclone *pcy);\r
+// Utility functions to get and set SR\r
+void CycloneSetSr(struct Cyclone *pcy, unsigned int sr);\r
+unsigned int CycloneGetSr(const struct Cyclone *pcy);\r
+\r
+// Generates irq exception if needed (if pcy->irq > mask).\r
+// Returns cycles used for exception if it was generated, 0 otherwise.\r
+int CycloneFlushIrq(struct Cyclone *pcy);\r
+\r
+// Functions for saving and restoring state.\r
+// CycloneUnpack() uses checkpc(), so it must be initialized.\r
+// save_buffer must point to buffer of 128 (0x80) bytes of size.\r
+void CyclonePack(const struct Cyclone *pcy, void *save_buffer);\r
+void CycloneUnpack(struct Cyclone *pcy, const void *save_buffer);\r
\r
// genesis: if 1, switch to normal TAS handlers\r
void CycloneSetRealTAS(int use_real);\r
\r
+\r
+// These values are special return values for IrqCallback.\r
+\r
+// Causes an interrupt autovector (0x18 + interrupt level) to be taken.\r
+// This happens in a real 68K if VPA or AVEC is asserted during an interrupt\r
+// acknowledge cycle instead of DTACK (the most common situation).\r
+#define CYCLONE_INT_ACK_AUTOVECTOR -1\r
+\r
+// Causes the spurious interrupt vector (0x18) to be taken\r
+// This happens in a real 68K if BERR is asserted during the interrupt\r
+// acknowledge cycle (i.e. no devices responded to the acknowledge).\r
+#define CYCLONE_INT_ACK_SPURIOUS -2\r
+\r
+\r
#ifdef __cplusplus\r
} // End of extern "C"\r
#endif\r
+\r
+#endif // __CYCLONE_H__\r
+\r
Replace (atsymbol) with @\r
\r
Additional coding and bugfixes done by notaz, 2005-2007\r
- Homepage: http://mif.vu.lt/~grig2790/Cyclone/ , http://notaz.gp2x.de\r
+ Homepage: http://notaz.gp2x.de\r
e-mail: notasas(atsymbol)gmail.com\r
___________________________________________________________________________\r
\r
\r
-What is it?\r
------------\r
+About\r
+-----\r
\r
Cyclone 68000 is an emulator for the 68000 microprocessor, written in ARM 32-bit assembly.\r
It is aimed at chips such as ARM7 and ARM9 cores, StrongARM and XScale, to interpret 68000\r
-code as fast as possible.\r
+code as fast as possible. It can emulate all 68000 instructions quite accurately, instruction\r
+timing was synchronized with MAME's Musashi. Most 68k features are emulated (trace mode,\r
+address errors), but prefetch is not emulated.\r
\r
-Flags are mapped onto ARM flags whenever possible, which speeds up the processing of opcode.\r
-\r
-\r
-What's New\r
-----------\r
-v0.0087 notaz\r
- - Reduced amount of code in opcode handlers by ~23% by doing the following:\r
- - Removed duplicate opcode handlers\r
- - Optimized code to use less ARM instructions\r
- - Merged some duplicate handler endings\r
- + Cyclone now does better job avoiding pipeline interlocks.\r
- + Replaced incorrect handler of DBT with proper one.\r
- + Changed "MOVEA (An)+ An" behaviour.\r
- + Fixed flag behaviour of ROXR, ASL, LSR and NBCD in certain situations.\r
- Hopefully got them right now.\r
- + Cyclone no longer sets most significant bits while pushing PC to stack.\r
- Amiga Kickstart depends on this.\r
- + Additional functionality added for MAME and other ports (see config.h).\r
-\r
-v0.0086 notaz\r
- + Cyclone now can be customized to better suit your project, see config.h .\r
- + Added an option to compress the jumptable at compile-time. Must call CycloneInit()\r
- at runtime to decompress it if enabled (see config.h).\r
- + Added missing CHK opcode handler (used by SeaQuest DSV).\r
- + Added missing TAS opcode handler (Gargoyles,Bubba N Stix,...). As in real genesis,\r
- memory write-back phase is ignored (but can be enabled in config.h if needed).\r
- + Added missing NBCD and TRAPV opcode handlers.\r
- + Added missing addressing mode for CMP/EOR.\r
- + Added some minor optimizations.\r
- - Removed 216 handlers for 2927 opcodes which were generated for invalid addressing modes.\r
- + Fixed flags for ASL, NEG, NEGX, DIVU, ADDX, SUBX, ROXR.\r
- + Bugs fixed in MOVEP, LINK, ADDQ, DIVS handlers.\r
- * Undocumented flags for CHK, ABCD, SBCD and NBCD are now emulated the same way as in Musashi.\r
- + Added Uninitialized Interrupt emulation.\r
- + Altered timing for about half of opcodes to match Musashi's.\r
-\r
-v0.0082 Reesy\r
- + Change cyclone to clear cycles before returning when halted\r
- + Added Irq call back function. This allows emulators to be notified\r
- when cyclone has taken an interrupt allowing them to set internal flags\r
- which can help fix timing problems.\r
-\r
-v0.0081 notaz\r
- + .asm version was broken and did not compile with armasm. Fixed.\r
- + Finished implementing Stop opcode. Now it really stops the processor.\r
-\r
-v0.0080 notaz\r
- + Added real cmpm opcode, it was using eor handler before this.\r
- Fixes Dune and Sensible Soccer.\r
-\r
-v0.0078 notaz\r
- note: these bugs were actually found Reesy, I reimplemented these by\r
- using his changelog as a guide.\r
- + Fixed a problem with divu which was using long divisor instead of word.\r
- Fixes gear switching in Top Gear 2.\r
- + Fixed btst opcode, The bit to test should shifted a max of 31 or 7\r
- depending on if a register or memory location is being tested.\r
- + Fixed abcd,sbcd. They did bad decimal correction on invalid BCD numbers\r
- Score counters in Streets of Rage level end work now.\r
- + Changed flag handling of abcd,sbcd,addx,subx,asl,lsl,...\r
- Some ops did not have flag handling at all.\r
- Some ops must not change Z flag when result is zero, but they did.\r
- Shift ops must not change X if shift count is zero, but they did.\r
- There are probably still some flag problems left.\r
- + Patially implemented Stop and Reset opcodes - Fixes Thunderforce IV\r
-\r
-v0.0075 notaz\r
- + Added missing displacement addressing mode for movem (Fantastic Dizzy)\r
- + Added OSP <-> A7 swapping code in opcodes, which change privilege mode\r
- + Implemented privilege violation, line emulator and divide by zero exceptions\r
- + Added negx opcode (Shining Force works!)\r
- + Added overflow detection for divs/divu\r
-\r
-v0.0072 notaz\r
- note: I could only get v0.0069 cyclone, so I had to implement these myself using Dave's\r
- changelog as a guide.\r
- + Fixed a problem with divs - remainder should be negative when divident is negative\r
- + Added movep opcode (Sonic 3 works)\r
- + Fixed a problem with DBcc incorrectly decrementing if the condition is true (Shadow of the Beast)\r
-\r
-v0.0069\r
- + Added SBCD and the flags for ABCD/SBCD. Score and time now works in games such as\r
- Rolling Thunder 2, Ghouls 'N Ghosts\r
- + Fixed a problem with addx and subx with 8-bit and 16-bit values.\r
- Ghouls 'N' Ghosts now works!\r
-\r
-v0.0068\r
- + Added ABCD opcode (Streets of Rage works now!)\r
-\r
-v0.0067\r
- + Added dbCC (After Burner)\r
- + Added asr EA (Sonic 1 Boss/Labyrinth Zone)\r
- + Added andi/ori/eori ccr (Altered Beast)\r
- + Added trap (After Burner)\r
- + Added special case for move.b (a7)+ and -(a7), stepping by 2\r
- After Burner is playable! Eternal Champions shows more\r
- + Fixed lsr.b/w zero flag (Ghostbusters)\r
- Rolling Thunder 2 now works!\r
- + Fixed N flag for .b and .w arithmetic. Golden Axe works!\r
-\r
-v0.0066\r
- + Fixed a stupid typo for exg (orr r10,r10, not orr r10,r8), which caused alignment\r
- crashes on Strider\r
-\r
-v0.0065\r
- + Fixed a problem with immediate values - they weren't being shifted up correctly for some\r
- opcodes. Spiderman works, After Burner shows a bit of graphics.\r
- + Fixed a problem with EA:"110nnn" extension word. 32-bit offsets were being decoded as 8-bit\r
- offsets by mistake. Castlevania Bloodlines seems fine now.\r
- + Added exg opcode\r
- + Fixed asr opcode (Sonic jumping left is fixed)\r
- + Fixed a problem with the carry bit in rol.b (Marble Madness)\r
-\r
-v0.0064\r
- + Added rtr\r
- + Fixed addq/subq.l (all An opcodes are 32-bit) (Road Rash)\r
- + Fixed various little timings\r
-\r
-v0.0063\r
- + Added link/unlk opcodes\r
- + Fixed various little timings\r
- + Fixed a problem with dbCC opcode being emitted at set opcodes\r
- + Improved long register access, the EA fetch now does ldr r0,[r7,r0,lsl #2] whenever\r
- possible, saving 1 or 2 cycles on many opcodes, which should give a nice speed up.\r
- + May have fixed N flag on ext opcode?\r
- + Added dasm for link opcode.\r
-\r
-v0.0062\r
- * I was a bit too keen with the Arithmetic opcodes! Some of them should have been abcd,\r
- exg and addx. Removed the incorrect opcodes, pending re-adding them as abcd, exg and addx.\r
- + Changed unknown opcodes to act as nops.\r
- Not very technical, but fun - a few more games show more graphics ;)\r
\r
-v0.0060\r
- + Fixed divu (EA intro)\r
- + Added sf (set false) opcode - SOR2\r
- * Todo: pea/link/unlk opcodes\r
-\r
-v0.0059: Added remainder to divide opcodes.\r
-\r
-\r
-The new stuff\r
--------------\r
-\r
-Before using Cyclone, be sure to customize config.h to better suit your project. All options\r
-are documented inside that file.\r
+How to Compile\r
+--------------\r
\r
-IrqCallback has been changed a bit, unlike in previous version, it should not return anything.\r
-If you need to change IRQ level, you can safely do that in your handler.\r
+Like Starscream and A68K, Cyclone uses a 'Core Creator' program which calculates and outputs\r
+all possible 68000 Opcodes and a jump table into file called Cyclone.s or Cyclone.asm.\r
+Only Cyclone.h and the mentioned .s or .asm file will be needed for your project, other files\r
+are here to produce or test it.\r
\r
-Cyclone has changed quite a bit from the time when Dave stopped updating it, but the rest of\r
-documentation still applies, so read it if you haven't done that yet. If you have, check the\r
-"Accessing ..." parts.\r
+First unzip "Cyclone.zip" into a "Cyclone" directory. The next thing to do is to edit config.h\r
+file to tune Cyclone for your project. There are lots of options in config.h, but all of them\r
+are documented and have defaults. You should set a define value to 1 to enable option, and\r
+to 0 to disable.\r
\r
+After you are done with config.h, save it and compile Cyclone. If you are using Linux, Cygwin,\r
+mingw or similar, you can simply cd to Cyclone/proj and type "make". If you are under Windows\r
+and have Visual Studio installed, you can import cyclone.dsp in the proj/ directory and compile\r
+it from there (this will produce cyclone.exe which you will have to run to get .s or .asm).\r
+You can also use Microsoft command line compile tools by entering Cyclone/proj directory and\r
+typing "nmake -f Makefile.win". Note that this step is done only to produce .s or .asm, and it\r
+is done using native tools on your PC (not using cross-compiler or similar).\r
\r
-ARM Register Usage\r
-------------------\r
+The .s file is meant to be compiled with GNU assembler, and .asm with ARMASM.EXE\r
+(the Microsoft ARM assembler). Once you have the file, you can add it to your\r
+Makefile/project/whatever.\r
\r
-See source code for up to date of register usage, however a summary is here:\r
\r
- r0-3: Temporary registers\r
- r4 : Current PC + Memory Base (i.e. pointer to next opcode)\r
- r5 : Cycles remaining\r
- r6 : Pointer to Opcode Jump table\r
- r7 : Pointer to Cpu Context\r
- r8 : Current Opcode\r
- r9 : Flags (NZCV) in highest four bits\r
- (r10 : Temporary source value or Memory Base)\r
- (r11 : Temporary register)\r
-\r
-\r
-How to Compile\r
---------------\r
+Adding to your project\r
+----------------------\r
\r
-Like Starscream and A68K, Cyclone uses a 'Core Creator' program which calculates and outputs\r
-all possible 68000 Opcodes and a jump table into files called Cyclone.s and .asm\r
-It then assembles these files into Cyclone.o and .obj\r
+Compiling the .s or .asm (from previous step) for your target platform may require custom\r
+build rules in your Makefile/project.\r
\r
-Cyclone.o is the GCC assembled version and Cyclone.obj is the Microsoft assembled version.\r
+If you use some gcc-based toolchain, you will need to add Cyclone.o to an object list in\r
+the Makefile. GNU make will use "as" to build Cyclone.o from Cyclone.s by default, so\r
+you may need to define correct cross-assembler by setting AS variable like this:\r
\r
-First unzip "Cyclone.zip" into a "Cyclone" directory.\r
-If you are compiling for Windows CE, find ARMASM.EXE (the Microsoft ARM assembler) and\r
-put it in the directory as well or put it on your path.\r
+AS = arm-linux-as\r
\r
-Open up Cyclone.dsw in Visual Studio 6.0, compile and run the project.\r
-Cyclone.obj and Cyclone.o will be created.\r
+This might be different in your case, basically it should be same prefix as for gcc.\r
+You may also need to specify floating point type in your assembler flags for Cyclone.o\r
+to link properly. This is done like this:\r
\r
+ASFLAGS = -mfloat-abi=soft\r
\r
-Compiling without Visual C++\r
-----------------------------\r
-If you aren't using Visual C++, it still shouldn't be too hard to compile, just get a C compiler,\r
-compile all the CPPs and C file, link them into an EXE, and run the exe.\r
+Note that Cyclone does not use floating points, this is just to make the linker happy.\r
\r
- e.g. gcc Main.cpp OpAny.cpp OpArith.cpp OpBranch.cpp OpLogic.cpp OpMove.cpp Disa.c\r
- Main.exe\r
\r
-\r
-Adding to your project\r
-----------------------\r
-\r
-To add Cyclone to you project, add Cyclone.o or obj, and include Cyclone.h\r
-There is one structure: 'struct Cyclone', and one function: CycloneRun\r
+If you are using Visual Studio, you may need to add "custom build step", which creates\r
+Cyclone.obj from Cyclone.asm (asmasm.exe Cyclone.asm). Alternatively you can create\r
+Cyclone.obj by using armasm once and then just add it to you project.\r
\r
Don't worry if this seem very minimal - its all you need to run as many 68000s as you want.\r
It works with both C and C++.\r
\r
+\r
Byteswapped Memory\r
------------------\r
\r
\r
Any memory which the 68000 can access directly must be have every two bytes swapped around.\r
This is to speed up 16-bit memory accesses, because the 68000 has Big-Endian memory\r
-and ARM has Little-Endian memory.\r
+and ARM has Little-Endian memory (in most cases).\r
\r
Now you may think you only technically have to byteswap ROM, not RAM, because\r
16-bit RAM reads go through a memory handler and you could just return (mem[a]<<8) | mem[a+1].\r
\r
The other 5 read/write functions are similar. I'll describe the CheckPc function later on.\r
\r
+\r
Declaring a CPU Context\r
-----------------------\r
\r
-To declare a CPU simple declare a struct Cyclone in your code. For example to declare\r
-two 68000s:\r
+To declare a CPU simple declare a struct Cyclone in your code (don't forget to include Cyclone.h).\r
+For example to declare two 68000s:\r
\r
struct Cyclone MyCpu;\r
struct Cyclone MyCpu2;\r
\r
-It's probably a good idea to initialise the memory to zero:\r
+It's probably a good idea to initialize the memory to zero:\r
\r
memset(&MyCpu, 0,sizeof(MyCpu));\r
memset(&MyCpu2,0,sizeof(MyCpu2));\r
If this is the case, you can set up different functions for fetch reads.\r
Generally though you don't need to. )\r
\r
-Now you are nearly ready to reset the 68000, except you need one more function: checkpc().\r
+Now you are nearly ready to reset the 68000, except a few more functions,\r
+one of them is: checkpc().\r
+\r
\r
The checkpc() function\r
----------------------\r
Cyclone's program counter would be 0x3000206.\r
\r
The difference between an ARM address and a 68000 address is also stored in a variable called\r
-'membase'. In the above example it's 0x3000000. To retrieve the real PC, Cyclone just\r
+'membase'. In the above example it's 0x3000000. To retrieve the real 68k PC, Cyclone just\r
subtracts 'membase'.\r
\r
When a long jump happens, Cyclone calls checkpc(). If the PC is in a different bank,\r
Notice that the membase is always ARM address minus 68000 address.\r
\r
The above example doesn't consider mirrored ram, but for an example of what to do see\r
-PicoDrive (in Memory.cpp).\r
+PicoDrive (in Memory.c).\r
+\r
+The exact cases when checkpc() is called can be configured in config.h.\r
+\r
+\r
+Initialization\r
+--------------\r
+\r
+Add a call to CycloneInit(). This is really only needed to be called once at startup\r
+if you enabled COMPRESS_JUMPTABLE in config.h, but you can add this in any case,\r
+it won't hurt.\r
\r
\r
Almost there - Reset the 68000!\r
-------------------------------\r
\r
-Next we need to Reset the 68000 to get the initial Program Counter and Stack Pointer. This\r
-is obtained from addresses 000000 and 000004.\r
+Cyclone doesn't provide a reset function, so next we need to Reset the 68000 to get\r
+the initial Program Counter and Stack Pointer. This is obtained from addresses\r
+000000 and 000004.\r
\r
Here is code which resets the 68000 (using your memory handlers):\r
\r
+ MyCpu.state_flags=0; // Go to default state (not stopped, halted, etc.)\r
MyCpu.srh=0x27; // Set supervisor mode\r
MyCpu.a[7]=MyCpu.read32(0); // Get Stack Pointer\r
- MyCpu.membase=0;\r
+ MyCpu.membase=0; // Will be set by checkpc()\r
MyCpu.pc=MyCpu.checkpc(MyCpu.read32(4)); // Get Program Counter\r
\r
And that's ready to go.\r
MyCpu.cycles=1000; CycloneRun(&MyCpu);\r
\r
For each opcode, the number of cycles it took is subtracted and the function returns when\r
-it reaches 0.\r
+it reaches negative number. The result is stored back to MyCpu.cycles.\r
\r
e.g.\r
// Execute one instruction on the 68000:\r
Note that the interrupt is not actually processed until the next call to CycloneRun,\r
and the interrupt may not be taken until the 68000 interrupt mask is changed to allow it.\r
\r
-( The IRQ isn't checked on exiting from a memory handler: I don't think this will cause\r
- me any trouble because I've never needed to trigger an interrupt from a memory handler,\r
- but if someone needs to, let me know...)\r
+If you need to force interrupt processing, you can use CycloneFlushIrq() function.\r
+It is the same as doing\r
\r
+MyCpu.cycles=0; CycloneRun(&MyCpu);\r
\r
-Accessing Cycle Counter\r
------------------------\r
+but is better optimized and doesn't update .cycles (returns them instead).\r
+This function can't be used from memory handlers and has no effect if interrupt is masked.\r
\r
-The cycle counter in the Cyclone structure is not, by default, updated before\r
-calling a memory handler, only at the end of an execution.\r
+The IRQ isn't checked on exiting from a memory handler. If you need to cause interrupt\r
+check immediately, you should change cycle counter to 0 to cause a return from CycloneRun(),\r
+and then call CycloneRun() again or just call CycloneFlushIrq(). Note that you need to\r
+enable MEMHANDLERS_CHANGE_CYCLES in config.h for this to work.\r
\r
-*update*\r
-Now this is configurable in config.h, there is no 'debug' variable.\r
+If you need to do something during the interrupt acknowledge (the moment when interrupt\r
+is taken), you can set USE_INT_ACK_CALLBACK in config.h and specify IrqCallback function.\r
+This function should update the IRQ level (.irq variable in context) and return the\r
+interrupt vector number. But for most cases it should return special constant\r
+CYCLONE_INT_ACK_AUTOVECTOR so that Cyclone uses autovectors, which is what most real\r
+systems were doing. Another less commonly used option is to return CYCLONE_INT_ACK_SPURIOUS\r
+for spurious interrupt.\r
\r
\r
Accessing Program Counter and registers\r
---------------------------------------\r
\r
-You can read Cyclone's registers directly from the structure at any time (as far as I know).\r
+You can read most Cyclone's registers directly from the structure at any time.\r
+However, the PC value, CCR and cycle counter are cached in ARM registers and can't\r
+be accessed from memory handlers by default. They are written back and can be\r
+accessed after execution.\r
+\r
+But if you need to access the mentioned registers during execution, you can set\r
+MEMHANDLERS_NEED_* and MEMHANDLERS_CHANGE_* options in config.h\r
\r
The Program Counter, should you need to read or write it, is stored with membase\r
added on. So use this formula to calculate the real 68000 program counter:\r
\r
pc = MyCpu.pc - MyCpu.membase;\r
\r
-The program counter is stored in r4 during execution, and isn't written back to the\r
-structure until the end of execution, which means you can't read normally real it from\r
-a memory handler.\r
-\r
-*update*\r
-Now this is configurable in config.h, there is no 'debug' variable. You can even enable\r
-access to SR if you need. However changing PC in memhandlers is still not safe, you should\r
-better clear cycles, wait untill CycloneRun() returns and then do whatever you need.\r
+For performance reasons Cyclone keeps the status register split into .srh\r
+(status register "high" supervisor byte), .xc for the X flag, and .flags for remaining\r
+CCR flags (in ARM order). To easily read/write the status register as normal 68k\r
+16bit SR register, use CycloneGetSr() and CycloneSetSr() utility functions.\r
\r
\r
Emulating more than one CPU\r
MyCpu2.cycles=1000; CycloneRun(&MyCpu2);\r
\r
\r
+Quick API reference\r
+-------------------\r
+\r
+void CycloneInit(void);\r
+ Initializes Cyclone. Must be called if the jumptable is compressed,\r
+ doesn't matter otherwise.\r
+\r
+void CycloneRun(struct Cyclone *pcy);\r
+ Runs cyclone for pcy->cycles. Writes amount of cycles left back to\r
+ pcy->cycles (always negative).\r
+\r
+unsigned int CycloneGetSr(const struct Cyclone *pcy);\r
+ Reads status register in internal form from pcy, converts to standard 68k SR and returns it.\r
+\r
+void CycloneSetSr(struct Cyclone *pcy, unsigned int sr);\r
+ Takes standard 68k status register (sr), and updates Cyclone context with it.\r
+ \r
+int CycloneFlushIrq(struct Cyclone *pcy);\r
+ If .irq is greater than IRQ mask in SR, or it is equal to 7 (NMI), processes interrupt\r
+ exception and returns number of cycles used. Otherwise, does nothing and returns 0.\r
+\r
+void CyclonePack(const struct Cyclone *pcy, void *save_buffer);\r
+ Writes Cyclone state to save_buffer. This allows to avoid all the trouble figuring what\r
+ actually needs to be saved from the Cyclone structure, as saving whole struct Cyclone\r
+ to a file will also save various pointers, which may become invalid after your program\r
+ is restarted, so simply reloading the structure will cause a crash. save_buffer size\r
+ should be 128 bytes (now it is really using less, but this allows future expansion).\r
+\r
+void CycloneUnpack(struct Cyclone *pcy, const void *save_buffer);\r
+ Reloads Cyclone state from save_buffer, which was previously saved by CyclonePack().\r
+ This function uses checkpc() callback to rebase the PC, so .checkpc must be initialized\r
+ before calling it.\r
+\r
+Callbacks:\r
+\r
+.checkpc\r
+unsigned int (*checkpc)(unsigned int pc);\r
+ This function is called when PC changes are performed in 68k code or because of exceptions.\r
+ It is passed ARM pointer and should return ARM pointer casted to int. It must also update\r
+ .membase if needed. See "The checkpc() function" section above.\r
+\r
+unsigned int (*read8 )(unsigned int a);\r
+unsigned int (*read16 )(unsigned int a);\r
+unsigned int (*read32 )(unsigned int a);\r
+ These are the read memory handler callbacks. They are called when 68k code reads from memory.\r
+ The parameter is a 68k address in data space, return value is a data value read. Data value\r
+ doesn't have to be masked to 8 or 16 bits for read8 or read16, Cyclone will do that itself\r
+ if needed.\r
+\r
+unsigned int (*fetch8 )(unsigned int a);\r
+unsigned int (*fetch16)(unsigned int a);\r
+unsigned int (*fetch32)(unsigned int a);\r
+ Same as above, but these are reads from program space (PC relative reads mostly).\r
+ \r
+void (*write8 )(unsigned int a,unsigned char d);\r
+void (*write16)(unsigned int a,unsigned short d);\r
+void (*write32)(unsigned int a,unsigned int d);\r
+ These are called when 68k code writes to data space. d is the data value.\r
+\r
+int (*IrqCallback)(int int_level);\r
+ This function is called when Cyclone acknowledges an interrupt. The parameter is the IRQ\r
+ level being acknowledged, and return value is exception vector to use, or one of these special\r
+ values: CYCLONE_INT_ACK_AUTOVECTOR or CYCLONE_INT_ACK_SPURIOUS. Can be disabled in config.h.\r
+ See "Interrupts" section for more information.\r
+\r
+void (*ResetCallback)(void);\r
+ Cyclone will call this function if it encounters RESET 68k instruction.\r
+ Can be disabled in config.h.\r
+\r
+int (*UnrecognizedCallback)(void);\r
+ Cyclone will call this function if it encounters illegal instructions (including A-line and\r
+ F-line ones). Can be tuned / disabled in config.h.\r
+\r
+\r
+Function codes\r
+--------------\r
+\r
+Cyclone doesn't pass function codes to it's memory handlers, but they can be calculated:\r
+FC2: just use supervisor state bit from status register (eg. (MyCpu.srh & 0x20) >> 5)\r
+FC1: if we are in fetch* function, then 1, else 0.\r
+FC0: if we are in read* or write*, then 1, else 0.\r
+CPU state (all FC bits set) is active in IrqCallback function.\r
+\r
+\r
+References\r
+----------\r
+\r
+These documents were used while writing Cyclone and should be useful for those who want to\r
+understand deeper how the 68000 works.\r
+\r
+MOTOROLA M68000 FAMILY Programmer's Reference Manual\r
+common name: 68kPM.pdf\r
+\r
+M68000 8-/16-/32-Bit Microprocessors User's Manual\r
+common name: MC68000UM.pdf\r
+\r
+68000 Undocumented Behavior Notes by Bart Trzynadlowski\r
+http://www.trzy.org/files/68knotes.txt\r
+\r
+Instruction prefetch on the Motorola 68000 processor by Jorge Cwik\r
+http://pasti.fxatari.com/68kdocs/68kPrefetch.html\r
+\r
+\r
+ARM Register Usage\r
+------------------\r
+\r
+See source code for up to date of register usage, however a summary is here:\r
+\r
+ r0-3: Temporary registers\r
+ r4 : Current PC + Memory Base (i.e. pointer to next opcode)\r
+ r5 : Cycles remaining\r
+ r6 : Pointer to Opcode Jump table\r
+ r7 : Pointer to Cpu Context\r
+ r8 : Current Opcode\r
+ r9 : Flags (NZCV) in highest four bits\r
+ (r10 : Temporary source value or Memory Base)\r
+ (r11 : Temporary register)\r
+\r
+Flags are mapped onto ARM flags whenever possible, which speeds up the processing of opcode.\r
+\r
+\r
Thanks to...\r
------------\r
\r
* All the previous code-generating assembler cpu core guys!\r
Who are iirc... Neill Corlett, Neil Bradley, Mike Coates, Darren Olafson\r
- and Bart Trzynadlowski\r
+ Karl Stenerud and Bart Trzynadlowski\r
\r
* Charles Macdonald, for researching just about every console ever\r
* MameDev+FBA, for keeping on going and going and going\r
\r
\r
--------------\r
+What's New\r
+----------\r
+v0.0088 notaz\r
+ - Reduced amount of code in opcode handlers by ~23% by doing the following:\r
+ - Removed duplicate opcode handlers\r
+ - Optimized code to use less ARM instructions\r
+ - Merged some duplicate handler endings\r
+ + Cyclone now does better job avoiding pipeline interlocks.\r
+ + Replaced incorrect handler of DBT with proper one.\r
+ + Changed "MOVEA (An)+ An" behavior.\r
+ + Fixed flag behavior of ROXR, ASL, LSR and NBCD in certain situations.\r
+ Hopefully got them right now.\r
+ + Cyclone no longer sets most significant bits while pushing PC to stack.\r
+ Amiga Kickstart depends on this.\r
+ + Added optional trace mode emulation.\r
+ + Added optional address error emulation.\r
+ + Additional functionality added for MAME and other ports (see config.h).\r
+ + Added return value for IrqCallback to make it suitable for emulating devices which\r
+ pass the vector number during interrupt acknowledge cycle. For usual autovector\r
+ processing this function must return CYCLONE_INT_ACK_AUTOVECTOR, so those who are\r
+ upgrading must add "return CYCLONE_INT_ACK_AUTOVECTOR;" to their IrqCallback functions.\r
+ * Updated documentation.\r
+\r
+v0.0086 notaz\r
+ + Cyclone now can be customized to better suit your project, see config.h .\r
+ + Added an option to compress the jumptable at compile-time. Must call CycloneInit()\r
+ at runtime to decompress it if enabled (see config.h).\r
+ + Added missing CHK opcode handler (used by SeaQuest DSV).\r
+ + Added missing TAS opcode handler (Gargoyles,Bubba N Stix,...). As in real genesis,\r
+ memory write-back phase is ignored (but can be enabled in config.h if needed).\r
+ + Added missing NBCD and TRAPV opcode handlers.\r
+ + Added missing addressing mode for CMP/EOR.\r
+ + Added some minor optimizations.\r
+ - Removed 216 handlers for 2927 opcodes which were generated for invalid addressing modes.\r
+ + Fixed flags for ASL, NEG, NEGX, DIVU, ADDX, SUBX, ROXR.\r
+ + Bugs fixed in MOVEP, LINK, ADDQ, DIVS handlers.\r
+ * Undocumented flags for CHK, ABCD, SBCD and NBCD are now emulated the same way as in Musashi.\r
+ + Added Uninitialized Interrupt emulation.\r
+ + Altered timing for about half of opcodes to match Musashi's.\r
+\r
+v0.0082 Reesy\r
+ + Change cyclone to clear cycles before returning when halted\r
+ + Added Irq call back function. This allows emulators to be notified\r
+ when cyclone has taken an interrupt allowing them to set internal flags\r
+ which can help fix timing problems.\r
+\r
+v0.0081 notaz\r
+ + .asm version was broken and did not compile with armasm. Fixed.\r
+ + Finished implementing Stop opcode. Now it really stops the processor.\r
+\r
+v0.0080 notaz\r
+ + Added real cmpm opcode, it was using eor handler before this.\r
+ Fixes Dune and Sensible Soccer.\r
+\r
+v0.0078 notaz\r
+ note: these bugs were actually found Reesy, I reimplemented these by\r
+ using his changelog as a guide.\r
+ + Fixed a problem with divu which was using long divisor instead of word.\r
+ Fixes gear switching in Top Gear 2.\r
+ + Fixed btst opcode, The bit to test should shifted a max of 31 or 7\r
+ depending on if a register or memory location is being tested.\r
+ + Fixed abcd,sbcd. They did bad decimal correction on invalid BCD numbers\r
+ Score counters in Streets of Rage level end work now.\r
+ + Changed flag handling of abcd,sbcd,addx,subx,asl,lsl,...\r
+ Some ops did not have flag handling at all.\r
+ Some ops must not change Z flag when result is zero, but they did.\r
+ Shift ops must not change X if shift count is zero, but they did.\r
+ There are probably still some flag problems left.\r
+ + Patially implemented Stop and Reset opcodes - Fixes Thunderforce IV\r
+\r
+v0.0075 notaz\r
+ + Added missing displacement addressing mode for movem (Fantastic Dizzy)\r
+ + Added OSP <-> A7 swapping code in opcodes, which change privilege mode\r
+ + Implemented privilege violation, line emulator and divide by zero exceptions\r
+ + Added negx opcode (Shining Force works!)\r
+ + Added overflow detection for divs/divu\r
+\r
+v0.0072 notaz\r
+ note: I could only get v0.0069 cyclone, so I had to implement these myself using Dave's\r
+ changelog as a guide.\r
+ + Fixed a problem with divs - remainder should be negative when divident is negative\r
+ + Added movep opcode (Sonic 3 works)\r
+ + Fixed a problem with DBcc incorrectly decrementing if the condition is true (Shadow of the Beast)\r
+\r
+v0.0069\r
+ + Added SBCD and the flags for ABCD/SBCD. Score and time now works in games such as\r
+ Rolling Thunder 2, Ghouls 'N Ghosts\r
+ + Fixed a problem with addx and subx with 8-bit and 16-bit values.\r
+ Ghouls 'N' Ghosts now works!\r
+\r
+v0.0068\r
+ + Added ABCD opcode (Streets of Rage works now!)\r
+\r
+v0.0067\r
+ + Added dbCC (After Burner)\r
+ + Added asr EA (Sonic 1 Boss/Labyrinth Zone)\r
+ + Added andi/ori/eori ccr (Altered Beast)\r
+ + Added trap (After Burner)\r
+ + Added special case for move.b (a7)+ and -(a7), stepping by 2\r
+ After Burner is playable! Eternal Champions shows more\r
+ + Fixed lsr.b/w zero flag (Ghostbusters)\r
+ Rolling Thunder 2 now works!\r
+ + Fixed N flag for .b and .w arithmetic. Golden Axe works!\r
+\r
+v0.0066\r
+ + Fixed a stupid typo for exg (orr r10,r10, not orr r10,r8), which caused alignment\r
+ crashes on Strider\r
+\r
+v0.0065\r
+ + Fixed a problem with immediate values - they weren't being shifted up correctly for some\r
+ opcodes. Spiderman works, After Burner shows a bit of graphics.\r
+ + Fixed a problem with EA:"110nnn" extension word. 32-bit offsets were being decoded as 8-bit\r
+ offsets by mistake. Castlevania Bloodlines seems fine now.\r
+ + Added exg opcode\r
+ + Fixed asr opcode (Sonic jumping left is fixed)\r
+ + Fixed a problem with the carry bit in rol.b (Marble Madness)\r
+\r
+v0.0064\r
+ + Added rtr\r
+ + Fixed addq/subq.l (all An opcodes are 32-bit) (Road Rash)\r
+ + Fixed various little timings\r
+\r
+v0.0063\r
+ + Added link/unlk opcodes\r
+ + Fixed various little timings\r
+ + Fixed a problem with dbCC opcode being emitted at set opcodes\r
+ + Improved long register access, the EA fetch now does ldr r0,[r7,r0,lsl #2] whenever\r
+ possible, saving 1 or 2 cycles on many opcodes, which should give a nice speed up.\r
+ + May have fixed N flag on ext opcode?\r
+ + Added dasm for link opcode.\r
+\r
+v0.0062\r
+ * I was a bit too keen with the Arithmetic opcodes! Some of them should have been abcd,\r
+ exg and addx. Removed the incorrect opcodes, pending re-adding them as abcd, exg and addx.\r
+ + Changed unknown opcodes to act as nops.\r
+ Not very technical, but fun - a few more games show more graphics ;)\r
+\r
+v0.0060\r
+ + Fixed divu (EA intro)\r
+ + Added sf (set false) opcode - SOR2\r
+ * Todo: pea/link/unlk opcodes\r
+\r
+v0.0059: Added remainder to divide opcodes.\r
\r
-Dave - 17th April 2004\r
-notaz - 17th July 2006\r
\r
-Homepage: http://www.finalburn.com/\r
-Dave's e-mail: dev(atsymbol)finalburn.com\r
-Replace (atsymbol) with @\r
return 0;\r
}\r
\r
-static int OpChk(op)\r
+static int OpChk(int op)\r
{\r
int sea=0,dea=0;\r
char seat[64]="",deat[64]="";\r
\r
#include "app.h"\r
\r
+int earead_check_addrerr = 1, eawrite_check_addrerr = 0;\r
+\r
// some ops use non-standard cycle counts for EAs, so are listed here.\r
// all constants borrowed from the MUSASHI core by Karl Stenerud.\r
\r
if (ea<0x28)\r
{\r
int step=1<<size, strr=a;\r
- int low=0,lsl,i;\r
+ int low=0,lsl=0,i;\r
\r
if ((ea&7)==7 && step<2) step=2; // move.b (a7)+ or -(a7) steps by 2 not 1\r
\r
ot("\n"); return 0;\r
}\r
\r
- if (ea>=0x3a && ea<=0x3b) MemHandler(2,size,a); // Fetch\r
- else MemHandler(0,size,a); // Read\r
+ if (ea>=0x3a && ea<=0x3b) MemHandler(2,size,a,earead_check_addrerr); // Fetch\r
+ else MemHandler(0,size,a,earead_check_addrerr); // Read\r
+\r
+ // defaults to 1, as most things begins with a read\r
+ earead_check_addrerr=1;\r
\r
if (sign_extend)\r
{\r
if (shift) ot(" mov r1,r%d,asr #%d\n",v,shift);\r
else if (v!=1) ot(" mov r1,r%d\n",v);\r
\r
- MemHandler(1,size,a); // Call write handler\r
+ MemHandler(1,size,a,eawrite_check_addrerr); // Call write handler\r
+\r
+ // not check by default, because most cases are rmw and\r
+ // address was already checked before reading\r
+ eawrite_check_addrerr = 0;\r
\r
ot("\n"); return 0;\r
}\r
\r
static FILE *AsmFile=NULL;\r
\r
-static int CycloneVer=0x0087; // Version number of library\r
+static int CycloneVer=0x0088; // Version number of library\r
int *CyJump=NULL; // Jump table\r
int ms=USE_MS_SYNTAX; // If non-zero, output in Microsoft ARMASM format\r
char *Narm[4]={ "b", "h","",""}; // Normal ARM Extensions for operand sizes 0,1,2\r
}\r
#endif\r
\r
-// trashes all temp regs\r
-static void PrintException(int ints)\r
+#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
+static void AddressErrorWrapper(char rw, char *dataprg, int iw)\r
{\r
- if(!ints) {\r
- ot(" ;@ Cause an Exception - Vector address in r0\n");\r
- ot(" mov r11,r0\n");\r
- }\r
-\r
- ot(" ldr r0,[r7,#0x44] ;@ Get SR high\n");\r
- ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
- ot(" tst r0,#0x20\n");\r
- ot(";@ get our SP:\n");\r
- ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");\r
- ot(" ldreq r1,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");\r
- ot(" streq r0,[r7,#0x48]\n");\r
- ot(" moveq r0,r1\n");\r
-\r
- ot(" sub r1,r4,r10 ;@ r1 = Old PC\n");\r
- ot(";@ Push r1 onto stack\n");\r
- ot(" sub r0,r0,#4 ;@ Predecrement A7\n");\r
- ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
- MemHandler(1,2);\r
- OpPushSr(1);\r
-\r
- ot(" mov r0,r11\n");\r
- ot(";@ Read IRQ Vector:\n");\r
- MemHandler(0,2);\r
- if(ints) {\r
- ot(" tst r0,r0 ;@ uninitialized int vector?\n");\r
- ot(" moveq r0,#0x3c\n");\r
- ot(" moveq lr,pc\n");\r
- ot(" ldreq pc,[r7,#0x70] ;@ Call read32(r0) handler\n");\r
- }\r
-#if USE_CHECKPC_CALLBACK\r
- ot(" add r0,r0,r10 ;@ r0 = Memory Base + New PC\n");\r
- ot(" mov lr,pc\n");\r
- ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
- ot(" mov r4,r0\n");\r
-#else\r
- ot(" add r4,r0,r10 ;@ r4 = Memory Base + New PC\n");\r
-#endif\r
+ ot("ExceptionAddressError_%c_%s%s\n", rw, dataprg, ms?"":":");\r
+ ot(" ldr r1,[r7,#0x44]\n");\r
+ ot(" mov r10,#0x%02x\n", iw);\r
+ ot(" mov r11,r0\n");\r
+ ot(" tst r1,#0x20\n");\r
+ ot(" orrne r10,r10,#4\n");\r
+ ot(" b ExceptionAddressError\n");\r
ot("\n");\r
-\r
- if(!ints) {\r
- ot(" ldr r0,[r7,#0x44] ;@ Get SR high\n");\r
- ot(" bic r0,r0,#0xd8 ;@ clear trace and unused flags\n");\r
- ot(" orr r0,r0,#0x20 ;@ set supervisor mode\n");\r
- ot(" strb r0,[r7,#0x44]\n");\r
- }\r
}\r
+#endif\r
\r
void FlushPC(void)\r
{\r
\r
static void PrintFramework()\r
{\r
+ int state_flags_to_check = 1; // stopped\r
+#if EMULATE_TRACE\r
+ state_flags_to_check |= 2; // tracing\r
+#endif\r
+#if EMULATE_HALT\r
+ state_flags_to_check |= 0x10; // halted\r
+#endif\r
+\r
ot(";@ --------------------------- Framework --------------------------\n");\r
if (ms) ot("CycloneRun\n");\r
else ot("CycloneRun:\n");\r
ot(" mov r9,r9,lsl #28 ;@ r9 = Flags 0xf0000000, cpsr format\n");\r
ot(" ;@ r10 = Source value / Memory Base\n");\r
ot("\n");\r
+#if (CYCLONE_FOR_GENESIS == 2) || EMULATE_TRACE\r
+ ot(" mov r2,#0\n");\r
+ ot(" str r2,[r7,#0x98] ;@ clear custom CycloneEnd\n");\r
+#endif\r
ot(";@ CheckInterrupt:\n");\r
ot(" movs r0,r1,lsr #24 ;@ Get IRQ level\n"); // same as ldrb r0,[r7,#0x47]\r
ot(" beq NoInts0\n");\r
ot(" bgt CycloneDoInterrupt\n");\r
ot("NoInts0%s\n", ms?"":":");\r
ot("\n");\r
- ot(";@ Check if our processor is in stopped state and jump to opcode handler if not\n");\r
- ot(" ldr r0,[r7,#0x58]\n");\r
+ ot(";@ Check if our processor is in special state\n");\r
+ ot(";@ and jump to opcode handler if not\n");\r
+ ot(" ldr r0,[r7,#0x58] ;@ state_flags\n");\r
ot(" ldrh r8,[r4],#2 ;@ Fetch first opcode\n");\r
- ot(" tst r0,r0 ;@ stopped?\n");\r
- ot(" bne CycloneStopped\n");\r
- ot(" ldr pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
+ ot(" tst r0,#0x%02x ;@ special state?\n", state_flags_to_check);\r
+ ot(" ldreq pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
+ ot("\n");\r
+ ot("CycloneSpecial%s\n", ms?"":":");\r
+#if EMULATE_TRACE\r
+ ot(" tst r0,#2 ;@ tracing?\n");\r
+ ot(" bne CycloneDoTrace\n");\r
+#endif\r
+ ot(";@ stopped or halted\n");\r
+ ot(" mov r5,#0\n");\r
+ ot(" str r5,[r7,#0x5C] ;@ eat all cycles\n");\r
+ ot(" ldmia sp!,{r4-r11,pc} ;@ we are stopped, do nothing!\n");\r
ot("\n");\r
ot("\n");\r
\r
ot("CycloneEnd%s\n", ms?"":":");\r
ot(" sub r4,r4,#2\n");\r
ot("CycloneEndNoBack%s\n", ms?"":":");\r
-#if (CYCLONE_FOR_GENESIS == 2)\r
- ot(" ldr r1,[r7,#0x54]\n");\r
+#if (CYCLONE_FOR_GENESIS == 2) || EMULATE_TRACE\r
+ ot(" ldr r1,[r7,#0x98]\n");\r
ot(" mov r9,r9,lsr #28\n");\r
ot(" tst r1,r1\n");\r
ot(" bxne r1 ;@ jump to alternative CycloneEnd\n");\r
ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
ot(" strb r9,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
ot(" ldmia sp!,{r4-r11,pc}\n");\r
+ ltorg();\r
ot("\n");\r
- ot("CycloneStopped%s\n", ms?"":":");\r
- ot(" mov r5,#0\n");\r
- ot(" str r5,[r7,#0x5C] ;@ eat all cycles\n");\r
- ot(" ldmia sp!,{r4-r11,pc} ;@ we are stopped, do nothing!\n");\r
ot("\n");\r
\r
- ltorg();\r
-\r
+ ot("CycloneInit%s\n", ms?"":":");\r
#if COMPRESS_JUMPTABLE\r
- ot(";@ uncompress jump table\n");\r
- if (ms) ot("CycloneInit\n");\r
- else ot("CycloneInit:\n");\r
- ot(" ldr r12,=CycloneJumpTab\n");\r
- ot(" add r0,r12,#0xe000*4 ;@ ctrl code pointer\n");\r
- ot(" ldr r1,[r0,#-4]\n");\r
- ot(" tst r1,r1\n");\r
- ot(" movne pc,lr ;@ already uncompressed\n");\r
- ot(" add r3,r12,#0xa000*4 ;@ handler table pointer, r12=dest\n");\r
- ot("unc_loop%s\n", ms?"":":");\r
- ot(" ldrh r1,[r0],#2\n");\r
- ot(" and r2,r1,#0xf\n");\r
- ot(" bic r1,r1,#0xf\n");\r
- ot(" ldr r1,[r3,r1,lsr #2] ;@ r1=handler\n");\r
- ot(" cmp r2,#0xf\n");\r
- ot(" addeq r2,r2,#1 ;@ 0xf is really 0x10\n");\r
- ot(" tst r2,r2\n");\r
- ot(" ldreqh r2,[r0],#2 ;@ counter is in next word\n");\r
- ot(" tst r2,r2\n");\r
- ot(" beq unc_finish ;@ done decompressing\n");\r
- ot(" tst r1,r1\n");\r
- ot(" addeq r12,r12,r2,lsl #2 ;@ 0 handler means we should skip those bytes\n");\r
- ot(" beq unc_loop\n");\r
- ot("unc_loop_in%s\n", ms?"":":");\r
- ot(" subs r2,r2,#1\n");\r
- ot(" str r1,[r12],#4\n");\r
- ot(" bgt unc_loop_in\n");\r
- ot(" b unc_loop\n");\r
- ot("unc_finish%s\n", ms?"":":");\r
- ot(" ldr r12,=CycloneJumpTab\n");\r
- ot(" ;@ set a-line and f-line handlers\n");\r
- ot(" add r0,r12,#0xa000*4\n");\r
- ot(" ldr r1,[r0,#4] ;@ a-line handler\n");\r
- ot(" ldr r3,[r0,#8] ;@ f-line handler\n");\r
- ot(" mov r2,#0x1000\n");\r
- ot("unc_fill3%s\n", ms?"":":");\r
- ot(" subs r2,r2,#1\n");\r
- ot(" str r1,[r0],#4\n");\r
- ot(" bgt unc_fill3\n");\r
- ot(" add r0,r12,#0xf000*4\n");\r
- ot(" mov r2,#0x1000\n");\r
- ot("unc_fill4%s\n", ms?"":":");\r
- ot(" subs r2,r2,#1\n");\r
- ot(" str r3,[r0],#4\n");\r
- ot(" bgt unc_fill4\n");\r
- ot(" bx lr\n");\r
- ltorg();\r
- ot("\n");\r
+ ot(";@ decompress jump table\n");\r
+ ot(" ldr r12,=CycloneJumpTab\n");\r
+ ot(" add r0,r12,#0xe000*4 ;@ ctrl code pointer\n");\r
+ ot(" ldr r1,[r0,#-4]\n");\r
+ ot(" tst r1,r1\n");\r
+ ot(" movne pc,lr ;@ already uncompressed\n");\r
+ ot(" add r3,r12,#0xa000*4 ;@ handler table pointer, r12=dest\n");\r
+ ot("unc_loop%s\n", ms?"":":");\r
+ ot(" ldrh r1,[r0],#2\n");\r
+ ot(" and r2,r1,#0xf\n");\r
+ ot(" bic r1,r1,#0xf\n");\r
+ ot(" ldr r1,[r3,r1,lsr #2] ;@ r1=handler\n");\r
+ ot(" cmp r2,#0xf\n");\r
+ ot(" addeq r2,r2,#1 ;@ 0xf is really 0x10\n");\r
+ ot(" tst r2,r2\n");\r
+ ot(" ldreqh r2,[r0],#2 ;@ counter is in next word\n");\r
+ ot(" tst r2,r2\n");\r
+ ot(" beq unc_finish ;@ done decompressing\n");\r
+ ot(" tst r1,r1\n");\r
+ ot(" addeq r12,r12,r2,lsl #2 ;@ 0 handler means we should skip those bytes\n");\r
+ ot(" beq unc_loop\n");\r
+ ot("unc_loop_in%s\n", ms?"":":");\r
+ ot(" subs r2,r2,#1\n");\r
+ ot(" str r1,[r12],#4\n");\r
+ ot(" bgt unc_loop_in\n");\r
+ ot(" b unc_loop\n");\r
+ ot("unc_finish%s\n", ms?"":":");\r
+ ot(" ldr r12,=CycloneJumpTab\n");\r
+ ot(" ;@ set a-line and f-line handlers\n");\r
+ ot(" add r0,r12,#0xa000*4\n");\r
+ ot(" ldr r1,[r0,#4] ;@ a-line handler\n");\r
+ ot(" ldr r3,[r0,#8] ;@ f-line handler\n");\r
+ ot(" mov r2,#0x1000\n");\r
+ ot("unc_fill3%s\n", ms?"":":");\r
+ ot(" subs r2,r2,#1\n");\r
+ ot(" str r1,[r0],#4\n");\r
+ ot(" bgt unc_fill3\n");\r
+ ot(" add r0,r12,#0xf000*4\n");\r
+ ot(" mov r2,#0x1000\n");\r
+ ot("unc_fill4%s\n", ms?"":":");\r
+ ot(" subs r2,r2,#1\n");\r
+ ot(" str r3,[r0],#4\n");\r
+ ot(" bgt unc_fill4\n");\r
+ ot(" bx lr\n");\r
+ ltorg();\r
#else\r
- ot(";@ do nothing\n");\r
- if (ms) ot("CycloneInit\n");\r
- else ot("CycloneInit:\n");\r
- ot(" bx lr\n");\r
- ot("\n");\r
+ ot(";@ do nothing\n");\r
+ ot(" bx lr\n");\r
#endif\r
+ ot("\n");\r
+\r
+ // --------------\r
// 68k: XNZVC, ARM: NZCV\r
- if (ms) ot("CycloneSetSr\n");\r
- else ot("CycloneSetSr:\n");\r
+ ot("CycloneSetSr%s\n", ms?"":":");\r
ot(" mov r2,r1,lsr #8\n");\r
- ot(" ldrb r3,[r0,#0x44] ;@ get SR high\n");\r
- ot(" eor r3,r3,r2\n");\r
- ot(" tst r3,#0x20\n");\r
- ot(" and r2,r2,#0xa7 ;@ only nonzero bits\n");\r
+// ot(" ldrb r3,[r0,#0x44] ;@ get SR high\n");\r
+// ot(" eor r3,r3,r2\n");\r
+// ot(" tst r3,#0x20\n");\r
+#if EMULATE_TRACE\r
+ ot(" and r2,r2,#0xa7 ;@ only defined bits\n");\r
+#else\r
+ ot(" and r2,r2,#0x27 ;@ only defined bits\n");\r
+#endif\r
ot(" strb r2,[r0,#0x44] ;@ set SR high\n");\r
- ot(" bne setsr_noswap\n");\r
- ot(" ldr r2,[r0,#0x3C] ;@ Get A7\n");\r
- ot(" ldr r3,[r0,#0x48] ;@ Get OSP\n");\r
- ot(" str r3,[r0,#0x3C]\n");\r
- ot(" str r2,[r0,#0x48]\n");\r
- ot("setsr_noswap%s\n",ms?"":":");\r
ot(" mov r2,r1,lsl #25\n");\r
ot(" str r2,[r0,#0x4c] ;@ the X flag\n");\r
ot(" bic r2,r1,#0xf3\n");\r
ot(" bx lr\n");\r
ot("\n");\r
\r
- if (ms) ot("CycloneGetSr\n");\r
- else ot("CycloneGetSr:\n");\r
+ // --------------\r
+ ot("CycloneGetSr%s\n", ms?"":":");\r
ot(" ldrb r1,[r0,#0x46] ;@ flags\n");\r
ot(" bic r2,r1,#0xf3\n");\r
ot(" tst r1,#1\n");\r
ot(" bx lr\n");\r
ot("\n");\r
\r
- if (ms) ot("CycloneSetRealTAS\n");\r
- else ot("CycloneSetRealTAS:\n");\r
+ // --------------\r
+ ot("CyclonePack%s\n", ms?"":":");\r
+ ot(" stmfd sp!,{r4,r5,lr}\n");\r
+ ot(" mov r4,r0\n");\r
+ ot(" mov r5,r1\n");\r
+ ot(" mov r3,#16\n");\r
+ ot(";@ 0x00-0x3f: DA registers\n");\r
+ ot("c_pack_loop%s\n",ms?"":":");\r
+ ot(" ldr r1,[r0],#4\n");\r
+ ot(" subs r3,r3,#1\n");\r
+ ot(" str r1,[r5],#4\n");\r
+ ot(" bne c_pack_loop\n");\r
+ ot(";@ 0x40: PC\n");\r
+ ot(" ldr r0,[r4,#0x40] ;@ PC + Memory Base\n");\r
+ ot(" ldr r1,[r4,#0x60] ;@ Memory base\n");\r
+ ot(" sub r0,r0,r1\n");\r
+ ot(" str r0,[r5],#4\n");\r
+ ot(";@ 0x44: SR\n");\r
+ ot(" mov r0,r4\n");\r
+ ot(" bl CycloneGetSr\n");\r
+ ot(" strh r0,[r5],#2\n");\r
+ ot(";@ 0x46: IRQ level\n");\r
+ ot(" ldrb r0,[r4,#0x47]\n");\r
+ ot(" strb r0,[r5],#2\n");\r
+ ot(";@ 0x48: other SP\n");\r
+ ot(" ldr r0,[r4,#0x48]\n");\r
+ ot(" str r0,[r5],#4\n");\r
+ ot(";@ 0x4c: CPU state flags\n");\r
+ ot(" ldr r0,[r4,#0x58]\n");\r
+ ot(" str r0,[r5],#4\n");\r
+ ot(" ldmfd sp!,{r4,r5,pc}\n");\r
+ ot("\n");\r
+\r
+ // --------------\r
+ ot("CycloneUnpack%s\n", ms?"":":");\r
+ ot(" stmfd sp!,{r4,r5,lr}\n");\r
+ ot(" mov r4,r0\n");\r
+ ot(" mov r5,r1\n");\r
+ ot(" mov r3,#16\n");\r
+ ot(";@ 0x00-0x3f: DA registers\n");\r
+ ot("c_unpack_loop%s\n",ms?"":":");\r
+ ot(" ldr r1,[r5],#4\n");\r
+ ot(" subs r3,r3,#1\n");\r
+ ot(" str r1,[r0],#4\n");\r
+ ot(" bne c_unpack_loop\n");\r
+ ot(";@ 0x40: PC\n");\r
+ ot(" ldr r0,[r5],#4 ;@ PC\n");\r
+#if USE_CHECKPC_CALLBACK\r
+ ot(" mov r1,#0\n");\r
+ ot(" str r1,[r4,#0x60] ;@ Memory base\n");\r
+ ot(" mov lr,pc\n");\r
+ ot(" ldr pc,[r4,#0x64] ;@ Call checkpc()\n");\r
+#else\r
+ ot(" ldr r1,[r4,#0x60] ;@ Memory base\n");\r
+ ot(" add r0,r0,r1 ;@ r0 = Memory Base + New PC\n");\r
+#endif\r
+ ot(" str r0,[r4,#0x40] ;@ PC + Memory Base\n");\r
+ ot(";@ 0x44: SR\n");\r
+ ot(" ldrh r1,[r5],#2\n");\r
+ ot(" mov r0,r4\n");\r
+ ot(" bl CycloneSetSr\n");\r
+ ot(";@ 0x46: IRQ level\n");\r
+ ot(" ldrb r0,[r5],#2\n");\r
+ ot(" strb r0,[r4,#0x47]\n");\r
+ ot(";@ 0x48: other SP\n");\r
+ ot(" ldr r0,[r5],#4\n");\r
+ ot(" str r0,[r4,#0x48]\n");\r
+ ot(";@ 0x4c: CPU state flags\n");\r
+ ot(" ldr r0,[r5],#4\n");\r
+ ot(" str r0,[r4,#0x58]\n");\r
+ ot(" ldmfd sp!,{r4,r5,pc}\n");\r
+ ot("\n");\r
+\r
+ // --------------\r
+ ot("CycloneFlushIrq%s\n", ms?"":":");\r
+ ot(" ldr r1,[r0,#0x44] ;@ Get SR high T_S__III and irq level\n");\r
+ ot(" mov r2,r1,lsr #24 ;@ Get IRQ level\n"); // same as ldrb r0,[r7,#0x47]\r
+ ot(" cmp r2,#6 ;@ irq>6 ?\n");\r
+ ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");\r
+ ot(" cmple r2,r1 ;@ irq<=6: Is irq<=mask ?\n");\r
+ ot(" movle r0,#0\n");\r
+ ot(" bxle lr ;@ no ints\n");\r
+ ot("\n");\r
+ ot(" stmdb sp!,{r4,r5,r7-r11,lr}\n");\r
+ ot(" mov r7,r0\n");\r
+ ot(" mov r0,r2\n");\r
+ ot(" ldrb r9,[r7,#0x46] ;@ r9 = Flags (NZCV)\n");\r
+ ot(" mov r5,#0\n");\r
+ ot(" ldr r4,[r7,#0x40] ;@ r4 = Current PC + Memory Base\n");\r
+ ot(" mov r9,r9,lsl #28 ;@ r9 = Flags 0xf0000000, cpsr format\n");\r
+ ot(" adr r2,CycloneFlushIrqEnd\n");\r
+ ot(" str r2,[r7,#0x98] ;@ set custom CycloneEnd\n");\r
+ ot(" b CycloneDoInterrupt\n");\r
+ ot("\n");\r
+ ot("CycloneFlushIrqEnd%s\n", ms?"":":");\r
+ ot(" rsb r0,r5,#0\n");\r
+ ot(" str r4,[r7,#0x40] ;@ Save Current PC + Memory Base\n");\r
+ ot(" strb r9,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
+ ot(" ldmia sp!,{r4,r5,r7-r11,lr}\n");\r
+ ot(" bx lr\n");\r
+ ot("\n");\r
+ ot("\n");\r
+\r
+ // --------------\r
+ ot("CycloneSetRealTAS%s\n", ms?"":":");\r
#if (CYCLONE_FOR_GENESIS == 2)\r
ot(" ldr r12,=CycloneJumpTab\n");\r
ot(" tst r0,r0\n");\r
ChangeTAS(0);\r
ot(" bx lr\n");\r
ltorg();\r
- ot("\n");\r
#else\r
ot(" bx lr\n");\r
- ot("\n");\r
#endif\r
+ ot("\n");\r
\r
- ot(";@ DoInterrupt - r0=IRQ number\n");\r
+ // --------------\r
+ ot(";@ DoInterrupt - r0=IRQ level\n");\r
ot("CycloneDoInterruptGoBack%s\n", ms?"":":");\r
ot(" sub r4,r4,#2\n");\r
ot("CycloneDoInterrupt%s\n", ms?"":":");\r
- ot(";@ Get IRQ Vector address:\n");\r
- ot(" mov r0,r0,asl #2\n");\r
- ot(" add r11,r0,#0x60\n");\r
- PrintException(1);\r
- \r
- ot(" ldrb r0,[r7,#0x47] ;@ IRQ\n");\r
- ot(" mov r2,#0\n");\r
- ot(" orr r1,r0,#0x20 ;@ Supervisor mode + IRQ number\n");\r
- ot(" strb r1,[r7,#0x44] ;@ Put SR high\n");\r
-\r
- ot(";@ Clear stopped states:\n");\r
+ ot(" bic r8,r8,#0xff000000\n");\r
+ ot(" orr r8,r8,r0,lsl #29 ;@ abuse r8\n");\r
+\r
+ // Steps are from "M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL", p. 6-4\r
+ // but their order is based on http://pasti.fxatari.com/68kdocs/68kPrefetch.html\r
+ // 1. Make a temporary copy of the status register and set the status register for exception processing.\r
+ ot(" ldr r2,[r7,#0x58] ;@ state flags\n");\r
+ ot(" and r0,r0,#7\n");\r
+ ot(" orr r3,r0,#0x20 ;@ Supervisor mode + IRQ level\n");\r
+ ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");\r
+#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
+ ot(" orr r2,r2,#4 ;@ set activity bit: 'not processing instruction'\n");\r
+#endif\r
ot(" str r2,[r7,#0x58]\n");\r
+ ot(" ldrb r10,[r7,#0x44] ;@ Get old SR high\n");\r
+ ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");\r
+ ot("\n");\r
+\r
+ // 3. Save the current processor context.\r
+ ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");\r
+ ot(" ldr r11,[r7,#0x3c] ;@ Get A7\n");\r
+ ot(" tst r10,#0x20\n");\r
+ ot(";@ get our SP:\n");\r
+ ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");\r
+ ot(" streq r11,[r7,#0x48]\n");\r
+ ot(" moveq r11,r2\n");\r
+ ot(";@ Push old PC onto stack\n");\r
+ ot(" sub r0,r11,#4 ;@ Predecremented A7\n");\r
+ ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");\r
+ MemHandler(1,2);\r
+ ot(";@ Push old SR:\n");\r
+ ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");\r
+ ot(" mov r1,r9,lsr #28 ;@ ____NZCV\n");\r
+ ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");\r
+ ot(" tst r2,#1 ;@ 1 if C!=V\n");\r
+ ot(" eorne r1,r1,#3 ;@ ____NZVC\n");\r
+ ot(" and r0,r0,#0x20000000\n");\r
+ ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");\r
+ ot(" orr r1,r1,r10,lsl #8 ;@ Include old SR high\n");\r
+ ot(" sub r0,r11,#6 ;@ Predecrement A7\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ MemHandler(1,1,0,0); // already checked for address error by prev MemHandler\r
ot("\n");\r
+\r
+ // 2. Obtain the exception vector.\r
+ ot(" mov r11,r8,lsr #29\n");\r
+ ot(" mov r0,r11\n");\r
#if USE_INT_ACK_CALLBACK\r
+ ot(";@ call IrqCallback if it is defined\n");\r
#if INT_ACK_NEEDS_STUFF\r
ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
ot(" mov r1,r9,lsr #28\n");\r
ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
#endif\r
- ot(" ldr r11,[r7,#0x8c] ;@ IrqCallback\n");\r
- ot(" tst r11,r11\n");\r
- ot(" movne lr,pc\n");\r
- ot(" movne pc,r11 ;@ call IrqCallback if it is defined\n");\r
-#if INT_ACK_CHANGES_STUFF\r
+ ot(" ldr r3,[r7,#0x8c] ;@ IrqCallback\n");\r
+ ot(" add lr,pc,#4*3\n");\r
+ ot(" tst r3,r3\n");\r
+ ot(" streqb r3,[r7,#0x47] ;@ just clear IRQ if there is no callback\n");\r
+ ot(" mvneq r0,#0 ;@ and simulate -1 return\n");\r
+ ot(" bxne r3\n");\r
+#if INT_ACK_CHANGES_CYCLES\r
ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
- ot(" ldrb r9,[r7,#0x46] ;@ r9 = Load Flags (NZCV)\n");\r
- ot(" mov r9,r9,lsl #28\n");\r
- ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
#endif\r
+ ot(";@ get IRQ vector address:\n");\r
+ ot(" cmn r0,#1 ;@ returned -1?\n");\r
+ ot(" addeq r0,r11,#0x18 ;@ use autovector then\n");\r
+ ot(" cmn r0,#2 ;@ returned -2?\n"); // should be safe as above add should never result in -2\r
+ ot(" moveq r0,#0x18 ;@ use spurious interrupt then\n");\r
#else // !USE_INT_ACK_CALLBACK\r
ot(";@ Clear irq:\n");\r
+ ot(" mov r2,#0\n");\r
ot(" strb r2,[r7,#0x47]\n");\r
+ ot(" add r0,r0,#0x18 ;@ use autovector\n");\r
+#endif\r
+ ot(" mov r0,r0,lsl #2 ;@ get vector address\n");\r
+ ot("\n");\r
+ ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
+ ot(";@ Read IRQ Vector:\n");\r
+ MemHandler(0,2,0,0);\r
+ ot(" tst r0,r0 ;@ uninitialized int vector?\n");\r
+ ot(" moveq r0,#0x3c\n");\r
+ ot(" moveq lr,pc\n");\r
+ ot(" ldreq pc,[r7,#0x70] ;@ Call read32(r0) handler\n");\r
+#if USE_CHECKPC_CALLBACK\r
+ ot(" add lr,pc,#4\n");\r
+ ot(" add r0,r0,r10 ;@ r0 = Memory Base + New PC\n");\r
+ ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
+ #if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" mov r4,r0\n");\r
+ #else\r
+ ot(" bic r4,r0,#1\n");\r
+ #endif\r
+#else\r
+ ot(" add r4,r0,r10 ;@ r4 = Memory Base + New PC\n");\r
+ #if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" bic r4,r4,#1\n");\r
+ #endif\r
+#endif\r
+ ot("\n");\r
+\r
+ // 4. Obtain a new context and resume instruction processing.\r
+ // note: the obtain part was already done in previous steps\r
+#if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" tst r4,#1\n");\r
+ ot(" bne ExceptionAddressError_r_prg_r4\n");\r
#endif\r
ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
ot(" subs r5,r5,#44 ;@ Subtract cycles\n");\r
ot(" b CycloneEnd\n");\r
ot("\n");\r
\r
+ // --------------\r
+ // trashes all temp regs\r
ot("Exception%s\n", ms?"":":");\r
- ot(" stmdb sp!,{lr} ;@ Preserve ARM return address\n");\r
- PrintException(0);\r
- ot(" ldmia sp!,{pc} ;@ Return\n");\r
+ ot(" ;@ Cause an Exception - Vector number in r0\n");\r
+ ot(" mov r11,lr ;@ Preserve ARM return address\n");\r
+ ot(" bic r8,r8,#0xff000000\n");\r
+ ot(" orr r8,r8,r0,lsl #24 ;@ abuse r8\n");\r
+\r
+ // 1. Make a temporary copy of the status register and set the status register for exception processing.\r
+ ot(" ldr r10,[r7,#0x44] ;@ Get old SR high\n");\r
+ ot(" ldr r2,[r7,#0x58] ;@ state flags\n");\r
+ ot(" and r3,r10,#0x27 ;@ clear trace and unused flags\n");\r
+ ot(" orr r3,r3,#0x20 ;@ set supervisor mode\n");\r
+ ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");\r
+ ot(" str r2,[r7,#0x58]\n");\r
+ ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");\r
+ ot("\n");\r
+\r
+ // 3. Save the current processor context.\r
+ ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");\r
+ ot(" tst r10,#0x20\n");\r
+ ot(";@ get our SP:\n");\r
+ ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");\r
+ ot(" streq r0,[r7,#0x48]\n");\r
+ ot(" moveq r0,r2\n");\r
+ ot(";@ Push old PC onto stack\n");\r
+ ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");\r
+ ot(" sub r0,r0,#4 ;@ Predecremented A7\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");\r
+ MemHandler(1,2);\r
+ ot(";@ Push old SR:\n");\r
+ ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");\r
+ ot(" mov r1,r9,lsr #28 ;@ ____NZCV\n");\r
+ ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");\r
+ ot(" tst r2,#1 ;@ 1 if C!=V\n");\r
+ ot(" eorne r1,r1,#3 ;@ ____NZVC\n");\r
+ ot(" and r0,r0,#0x20000000\n");\r
+ ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");\r
+ ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
+ ot(" orr r1,r1,r10,lsl #8 ;@ Include SR high\n");\r
+ ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ MemHandler(1,1,0,0);\r
+ ot("\n");\r
+\r
+ // 2. Obtain the exception vector\r
+ ot(";@ Read Exception Vector:\n");\r
+ ot(" mov r0,r8,lsr #24\n");\r
+ ot(" mov r0,r0,lsl #2\n");\r
+ MemHandler(0,2,0,0);\r
+ ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");\r
+#if USE_CHECKPC_CALLBACK\r
+ ot(" add lr,pc,#4\n");\r
+ ot(" add r0,r0,r3 ;@ r0 = Memory Base + New PC\n");\r
+ ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
+ #if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" mov r4,r0\n");\r
+ #else\r
+ ot(" bic r4,r0,#1\n");\r
+ #endif\r
+#else\r
+ ot(" add r4,r0,r3 ;@ r4 = Memory Base + New PC\n");\r
+ #if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" bic r4,r4,#1\n");\r
+ #endif\r
+#endif\r
+ ot("\n");\r
+\r
+ // 4. Resume execution.\r
+#if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" tst r4,#1\n");\r
+ ot(" bne ExceptionAddressError_r_prg_r4\n");\r
+#endif\r
+ ot(" bx r11 ;@ Return\n");\r
+ ot("\n");\r
+\r
+ // --------------\r
+#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
+ // first some wrappers: I see no point inlining this code,\r
+ // as it will be executed in really rare cases.\r
+ AddressErrorWrapper('r', "data", 0x11);\r
+ AddressErrorWrapper('r', "prg", 0x12);\r
+ AddressErrorWrapper('w', "data", 0x01);\r
+ // there are no program writes\r
+ // cpu space is only for bus errors?\r
+ ot("ExceptionAddressError_r_prg_r4%s\n", ms?"":":");\r
+ ot(" ldr r1,[r7,#0x44]\n");\r
+ ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");\r
+ ot(" mov r10,#0x12\n");\r
+ ot(" sub r11,r4,r3\n");\r
+ ot(" tst r1,#0x20\n");\r
+ ot(" orrne r10,r10,#4\n");\r
+ ot("\n");\r
+\r
+ ot("ExceptionAddressError%s\n", ms?"":":");\r
+ ot(";@ r10 - info word (without instruction/not bit), r11 - faulting address\n");\r
+\r
+ // 1. Make a temporary copy of the status register and set the status register for exception processing.\r
+ ot(" ldrb r0,[r7,#0x44] ;@ Get old SR high\n");\r
+ ot(" ldr r2,[r7,#0x58] ;@ state flags\n");\r
+ ot(" and r3,r0,#0x27 ;@ clear trace and unused flags\n");\r
+ ot(" orr r3,r3,#0x20 ;@ set supervisor mode\n");\r
+ ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");\r
+ ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");\r
+ ot(" tst r2,#4\n");\r
+ ot(" orrne r10,r10,#8 ;@ complete info word\n");\r
+ ot(" orr r2,r2,#4 ;@ set activity bit: 'not processing instruction'\n");\r
+#if EMULATE_HALT\r
+ ot(" tst r2,#8\n");\r
+ ot(" orrne r2,r2,#0x10 ;@ HALT\n");\r
+ ot(" orr r2,r2,#8 ;@ processing address error\n");\r
+ ot(" str r2,[r7,#0x58]\n");\r
+ ot(" movne r5,#0\n");\r
+ ot(" bne CycloneEndNoBack ;@ bye bye\n");\r
+#else\r
+ ot(" str r2,[r7,#0x58]\n");\r
+#endif\r
+ ot(" and r9,r9,#0xf0000000\n");\r
+ ot(" orr r9,r9,r0,lsl #4 ;@ some preparations for SR push\n");\r
+ ot("\n");\r
+\r
+ // 3. Save the current processor context + additional information.\r
+ ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");\r
+ ot(" tst r9,#0x200\n");\r
+ ot(";@ get our SP:\n");\r
+ ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");\r
+ ot(" streq r0,[r7,#0x48]\n");\r
+ ot(" moveq r0,r2\n");\r
+ // PC\r
+ ot(";@ Push old PC onto stack\n");\r
+ ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");\r
+ ot(" sub r0,r0,#4 ;@ Predecremented A7\n");\r
+ ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ MemHandler(1,2,0,EMULATE_HALT);\r
+ // SR\r
+ ot(";@ Push old SR:\n");\r
+ ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");\r
+ ot(" mov r1,r9,ror #28 ;@ ____NZCV\n");\r
+ ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");\r
+ ot(" tst r2,#1 ;@ 1 if C!=V\n");\r
+ ot(" eorne r1,r1,#3 ;@ ____NZVC\n");\r
+ ot(" and r0,r0,#0x20000000\n");\r
+ ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");\r
+ ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
+ ot(" and r9,r9,#0xf0000000\n");\r
+ ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ MemHandler(1,1,0,0);\r
+ // IR (instruction register)\r
+ ot(";@ Push IR:\n");\r
+ ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
+ ot(" mov r1,r8\n");\r
+ ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ MemHandler(1,1,0,0);\r
+ // access address\r
+ ot(";@ Push address:\n");\r
+ ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
+ ot(" mov r1,r11\n");\r
+ ot(" sub r0,r0,#4 ;@ Predecrement A7\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ MemHandler(1,2,0,0);\r
+ // information word\r
+ ot(";@ Push info word:\n");\r
+ ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
+ ot(" mov r1,r10\n");\r
+ ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ MemHandler(1,1,0,0);\r
+ ot("\n");\r
+\r
+ // 2. Obtain the exception vector\r
+ ot(";@ Read Exception Vector:\n");\r
+ ot(" mov r0,#0x0c\n");\r
+ MemHandler(0,2,0,0);\r
+ ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");\r
+#if USE_CHECKPC_CALLBACK\r
+ ot(" add lr,pc,#4\n");\r
+ ot(" add r0,r0,r3 ;@ r0 = Memory Base + New PC\n");\r
+ ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
+ ot(" mov r4,r0\n");\r
+#else\r
+ ot(" add r4,r0,r3 ;@ r4 = Memory Base + New PC\n");\r
+#endif\r
+ ot("\n");\r
+\r
+#if EMULATE_ADDRESS_ERRORS_JUMP && EMULATE_HALT\r
+ ot(" tst r4,#1\n");\r
+ ot(" bne ExceptionAddressError_r_prg_r4\n");\r
+#else\r
+ ot(" bic r4,r4,#1\n");\r
+#endif\r
+\r
+ // 4. Resume execution.\r
+ ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
+ ot(" subs r5,r5,#50 ;@ Subtract cycles\n");\r
+ ot(" ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
+ ot(" b CycloneEnd\n");\r
+ ot("\n");\r
+#endif\r
+\r
+ // --------------\r
+#if EMULATE_TRACE\r
+ // expects srh and irq level in r1, next opcode already fetched to r8\r
+ ot("CycloneDoTraceWithChecks%s\n", ms?"":":");\r
+ ot(" ldr r0,[r7,#0x58]\n");\r
+ ot(" cmp r5,#0\n");\r
+ ot(" orr r0,r0,#2 ;@ go to trace mode\n");\r
+ ot(" str r0,[r7,#0x58]\n");\r
+ ot(" blt CycloneEnd\n"); // should take care of situation where we come here when already tracing\r
+ ot(";@ CheckInterrupt:\n");\r
+ ot(" movs r0,r1,lsr #24 ;@ Get IRQ level\n");\r
+ ot(" beq CycloneDoTrace\n");\r
+ ot(" cmp r0,#6 ;@ irq>6 ?\n");\r
+ ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");\r
+ ot(" cmple r0,r1 ;@ irq<=6: Is irq<=mask ?\n");\r
+ ot(" bgt CycloneDoInterruptGoBack\n");\r
+ ot("\n");\r
+\r
+ // expects next opcode to be already fetched to r8\r
+ ot("CycloneDoTrace%s\n", ms?"":":");\r
+ ot(" str r5,[r7,#0x9c] ;@ save cycles\n");\r
+ ot(" ldr r1,[r7,#0x98]\n");\r
+ ot(" mov r5,#0\n");\r
+ ot(" str r1,[r7,#0xa0]\n");\r
+ ot(" adr r0,TraceEnd\n");\r
+ ot(" str r0,[r7,#0x98] ;@ store TraceEnd as CycloneEnd hadler\n");\r
+ ot(" ldr pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
+ ot("\n");\r
+\r
+ ot("TraceEnd%s\n", ms?"":":");\r
+ ot(" ldr r2,[r7,#0x58]\n");\r
+ ot(" ldr r0,[r7,#0x9c] ;@ restore cycles\n");\r
+ ot(" ldr r1,[r7,#0xa0] ;@ old CycloneEnd handler\n");\r
+ ot(" mov r9,r9,lsl #28\n");\r
+ ot(" add r5,r0,r5\n");\r
+ ot(" str r1,[r7,#0x98]\n");\r
+ ot(";@ still tracing?\n"); // exception might have happend\r
+ ot(" tst r2,#2\n");\r
+ ot(" beq TraceDisabled\n");\r
+ ot(";@ trace exception\n");\r
+#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
+ ot(" ldr r1,[r7,#0x58]\n");\r
+ ot(" mov r0,#9\n");\r
+ ot(" orr r1,r1,#4 ;@ set activity bit: 'not processing instruction'\n");\r
+ ot(" str r1,[r7,#0x58]\n");\r
+#else\r
+ ot(" mov r0,#9\n");\r
+#endif\r
+ ot(" bl Exception\n");\r
+ ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
+ ot(" subs r5,r5,#34 ;@ Subtract cycles\n");\r
+ ot(" ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
+ ot(" b CycloneEnd\n");\r
ot("\n");\r
+ ot("TraceDisabled%s\n", ms?"":":");\r
+ ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
+ ot(" cmp r5,#0\n");\r
+ ot(" ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
+ ot(" b CycloneEnd\n");\r
+ ot("\n");\r
+#endif\r
}\r
\r
// ---------------------------------------------------------------------------\r
// Call Read(r0), Write(r0,r1) or Fetch(r0)\r
// Trashes r0-r3,r12,lr\r
-int MemHandler(int type,int size,int addrreg)\r
+int MemHandler(int type,int size,int addrreg,int need_addrerr_check)\r
{\r
int func=0;\r
func=0x68+type*0xc+(size<<2); // Find correct offset\r
ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0x000000ff);\r
addrreg=0;\r
#endif\r
+\r
+#if EMULATE_ADDRESS_ERRORS_IO\r
+ if (size > 0 && need_addrerr_check)\r
+ {\r
+ ot(" add lr,pc,#4*%i\n", addrreg==0?2:3); // helps to prevent interlocks\r
+ if (addrreg != 0) ot(" mov r0,r%i\n", addrreg);\r
+ ot(" tst r0,#1 ;@ address error?\n");\r
+ switch (type) {\r
+ case 0: ot(" bne ExceptionAddressError_r_data\n"); break;\r
+ case 1: ot(" bne ExceptionAddressError_w_data\n"); break;\r
+ case 2: ot(" bne ExceptionAddressError_r_prg\n"); break;\r
+ }\r
+ }\r
+ else\r
+#endif\r
if (addrreg != 0)\r
{\r
- ot(" add lr,pc,#4\n"); // helps to prevent interlocks\r
+ ot(" add lr,pc,#4\n");\r
ot(" mov r0,r%i\n", addrreg);\r
}\r
else\r
\r
// Emit null opcode:\r
ot("Op____%s ;@ Called if an opcode is not recognised\n", ms?"":":");\r
+#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
+ ot(" ldr r1,[r7,#0x58]\n");\r
ot(" sub r4,r4,#2\n");\r
+ ot(" orr r1,r1,#4 ;@ set activity bit: 'not processing instruction'\n");\r
+ ot(" str r1,[r7,#0x58]\n");\r
+#else\r
+ ot(" sub r4,r4,#2\n");\r
+#endif\r
#if USE_UNRECOGNIZED_CALLBACK\r
ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
ot(" mov r1,r9,lsr #28\n");\r
ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
ot(" mov r9,r9,lsl #28\n");\r
ot(" tst r0,r0\n");\r
- ot(" moveq r0,#0x10\n");\r
+ ot(" moveq r0,#4\n");\r
ot(" bleq Exception\n");\r
#else\r
- ot(" mov r0,#0x10\n");\r
+ ot(" mov r0,#4\n");\r
ot(" bl Exception\n");\r
#endif\r
ot("\n");\r
ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
ot(" mov r9,r9,lsl #28\n");\r
ot(" tst r0,r0\n");\r
- ot(" moveq r0,#0x28\n");\r
+ ot(" moveq r0,#0x0a\n");\r
ot(" bleq Exception\n");\r
#else\r
- ot(" mov r0,#0x28\n");\r
+ ot(" mov r0,#0x0a\n");\r
ot(" bl Exception\n");\r
#endif\r
ot("\n");\r
ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
ot(" mov r9,r9,lsl #28\n");\r
ot(" tst r0,r0\n");\r
- ot(" moveq r0,#0x2c\n");\r
+ ot(" moveq r0,#0x0b\n");\r
ot(" bleq Exception\n");\r
#else\r
- ot(" mov r0,#0x2c\n");\r
+ ot(" mov r0,#0x0b\n");\r
ot(" bl Exception\n");\r
#endif\r
ot("\n");\r
{\r
int i;\r
char *name="Cyclone.s";\r
+ const char *globl=ms?"export":".global";\r
\r
// Open the assembly file\r
if (ms) name="Cyclone.asm";\r
for(i=0xa000; i<0xb000; i++) CyJump[i] = -2; // a-line emulation\r
for(i=0xf000; i<0x10000; i++) CyJump[i] = -3; // f-line emulation\r
\r
- if (ms)\r
- {\r
- ot(" area |.text|, code\n");\r
- ot(" export CycloneInit\n");\r
- ot(" export CycloneRun\n");\r
- ot(" export CycloneSetSr\n");\r
- ot(" export CycloneGetSr\n");\r
- ot(" export CycloneSetRealTAS\n");\r
- ot(" export CycloneVer\n");\r
- ot("\n");\r
- ot("CycloneVer dcd 0x%.4x\n",CycloneVer);\r
- }\r
- else\r
- {\r
- ot(" .global CycloneInit\n");\r
- ot(" .global CycloneRun\n");\r
- ot(" .global CycloneSetSr\n");\r
- ot(" .global CycloneGetSr\n");\r
- ot(" .global CycloneVer\n");\r
+ ot(ms?" area |.text|, code\n":" .text\n .align 4\n\n");\r
+ ot(" %s CycloneInit\n",globl);\r
+ ot(" %s CycloneRun\n",globl);\r
+ ot(" %s CycloneSetSr\n",globl);\r
+ ot(" %s CycloneGetSr\n",globl);\r
+ ot(" %s CycloneFlushIrq\n",globl);\r
+ ot(" %s CyclonePack\n",globl);\r
+ ot(" %s CycloneUnpack\n",globl);\r
+ ot(" %s CycloneVer\n",globl);\r
#if (CYCLONE_FOR_GENESIS == 2)\r
- ot(" .global CycloneSetRealTAS\n");\r
- ot(" .global CycloneDoInterrupt\n");\r
- ot(" .global CycloneJumpTab\n");\r
+ ot(" %s CycloneSetRealTAS\n",globl);\r
+ ot(" %s CycloneDoInterrupt\n",globl);\r
+ ot(" %s CycloneDoTrace\n",globl);\r
+ ot(" %s CycloneJumpTab\n",globl);\r
#endif\r
- ot("CycloneVer: .long 0x%.4x\n",CycloneVer);\r
- }\r
+ ot("\n");\r
+ ot(ms?"CycloneVer dcd 0x":"CycloneVer: .long 0x");\r
+ ot("%.4x\n",CycloneVer);\r
ot("\n");\r
\r
PrintFramework();\r
\r
#include "app.h"\r
\r
+int opend_op_changes_cycles, opend_check_interrupt, opend_check_trace;\r
+\r
static unsigned char OpData[16]={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};\r
\r
static unsigned short CPU_CALL OpRead16(unsigned int a)\r
if (last_op_count!=arm_op_count)\r
ot("\n");\r
pc_dirty = 1;\r
+ opend_op_changes_cycles = opend_check_interrupt = opend_check_trace = 0;\r
}\r
\r
-void OpEnd(int sea, int tea, int op_changes_cycles, int check_interrupt)\r
+void OpEnd(int sea, int tea)\r
{\r
int did_fetch=0;\r
+ opend_check_trace = opend_check_trace && EMULATE_TRACE;\r
#if MEMHANDLERS_CHANGE_CYCLES\r
if ((sea >= 0x10 && sea != 0x3c) || (tea >= 0x10 && tea != 0x3c))\r
{\r
- if (op_changes_cycles)\r
+ if (opend_op_changes_cycles)\r
{\r
ot(" ldr r0,[r7,#0x5c] ;@ Load Cycles\n");\r
ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
#endif\r
if (!did_fetch)\r
ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
+ if (opend_check_trace)\r
+ ot(" ldr r1,[r7,#0x44]\n");\r
ot(" subs r5,r5,#%d ;@ Subtract cycles\n",Cycles);\r
- if (check_interrupt)\r
+ if (opend_check_trace)\r
+ {\r
+ ot(";@ CheckTrace:\n");\r
+ ot(" tst r1,#0x80\n");\r
+ ot(" bne CycloneDoTraceWithChecks\n");\r
+ ot(" cmp r5,#0\n");\r
+ }\r
+ if (opend_check_interrupt)\r
{\r
ot(" blt CycloneEnd\n");\r
ot(";@ CheckInterrupt:\n");\r
- ot(" ldr r1,[r7,#0x44] ;@ Get SR high T_S__III and irq level\n");\r
+ if (!opend_check_trace)\r
+ ot(" ldr r1,[r7,#0x44]\n");\r
ot(" movs r0,r1,lsr #24 ;@ Get IRQ level\n"); // same as ldrb r0,[r7,#0x47]\r
ot(" ldreq pc,[r6,r8,asl #2] ;@ Jump to next opcode handler\n");\r
ot(" cmp r0,#6 ;@ irq>6 ?\n");\r
if (type==0) // div\r
{\r
ot("divzero%.4x%s\n",op,ms?"":":");\r
- ot(" mov r0,#0x14 ;@ Divide by zero\n");\r
+ ot(" mov r0,#5 ;@ Divide by zero\n");\r
ot(" bl Exception\n");\r
Cycles+=38;\r
OpEnd(ea);\r
\r
// EA calculation order defines how situations like suba.w (A0)+, A0 get handled.\r
// different emus act differently in this situation, I couldn't fugure which is right behaviour.\r
- if (/*type == */1)\r
+ //if (type == 1)\r
{\r
EaCalcReadNoSE(-1,0,sea,size,0x003f);\r
EaCalcReadNoSE(type!=1?10:-1,11,dea,2,0x0e00);\r
}\r
+#if 0\r
else\r
{\r
EaCalcReadNoSE(type!=1?10:-1,11,dea,2,0x0e00);\r
EaCalcReadNoSE(-1,0,sea,size,0x003f);\r
}\r
+#endif\r
\r
if (size<2) ot(" mov r0,r0,asl #%d\n\n",size?16:24);\r
if (size<2) asr=(char *)(size?",asr #16":",asr #24");\r
OpEnd(ea);\r
\r
ot("chktrap%.4x%s ;@ CHK exception:\n",op,ms?"":":");\r
- ot(" mov r0,#0x18\n");\r
+ ot(" mov r0,#6\n");\r
ot(" bl Exception\n");\r
Cycles+=40;\r
OpEnd(ea);\r
\r
#include "app.h"\r
\r
-static void CheckPc(int reg)\r
+// in/out address in r0, trashes all temp regs\r
+static void CheckPc(void)\r
{\r
#if USE_CHECKPC_CALLBACK\r
- ot(";@ Check Memory Base+pc (r%i)\n",reg);\r
- if (reg != 0)\r
- ot(" mov r0,r%i\n", reg);\r
+ ot(";@ Check Memory Base+pc\n");\r
ot(" mov lr,pc\n");\r
ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
- ot(" mov r4,r0\n");\r
-#else\r
- ot(" bic r4,r%d,#1\n",reg); // we do not emulate address errors\r
-#endif\r
ot("\n");\r
+#endif\r
}\r
\r
// Push 32-bit value in r1 - trashes r0-r3,r12,lr\r
MemHandler(0,2);\r
ot(" add r0,r0,r10 ;@ Memory Base+PC\n");\r
ot("\n");\r
- CheckPc(0);\r
+ CheckPc();\r
+#if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" mov r4,r0\n");\r
+#else\r
+ ot(" bic r4,r0,#1\n");\r
+#endif\r
}\r
\r
int OpTrap(int op)\r
\r
OpStart(op,0x10);\r
ot(" and r0,r8,#0xf ;@ Get trap number\n");\r
- ot(" orr r0,r0,#0x20\n");\r
- ot(" mov r0,r0,asl #2\n");\r
+ ot(" orr r0,r0,#0x20 ;@ 32+n\n");\r
ot(" bl Exception\n");\r
ot("\n");\r
\r
PopSr(1);\r
ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
PopPc();\r
- SuperChange(op);\r
- OpEnd(0x10,0,0,1);\r
+ ot(" ldr r1,[r7,#0x44] ;@ reload SR high\n");\r
+ SuperChange(op,1);\r
+#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO || EMULATE_HALT\r
+ ot(" ldr r1,[r7,#0x58]\n");\r
+ ot(" bic r1,r1,#0x0c ;@ clear 'not processing instruction' and 'doing addr error' bits\n");\r
+ ot(" str r1,[r7,#0x58]\n");\r
+#endif\r
+#if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" tst r4,#1 ;@ address error?\n");\r
+ ot(" bne ExceptionAddressError_r_prg_r4\n");\r
+#endif\r
+ opend_check_interrupt = 1;\r
+ opend_check_trace = 1;\r
+ OpEnd(0x10,0);\r
return 0;\r
\r
case 5: // rts\r
OpStart(op,0x10); Cycles=16;\r
ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
PopPc();\r
+#if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" tst r4,#1 ;@ address error?\n");\r
+ ot(" bne ExceptionAddressError_r_prg_r4\n");\r
+#endif\r
OpEnd(0x10);\r
return 0;\r
\r
OpStart(op,0x10,0,1); Cycles=4;\r
ot(" tst r9,#0x10000000\n");\r
ot(" subne r5,r5,#%i\n",34);\r
- ot(" movne r0,#0x1c ;@ TRAPV exception\n");\r
+ ot(" movne r0,#7 ;@ TRAPV exception\n");\r
ot(" blne Exception\n");\r
- OpEnd(0x10,0,1);\r
+ opend_op_changes_cycles = 1;\r
+ OpEnd(0x10,0);\r
return 0;\r
\r
case 7: // rtr\r
PopSr(0);\r
ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
PopPc();\r
+#if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" tst r4,#1 ;@ address error?\n");\r
+ ot(" bne ExceptionAddressError_r_prg_r4\n");\r
+#endif\r
OpEnd(0x10);\r
return 0;\r
\r
ot("\n");\r
EaCalc(11,0x003f,sea,0);\r
\r
+ ot(";@ Jump - Get new PC from r11\n");\r
+ ot(" add r0,r11,r10 ;@ Memory Base + New PC\n");\r
+ ot("\n");\r
+ CheckPc();\r
if (!(op&0x40))\r
{\r
- ot(";@ Jsr - Push old PC first\n");\r
- ot(" ldr r0,[r7,#0x3c]\n");\r
+ ot(" ldr r2,[r7,#0x3c]\n");\r
ot(" sub r1,r4,r10 ;@ r1 = Old PC\n");\r
- ot(";@ Push r1 onto stack\n");\r
- ot(" sub r0,r0,#4 ;@ Predecrement A7\n");\r
+ }\r
+#if EMULATE_ADDRESS_ERRORS_JUMP\r
+ // jsr prefetches next instruction before pushing old PC,\r
+ // according to http://pasti.fxatari.com/68kdocs/68kPrefetch.html\r
+ ot(" mov r4,r0\n");\r
+ ot(" tst r4,#1 ;@ address error?\n");\r
+ ot(" bne ExceptionAddressError_r_prg_r4\n");\r
+#else\r
+ ot(" bic r4,r0,#1\n");\r
+#endif\r
+\r
+ if (!(op&0x40))\r
+ {\r
+ ot(";@ Push old PC onto stack\n");\r
+ ot(" sub r0,r2,#4 ;@ Predecrement A7\n");\r
ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
MemHandler(1,2);\r
}\r
- ot(";@ Jump - Get new PC from r11\n");\r
- ot(" add r0,r11,r10 ;@ Memory Base + New PC\n");\r
- ot("\n");\r
-\r
- CheckPc(0);\r
\r
Cycles=(op&0x40) ? 4 : 12;\r
Cycles+=Ea_add_ns((op&0x40) ? g_jmp_cycle_table : g_jsr_cycle_table, sea);\r
ot(";@ Check if Dn.w is -1\n");\r
ot(" cmn r0,#1\n");\r
\r
-#if USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA\r
+#if (USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA) || EMULATE_ADDRESS_ERRORS_JUMP\r
ot(" beq DbraMin1\n");\r
ot("\n");\r
\r
ot(";@ Get Branch offset:\n");\r
ot(" ldrsh r0,[r4]\n");\r
- ot(" add r0,r4,r0 ;@ r4 = New PC\n");\r
- CheckPc(0);\r
+ ot(" add r0,r4,r0 ;@ r0 = New PC\n");\r
+ CheckPc();\r
+#if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" mov r4,r0\n");\r
+ ot(" tst r4,#1 ;@ address error?\n");\r
+ ot(" bne ExceptionAddressError_r_prg_r4\n");\r
+#else\r
+ ot(" bic r4,r0,#1\n");\r
+#endif\r
#else\r
ot("\n");\r
ot(";@ Get Branch offset:\n");\r
OpEnd();\r
}\r
\r
-#if USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA\r
+#if (USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA) || EMULATE_ADDRESS_ERRORS_JUMP\r
if (op==0x51c8)\r
{\r
ot(";@ Dn.w is -1:\n");\r
#if USE_CHECKPC_CALLBACK\r
if (offset==-1) checkpc=1;\r
#endif\r
- if (checkpc)\r
- {\r
- CheckPc(0);\r
- }\r
- else\r
- {\r
- ot(" bic r4,r0,#1\n"); // we do not emulate address errors\r
- ot("\n");\r
- }\r
+ if (checkpc) CheckPc();\r
+#if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" mov r4,r0\n");\r
+ ot(" tst r4,#1 ;@ address error?\n");\r
+ ot(" bne ExceptionAddressError_r_prg_r4\n");\r
+#else\r
+ ot(" bic r4,r0,#1\n");\r
+#endif\r
+ ot("\n");\r
\r
OpEnd(size?0x10:0);\r
\r
ot("\n");\r
}\r
\r
+ if (type==1) eawrite_check_addrerr=1;\r
EaWrite(10, 1,ea,size,0x003f,0,0);\r
\r
OpEnd(ea);\r
\r
ot("\n");\r
\r
+ eawrite_check_addrerr=1;\r
EaCalc (0,0x003f, ea,size,0,0);\r
EaWrite(0, 1, ea,size,0x003f,0,0);\r
\r
- OpEnd(ea,0,changed_cycles);\r
+ opend_op_changes_cycles=changed_cycles;\r
+ OpEnd(ea,0);\r
return 0;\r
}\r
\r
\r
EaWrite(10, 0, ea,size,0x0007,1);\r
\r
- OpEnd(ea,0,count<0);\r
+ opend_op_changes_cycles = (count<0);\r
+ OpEnd(ea,0);\r
\r
return 0;\r
}\r
\r
// Convert SR/CRR register in r0 to our flags\r
// trashes r0,r1\r
-void OpRegToFlags(int high)\r
+void OpRegToFlags(int high, int srh_reg)\r
{\r
ot(" eor r1,r0,r0,ror #1 ;@ Bit 0=C^V\n");\r
ot(" mov r2,r0,lsl #25\n");\r
\r
if (high)\r
{\r
- ot(" mov r0,r0,ror #8\n");\r
- ot(" and r0,r0,#0xa7 ;@ only take defined bits\n");\r
- ot(" strb r0,[r7,#0x44] ;@ Store SR high\n");\r
+ int mask=EMULATE_TRACE?0xa7:0x27;\r
+ ot(" mov r%i,r0,ror #8\n",srh_reg);\r
+ ot(" and r%i,r%i,#0x%02x ;@ only take defined bits\n",srh_reg,srh_reg,mask);\r
+ ot(" strb r%i,[r7,#0x44] ;@ Store SR high\n",srh_reg);\r
}\r
ot("\n");\r
}\r
ot(";@ ----------\n");\r
ot(";@ tried execute privileged instruction in user mode\n");\r
ot("WrongPrivilegeMode%s\n",ms?"":":");\r
+#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
+ ot(" ldr r1,[r7,#0x58]\n");\r
ot(" sub r4,r4,#2 ;@ last opcode wasn't executed - go back\n");\r
- ot(" mov r0,#0x20 ;@ privilege violation\n");\r
+ ot(" orr r1,r1,#4 ;@ set activity bit: 'not processing instruction'\n");\r
+ ot(" str r1,[r7,#0x58]\n");\r
+#else\r
+ ot(" sub r4,r4,#2 ;@ last opcode wasn't executed - go back\n");\r
+#endif\r
+ ot(" mov r0,#8 ;@ privilege violation\n");\r
ot(" bl Exception\n");\r
Cycles=34;\r
OpEnd(0);\r
\r
// does OSP and A7 swapping if needed\r
// new or old SR (not the one already in [r7,#0x44]) should be passed in r11\r
-// trashes r0,r11\r
-void SuperChange(int op,int load_srh)\r
+// uses srh from srh_reg (loads if < 0), trashes r0,r11\r
+void SuperChange(int op,int srh_reg)\r
{\r
ot(";@ A7 <-> OSP?\n");\r
- if (load_srh)\r
+ if (srh_reg < 0) {\r
ot(" ldr r0,[r7,#0x44] ;@ Get other SR high\n");\r
- ot(" eor r0,r0,r11\n");\r
+ srh_reg=0;\r
+ }\r
+ ot(" eor r0,r%i,r11\n",srh_reg);\r
ot(" tst r0,#0x20\n");\r
ot(" beq no_sp_swap%.4x\n",op);\r
ot(" ;@ swap OSP and A7:\n");\r
\r
if (movea) size=2; // movea always expands to 32-bits\r
\r
+ eawrite_check_addrerr=1;\r
#if SPLIT_MOVEL_PD\r
if ((tea&0x38)==0x20 && size==2) { // -(An)\r
EaCalc (10,0x0e00,tea,size,0,0);\r
\r
OpStart(op,sea,tea);\r
\r
+ eawrite_check_addrerr=1;\r
EaCalc (1,0x003f,sea,0); // Lea\r
EaCalc (0,0x0e00,tea,2);\r
EaWrite(0, 1,tea,2,0x0e00);\r
\r
if (type==0 || type==1)\r
{\r
+ eawrite_check_addrerr=1;\r
OpFlagsToReg(type==0);\r
EaCalc (0,0x003f,ea,size,0,0);\r
EaWrite(0, 1,ea,size,0x003f,0,0);\r
if (type==2 || type==3)\r
{\r
EaCalcReadNoSE(-1,0,ea,size,0x003f);\r
- OpRegToFlags(type==3);\r
+ OpRegToFlags(type==3,1);\r
if (type==3) {\r
- SuperChange(op,0);\r
+ SuperChange(op,1);\r
+ opend_check_interrupt = 1;\r
+ opend_check_trace = 1;\r
+ OpEnd(ea);\r
+ return 0;\r
}\r
}\r
\r
- OpEnd(ea,0,0,type==3);\r
+ OpEnd(ea);\r
\r
return 0;\r
}\r
{\r
int type=0,ea=0;\r
int use=0,size=0;\r
+ int sr_mask=EMULATE_TRACE?0xa7:0x27;\r
\r
type=(op>>9)&5; if (type==4) return 1;\r
size=(op>>6)&1; // ccr or sr?\r
\r
OpStart(op,ea,0,0,size!=0); Cycles=16;\r
\r
- EaCalc(10,0x003f,ea,size);\r
- EaRead(10, 10,ea,size,0x003f);\r
+ EaCalcRead(-1,0,ea,size,0x003f);\r
\r
- OpFlagsToReg(size);\r
- if (type==0) ot(" orr r0,r1,r10\n");\r
- if (type==1) ot(" and r0,r1,r10\n");\r
- if (type==5) ot(" eor r0,r1,r10\n");\r
- OpRegToFlags(size);\r
- if (size && type!=0) { // we can't enter supervisor mode, nor unmask irqs just by using OR\r
- SuperChange(op,0);\r
+ ot(" eor r1,r0,r0,ror #1 ;@ Bit 0=C^V\n");\r
+ ot(" tst r1,#1 ;@ 1 if C!=V\n");\r
+ ot(" eorne r0,r0,#3 ;@ ___XNZCV\n");\r
+ ot(" ldr r2,[r7,#0x4c] ;@ Load old X bit\n");\r
+\r
+ // note: old srh is already in r11 (done by OpStart)\r
+ if (type==0) {\r
+ ot(" orr r9,r9,r0,lsl #28\n");\r
+ ot(" orr r2,r2,r0,lsl #25 ;@ X bit\n");\r
+ if (size!=0) {\r
+ ot(" orr r1,r11,r0,lsr #8\n");\r
+ ot(" and r1,r1,#0x%02x ;@ mask-out unused bits\n",sr_mask);\r
+ }\r
+ }\r
+ if (type==1) {\r
+ ot(" and r9,r9,r0,lsl #28\n");\r
+ ot(" and r2,r2,r0,lsl #25 ;@ X bit\n");\r
+ if (size!=0)\r
+ ot(" and r1,r11,r0,lsr #8\n");\r
+ }\r
+ if (type==5) {\r
+ ot(" eor r9,r9,r0,lsl #28\n");\r
+ ot(" eor r2,r2,r0,lsl #25 ;@ X bit\n");\r
+ if (size!=0) {\r
+ ot(" eor r1,r11,r0,lsr #8\n");\r
+ ot(" and r1,r1,#0x%02x ;@ mask-out unused bits\n",sr_mask);\r
+ }\r
}\r
\r
- OpEnd(ea,0,0,size!=0 && type!=0);\r
+ ot(" str r2,[r7,#0x4c] ;@ Save X bit\n");\r
+ if (size!=0)\r
+ ot(" strb r1,[r7,#0x44]\n");\r
+ ot("\n");\r
+\r
+ // we can't enter supervisor mode, nor unmask irqs just by using OR\r
+ if (size!=0 && type!=0) {\r
+ SuperChange(op,1);\r
+ ot("\n");\r
+ opend_check_interrupt = 1;\r
+ }\r
+ // also can't set trace bit with AND\r
+ if (size!=0 && type!=1)\r
+ opend_check_trace = 1;\r
+\r
+ OpEnd(ea);\r
\r
return 0;\r
}\r
ot(" tst r11,r11\n"); // sanity check\r
ot(" beq NoRegs%.4x\n",op);\r
\r
+#if EMULATE_ADDRESS_ERRORS_IO\r
+ ot("\n");\r
+ ot(" tst r6,#1 ;@ address error?\n");\r
+ ot(" movne r0,r6\n");\r
+ ot(" bne ExceptionAddressError_%c_data\n",dir?'r':'w');\r
+#endif\r
+\r
ot("\n");\r
ot("Movemloop%.4x%s\n",op, ms?"":":");\r
ot(" add r10,r10,#%d ;@ r10=Next Register\n",decr?-4:4);\r
if (dir)\r
{\r
ot(" ;@ Copy memory to register:\n",1<<size);\r
+ earead_check_addrerr=0; // already checked\r
EaRead (6,0,ea,size,0x003f);\r
ot(" str r0,[r7,r10] ;@ Save value into Dn/An\n");\r
}\r
\r
Cycles+=Ea_add_ns(g_movem_cycle_table,ea);\r
\r
- OpEnd(ea,0,1);\r
+ opend_op_changes_cycles = 1;\r
+ OpEnd(ea);\r
ltorg();\r
ot("\n");\r
\r
\r
if (dir)\r
{\r
+ eawrite_check_addrerr=1;\r
ot(" ldr r1,[r7,#0x48] ;@ Get from USP\n\n");\r
EaCalc (0,0x000f,8,2,1);\r
EaWrite(0, 1,8,2,0x000f,1);\r
\r
ot("\n");\r
\r
- ot(" mov r0,#1\n");\r
- ot(" str r0,[r7,#0x58] ;@ stopped\n");\r
+ ot(" ldr r0,[r7,#0x58]\n");\r
+ ot(" mov r5,#0 ;@ eat cycles\n");\r
+ ot(" orr r0,r0,#1 ;@ stopped\n");\r
+ ot(" str r0,[r7,#0x58]\n");\r
ot("\n");\r
\r
- ot(" mov r5,#0 ;@ eat cycles\n");\r
Cycles = 4;\r
ot("\n");\r
}\r
#include <stdlib.h>\r
#include <string.h>\r
\r
-#include "config.h"\r
+#ifndef CONFIG_FILE\r
+#define CONFIG_FILE "config.h"\r
+#endif\r
+#include CONFIG_FILE\r
\r
// Disa.c\r
#include "Disa/Disa.h"\r
\r
// Ea.cpp\r
+extern int earead_check_addrerr;\r
+extern int eawrite_check_addrerr;\r
extern int g_jmp_cycle_table[];\r
extern int g_jsr_cycle_table[];\r
extern int g_lea_cycle_table[];\r
extern int arm_op_count; // for stats\r
void ot(const char *format, ...);\r
void ltorg();\r
-int MemHandler(int type,int size,int addrreg=0);\r
+int MemHandler(int type,int size,int addrreg=0,int need_addrerr_check=1);\r
void FlushPC(void);\r
\r
// OpAny.cpp\r
extern int g_op;\r
+extern int opend_op_changes_cycles, opend_check_interrupt, opend_check_trace;\r
int OpGetFlags(int subtract,int xbit,int sprecialz=0);\r
void OpUse(int op,int use);\r
void OpStart(int op,int sea=0,int tea=0,int op_changes_cycles=0,int supervisor_check=0);\r
-void OpEnd(int sea=0,int tea=0,int op_changes_cycles=0,int check_interrupt=0);\r
+void OpEnd(int sea=0,int tea=0);\r
int OpBase(int op,int size,int sepa=0);\r
void OpAny(int op);\r
\r
int OpMove(int op);\r
int OpLea(int op);\r
void OpFlagsToReg(int high);\r
-void OpRegToFlags(int high);\r
+void OpRegToFlags(int high,int srh_reg=0);\r
int OpMoveSr(int op);\r
int OpArithSr(int op);\r
int OpPea(int op);\r
int OpMovep(int op);\r
int OpStopReset(int op);\r
void SuperEnd(void);\r
-void SuperChange(int op,int load_srh=1);\r
+void SuperChange(int op,int srh_reg=-1);\r
\r
\r
\r
/*\r
- * If this option is enabled, Microsoft ARMASM compatible output is generated.\r
- * Otherwise GNU as syntax is used.\r
+ * If this option is enabled, Microsoft ARMASM compatible output is generated\r
+ * (output file - Cyclone.asm). Otherwise GNU as syntax is used (Cyclone.s).\r
*/\r
-#define USE_MS_SYNTAX 0\r
+#define USE_MS_SYNTAX 0\r
\r
/*\r
* Enable this option if you are going to use Cyclone to emulate Genesis /\r
* the write-back phase. That will be emulated, if this option is enabled.\r
* This option also alters timing slightly.\r
*/\r
-#define CYCLONE_FOR_GENESIS 0\r
+#define CYCLONE_FOR_GENESIS 0\r
\r
/*\r
* This option compresses Cyclone's jumptable. Because of this the executable\r
* Warning: if you enable this, you MUST call CycloneInit() before calling\r
* CycloneRun(), or else it will crash.\r
*/\r
-#define COMPRESS_JUMPTABLE 1\r
+#define COMPRESS_JUMPTABLE 1\r
\r
/*\r
* Address mask for memory hadlers. The bits set will be masked out of address\r
* Using 0xff000000 means that only 24 least significant bits should be used.\r
* Set to 0 if you want to mask unused address bits in the memory handlers yourself.\r
*/\r
-#define MEMHANDLERS_ADDR_MASK 0\r
+#define MEMHANDLERS_ADDR_MASK 0\r
\r
/*\r
* Cyclone keeps the 4 least significant bits of SR, PC+membase and it's cycle\r
- * count in ARM registers instead of the context for performance reasons. If you for\r
+ * counter in ARM registers instead of the context for performance reasons. If you for\r
* any reason need to access them in your memory handlers, enable the options below,\r
* otherwise disable them to improve performance.\r
+ *\r
* MEMHANDLERS_NEED_PC updates .pc context field with PC value effective at the time\r
- * when memhandler was called (opcode address + unknown amount).\r
+ * when memhandler was called (opcode address + 2-10 bytes).\r
* MEMHANDLERS_NEED_PREV_PC updates .prev_pc context field to currently executed\r
* opcode address + 2.\r
* Note that .pc and .prev_pc values are always real pointers to memory, so you must\r
* subtract .membase to get M68k PC value.\r
+ *\r
* Warning: updating PC in memhandlers is dangerous, as Cyclone may internally\r
* increment the PC before fetching the next instruction and continue executing\r
- * at wrong location.\r
+ * at wrong location. It's better to wait until Cyclone CycloneRun() finishes.\r
+ *\r
+ * Warning: if you enable MEMHANDLERS_CHANGE_CYCLES, you must also enable\r
+ * MEMHANDLERS_NEED_CYCLES, or else Cyclone will keep reloading the same cycle\r
+ * count and this will screw timing (if not cause a deadlock).\r
*/\r
-#define MEMHANDLERS_NEED_PC 1\r
-#define MEMHANDLERS_NEED_PREV_PC 0\r
-#define MEMHANDLERS_NEED_FLAGS 0\r
-#define MEMHANDLERS_NEED_CYCLES 1\r
-#define MEMHANDLERS_CHANGE_PC 0\r
-#define MEMHANDLERS_CHANGE_FLAGS 0\r
-#define MEMHANDLERS_CHANGE_CYCLES 1\r
+#define MEMHANDLERS_NEED_PC 0\r
+#define MEMHANDLERS_NEED_PREV_PC 0\r
+#define MEMHANDLERS_NEED_FLAGS 0\r
+#define MEMHANDLERS_NEED_CYCLES 0\r
+#define MEMHANDLERS_CHANGE_PC 0\r
+#define MEMHANDLERS_CHANGE_FLAGS 0\r
+#define MEMHANDLERS_CHANGE_CYCLES 0\r
\r
/*\r
- * If enabled, Cyclone will call IrqCallback routine from it's context whenever it\r
- * acknowledges an IRQ. IRQ level is not cleared automatically, do this in your\r
- * hadler if needed. PC, flags and cycles are valid in the context and can be read.\r
- * If disabled, it simply clears the IRQ level and continues execution.\r
+ * If enabled, Cyclone will call .IrqCallback routine from it's context whenever it\r
+ * acknowledges an IRQ. IRQ level (.irq) is not cleared automatically, do this in your\r
+ * handler if needed.\r
+ * This function must either return vector number to use for interrupt exception,\r
+ * CYCLONE_INT_ACK_AUTOVECTOR to use autovector (this is the most common case), or\r
+ * CYCLONE_INT_ACK_SPURIOUS (least common case).\r
+ * If disabled, it simply uses appropriate autovector, clears the IRQ level and\r
+ * continues execution.\r
*/\r
-#define USE_INT_ACK_CALLBACK 1\r
+#define USE_INT_ACK_CALLBACK 0\r
\r
/*\r
- * Enable this if you need/change PC, flags or cycles in your IrqCallback function.\r
+ * Enable this if you need old PC, flags or cycles;\r
+ * or you change cycles in your IrqCallback function.\r
*/\r
-#define INT_ACK_NEEDS_STUFF 0\r
-#define INT_ACK_CHANGES_STUFF 0\r
+#define INT_ACK_NEEDS_STUFF 0\r
+#define INT_ACK_CHANGES_CYCLES 0\r
\r
/*\r
- * If enabled, ResetCallback is called from the context, whenever RESET opcode is\r
+ * If enabled, .ResetCallback is called from the context, whenever RESET opcode is\r
* encountered. All context members are valid and can be changed.\r
* If disabled, RESET opcode acts as an NOP.\r
*/\r
-#define USE_RESET_CALLBACK 0\r
+#define USE_RESET_CALLBACK 0\r
\r
/*\r
* If enabled, UnrecognizedCallback is called if an invalid opcode is\r
* If disabled, "Illegal Instruction" exception is generated and execution is\r
* continued.\r
*/\r
-#define USE_UNRECOGNIZED_CALLBACK 1\r
+#define USE_UNRECOGNIZED_CALLBACK 0\r
\r
/*\r
* This option will also call UnrecognizedCallback for a-line and f-line\r
* (0xa*** and 0xf***) opcodes the same way as described above, only appropriate\r
* exceptions will be generated.\r
*/\r
-#define USE_AFLINE_CALLBACK 1\r
+#define USE_AFLINE_CALLBACK 0\r
\r
/*\r
* This makes Cyclone to call checkpc from it's context whenever it changes the PC\r
* by a large value. It takes and should return the PC value in PC+membase form.\r
* The flags and cycle counter are not valid in this function.\r
*/\r
-#define USE_CHECKPC_CALLBACK 1\r
+#define USE_CHECKPC_CALLBACK 1\r
\r
/*\r
* This determines if checkpc() should be called after jumps when 8 and 16 bit\r
* displacement values were used.\r
*/\r
-#define USE_CHECKPC_OFFSETBITS_16 1\r
-#define USE_CHECKPC_OFFSETBITS_8 0\r
+#define USE_CHECKPC_OFFSETBITS_16 1\r
+#define USE_CHECKPC_OFFSETBITS_8 0\r
\r
/*\r
* Call checkpc() after DBcc jumps (which use 16bit displacement). Cyclone prior to\r
* 0.0087 never did that.\r
*/\r
-#define USE_CHECKPC_DBRA 0\r
+#define USE_CHECKPC_DBRA 0\r
\r
/*\r
* When this option is enabled Cyclone will do two word writes instead of one\r
* Bart Trzynadlowski's doc (http://www.trzy.org/files/68knotes.txt).\r
* Enable this if you are emulating a 16 bit system.\r
*/\r
-#define SPLIT_MOVEL_PD 1\r
+#define SPLIT_MOVEL_PD 1\r
+\r
+/*\r
+ * Enable emulation of trace mode. Shouldn't cause any performance decrease, so it\r
+ * should be safe to keep this ON.\r
+ */\r
+#define EMULATE_TRACE 1\r
+\r
+/*\r
+ * If enabled, address error exception will be generated if 68k code jumps to an\r
+ * odd address. Causes very small performance hit (2 ARM instructions for every\r
+ * emulated jump/return/exception in normal case).\r
+ * Note: checkpc() must not clear least significant bit of rebased address\r
+ * for this to work, as checks are performed after calling checkpc().\r
+ */\r
+#define EMULATE_ADDRESS_ERRORS_JUMP 1\r
+\r
+/*\r
+ * If enabled, address error exception will be generated if 68k code tries to\r
+ * access a word or longword at an odd address. The performance cost is also 2 ARM\r
+ * instructions per access (for address error checks).\r
+ */\r
+#define EMULATE_ADDRESS_ERRORS_IO 0\r
+\r
+/*\r
+ * If an address error happens during another address error processing,\r
+ * the processor halts until it is reset (catastrophic system failure, as the manual\r
+ * states). This option enables halt emulation.\r
+ * Note that this might be not desired if it is known that emulated system should\r
+ * never reach this state.\r
+ */\r
+#define EMULATE_HALT 0\r
+\r
--- /dev/null
+\r
+\r
+/**\r
+ * Cyclone 68000 configuration file\r
+**/\r
+\r
+\r
+/*\r
+ * If this option is enabled, Microsoft ARMASM compatible output is generated\r
+ * (output file - Cyclone.asm). Otherwise GNU as syntax is used (Cyclone.s).\r
+ */\r
+#define USE_MS_SYNTAX 0\r
+\r
+/*\r
+ * Enable this option if you are going to use Cyclone to emulate Genesis /\r
+ * Mega Drive system. As VDP chip in these systems had control of the bus,\r
+ * several instructions were acting differently, for example TAS did'n have\r
+ * the write-back phase. That will be emulated, if this option is enabled.\r
+ * This option also alters timing slightly.\r
+ */\r
+#define CYCLONE_FOR_GENESIS 0\r
+\r
+/*\r
+ * This option compresses Cyclone's jumptable. Because of this the executable\r
+ * will be smaller and load slightly faster and less relocations will be needed.\r
+ * This also fixes the crash problem with 0xfffe and 0xffff opcodes.\r
+ * Warning: if you enable this, you MUST call CycloneInit() before calling\r
+ * CycloneRun(), or else it will crash.\r
+ */\r
+#define COMPRESS_JUMPTABLE 1\r
+\r
+/*\r
+ * Address mask for memory hadlers. The bits set will be masked out of address\r
+ * parameter, which is passed to r/w memory handlers.\r
+ * Using 0xff000000 means that only 24 least significant bits should be used.\r
+ * Set to 0 if you want to mask unused address bits in the memory handlers yourself.\r
+ */\r
+#define MEMHANDLERS_ADDR_MASK 0xff000000\r
+\r
+/*\r
+ * Cyclone keeps the 4 least significant bits of SR, PC+membase and it's cycle\r
+ * counter in ARM registers instead of the context for performance reasons. If you for\r
+ * any reason need to access them in your memory handlers, enable the options below,\r
+ * otherwise disable them to improve performance.\r
+ *\r
+ * MEMHANDLERS_NEED_PC updates .pc context field with PC value effective at the time\r
+ * when memhandler was called (opcode address + 2-10 bytes).\r
+ * MEMHANDLERS_NEED_PREV_PC updates .prev_pc context field to currently executed\r
+ * opcode address + 2.\r
+ * Note that .pc and .prev_pc values are always real pointers to memory, so you must\r
+ * subtract .membase to get M68k PC value.\r
+ *\r
+ * Warning: updating PC in memhandlers is dangerous, as Cyclone may internally\r
+ * increment the PC before fetching the next instruction and continue executing\r
+ * at wrong location. It's better to wait until Cyclone CycloneRun() finishes.\r
+ *\r
+ * Warning: if you enable MEMHANDLERS_CHANGE_CYCLES, you must also enable\r
+ * MEMHANDLERS_NEED_CYCLES, or else Cyclone will keep reloading the same cycle\r
+ * count and this will screw timing (if not cause a deadlock).\r
+ */\r
+#define MEMHANDLERS_NEED_PC 1\r
+#define MEMHANDLERS_NEED_PREV_PC 1\r
+#define MEMHANDLERS_NEED_FLAGS 0\r
+#define MEMHANDLERS_NEED_CYCLES 1\r
+#define MEMHANDLERS_CHANGE_PC 0\r
+#define MEMHANDLERS_CHANGE_FLAGS 0\r
+#define MEMHANDLERS_CHANGE_CYCLES 1\r
+\r
+/*\r
+ * If enabled, Cyclone will call .IrqCallback routine from it's context whenever it\r
+ * acknowledges an IRQ. IRQ level (.irq) is not cleared automatically, do this in your\r
+ * handler if needed.\r
+ * This function must either return vector number to use for interrupt exception,\r
+ * CYCLONE_INT_ACK_AUTOVECTOR to use autovector (this is the most common case), or\r
+ * CYCLONE_INT_ACK_SPURIOUS (least common case).\r
+ * If disabled, it simply uses appropriate autovector, clears the IRQ level and\r
+ * continues execution.\r
+ */\r
+#define USE_INT_ACK_CALLBACK 1\r
+\r
+/*\r
+ * Enable this if you need old PC, flags or cycles;\r
+ * or you change cycles in your IrqCallback function.\r
+ */\r
+#define INT_ACK_NEEDS_STUFF 0\r
+#define INT_ACK_CHANGES_CYCLES 0\r
+\r
+/*\r
+ * If enabled, .ResetCallback is called from the context, whenever RESET opcode is\r
+ * encountered. All context members are valid and can be changed.\r
+ * If disabled, RESET opcode acts as an NOP.\r
+ */\r
+#define USE_RESET_CALLBACK 0\r
+\r
+/*\r
+ * If enabled, UnrecognizedCallback is called if an invalid opcode is\r
+ * encountered. All context members are valid and can be changed. The handler\r
+ * should return zero if you want Cyclone to gererate "Illegal Instruction"\r
+ * exception after this, or nonzero if not. In the later case you should change\r
+ * the PC by yourself, or else Cyclone will keep executing that opcode all over\r
+ * again.\r
+ * If disabled, "Illegal Instruction" exception is generated and execution is\r
+ * continued.\r
+ */\r
+#define USE_UNRECOGNIZED_CALLBACK 0\r
+\r
+/*\r
+ * This option will also call UnrecognizedCallback for a-line and f-line\r
+ * (0xa*** and 0xf***) opcodes the same way as described above, only appropriate\r
+ * exceptions will be generated.\r
+ */\r
+#define USE_AFLINE_CALLBACK 0\r
+\r
+/*\r
+ * This makes Cyclone to call checkpc from it's context whenever it changes the PC\r
+ * by a large value. It takes and should return the PC value in PC+membase form.\r
+ * The flags and cycle counter are not valid in this function.\r
+ */\r
+#define USE_CHECKPC_CALLBACK 1\r
+\r
+/*\r
+ * This determines if checkpc() should be called after jumps when 8 and 16 bit\r
+ * displacement values were used.\r
+ */\r
+#define USE_CHECKPC_OFFSETBITS_16 1\r
+#define USE_CHECKPC_OFFSETBITS_8 0\r
+\r
+/*\r
+ * Call checkpc() after DBcc jumps (which use 16bit displacement). Cyclone prior to\r
+ * 0.0087 never did that.\r
+ */\r
+#define USE_CHECKPC_DBRA 0\r
+\r
+/*\r
+ * When this option is enabled Cyclone will do two word writes instead of one\r
+ * long write when handling MOVE.L with pre-decrementing destination, as described in\r
+ * Bart Trzynadlowski's doc (http://www.trzy.org/files/68knotes.txt).\r
+ * Enable this if you are emulating a 16 bit system.\r
+ */\r
+#define SPLIT_MOVEL_PD 1\r
+\r
+/*\r
+ * Enable emulation of trace mode. Shouldn't cause any performance decrease, so it\r
+ * should be safe to keep this ON.\r
+ */\r
+#define EMULATE_TRACE 1\r
+\r
+/*\r
+ * If enabled, address error exception will be generated if 68k code jumps to an\r
+ * odd address. Causes very small performance hit (2 ARM instructions for every\r
+ * emulated jump/return/exception in normal case).\r
+ * Note: checkpc() must not clear least significant bit of rebased address\r
+ * for this to work, as checks are performed after calling checkpc().\r
+ */\r
+#define EMULATE_ADDRESS_ERRORS_JUMP 1\r
+\r
+/*\r
+ * If enabled, address error exception will be generated if 68k code tries to\r
+ * access a word or longword at an odd address. The performance cost is also 2 ARM\r
+ * instructions per access (for address error checks).\r
+ */\r
+#define EMULATE_ADDRESS_ERRORS_IO 0\r
+\r
+/*\r
+ * If an address error happens during another address error processing,\r
+ * the processor halts until it is reset (catastrophic system failure, as the manual\r
+ * states). This option enables halt emulation.\r
+ * Note that this might be not desired if it is known that emulated system should\r
+ * never reach this state.\r
+ */\r
+#define EMULATE_HALT 0\r
+\r
--- /dev/null
+\r
+\r
+/**\r
+ * Cyclone 68000 configuration file\r
+**/\r
+\r
+\r
+/*\r
+ * If this option is enabled, Microsoft ARMASM compatible output is generated\r
+ * (output file - Cyclone.asm). Otherwise GNU as syntax is used (Cyclone.s).\r
+ */\r
+#define USE_MS_SYNTAX 0\r
+\r
+/*\r
+ * Enable this option if you are going to use Cyclone to emulate Genesis /\r
+ * Mega Drive system. As VDP chip in these systems had control of the bus,\r
+ * several instructions were acting differently, for example TAS did'n have\r
+ * the write-back phase. That will be emulated, if this option is enabled.\r
+ * This option also alters timing slightly.\r
+ */\r
+#define CYCLONE_FOR_GENESIS 2\r
+\r
+/*\r
+ * This option compresses Cyclone's jumptable. Because of this the executable\r
+ * will be smaller and load slightly faster and less relocations will be needed.\r
+ * This also fixes the crash problem with 0xfffe and 0xffff opcodes.\r
+ * Warning: if you enable this, you MUST call CycloneInit() before calling\r
+ * CycloneRun(), or else it will crash.\r
+ */\r
+#define COMPRESS_JUMPTABLE 1\r
+\r
+/*\r
+ * Address mask for memory hadlers. The bits set will be masked out of address\r
+ * parameter, which is passed to r/w memory handlers.\r
+ * Using 0xff000000 means that only 24 least significant bits should be used.\r
+ * Set to 0 if you want to mask unused address bits in the memory handlers yourself.\r
+ */\r
+#define MEMHANDLERS_ADDR_MASK 0\r
+\r
+/*\r
+ * Cyclone keeps the 4 least significant bits of SR, PC+membase and it's cycle\r
+ * counter in ARM registers instead of the context for performance reasons. If you for\r
+ * any reason need to access them in your memory handlers, enable the options below,\r
+ * otherwise disable them to improve performance.\r
+ *\r
+ * MEMHANDLERS_NEED_PC updates .pc context field with PC value effective at the time\r
+ * when memhandler was called (opcode address + 2-10 bytes).\r
+ * MEMHANDLERS_NEED_PREV_PC updates .prev_pc context field to currently executed\r
+ * opcode address + 2.\r
+ * Note that .pc and .prev_pc values are always real pointers to memory, so you must\r
+ * subtract .membase to get M68k PC value.\r
+ *\r
+ * Warning: updating PC in memhandlers is dangerous, as Cyclone may internally\r
+ * increment the PC before fetching the next instruction and continue executing\r
+ * at wrong location. It's better to wait until Cyclone CycloneRun() finishes.\r
+ *\r
+ * Warning: if you enable MEMHANDLERS_CHANGE_CYCLES, you must also enable\r
+ * MEMHANDLERS_NEED_CYCLES, or else Cyclone will keep reloading the same cycle\r
+ * count and this will screw timing (if not cause a deadlock).\r
+ */\r
+#define MEMHANDLERS_NEED_PC 0\r
+#define MEMHANDLERS_NEED_PREV_PC 0\r
+#define MEMHANDLERS_NEED_FLAGS 0\r
+#define MEMHANDLERS_NEED_CYCLES 1\r
+#define MEMHANDLERS_CHANGE_PC 0\r
+#define MEMHANDLERS_CHANGE_FLAGS 0\r
+#define MEMHANDLERS_CHANGE_CYCLES 0\r
+\r
+/*\r
+ * If enabled, Cyclone will call .IrqCallback routine from it's context whenever it\r
+ * acknowledges an IRQ. IRQ level (.irq) is not cleared automatically, do this in your\r
+ * handler if needed.\r
+ * This function must either return vector number to use for interrupt exception,\r
+ * CYCLONE_INT_ACK_AUTOVECTOR to use autovector (this is the most common case), or\r
+ * CYCLONE_INT_ACK_SPURIOUS (least common case).\r
+ * If disabled, it simply uses appropriate autovector, clears the IRQ level and\r
+ * continues execution.\r
+ */\r
+#define USE_INT_ACK_CALLBACK 1\r
+\r
+/*\r
+ * Enable this if you need old PC, flags or cycles;\r
+ * or you change cycles in your IrqCallback function.\r
+ */\r
+#define INT_ACK_NEEDS_STUFF 0\r
+#define INT_ACK_CHANGES_CYCLES 0\r
+\r
+/*\r
+ * If enabled, .ResetCallback is called from the context, whenever RESET opcode is\r
+ * encountered. All context members are valid and can be changed.\r
+ * If disabled, RESET opcode acts as an NOP.\r
+ */\r
+#define USE_RESET_CALLBACK 1\r
+\r
+/*\r
+ * If enabled, UnrecognizedCallback is called if an invalid opcode is\r
+ * encountered. All context members are valid and can be changed. The handler\r
+ * should return zero if you want Cyclone to gererate "Illegal Instruction"\r
+ * exception after this, or nonzero if not. In the later case you should change\r
+ * the PC by yourself, or else Cyclone will keep executing that opcode all over\r
+ * again.\r
+ * If disabled, "Illegal Instruction" exception is generated and execution is\r
+ * continued.\r
+ */\r
+#define USE_UNRECOGNIZED_CALLBACK 1\r
+\r
+/*\r
+ * This option will also call UnrecognizedCallback for a-line and f-line\r
+ * (0xa*** and 0xf***) opcodes the same way as described above, only appropriate\r
+ * exceptions will be generated.\r
+ */\r
+#define USE_AFLINE_CALLBACK 1\r
+\r
+/*\r
+ * This makes Cyclone to call checkpc from it's context whenever it changes the PC\r
+ * by a large value. It takes and should return the PC value in PC+membase form.\r
+ * The flags and cycle counter are not valid in this function.\r
+ */\r
+#define USE_CHECKPC_CALLBACK 1\r
+\r
+/*\r
+ * This determines if checkpc() should be called after jumps when 8 and 16 bit\r
+ * displacement values were used.\r
+ */\r
+#define USE_CHECKPC_OFFSETBITS_16 1\r
+#define USE_CHECKPC_OFFSETBITS_8 0\r
+\r
+/*\r
+ * Call checkpc() after DBcc jumps (which use 16bit displacement). Cyclone prior to\r
+ * 0.0087 never did that.\r
+ */\r
+#define USE_CHECKPC_DBRA 0\r
+\r
+/*\r
+ * When this option is enabled Cyclone will do two word writes instead of one\r
+ * long write when handling MOVE.L with pre-decrementing destination, as described in\r
+ * Bart Trzynadlowski's doc (http://www.trzy.org/files/68knotes.txt).\r
+ * Enable this if you are emulating a 16 bit system.\r
+ */\r
+#define SPLIT_MOVEL_PD 1\r
+\r
+/*\r
+ * Enable emulation of trace mode. Shouldn't cause any performance decrease, so it\r
+ * should be safe to keep this ON.\r
+ */\r
+#define EMULATE_TRACE 1\r
+\r
+/*\r
+ * If enabled, address error exception will be generated if 68k code jumps to an\r
+ * odd address. Causes very small performance hit (2 ARM instructions for every\r
+ * emulated jump/return/exception in normal case).\r
+ * Note: checkpc() must not clear least significant bit of rebased address\r
+ * for this to work, as checks are performed after calling checkpc().\r
+ */\r
+#define EMULATE_ADDRESS_ERRORS_JUMP 1\r
+\r
+/*\r
+ * If enabled, address error exception will be generated if 68k code tries to\r
+ * access a word or longword at an odd address. The performance cost is also 2 ARM\r
+ * instructions per access (for address error checks).\r
+ */\r
+#define EMULATE_ADDRESS_ERRORS_IO 0\r
+\r
+/*\r
+ * If an address error happens during another address error processing,\r
+ * the processor halts until it is reset (catastrophic system failure, as the manual\r
+ * states). This option enables halt emulation.\r
+ * Note that this might be not desired if it is known that emulated system should\r
+ * never reach this state.\r
+ */\r
+#define EMULATE_HALT 0\r
+\r
--- /dev/null
+\r
+\r
+/**\r
+ * Cyclone 68000 configuration file\r
+**/\r
+\r
+\r
+/*\r
+ * If this option is enabled, Microsoft ARMASM compatible output is generated\r
+ * (output file - Cyclone.asm). Otherwise GNU as syntax is used (Cyclone.s).\r
+ */\r
+#define USE_MS_SYNTAX 0\r
+\r
+/*\r
+ * Enable this option if you are going to use Cyclone to emulate Genesis /\r
+ * Mega Drive system. As VDP chip in these systems had control of the bus,\r
+ * several instructions were acting differently, for example TAS did'n have\r
+ * the write-back phase. That will be emulated, if this option is enabled.\r
+ * This option also alters timing slightly.\r
+ */\r
+#define CYCLONE_FOR_GENESIS 0\r
+\r
+/*\r
+ * This option compresses Cyclone's jumptable. Because of this the executable\r
+ * will be smaller and load slightly faster and less relocations will be needed.\r
+ * This also fixes the crash problem with 0xfffe and 0xffff opcodes.\r
+ * Warning: if you enable this, you MUST call CycloneInit() before calling\r
+ * CycloneRun(), or else it will crash.\r
+ */\r
+#define COMPRESS_JUMPTABLE 1\r
+\r
+/*\r
+ * Address mask for memory hadlers. The bits set will be masked out of address\r
+ * parameter, which is passed to r/w memory handlers.\r
+ * Using 0xff000000 means that only 24 least significant bits should be used.\r
+ * Set to 0 if you want to mask unused address bits in the memory handlers yourself.\r
+ */\r
+#define MEMHANDLERS_ADDR_MASK 0\r
+\r
+/*\r
+ * Cyclone keeps the 4 least significant bits of SR, PC+membase and it's cycle\r
+ * counter in ARM registers instead of the context for performance reasons. If you for\r
+ * any reason need to access them in your memory handlers, enable the options below,\r
+ * otherwise disable them to improve performance.\r
+ *\r
+ * MEMHANDLERS_NEED_PC updates .pc context field with PC value effective at the time\r
+ * when memhandler was called (opcode address + 2-10 bytes).\r
+ * MEMHANDLERS_NEED_PREV_PC updates .prev_pc context field to currently executed\r
+ * opcode address + 2.\r
+ * Note that .pc and .prev_pc values are always real pointers to memory, so you must\r
+ * subtract .membase to get M68k PC value.\r
+ *\r
+ * Warning: updating PC in memhandlers is dangerous, as Cyclone may internally\r
+ * increment the PC before fetching the next instruction and continue executing\r
+ * at wrong location. It's better to wait until Cyclone CycloneRun() finishes.\r
+ *\r
+ * Warning: if you enable MEMHANDLERS_CHANGE_CYCLES, you must also enable\r
+ * MEMHANDLERS_NEED_CYCLES, or else Cyclone will keep reloading the same cycle\r
+ * count and this will screw timing (if not cause a deadlock).\r
+ */\r
+#define MEMHANDLERS_NEED_PC 1\r
+#define MEMHANDLERS_NEED_PREV_PC 0\r
+#define MEMHANDLERS_NEED_FLAGS 0\r
+#define MEMHANDLERS_NEED_CYCLES 1\r
+#define MEMHANDLERS_CHANGE_PC 0\r
+#define MEMHANDLERS_CHANGE_FLAGS 0\r
+#define MEMHANDLERS_CHANGE_CYCLES 1\r
+\r
+/*\r
+ * If enabled, Cyclone will call .IrqCallback routine from it's context whenever it\r
+ * acknowledges an IRQ. IRQ level (.irq) is not cleared automatically, do this in your\r
+ * handler if needed.\r
+ * This function must either return vector number to use for interrupt exception,\r
+ * CYCLONE_INT_ACK_AUTOVECTOR to use autovector (this is the most common case), or\r
+ * CYCLONE_INT_ACK_SPURIOUS (least common case).\r
+ * If disabled, it simply uses appropriate autovector, clears the IRQ level and\r
+ * continues execution.\r
+ */\r
+#define USE_INT_ACK_CALLBACK 1\r
+\r
+/*\r
+ * Enable this if you need old PC, flags or cycles;\r
+ * or you change cycles in your IrqCallback function.\r
+ */\r
+#define INT_ACK_NEEDS_STUFF 0\r
+#define INT_ACK_CHANGES_CYCLES 0\r
+\r
+/*\r
+ * If enabled, .ResetCallback is called from the context, whenever RESET opcode is\r
+ * encountered. All context members are valid and can be changed.\r
+ * If disabled, RESET opcode acts as an NOP.\r
+ */\r
+#define USE_RESET_CALLBACK 0\r
+\r
+/*\r
+ * If enabled, UnrecognizedCallback is called if an invalid opcode is\r
+ * encountered. All context members are valid and can be changed. The handler\r
+ * should return zero if you want Cyclone to gererate "Illegal Instruction"\r
+ * exception after this, or nonzero if not. In the later case you should change\r
+ * the PC by yourself, or else Cyclone will keep executing that opcode all over\r
+ * again.\r
+ * If disabled, "Illegal Instruction" exception is generated and execution is\r
+ * continued.\r
+ */\r
+#define USE_UNRECOGNIZED_CALLBACK 1\r
+\r
+/*\r
+ * This option will also call UnrecognizedCallback for a-line and f-line\r
+ * (0xa*** and 0xf***) opcodes the same way as described above, only appropriate\r
+ * exceptions will be generated.\r
+ */\r
+#define USE_AFLINE_CALLBACK 1\r
+\r
+/*\r
+ * This makes Cyclone to call checkpc from it's context whenever it changes the PC\r
+ * by a large value. It takes and should return the PC value in PC+membase form.\r
+ * The flags and cycle counter are not valid in this function.\r
+ */\r
+#define USE_CHECKPC_CALLBACK 1\r
+\r
+/*\r
+ * This determines if checkpc() should be called after jumps when 8 and 16 bit\r
+ * displacement values were used.\r
+ */\r
+#define USE_CHECKPC_OFFSETBITS_16 1\r
+#define USE_CHECKPC_OFFSETBITS_8 0\r
+\r
+/*\r
+ * Call checkpc() after DBcc jumps (which use 16bit displacement). Cyclone prior to\r
+ * 0.0087 never did that.\r
+ */\r
+#define USE_CHECKPC_DBRA 0\r
+\r
+/*\r
+ * When this option is enabled Cyclone will do two word writes instead of one\r
+ * long write when handling MOVE.L with pre-decrementing destination, as described in\r
+ * Bart Trzynadlowski's doc (http://www.trzy.org/files/68knotes.txt).\r
+ * Enable this if you are emulating a 16 bit system.\r
+ */\r
+#define SPLIT_MOVEL_PD 1\r
+\r
+/*\r
+ * Enable emulation of trace mode. Shouldn't cause any performance decrease, so it\r
+ * should be safe to keep this ON.\r
+ */\r
+#define EMULATE_TRACE 1\r
+\r
+/*\r
+ * If enabled, address error exception will be generated if 68k code jumps to an\r
+ * odd address. Causes very small performance hit (2 ARM instructions for every\r
+ * emulated jump/return/exception in normal case).\r
+ * Note: checkpc() must not clear least significant bit of rebased address\r
+ * for this to work, as checks are performed after calling checkpc().\r
+ */\r
+#define EMULATE_ADDRESS_ERRORS_JUMP 1\r
+\r
+/*\r
+ * If enabled, address error exception will be generated if 68k code tries to\r
+ * access a word or longword at an odd address. The performance cost is also 2 ARM\r
+ * instructions per access (for address error checks).\r
+ */\r
+#define EMULATE_ADDRESS_ERRORS_IO 1\r
+\r
+/*\r
+ * If an address error happens during another address error processing,\r
+ * the processor halts until it is reset (catastrophic system failure, as the manual\r
+ * states). This option enables halt emulation.\r
+ * Note that this might be not desired if it is known that emulated system should\r
+ * never reach this state.\r
+ */\r
+#define EMULATE_HALT 0\r
+\r
CFLAGS = -Wall
+ifdef CONFIG_FILE
+CFLAGS += -DCONFIG_FILE=\"$(CONFIG_FILE)\"
+endif
all : cyclone.s
# Makefile for MS Visual C\r
\r
CPP=cl.exe\r
-CPP_PROJ=/nologo /ML /W4 /GX /O2 /D "WIN32" /D "NDEBUG" /D "_CONSOLE" /D "_MBCS" $(RC_FLAGS) /YX /FD /c \r
+CPP_PROJ=/nologo /W4 /O2 /D "_CRT_SECURE_NO_WARNINGS" /c \r
\r
LINK32=link.exe\r
LINK32_FLAGS=user32.lib /nologo /subsystem:console /machine:I386 /out:Cyclone.exe\r
$(CPP) $(CPP_PROJ) ..\OpMove.cpp\r
\r
Disa.obj : ..\disa\Disa.c ..\disa\Disa.h\r
- $(CPP) /nologo /ML /W4 /O2 /D "WIN32" /D "NDEBUG" /D "_CONSOLE" /D "_MBCS" /c ..\disa\Disa.c\r
+ $(CPP) $(CPP_PROJ) ..\disa\Disa.c\r
\r
..\app.h : ..\config.h\r
\r
-@erase "Cyclone.exe"\r
-@erase "Cyclone.asm"\r
-@erase "Cyclone.s"\r
- -@erase "Cyclone.o"\r
\r
# PROP Intermediate_Dir "Release"\r
# PROP Ignore_Export_Lib 0\r
# PROP Target_Dir ""\r
-# ADD BASE CPP /nologo /W3 /GX /O2 /D "WIN32" /D "NDEBUG" /D "_CONSOLE" /D "_MBCS" /YX /FD /c\r
-# ADD CPP /nologo /W3 /GX /O2 /D "WIN32" /D "NDEBUG" /D "_CONSOLE" /D "_MBCS" /YX /FD /c\r
+# ADD BASE CPP /nologo /W4 /O2 /D "_CRT_SECURE_NO_WARNINGS" /c\r
+# ADD CPP /nologo /W4 /O2 /D "_CRT_SECURE_NO_WARNINGS" /c\r
# ADD BASE RSC /l 0x427 /d "NDEBUG"\r
# ADD RSC /l 0x427 /d "NDEBUG"\r
BSC32=bscmake.exe\r
# PROP Intermediate_Dir "Debug"\r
# PROP Ignore_Export_Lib 0\r
# PROP Target_Dir ""\r
-# ADD BASE CPP /nologo /W3 /Gm /GX /ZI /Od /D "WIN32" /D "_DEBUG" /D "_CONSOLE" /D "_MBCS" /YX /FD /GZ /c\r
-# ADD CPP /nologo /W4 /Gm /GX /ZI /Od /D "WIN32" /D "_DEBUG" /D "_CONSOLE" /D "_MBCS" /YX /FD /GZ /c\r
+# ADD BASE CPP /nologo /W4 /O2 /D "_CRT_SECURE_NO_WARNINGS" /c\r
+# ADD CPP /nologo /W4 /O2 /D "_CRT_SECURE_NO_WARNINGS" /c\r
# ADD BASE RSC /l 0x427 /d "_DEBUG"\r
# ADD RSC /l 0x427 /d "_DEBUG"\r
BSC32=bscmake.exe\r
--- /dev/null
+| Processor: 68K\r
+| Target Assembler: 680x0 Assembler by GNU project\r
+\r
+| ___________________________________________________________________________\r
+\r
+| Segment type: Pure code\r
+| segment "ROM"\r
+dword_0: .long 0 | DATA XREF: ROM:00007244\19r\r
+ | sub_764E+3E\19o ...\r
+ | initial interrupt stack pointer\r
+dword_4: .long _start | DATA XREF: ROM:00007248\19r\r
+ | ROM:000142C2\19w\r
+ | reset initial PC\r
+dword_8: .long 0x4DE | DATA XREF: sub_20050+B54\19w\r
+ .long 0x490\r
+ .long 0x4AA | illegal instruction\r
+ .long 0x4C4\r
+ .long 0x4DE\r
+ .long 0x4DE\r
+ .long 0x4DE\r
+ .long _trace | trace\r
+ .long 0x4DE\r
+ .long 0x4DE\r
+ .long 0x4DE\r
+ .long 0x4DE\r
+ .long 0x4DE\r
+ .long 0x4DE\r
+ .long 0x4DE\r
+ .long 0x4DE\r
+ .long 0x4DE\r
+ .long 0x4DE\r
+ .long 0x4DE\r
+ .long 0x4DE\r
+ .long 0x4DE\r
+ .long 0x4DE\r
+ .long 0x4DE\r
+ .long 0x548 | Level 1 Interrupt Autovector\r
+ .long 0x548 | 2 = ext interrupt\r
+ .long 0x548\r
+ .long 0x592 | 4 = horizontal interrupt?\r
+ .long 0x548\r
+ .long 0x594 | 6 = verticai interrupt?\r
+ .long 0x552\r
+dword_80: .long 0x45C | DATA XREF: ROM:00152F29\19o\r
+ | trap vector table? trap 0?\r
+ .long 0x1738\r
+ .long 0x171C\r
+ .long 0x1754\r
+ .long 0x1700\r
+ .long 0x556\r
+ .long 0x57A\r
+ .long 0x548\r
+ .long 0x548\r
+ .long 0x7CE | 9\r
+ .long 0x548\r
+ .long 0x548\r
+ .long 0x548\r
+ .long 0x548\r
+ .long 0x548\r
+ .long 0x548\r
+ .long 0x4DE\r
+ .long 0x4DE\r
+ .long 0x4DE\r
+ .long 0x4DE\r
+ .long 0x4DE\r
+ .long 0x4DE\r
+ .long 0x4DE\r
+ .long 0x4DE\r
+ .long 0x4DE\r
+ .long 0x4DE\r
+ .long 0x4DE\r
+ .long 0x4DE\r
+ .long 0x4DE\r
+ .long 0x4DE\r
+ .long 0x4DE\r
+ .long 0x4DE\r
+aSegaGenesis: .ascii "SEGA GENESIS " | DATA XREF: ROM:00045C6A\19o\r
+aCSega1994_jul: .ascii "(C)SEGA 1994.JUL"\r
+aDumpedByTsd: .ascii "Dumped By TSD "\r
+aShiningForce2: .ascii "SHINING FORCE 2 "\r
+aGmMk131500: .ascii "GM MK-1315 -00"\r
+ .word 0x8921 | checksum\r
+aJ: .ascii "J " | IO_Support\r
+ .long 0 | Rom_Start_Adress\r
+dword_1A4: .long 0x1FFFFF | DATA XREF: sub_28008+F66\19o\r
+ | Rom_End_Adress\r
+ .long 0xFF0000 | Ram_Start_Adress\r
+ .long 0xFFFFFF | Ram_End_Adress\r
+aRaa: .ascii "RA° "<0>" "<0><1><0>" ?"<0xFF> | Modem_Infos\r
+ .ascii " "\r
+ .byte 0x20 | \r
+ .byte 0x20 | \r
+ .byte 0x20 | \r
+ .byte 0x20 | \r
+ .byte 0x20 | \r
+ .byte 0x20 | \r
+ .byte 0x20 | \r
+ .byte 0x20 | \r
+ .byte 0x20 | \r
+ .byte 0x20 | \r
+ .byte 0x20 | \r
+ .byte 0x20 | \r
+aU: .ascii "U " | Countries\r
+ .byte 0x20 | \r
+ .byte 0x20 | \r
+ .byte 0x20 | \r
+ .byte 0x20 | \r
+ .byte 0x20 | \r
+ .byte 0x20 | \r
+ .byte 0x20 | \r
+ .byte 0x20 | \r
+ .byte 0x20 | \r
+ .byte 0x20 | \r
+ .byte 0x20 | \r
+ .byte 0x20 | \r
+ .byte 0x20 | \r
+_trace:\r
+ nop\r
+ nop\r
+ rte\r
+\r
+.globl _start\r
+_start:\r
+ move.l #0xFFFFFFFF, %d0\r
+ move.l #0xFFFFFFFF, %d1\r
+ move.w #0xa711, %sr\r
+ move.l #0x1, %d2\r
+ move.l #0x8000, %d3\r
+ negx.l %d0\r
+ negx.l %d1\r
+ move.w #0x270f, %sr\r
+ negx.b %d2\r
+ negx.w %d3\r
+_loop:\r
+ bra _loop\r
+\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
notaz.gp2x.de / picodrive.git / commitdiff