optimizations, bugfixes, uae works (but with timing glitches?)

git-svn-id: file:///home/notaz/opt/svn/PicoDrive@191 be3aeb3a-fb24-0410-a615-afba39da0efa

diff --git a/cpu/Cyclone/Cyclone.txt b/cpu/Cyclone/Cyclone.txt
index b2c675d..8a68e16 100644 (file)
--- a/cpu/Cyclone/Cyclone.txt
+++ b/cpu/Cyclone/Cyclone.txt
@@ -45,6 +45,8 @@ v0.0087 notaz
   + Changed "MOVEA (An)+ An" behaviour.\r
   + Fixed flag behaviour of ROXR, ASL, LSR and NBCD in certain situations.\r
     Hopefully got them right now.\r
+  + Cyclone no longer sets most significant bits while pushing PC to stack.\r
+    Amiga Kickstart depends on this.\r
   + Additional functionality added for MAME and other ports (see config.h).\r
 \r
 v0.0086 notaz\r

diff --git a/cpu/Cyclone/Main.cpp b/cpu/Cyclone/Main.cpp
index 5647fb1..5fed8ee 100644 (file)
--- a/cpu/Cyclone/Main.cpp
+++ b/cpu/Cyclone/Main.cpp
@@ -10,7 +10,7 @@ char *Narm[4]={ "b", "h","",""}; // Normal ARM Extensions for operand sizes 0,1,
 char *Sarm[4]={"sb","sh","",""}; // Sign-extend ARM Extensions for operand sizes 0,1,2\r
 int Cycles; // Current cycles for opcode\r
 int pc_dirty; // something changed PC during processing\r
-static int arm_op_count;\r
+int arm_op_count;\r
 \r
 \r
 void ot(const char *format, ...)\r
@@ -90,24 +90,22 @@ static void PrintException(int ints)
     ot("  mov r11,r0\n");\r
   }\r
 \r
-  ot(";@ swap OSP <-> A7?\n");\r
   ot("  ldr r0,[r7,#0x44] ;@ Get SR high\n");\r
+  ot("  ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
   ot("  tst r0,#0x20\n");\r
-  ot("  bne no_sp_swap%i\n",ints);\r
-  ot(";@ swap OSP and A7:\n");\r
-  ot("  ldr r0,[r7,#0x3C] ;@ Get A7\n");\r
-  ot("  ldr r1,[r7,#0x48] ;@ Get OSP\n");\r
-  ot("  str r0,[r7,#0x48]\n");\r
-  ot("  str r1,[r7,#0x3C]\n");\r
-  ot("no_sp_swap%i%s\n",ints,ms?"":":");\r
+  ot(";@ get our SP:\n");\r
+  ot("  ldr r0,[r7,#0x3c] ;@ Get A7\n");\r
+  ot("  ldreq r1,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");\r
+  ot("  streq r0,[r7,#0x48]\n");\r
+  ot("  moveq r0,r1\n");\r
 \r
-  ot("  ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
-//  ot("  mov r1,r4,lsl #8\n");\r
-//  ot("  sub r1,r1,r10,lsl #8 ;@ r1 = Old PC\n");\r
-//  ot("  mov r1,r1,asr #8 ;@ push sign extended\n");\r
   ot("  sub r1,r4,r10 ;@ r1 = Old PC\n");\r
-  OpPush32();\r
+  ot(";@ Push r1 onto stack\n");\r
+  ot("  sub r0,r0,#4 ;@ Predecrement A7\n");\r
+  ot("  str r0,[r7,#0x3c] ;@ Save A7\n");\r
+  MemHandler(1,2);\r
   OpPushSr(1);\r
+\r
   ot("  mov r0,r11\n");\r
   ot(";@ Read IRQ Vector:\n");\r
   MemHandler(0,2);\r
@@ -122,6 +120,8 @@ static void PrintException(int ints)
   ot("  mov lr,pc\n");\r
   ot("  ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
   ot("  mov r4,r0\n");\r
+#else\r
+  ot("  add r4,r0,r10 ;@ r4 = Memory Base + New PC\n");\r
 #endif\r
   ot("\n");\r
 \r
@@ -133,21 +133,6 @@ static void PrintException(int ints)
   }\r
 }\r
 \r
-// Trashes r0,r1\r
-void CheckInterrupt(int op)\r
-{\r
-  ot(";@ CheckInterrupt:\n");\r
-  ot("  ldr r1,[r7,#0x44] ;@ Get SR high T_S__III and irq level\n");\r
-  ot("  movs r0,r1,lsr #24 ;@ Get IRQ level\n"); // same as  ldrb r0,[r7,#0x47]\r
-  ot("  beq NoInts%x\n",op);\r
-  ot("  cmp r0,#6 ;@ irq>6 ?\n");\r
-  ot("  andle r1,r1,#7 ;@ Get interrupt mask\n");\r
-  ot("  cmple r0,r1 ;@ irq<=6: Is irq<=mask ?\n");\r
-  ot("  blgt CycloneDoInterrupt\n");\r
-  ot("NoInts%x%s\n", op,ms?"":":");\r
-  ot("\n");\r
-}\r
-\r
 void FlushPC(void)\r
 {\r
 #if MEMHANDLERS_NEED_PC\r
@@ -182,10 +167,7 @@ static void PrintFramework()
   ot("  cmp r0,#6 ;@ irq>6 ?\n");\r
   ot("  andle r1,r1,#7 ;@ Get interrupt mask\n");\r
   ot("  cmple r0,r1 ;@ irq<=6: Is irq<=mask ?\n");\r
-  ot("  blgt CycloneDoInterrupt\n");\r
-  ot(";@ Check if interrupt used up all the cycles:\n");\r
-  ot("  subs r5,r5,#0\n");\r
-  ot("  blt CycloneEndNoBack\n");\r
+  ot("  bgt CycloneDoInterrupt\n");\r
   ot("NoInts0%s\n", ms?"":":");\r
   ot("\n");\r
   ot(";@ Check if our processor is in stopped state and jump to opcode handler if not\n");\r
@@ -341,9 +323,9 @@ static void PrintFramework()
 #endif\r
 \r
   ot(";@ DoInterrupt - r0=IRQ number\n");\r
+  ot("CycloneDoInterruptGoBack%s\n", ms?"":":");\r
+  ot("  sub r4,r4,#2\n");\r
   ot("CycloneDoInterrupt%s\n", ms?"":":");\r
-  ot("  stmdb sp!,{lr} ;@ Push ARM return address\n");\r
-\r
   ot(";@ Get IRQ Vector address:\n");\r
   ot("  mov r0,r0,asl #2\n");\r
   ot("  add r11,r0,#0x60\n");\r
@@ -356,7 +338,6 @@ static void PrintFramework()
 \r
   ot(";@ Clear stopped states:\n");\r
   ot("  str r2,[r7,#0x58]\n");\r
-  ot("  sub r5,r5,#%d ;@ Subtract cycles\n",44);\r
   ot("\n");\r
 #if USE_INT_ACK_CALLBACK\r
 #if INT_ACK_NEEDS_STUFF\r
@@ -375,11 +356,14 @@ static void PrintFramework()
   ot("  mov r9,r9,lsl #28\n");\r
   ot("  ldr r4,[r7,#0x40] ;@ Load PC\n");\r
 #endif\r
-#else // not USE_INT_ACK_CALLBACK\r
+#else // !USE_INT_ACK_CALLBACK\r
   ot(";@ Clear irq:\n");\r
-  ot("  strb r1,[r7,#0x47]\n");\r
+  ot("  strb r2,[r7,#0x47]\n");\r
 #endif\r
-  ot("  ldmia sp!,{pc} ;@ Return\n");\r
+  ot("  ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
+  ot("  subs r5,r5,#44 ;@ Subtract cycles\n");\r
+  ot("  ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
+  ot("  b CycloneEnd\n");\r
   ot("\n");\r
   \r
   ot("Exception%s\n", ms?"":":");\r

diff --git a/cpu/Cyclone/OpAny.cpp b/cpu/Cyclone/OpAny.cpp
index 8e12015..cbdf5bb 100644 (file)
--- a/cpu/Cyclone/OpAny.cpp
+++ b/cpu/Cyclone/OpAny.cpp
@@ -25,35 +25,85 @@ void OpUse(int op,int use)
   ot(";@ ---------- [%.4x] %s uses Op%.4x ----------\n",op,text,use);\r
 }\r
 \r
-void OpStart(int op, int sea, int tea)\r
+void OpStart(int op, int sea, int tea, int op_changes_cycles, int supervisor_check)\r
 {\r
+  int last_op_count=arm_op_count;\r
+\r
   Cycles=0;\r
   OpUse(op,op); // This opcode obviously uses this handler\r
   ot("Op%.4x%s\n", op, ms?"":":");\r
-#if (MEMHANDLERS_NEED_PREV_PC || MEMHANDLERS_NEED_CYCLES)\r
-  if ((sea >= 0x10 && sea != 0x3c) || (tea >= 0x10 && tea != 0x3c)) {\r
+\r
+  if (supervisor_check)\r
+  {\r
+    // checks for supervisor bit, if not set, jumps to SuperEnd()\r
+    // also sets r11 to SR high value, SuperChange() uses this\r
+    ot("  ldr r11,[r7,#0x44] ;@ Get SR high\n");\r
+  }\r
+  if ((sea >= 0x10 && sea != 0x3c) || (tea >= 0x10 && tea != 0x3c))\r
+  {\r
 #if MEMHANDLERS_NEED_PREV_PC\r
     ot("  str r4,[r7,#0x50] ;@ Save prev PC + 2\n");\r
 #endif\r
 #if MEMHANDLERS_NEED_CYCLES\r
     ot("  str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
 #endif\r
-    ot("\n");\r
   }\r
+  if (supervisor_check)\r
+  {\r
+    ot("  tst r11,#0x20 ;@ Check we are in supervisor mode\n");\r
+    ot("  beq WrongPrivilegeMode ;@ No\n");\r
+  }\r
+  if ((sea >= 0x10 && sea != 0x3c) || (tea >= 0x10 && tea != 0x3c)) {\r
+#if MEMHANDLERS_CHANGE_CYCLES\r
+    if (op_changes_cycles)\r
+      ot("  mov r5,#0\n");\r
 #endif\r
+  }\r
+  if (last_op_count!=arm_op_count)\r
+    ot("\n");\r
   pc_dirty = 1;\r
 }\r
 \r
-void OpEnd(int sea, int tea)\r
+void OpEnd(int sea, int tea, int op_changes_cycles, int check_interrupt)\r
 {\r
+  int did_fetch=0;\r
 #if MEMHANDLERS_CHANGE_CYCLES\r
   if ((sea >= 0x10 && sea != 0x3c) || (tea >= 0x10 && tea != 0x3c))\r
-    ot("  ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
+  {\r
+    if (op_changes_cycles)\r
+    {\r
+      ot("  ldr r0,[r7,#0x5c] ;@ Load Cycles\n");\r
+      ot("  ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
+      ot("  add r5,r0,r5\n");\r
+      did_fetch=1;\r
+    }\r
+    else\r
+    {\r
+      ot("  ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
+    }\r
+  }\r
 #endif\r
-  ot("  ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
+  if (!did_fetch)\r
+    ot("  ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
   ot("  subs r5,r5,#%d ;@ Subtract cycles\n",Cycles);\r
-  ot("  ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
-  ot("  b CycloneEnd\n");\r
+  if (check_interrupt)\r
+  {\r
+    ot("  blt CycloneEnd\n");\r
+    ot(";@ CheckInterrupt:\n");\r
+    ot("  ldr r1,[r7,#0x44] ;@ Get SR high T_S__III and irq level\n");\r
+    ot("  movs r0,r1,lsr #24 ;@ Get IRQ level\n"); // same as  ldrb r0,[r7,#0x47]\r
+    ot("  ldreq pc,[r6,r8,asl #2] ;@ Jump to next opcode handler\n");\r
+    ot("  cmp r0,#6 ;@ irq>6 ?\n");\r
+    ot("  andle r1,r1,#7 ;@ Get interrupt mask\n");\r
+    ot("  cmple r0,r1 ;@ irq<=6: Is irq<=mask ?\n");\r
+    ot("  ldrle pc,[r6,r8,asl #2] ;@ Jump to next opcode handler\n");\r
+    ot("  b CycloneDoInterruptGoBack\n");\r
+  }\r
+  else\r
+  {\r
+    ot("  ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
+    ot("  b CycloneEnd\n");\r
+  }\r
   ot("\n");\r
 }\r
 \r

diff --git a/cpu/Cyclone/OpBranch.cpp b/cpu/Cyclone/OpBranch.cpp
index d1c2391..320b898 100644 (file)
--- a/cpu/Cyclone/OpBranch.cpp
+++ b/cpu/Cyclone/OpBranch.cpp
@@ -4,7 +4,7 @@
 static void CheckPc(int reg)\r
 {\r
 #if USE_CHECKPC_CALLBACK\r
-  ot(";@ Check Memory Base+pc (r4)\n");\r
+  ot(";@ Check Memory Base+pc (r%i)\n",reg);\r
   if (reg != 0)\r
     ot("  mov r0,r%i\n", reg);\r
   ot("  mov lr,pc\n");\r
@@ -173,14 +173,12 @@ int Op4E70(int op)
     return 0;\r
 \r
     case 3: // rte\r
-    OpStart(op,0x10); Cycles=20;\r
-    SuperCheck(op);\r
+    OpStart(op,0x10,0,0,1); Cycles=20;\r
     PopSr(1);\r
     ot("  ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
     PopPc();\r
     SuperChange(op);\r
-    CheckInterrupt(op);\r
-    OpEnd(0x10);\r
+    OpEnd(0x10,0,0,1);\r
     return 0;\r
 \r
     case 5: // rts\r
@@ -191,12 +189,12 @@ int Op4E70(int op)
     return 0;\r
 \r
     case 6: // trapv\r
-    OpStart(op,0x10); Cycles=4;\r
+    OpStart(op,0x10,0,1); Cycles=4;\r
     ot("  tst r9,#0x10000000\n");\r
     ot("  subne r5,r5,#%i\n",34);\r
     ot("  movne r0,#0x1c ;@ TRAPV exception\n");\r
     ot("  blne Exception\n");\r
-    OpEnd(0x10);\r
+    OpEnd(0x10,0,1);\r
     return 0;\r
 \r
     case 7: // rtr\r
@@ -233,27 +231,19 @@ int OpJsr(int op)
   ot("\n");\r
   EaCalc(11,0x003f,sea,0);\r
 \r
-  ot(";@ Jump - Get new PC from r0\n");\r
-  if (op&0x40)\r
-  {\r
-    // Jmp - Get new PC from r11\r
-    ot("  add r0,r11,r10 ;@ Memory Base + New PC\n");\r
-    ot("\n");\r
-  }\r
-  else\r
+  if (!(op&0x40))\r
   {\r
     ot(";@ Jsr - Push old PC first\n");\r
     ot("  ldr r0,[r7,#0x3c]\n");\r
     ot("  sub r1,r4,r10 ;@ r1 = Old PC\n");\r
-//    ot("  mov r1,r1,lsl #8\n");\r
-//    ot("  mov r1,r1,asr #8\n");\r
     ot(";@ Push r1 onto stack\n");\r
     ot("  sub r0,r0,#4 ;@ Predecrement A7\n");\r
     ot("  str r0,[r7,#0x3c] ;@ Save A7\n");\r
     MemHandler(1,2);\r
-    ot("  add r0,r11,r10 ;@ Memory Base + New PC\n");\r
-    ot("\n");\r
   }\r
+  ot(";@ Jump - Get new PC from r11\n");\r
+  ot("  add r0,r11,r10 ;@ Memory Base + New PC\n");\r
+  ot("\n");\r
 \r
   CheckPc(0);\r
 \r
@@ -441,8 +431,6 @@ int OpBranch(int op)
     ot("  ldr r2,[r7,#0x3c]\n");\r
     ot("  sub r1,r4,r10 ;@ r1 = Old PC\n");\r
     if (size) ot("  add r1,r1,#%d\n",1<<size);\r
-//    ot("  mov r1,r1, lsl #8\n");\r
-//    ot("  mov r1,r1, asr #8\n");\r
     ot("\n");\r
     ot(";@ Push r1 onto stack\n");\r
     ot("  sub r0,r2,#4 ;@ Predecrement A7\n");\r

diff --git a/cpu/Cyclone/OpLogic.cpp b/cpu/Cyclone/OpLogic.cpp
index 65d2293..a081605 100644 (file)
--- a/cpu/Cyclone/OpLogic.cpp
+++ b/cpu/Cyclone/OpLogic.cpp
@@ -307,7 +307,7 @@ int OpExt(int op)
 int OpSet(int op)\r
 {\r
   int cc=0,ea=0;\r
-  int size=0,use=0;\r
+  int size=0,use=0,changed_cycles=0;\r
   char *cond[16]=\r
   {\r
     "al","", "hi","ls","cc","cs","ne","eq",\r
@@ -325,7 +325,8 @@ int OpSet(int op)
   use=OpBase(op,size);\r
   if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
 \r
-  OpStart(op,ea); Cycles=8;\r
+  changed_cycles=ea<8 && cc>=2;\r
+  OpStart(op,ea,0,changed_cycles); Cycles=8;\r
   if (ea<8) Cycles=4;\r
 \r
   if (cc)\r
@@ -362,7 +363,7 @@ int OpSet(int op)
   EaCalc (0,0x003f, ea,size,0,0);\r
   EaWrite(0,     1, ea,size,0x003f,0,0);\r
 \r
-  OpEnd(ea);\r
+  OpEnd(ea,0,changed_cycles);\r
   return 0;\r
 }\r
 \r
@@ -586,7 +587,6 @@ int OpAsr(int op)
   int count=0,dir=0;\r
   int size=0,usereg=0,type=0;\r
 \r
-  ea=0;\r
   count =(op>>9)&7;\r
   dir   =(op>>8)&1;\r
   size  =(op>>6)&3;\r
@@ -605,7 +605,7 @@ int OpAsr(int op)
 \r
   if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
 \r
-  OpStart(op); Cycles=size<2?6:8;\r
+  OpStart(op,ea,0,count<0); Cycles=size<2?6:8;\r
 \r
   EaCalc(10,0x0007, ea,size,1);\r
   EaRead(10,     0, ea,size,0x0007,1);\r
@@ -614,7 +614,7 @@ int OpAsr(int op)
 \r
   EaWrite(10,    0, ea,size,0x0007,1);\r
 \r
-  OpEnd();\r
+  OpEnd(ea,0,count<0);\r
 \r
   return 0;\r
 }\r

diff --git a/cpu/Cyclone/OpMove.cpp b/cpu/Cyclone/OpMove.cpp
index b0916ea..64c0f59 100644 (file)
--- a/cpu/Cyclone/OpMove.cpp
+++ b/cpu/Cyclone/OpMove.cpp
@@ -39,16 +39,6 @@ void OpRegToFlags(int high)
   ot("\n");\r
 }\r
 \r
-// checks for supervisor bit, if not set, jumps to SuperEnd()\r
-// also sets r11 to SR high value, SuperChange() uses this\r
-void SuperCheck(int op)\r
-{\r
-  ot("  ldr r11,[r7,#0x44] ;@ Get SR high\n");\r
-  ot("  tst r11,#0x20 ;@ Check we are in supervisor mode\n");\r
-  ot("  beq WrongPrivilegeMode ;@ No\n");\r
-  ot("\n");\r
-}\r
-\r
 void SuperEnd(void)\r
 {\r
   ot(";@ ----------\n");\r
@@ -58,7 +48,7 @@ void SuperEnd(void)
   ot("  mov r0,#0x20 ;@ privilege violation\n");\r
   ot("  bl Exception\n");\r
   Cycles=34;\r
-  OpEnd(0x10);\r
+  OpEnd(0);\r
 }\r
 \r
 // does OSP and A7 swapping if needed\r
@@ -217,12 +207,11 @@ int OpMoveSr(int op)
   use=OpBase(op,size);\r
   if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
 \r
-  OpStart(op,ea);\r
+  // 68000 model allows reading whole SR in user mode (but newer models don't)\r
+  OpStart(op,ea,0,0,type==3);\r
   Cycles=12;\r
   if (type==0) Cycles=(ea>=8)?8:6;\r
 \r
-  if (type==3) SuperCheck(op); // 68000 model allows reading whole SR in user mode (but newer models don't)\r
-\r
   if (type==0 || type==1)\r
   {\r
     OpFlagsToReg(type==0);\r
@@ -236,11 +225,10 @@ int OpMoveSr(int op)
     OpRegToFlags(type==3);\r
     if (type==3) {\r
       SuperChange(op,0);\r
-      CheckInterrupt(op);\r
     }\r
   }\r
 \r
-  OpEnd(ea);\r
+  OpEnd(ea,0,0,type==3);\r
 \r
   return 0;\r
 }\r
@@ -259,9 +247,7 @@ int OpArithSr(int op)
   use=OpBase(op,size);\r
   if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
 \r
-  OpStart(op,ea); Cycles=16;\r
-\r
-  if (size) SuperCheck(op);\r
+  OpStart(op,ea,0,0,size!=0); Cycles=16;\r
 \r
   EaCalc(10,0x003f,ea,size);\r
   EaRead(10,    10,ea,size,0x003f);\r
@@ -271,12 +257,11 @@ int OpArithSr(int op)
   if (type==1) ot("  and r0,r1,r10\n");\r
   if (type==5) ot("  eor r0,r1,r10\n");\r
   OpRegToFlags(size);\r
-  if (size) {\r
+  if (size && type!=0) { // we can't enter supervisor mode, nor unmask irqs just by using OR\r
     SuperChange(op,0);\r
-    CheckInterrupt(op);\r
   }\r
 \r
-  OpEnd(ea);\r
+  OpEnd(ea,0,0,size!=0 && type!=0);\r
 \r
   return 0;\r
 }\r
@@ -337,7 +322,7 @@ int OpMovem(int op)
   use=OpBase(op,size);\r
   if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
 \r
-  OpStart(op,ea);\r
+  OpStart(op,ea,0,1);\r
 \r
   ot("  ldrh r11,[r4],#2 ;@ r11=register mask\n");\r
 \r
@@ -370,6 +355,9 @@ int OpMovem(int op)
   }\r
   else\r
   {\r
+    // if (size == 2 && decr && SPLIT_MOVEL_PD) we should do 2xWrite16 here\r
+    // (same as in movel.l ?, -(An)), but as this is not likely to be needed and\r
+    // we do not want the performance hit, we do single Write32 instead.\r
     ot("  ;@ Copy register to memory:\n",1<<size);\r
     ot("  ldr r1,[r7,r10] ;@ Load value from Dn/An\n");\r
     EaWrite(6,1,ea,size,0x003f);\r
@@ -403,7 +391,7 @@ int OpMovem(int op)
 \r
   Cycles+=Ea_add_ns(g_movem_cycle_table,ea);\r
 \r
-  OpEnd(ea);\r
+  OpEnd(ea,0,1);\r
   ltorg();\r
   ot("\n");\r
 \r
@@ -421,9 +409,7 @@ int OpMoveUsp(int op)
 \r
   if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
 \r
-  OpStart(op); Cycles=4;\r
-\r
-  SuperCheck(op);\r
+  OpStart(op,0,0,0,1); Cycles=4;\r
 \r
   if (dir)\r
   {\r
@@ -572,9 +558,7 @@ int OpStopReset(int op)
 {\r
   int type=(op>>1)&1; // stop/reset\r
 \r
-  OpStart(op);\r
-\r
-  SuperCheck(op);\r
+  OpStart(op,0,0,0,1);\r
 \r
   if(type) {\r
     // copy immediate to SR, stop the CPU and eat all remaining cycles.\r

diff --git a/cpu/Cyclone/app.h b/cpu/Cyclone/app.h
index f61432f..1d437d5 100644 (file)
--- a/cpu/Cyclone/app.h
+++ b/cpu/Cyclone/app.h
@@ -32,9 +32,9 @@ extern char *Narm[4]; // Normal ARM Extensions for operand sizes 0,1,2
 extern char *Sarm[4]; // Sign-extend ARM Extensions for operand sizes 0,1,2\r
 extern int  Cycles;   // Current cycles for opcode\r
 extern int  pc_dirty; // something changed PC during processing\r
+extern int  arm_op_count; // for stats\r
 void ot(const char *format, ...);\r
 void ltorg();\r
-void CheckInterrupt(int op);\r
 int MemHandler(int type,int size,int addrreg=0);\r
 void FlushPC(void);\r
 \r
@@ -42,8 +42,8 @@ void FlushPC(void);
 extern int g_op;\r
 int OpGetFlags(int subtract,int xbit,int sprecialz=0);\r
 void OpUse(int op,int use);\r
-void OpStart(int op,int sea=0,int tea=0);\r
-void OpEnd(int sea=0,int tea=0);\r
+void OpStart(int op,int sea=0,int tea=0,int op_changes_cycles=0,int supervisor_check=0);\r
+void OpEnd(int sea=0,int tea=0,int op_changes_cycles=0,int check_interrupt=0);\r
 int OpBase(int op,int size,int sepa=0);\r
 void OpAny(int op);\r
 \r
@@ -100,7 +100,6 @@ int OpMoveUsp(int op);
 int OpExg(int op);\r
 int OpMovep(int op);\r
 int OpStopReset(int op);\r
-void SuperCheck(int op);\r
 void SuperEnd(void);\r
 void SuperChange(int op,int load_srh=1);\r
 \r

diff --git a/cpu/Cyclone/config.h b/cpu/Cyclone/config.h
index 6fc6571..24b73a1 100644 (file)
--- a/cpu/Cyclone/config.h
+++ b/cpu/Cyclone/config.h
@@ -18,7 +18,7 @@
  * the write-back phase. That will be emulated, if this option is enabled.\r
  * This option also alters timing slightly.\r
  */\r
-#define CYCLONE_FOR_GENESIS       2\r
+#define CYCLONE_FOR_GENESIS       0\r
 \r
 /*\r
  * This option compresses Cyclone's jumptable. Because of this the executable\r
@@ -52,13 +52,13 @@
  * increment the PC before fetching the next instruction and continue executing\r
  * at wrong location.\r
  */\r
-#define MEMHANDLERS_NEED_PC       0\r
+#define MEMHANDLERS_NEED_PC       1\r
 #define MEMHANDLERS_NEED_PREV_PC  0\r
 #define MEMHANDLERS_NEED_FLAGS    0\r
 #define MEMHANDLERS_NEED_CYCLES   1\r
 #define MEMHANDLERS_CHANGE_PC     0\r
 #define MEMHANDLERS_CHANGE_FLAGS  0\r
-#define MEMHANDLERS_CHANGE_CYCLES 0\r
+#define MEMHANDLERS_CHANGE_CYCLES 1\r
 \r
 /*\r
  * If enabled, Cyclone will call IrqCallback routine from it's context whenever it\r
@@ -79,7 +79,7 @@
  * encountered. All context members are valid and can be changed.\r
  * If disabled, RESET opcode acts as an NOP.\r
  */\r
-#define USE_RESET_CALLBACK        1\r
+#define USE_RESET_CALLBACK        0\r
 \r
 /*\r
  * If enabled, UnrecognizedCallback is called if an invalid opcode is\r