sioWrite8((unsigned char)(value >> 24));
}
-static u32 io_read_sio2_status()
-{
- return 0x80;
-}
-
#if !defined(DRC_DBG) && defined(__arm__)
static void map_rcnt_rcount0(u32 mode)
map_item(&mem_iortab[IOMEM16(0x1048)], sioReadMode16, 1);
map_item(&mem_iortab[IOMEM16(0x104a)], sioReadCtrl16, 1);
map_item(&mem_iortab[IOMEM16(0x104e)], sioReadBaud16, 1);
- map_item(&mem_iortab[IOMEM16(0x1054)], io_read_sio2_status, 1);
+ map_item(&mem_iortab[IOMEM16(0x1054)], sio1ReadStat16, 1);
map_item(&mem_iortab[IOMEM16(0x1100)], psxRcntRcount0, 1);
map_item(&mem_iortab[IOMEM16(0x1104)], io_rcnt_read_mode0, 1);
map_item(&mem_iortab[IOMEM16(0x1108)], io_rcnt_read_target0, 1);
return v;
}
+u32 sio1ReadStat16(void)
+{
+ // Armored Core, F1 Link cable misdetection
+ return 0xa0;
+}
+
u8 psxHwRead8(u32 add) {
u8 hard;
case 0x1048: hard = sioReadMode16(); break;
case 0x104a: hard = sioReadCtrl16(); break;
case 0x104e: hard = sioReadBaud16(); break;
- case 0x1054: hard = 0x80; break; // Armored Core Link cable misdetection
+ case 0x1054: hard = sio1ReadStat16(); break;
case 0x1100: hard = psxRcntRcount0(); break;
case 0x1104: hard = psxRcntRmode(0); break;
case 0x1108: hard = psxRcntRtarget(0); break;
void psxHwWrite8(u32 add, u32 value);
void psxHwWrite16(u32 add, u32 value);
void psxHwWrite32(u32 add, u32 value);
+u32 sio1ReadStat16(void);
int psxHwFreeze(void *f, int Mode);
void psxHwWriteIstat(u32 value);