-/* Copyright (C) 2010-2015 The RetroArch team
+/* Copyright (C) 2010-2016 The RetroArch team
*
* ---------------------------------------------------------------------------------------
* The following license statement only applies to this file (psp_pthread.h).
#ifdef VITA
#include <psp2/kernel/threadmgr.h>
+#include <sys/time.h>
#else
#include <pspkernel.h>
#include <pspthreadman.h>
#include <stdio.h>
#include <retro_inline.h>
-#define STACKSIZE (64 * 1024)
+#define STACKSIZE (8 * 1024)
typedef SceUID pthread_t;
typedef SceUID pthread_mutex_t;
typedef void* pthread_mutexattr_t;
typedef int pthread_attr_t;
-typedef SceUID pthread_cond_t;
+
+typedef struct
+{
+ SceUID mutex;
+ SceUID sema;
+ int waiting;
+} pthread_cond_t;
+
typedef SceUID pthread_condattr_t;
/* Use pointer values to create unique names for threads/mutexes */
static INLINE int pthread_create(pthread_t *thread,
const pthread_attr_t *attr, void *(*start_routine)(void*), void *arg)
{
- sprintf(name_buffer, "0x%08X", (uint32_t) thread);
+ sprintf(name_buffer, "0x%08X", (unsigned int) thread);
- *thread = sceKernelCreateThread(name_buffer,
- psp_thread_wrap, 0x20, STACKSIZE, 0,
#ifdef VITA
- 0,
+ *thread = sceKernelCreateThread(name_buffer, psp_thread_wrap,
+ 0x10000100, 0x10000, 0, 0, NULL);
+#else
+ *thread = sceKernelCreateThread(name_buffer,
+ psp_thread_wrap, 0x20, STACKSIZE, 0, NULL);
#endif
- NULL);
sthread_args_struct sthread_args;
sthread_args.arg = arg;
static INLINE int pthread_mutex_init(pthread_mutex_t *mutex,
const pthread_mutexattr_t *attr)
{
- sprintf(name_buffer, "0x%08X", (uint32_t) mutex);
+ sprintf(name_buffer, "0x%08X", (unsigned int) mutex);
#ifdef VITA
- return *mutex = sceKernelCreateMutex(name_buffer, 0, 0, 0);
+ *mutex = sceKernelCreateMutex(name_buffer, 0, 0, 0);
+ if(*mutex<0)
+ return *mutex;
+ return 0;
#else
return *mutex = sceKernelCreateSema(name_buffer, 0, 1, 1, NULL);
#endif
static INLINE int pthread_mutex_lock(pthread_mutex_t *mutex)
{
#ifdef VITA
- return sceKernelLockMutex(*mutex, 1, 0);
+ int ret = sceKernelLockMutex(*mutex, 1, 0);
+ return ret;
+
#else
/* FIXME: stub */
return 1;
static INLINE int pthread_mutex_unlock(pthread_mutex_t *mutex)
{
#ifdef VITA
- return sceKernelUnlockMutex(*mutex, 1);
+ int ret = sceKernelUnlockMutex(*mutex, 1);
+ return ret;
#else
/* FIXME: stub */
return 1;
static INLINE int pthread_join(pthread_t thread, void **retval)
{
- int exit_status;
- SceUInt timeout = (SceUInt)-1;
#ifdef VITA
- sceKernelWaitThreadEnd(thread, &exit_status, &timeout);
+ int res = sceKernelWaitThreadEnd(thread, 0, 0);
+ if (res < 0)
+ return res;
+ return sceKernelDeleteThread(thread);
#else
+ SceUInt timeout = (SceUInt)-1;
sceKernelWaitThreadEnd(thread, &timeout);
exit_status = sceKernelGetThreadExitStatus(thread);
-#endif
sceKernelDeleteThread(thread);
return exit_status;
+#endif
}
static INLINE int pthread_mutex_trylock(pthread_mutex_t *mutex)
static INLINE int pthread_cond_wait(pthread_cond_t *cond,
pthread_mutex_t *mutex)
{
+#ifdef VITA
+ int ret = pthread_mutex_lock(&cond->mutex);
+ if (ret < 0)
+ return ret;
+ ++cond->waiting;
+ pthread_mutex_unlock(mutex);
+ pthread_mutex_unlock(&cond->mutex);
+
+ ret = sceKernelWaitSema(cond->sema, 1, 0);
+ if (ret < 0)
+ sceClibPrintf("Premature wakeup: %08X", ret);
+ pthread_mutex_lock(mutex);
+ return ret;
+#else
+ /* FIXME: stub */
sceKernelDelayThread(10000);
return 1;
+#endif
}
static INLINE int pthread_cond_timedwait(pthread_cond_t *cond,
pthread_mutex_t *mutex, const struct timespec *abstime)
{
- //FIXME: stub
+#ifdef VITA
+ int ret = pthread_mutex_lock(&cond->mutex);
+ if (ret < 0)
+ return ret;
+ ++cond->waiting;
+ pthread_mutex_unlock(mutex);
+ pthread_mutex_unlock(&cond->mutex);
+
+ SceUInt timeout = 0;
+
+ timeout = abstime->tv_sec;
+ timeout += abstime->tv_nsec / 1.0e6;
+
+ ret = sceKernelWaitSema(cond->sema, 1, &timeout);
+ if (ret < 0)
+ sceClibPrintf("Premature wakeup: %08X", ret);
+ pthread_mutex_lock(mutex);
+ return ret;
+
+#else
+ /* FIXME: stub */
return 1;
+#endif
}
static INLINE int pthread_cond_init(pthread_cond_t *cond,
const pthread_condattr_t *attr)
{
- //FIXME: stub
+#ifdef VITA
+
+ pthread_mutex_init(&cond->mutex,NULL);
+ if(cond->mutex<0){
+ return cond->mutex;
+ }
+ sprintf(name_buffer, "0x%08X", (unsigned int) cond);
+ //cond->sema = sceKernelCreateCond(name_buffer, 0, cond->mutex, 0);
+ cond->sema = sceKernelCreateSema(name_buffer, 0, 0, 1, 0);
+ if(cond->sema<0){
+ pthread_mutex_destroy(&cond->mutex);
+ return cond->sema;
+ }
+
+ cond->waiting = 0;
+
+
+ return 0;
+
+
+#else
+ /* FIXME: stub */
return 1;
+#endif
}
static INLINE int pthread_cond_signal(pthread_cond_t *cond)
{
- //FIXME: stub
+#ifdef VITA
+ pthread_mutex_lock(&cond->mutex);
+ if (cond->waiting)
+ {
+ --cond->waiting;
+ sceKernelSignalSema(cond->sema, 1);
+ }
+ pthread_mutex_unlock(&cond->mutex);
+ return 0;
+#else
+ /* FIXME: stub */
return 1;
+#endif
}
static INLINE int pthread_cond_broadcast(pthread_cond_t *cond)
{
- //FIXME: stub
+ /* FIXME: stub */
return 1;
}
static INLINE int pthread_cond_destroy(pthread_cond_t *cond)
{
- //FIXME: stub
- return 1;
+#ifdef VITA
+ int ret = sceKernelDeleteSema(cond->sema);
+ if(ret < 0)
+ return ret;
+
+ return sceKernelDeleteMutex(cond->mutex);
+#else
+ /* FIXME: stub */
+ return 1;
+#endif
}
static INLINE int pthread_detach(pthread_t thread)
{
- return 1;
+ return 0;
}
static INLINE void pthread_exit(void *retval)
{
- (void)retval;
+#ifdef VITA
+ sceKernelExitDeleteThread(sceKernelGetThreadId());
+#endif
+}
+
+static INLINE pthread_t pthread_self(void)
+{
+ /* zero 20-mar-2016: untested */
+ return sceKernelGetThreadId();
+}
+
+static INLINE int pthread_equal(pthread_t t1, pthread_t t2)
+{
+ return t1 == t2;
}
#endif //_PSP_PTHREAD_WRAP__
#elif defined(_3DS)
#include "3ds_utils.h"
#define __clear_cache(start,end) svcFlushProcessDataCache(0xFFFF8001, start, (u32)(end)-(u32)(start))
+#elif defined(VITA)
+#define __clear_cache vita_clear_cache
+static void __clear_cache(void *start, void *end) {
+ size_t len = (char *)end - (char *)start;
+ int block = sceKernelFindMemBlockByAddr(start,len);
+ sceKernelSyncVMDomain(block, start, len);
+}
#endif
#define MAXBLOCK 4096
#define STORE 2 // Store
#define LOADLR 3 // Unaligned load
#define STORELR 4 // Unaligned store
-#define MOV 5 // Move
+#define MOV 5 // Move
#define ALU 6 // Arithmetic/logic
#define MULTDIV 7 // Multiply/divide
#define SHIFT 8 // Shift by register
{
u_int addr;
int n;
- switch (ROM_HEADER->Country_code&0xFF)
+ switch (ROM_HEADER->Country_code&0xFF)
{
case 0x45: // U
addr=0x34b30;
- break;
- case 0x4A: // J
- addr=0x34b70;
- break;
- case 0x50: // E
+ break;
+ case 0x4A: // J
+ addr=0x34b70;
+ break;
+ case 0x50: // E
addr=0x329f0;
- break;
- default:
+ break;
+ default:
// Unknown country code
addr=0;
break;
for (hr=0;hr<HOST_REGS;hr++) {
if((cur->dirty>>hr)&1) {
reg=cur->regmap[hr];
- if(reg>=64)
+ if(reg>=64)
if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
}
}
int j;
int b=-1;
int rn=10;
-
+
if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
{
if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
void alloc_all(struct regstat *cur,int i)
{
int hr;
-
+
for(hr=0;hr<HOST_REGS;hr++) {
if(hr!=EXCLUDE_REG) {
if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
unsigned long long int result1, result2, result3, result4;
unsigned long long int temp1, temp2, temp3, temp4;
int sign = 0;
-
+
if (m1 < 0)
{
op2 = -m1;
sign = 1 - sign;
}
else op4 = m2;
-
+
op1 = op2 & 0xFFFFFFFF;
op2 = (op2 >> 32) & 0xFFFFFFFF;
op3 = op4 & 0xFFFFFFFF;
op4 = (op4 >> 32) & 0xFFFFFFFF;
-
+
temp1 = op1 * op3;
temp2 = (temp1 >> 32) + op1 * op4;
temp3 = op2 * op3;
temp4 = (temp3 >> 32) + op2 * op4;
-
+
result1 = temp1 & 0xFFFFFFFF;
result2 = temp2 + (temp3 & 0xFFFFFFFF);
result3 = (result2 >> 32) + temp4;
result4 = (result3 >> 32);
-
+
lo = result1 | (result2 << 32);
hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
if (sign)
unsigned long long int op1, op2, op3, op4;
unsigned long long int result1, result2, result3, result4;
unsigned long long int temp1, temp2, temp3, temp4;
-
+
op1 = m1 & 0xFFFFFFFF;
op2 = (m1 >> 32) & 0xFFFFFFFF;
op3 = m2 & 0xFFFFFFFF;
op4 = (m2 >> 32) & 0xFFFFFFFF;
-
+
temp1 = op1 * op3;
temp2 = (temp1 >> 32) + op1 * op4;
temp3 = op2 * op3;
temp4 = (temp3 >> 32) + op2 * op4;
-
+
result1 = temp1 & 0xFFFFFFFF;
result2 = temp2 + (temp3 & 0xFFFFFFFF);
result3 = (result2 >> 32) + temp4;
result4 = (result3 >> 32);
-
+
lo = result1 | (result2 << 32);
hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
-
+
//printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
// ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
}
{
struct ll_entry *next;
while(*head) {
- if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
+ if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
{
inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
#ifdef __arm__
do_clear_cache();
#endif
-
+
// Don't trap writes
invalid_code[block]=1;
#ifndef DISABLE_TLB
if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
gen_tlb_addr_w(temp,map);
#else
- if((u_int)rdram!=0x80000000)
+ if((u_int)rdram!=0x80000000)
emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
#endif
}else{ // using tlb
int mgr=MGEN1+(i&1);
if(itype[i]==LOAD) {
ra=get_reg(i_regs->regmap,rt1[i]);
- if(ra<0) ra=get_reg(i_regs->regmap,-1);
+ if(ra<0) ra=get_reg(i_regs->regmap,-1);
assert(ra>=0);
}
if(itype[i]==LOADLR) {
{
return 0;
}
- else
+ else
if((i_dirty>>hr)&1)
{
if(i_regmap[hr]<TEMPREG)
if(rs1[i]) {
if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
emit_loadreg(rs1[i],s1l);
- }
+ }
else {
if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
emit_loadreg(rs2[i],s1l);
load_all_regs(branch_regs[i].regmap);
}
emit_jmp(stubs[n][2]); // return address
-
+
/* This works but uses a lot of memory...
emit_readword((int)&last_count,ECX);
emit_add(HOST_CCREG,ECX,EAX);
{
link_addr[linkcount][0]=addr;
link_addr[linkcount][1]=target;
- link_addr[linkcount][2]=ext;
+ link_addr[linkcount][2]=ext;
linkcount++;
}
#endif
{
#ifdef REG_PREFETCH
- if(temp>=0)
+ if(temp>=0)
{
if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
}
address_generation(i+1,i_regs,regs[i].regmap_entry);
#ifdef REG_PREFETCH
int temp=get_reg(branch_regs[i].regmap,PTEMP);
- if(rt1[i]==31&&temp>=0)
+ if(rt1[i]==31&&temp>=0)
{
int return_address=start+i*4+8;
- if(get_reg(branch_regs[i].regmap,31)>0)
+ if(get_reg(branch_regs[i].regmap,31)>0)
if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
}
#endif
assert(rt>=0);
return_address=start+i*4+8;
#ifdef REG_PREFETCH
- if(temp>=0)
+ if(temp>=0)
{
if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
}
}
address_generation(i+1,i_regs,regs[i].regmap_entry);
#ifdef REG_PREFETCH
- if(rt1[i]==31)
+ if(rt1[i]==31)
{
if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
int return_address=start+i*4+8;
#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
if(i>(ba[i]-start)>>2) invert=1;
#endif
-
+
if(ooo[i]) {
s1l=get_reg(branch_regs[i].regmap,rs1[i]);
s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
cc=get_reg(branch_regs[i].regmap,CCREG);
assert(cc==HOST_CCREG);
- if(unconditional)
+ if(unconditional)
store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
//do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
//assem_debug("cycle count (adj)\n");
emit_jne(0);
}
} // if(!only32)
-
+
//printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
assert(s1l>=0);
if(opcode[i]==4) // BEQ
emit_jne(1);
}
} // if(!only32)
-
+
//printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
assert(s1l>=0);
if((opcode[i]&0x2f)==4) // BEQ
}
cc=get_reg(branch_regs[i].regmap,CCREG);
assert(cc==HOST_CCREG);
- if(unconditional)
+ if(unconditional)
store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
//do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
assem_debug("cycle count (adj)\n");
}
}
} // if(!only32)
-
+
if(invert) {
#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
{
}
} // if(!only32)
-
+
if(invert) {
if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
{
// If subroutine call, flag return address as a possible branch target
if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
-
+
if(ba[i]<start || ba[i]>=(start+slen*4))
{
// Branch out of this block, flush all regs
u=1;
uu=1;
gte_u=gte_u_unknown;
- /* Hexagon hack
+ /* Hexagon hack
if(itype[i]==UJUMP&&rt1[i]==31)
{
uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
int i,j;
uint64_t is32=1;
uint64_t lastbranch=1;
-
+
for(i=0;i<slen;i++)
{
if(i>0) {
uint64_t temp_is32=is32;
for(j=i-1;j>=0;j--)
{
- if(ba[j]==start+i*4)
+ if(ba[j]==start+i*4)
//temp_is32&=branch_regs[j].is32;
temp_is32&=p32[j];
}
for(j=i;j<slen;j++)
{
- if(ba[j]==start+i*4)
+ if(ba[j]==start+i*4)
temp_is32=1;
}
is32=temp_is32;
{
u_int r32=0;
int i;
-
+
for (i=slen-1;i>=0;i--)
{
int hr;
}
//requires_32bit[i]=r32;
pr32[i]=r32;
-
+
// Dirty registers which are 32-bit, require 32-bit input
// as they will be written as 32-bit values
for(hr=0;hr<HOST_REGS;hr++)
if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
if(i>istart) {
- if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
+ if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
{
// Don't store a register immediately after writing it,
// may prevent dual-issue.
{
SysPrintf("Init new dynarec\n");
out=(u_char *)BASE_ADDR;
-#if BASE_ADDR_FIXED
+#if defined(VITA)
+
if (mmap (out, 1<<TARGET_SIZE_2,
- PROT_READ | PROT_WRITE | PROT_EXEC,
- MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
+ 0,
+ 0,
-1, 0) <= 0) {
SysPrintf("mmap() failed: %s\n", strerror(errno));
}
+
#else
- // not all systems allow execute in data segment by default
- if (mprotect(out, 1<<TARGET_SIZE_2, PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
- SysPrintf("mprotect() failed: %s\n", strerror(errno));
+ #if BASE_ADDR_FIXED
+ if (mmap (out, 1<<TARGET_SIZE_2,
+ PROT_READ | PROT_WRITE | PROT_EXEC,
+ MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
+ -1, 0) <= 0) {
+ SysPrintf("mmap() failed: %s\n", strerror(errno));
+ }
+ #else
+ // not all systems allow execute in data segment by default
+ if (mprotect(out, 1<<TARGET_SIZE_2, PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
+ SysPrintf("mprotect() failed: %s\n", strerror(errno));
+ #endif
#endif
#ifdef MUPEN64
rdword=&readmem_dword;
assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
//printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
//printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
- //if(debug)
+ //if(debug)
//printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
//printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
/*if(Count>=312978186) {
unsigned int type,op,op2;
//printf("addr = %x source = %x %x\n", addr,source,source[0]);
-
+
/* Pass 1 disassembly */
for(i=0;!done;i++) {
/* Pass 2 - Register dependencies and branch targets */
unneeded_registers(0,slen-1,0);
-
+
/* Pass 3 - Register allocation */
struct regstat current; // Current register allocations/status
unneeded_reg_upper[0]=1;
current.regmap[HOST_BTREG]=BTREG;
}
-
+
for(i=0;i<slen;i++)
{
if(bt[i])
uint64_t temp_is32=current.is32;
for(j=i-1;j>=0;j--)
{
- if(ba[j]==start+i*4)
+ if(ba[j]==start+i*4)
temp_is32&=branch_regs[j].is32;
}
for(j=i;j<slen;j++)
{
- if(ba[j]==start+i*4)
+ if(ba[j]==start+i*4)
//temp_is32=1;
temp_is32&=p32[j];
}
uint64_t temp_is32=current.is32;
for(j=i-1;j>=0;j--)
{
- if(ba[j]==start+i*4+4)
+ if(ba[j]==start+i*4+4)
temp_is32&=branch_regs[j].is32;
}
for(j=i;j<slen;j++)
{
- if(ba[j]==start+i*4+4)
+ if(ba[j]==start+i*4+4)
//temp_is32=1;
temp_is32&=p32[j];
}
{
//printf("dump %d/r%d\n",hr,r);
current.regmap[hr]=-1;
- if(get_reg(current.regmap,r|64)>=0)
+ if(get_reg(current.regmap,r|64)>=0)
current.regmap[get_reg(current.regmap,r|64)]=-1;
}
}
uint64_t temp_is32=current.is32;
for(j=i-1;j>=0;j--)
{
- if(ba[j]==start+i*4+8)
+ if(ba[j]==start+i*4+8)
temp_is32&=branch_regs[j].is32;
}
for(j=i;j<slen;j++)
{
- if(ba[j]==start+i*4+8)
+ if(ba[j]==start+i*4+8)
//temp_is32=1;
temp_is32&=p32[j];
}
{
//printf("dump %d/r%d\n",hr,r);
current.regmap[hr]=-1;
- if(get_reg(current.regmap,r|64)>=0)
+ if(get_reg(current.regmap,r|64)>=0)
current.regmap[get_reg(current.regmap,r|64)]=-1;
}
}
}
} else {
// First instruction expects CCREG to be allocated
- if(i==0&&hr==HOST_CCREG)
+ if(i==0&&hr==HOST_CCREG)
regs[i].regmap_entry[hr]=CCREG;
else
regs[i].regmap_entry[hr]=-1;
pagespan_alloc(¤t,i);
break;
}
-
+
// Drop the upper half of registers that have become 32-bit
current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
}
} else {
// Branches expect CCREG to be allocated at the target
- if(regmap_pre[i][hr]==CCREG)
+ if(regmap_pre[i][hr]==CCREG)
regs[i].regmap_entry[hr]=CCREG;
else
regs[i].regmap_entry[hr]=-1;
if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
regs[i].waswritten=current.waswritten;
}
-
+
/* Pass 4 - Cull unused host registers */
-
+
uint64_t nr=0;
-
+
for (i=slen-1;i>=0;i--)
{
int hr;
}
// Save it
needed_reg[i]=nr;
-
+
// Deallocate unneeded registers
for(hr=0;hr<HOST_REGS;hr++)
{
}
}
}
-
+
/* Pass 5 - Pre-allocate registers */
-
+
// If a register is allocated during a loop, try to allocate it for the
// entire loop, if possible. This avoids loading/storing registers
// inside of the loop.
-
+
signed char f_regmap[HOST_REGS];
clear_all_regs(f_regmap);
for(i=0;i<slen-1;i++)
{
if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
{
- if(ba[i]>=start && ba[i]<(start+i*4))
+ if(ba[i]>=start && ba[i]<(start+i*4))
if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
}
}
if(ooo[i]) {
- if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
+ if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
f_regmap[hr]=branch_regs[i].regmap[hr];
}else{
- if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
+ if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
f_regmap[hr]=branch_regs[i].regmap[hr];
}
// Avoid dirty->clean transition
if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
{
if(ooo[j]) {
- if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
+ if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
break;
}else{
- if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
+ if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
break;
}
if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
regs[k].isconst&=~(1<<HOST_CCREG);
k++;
}
- regs[j].regmap_entry[HOST_CCREG]=CCREG;
+ regs[j].regmap_entry[HOST_CCREG]=CCREG;
}
// Work backwards from the branch target
if(j>i&&f_regmap[HOST_CCREG]==CCREG)
}
}
}
-
+
// Cache memory offset or tlb map pointer if a register is available
#ifndef HOST_IMM_ADDR32
#ifndef RAM_OFFSET
}
}
#endif
-
+
// This allocates registers (if possible) one instruction prior
// to use, which can avoid a load-use penalty on certain CPUs.
for(i=0;i<slen-1;i++)
}
}
}
- // Load source into target register
+ // Load source into target register
if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
{
}
}
if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
- if(itype[i+1]==LOAD)
+ if(itype[i+1]==LOAD)
hr=get_reg(regs[i+1].regmap,rt1[i+1]);
if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
hr=get_reg(regs[i+1].regmap,FTEMP);
}
}
}
-
+
/* Pass 6 - Optimize clean/dirty state */
clean_registers(0,slen-1,1);
-
+
/* Pass 7 - Identify 32-bit registers */
#ifndef FORCE32
provisional_r32();
u_int r32=0;
-
+
for (i=slen-1;i>=0;i--)
{
int hr;
if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
}
requires_32bit[i]=r32;
-
+
// Dirty registers which are 32-bit, require 32-bit input
// as they will be written as 32-bit values
for(hr=0;hr<HOST_REGS;hr++)
//printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
memcpy(copy,source,slen*4);
copy+=slen*4;
-
+
#ifdef __arm__
__clear_cache((void *)beginning,out);
#endif
-
+
// If we're within 256K of the end of the buffer,
// start over from the beginning. (Is 256K enough?)
if((u_int)out>(u_int)BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
-
+
// Trap writes to any of the pages we compiled
for(i=start>>12;i<=(start+slen*4)>>12;i++) {
invalid_code[i]=0;
invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
#endif
-
+
/* Pass 10 - Free memory by expiring oldest blocks */
-
+
int end=((((int)out-(int)BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
while(expirep!=end)
{
case 3:
// Clear jump_out
#ifdef __arm__
- if((expirep&2047)==0)
+ if((expirep&2047)==0)
do_clear_cache();
#endif
ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);