if(rom != NULL)\r
*(unsigned long *)(rom+romsize) = 0xFFFE4EFA; // 4EFA FFFE byteswapped\r
\r
- SRam.resize=1;\r
Pico.rom=rom;\r
Pico.romsize=romsize;\r
\r
+ // setup correct memory map for loaded ROM\r
+ if (PicoMCD & 1)\r
+ PicoMemSetupCD();\r
+ else PicoMemSetup();\r
+ PicoMemReset();\r
+\r
+ if (!(PicoMCD & 1))\r
+ PicoCartDetect();\r
+\r
return PicoReset(1);\r
}\r
\r
return 0;\r
}\r
\r
+static int name_cmp(const char *name)\r
+{\r
+ int i, len = strlen(name);\r
+ const char *name_rom = (const char *)Pico.rom+0x150;\r
+ for (i = 0; i < len; i++)\r
+ if (name[i] != name_rom[i^1])\r
+ return 1;\r
+ return 0;\r
+}\r
+\r
+/* various cart-specific things, which can't be handled by generic code */\r
+void PicoCartDetect(void)\r
+{\r
+ int sram_size = 0, csum;\r
+ if(SRam.data) free(SRam.data); SRam.data=0;\r
+ Pico.m.sram_reg = 0;\r
+\r
+ csum = PicoRead32(0x18c) & 0xffff;\r
+\r
+ if (Pico.rom[0x1B1] == 'R' && Pico.rom[0x1B0] == 'A')\r
+ {\r
+ if (Pico.rom[0x1B2] & 0x40)\r
+ {\r
+ // EEPROM\r
+ SRam.start = PicoRead32(0x1B4) & ~1; // zero address is used for clock by some games\r
+ SRam.end = PicoRead32(0x1B8);\r
+ sram_size = 0x2000;\r
+ Pico.m.sram_reg |= 4;\r
+ } else {\r
+ // normal SRAM\r
+ SRam.start = PicoRead32(0x1B4) & 0xFFFF00;\r
+ SRam.end = PicoRead32(0x1B8) | 1;\r
+ sram_size = SRam.end - SRam.start + 1;\r
+ }\r
+ Pico.m.sram_reg |= 0x10; // SRAM was detected\r
+ }\r
+ if (sram_size <= 0)\r
+ {\r
+ // some games may have bad headers, like S&K and Sonic3\r
+ // note: majority games use 0x200000 as starting address, but there are some which\r
+ // use something else (0x300000 by HardBall '95). Luckily they have good headers.\r
+ SRam.start = 0x200000;\r
+ SRam.end = 0x203FFF;\r
+ sram_size = 0x004000;\r
+ }\r
+\r
+ if (sram_size)\r
+ {\r
+ SRam.data = (unsigned char *) calloc(sram_size, 1);\r
+ if(!SRam.data) return;\r
+ }\r
+ SRam.changed = 0;\r
+\r
+ // set EEPROM defaults, in case it gets detected\r
+ SRam.eeprom_type = 0; // 7bit (24C01)\r
+ SRam.eeprom_abits = 3; // eeprom access must be odd addr for: bit0 ~ cl, bit1 ~ in\r
+ SRam.eeprom_bit_cl = 1;\r
+ SRam.eeprom_bit_in = 0;\r
+ SRam.eeprom_bit_out= 0;\r
+\r
+ // some known EEPROM data (thanks to EkeEke)\r
+ if (name_cmp("COLLEGE SLAM") == 0 ||\r
+ name_cmp("FRANK THOMAS BIGHURT BASEBAL") == 0)\r
+ {\r
+ SRam.eeprom_type = 3;\r
+ SRam.eeprom_abits = 2;\r
+ SRam.eeprom_bit_cl = 0;\r
+ }\r
+ else if (name_cmp("NBA JAM TOURNAMENT EDITION") == 0 ||\r
+ name_cmp("NFL QUARTERBACK CLUB") == 0)\r
+ {\r
+ SRam.eeprom_type = 2;\r
+ SRam.eeprom_abits = 2;\r
+ SRam.eeprom_bit_cl = 0;\r
+ }\r
+ else if (name_cmp("NBA JAM") == 0)\r
+ {\r
+ SRam.eeprom_type = 2;\r
+ SRam.eeprom_bit_out = 1;\r
+ SRam.eeprom_abits = 0;\r
+ }\r
+ else if (name_cmp("NHLPA HOCKEY '93") == 0 ||\r
+ name_cmp("NHLPA Hockey '93") == 0 ||\r
+ name_cmp("RINGS OF POWER") == 0)\r
+ {\r
+ SRam.start = SRam.end = 0x200000;\r
+ Pico.m.sram_reg = 0x14;\r
+ SRam.eeprom_abits = 0;\r
+ SRam.eeprom_bit_cl = 6;\r
+ SRam.eeprom_bit_in = 7;\r
+ SRam.eeprom_bit_out= 7;\r
+ }\r
+ else if ( name_cmp("MICRO MACHINES II") == 0 ||\r
+ (name_cmp(" ") == 0 && // Micro Machines {Turbo Tournament '96, Military - It's a Blast!}\r
+ (csum == 0x165e || csum == 0x168b || csum == 0xCEE0 || csum == 0x2C41)))\r
+ {\r
+ SRam.start = 0x300000;\r
+ SRam.end = 0x380001;\r
+ Pico.m.sram_reg = 0x14;\r
+ SRam.eeprom_type = 2;\r
+ SRam.eeprom_abits = 0;\r
+ SRam.eeprom_bit_cl = 1;\r
+ SRam.eeprom_bit_in = 0;\r
+ SRam.eeprom_bit_out= 7;\r
+ }\r
+\r
+ // Some games malfunction if SRAM is not filled with 0xff\r
+ if (name_cmp("DINO DINI'S SOCCER") == 0 ||\r
+ name_cmp("MICRO MACHINES II") == 0)\r
+ memset(SRam.data, 0xff, sram_size);\r
+}\r
+\r
{\r
unsigned int sreg = Pico.m.sram_reg;\r
if(!(sreg & 0x10) && (sreg & 1) && a > 0x200001) { // not yet detected SRAM\r
+ elprintf(EL_SRAMIO, "normal sram detected.");\r
Pico.m.sram_reg|=0x10; // should be normal SRAM\r
}\r
if(sreg & 4) // EEPROM read\r
\r
static void SRAMWrite(u32 a, u32 d)\r
{\r
- dprintf("sram_w: %06x, %08x @%06x", a&0xffffff, d, SekPc);\r
unsigned int sreg = Pico.m.sram_reg;\r
if(!(sreg & 0x10)) {\r
// not detected SRAM\r
if((a&~1)==0x200000) {\r
- Pico.m.sram_reg|=4; // this should be a game with EEPROM (like NBA Jam)\r
+ elprintf(EL_SRAMIO, "eeprom detected.");\r
+ sreg|=4; // this should be a game with EEPROM (like NBA Jam)\r
SRam.start=0x200000; SRam.end=SRam.start+1;\r
- }\r
- Pico.m.sram_reg|=0x10;\r
+ } else\r
+ elprintf(EL_SRAMIO, "normal sram detected.");\r
+ sreg|=0x10;\r
+ Pico.m.sram_reg=sreg;\r
}\r
if(sreg & 4) { // EEPROM write\r
- if(SekCyclesDoneT()-lastSSRamWrite < 46) {\r
+ // this diff must be at most 16 for NBA Jam to work\r
+ if(SekCyclesDoneT()-lastSSRamWrite < 16) {\r
// just update pending state\r
+ elprintf(EL_EEPROM, "eeprom: skip because cycles=%i", SekCyclesDoneT()-lastSSRamWrite);\r
SRAMUpdPending(a, d);\r
} else {\r
+ int old=sreg;\r
SRAMWriteEEPROM(sreg>>6); // execute pending\r
SRAMUpdPending(a, d);\r
- lastSSRamWrite = SekCyclesDoneT();\r
+ if ((old^Pico.m.sram_reg)&0xc0) // update time only if SDA/SCL changed\r
+ lastSSRamWrite = SekCyclesDoneT();\r
}\r
} else if(!(sreg & 2)) {\r
u8 *pm=(u8 *)(SRam.data-SRam.start+a);\r
{\r
u32 d=0;\r
\r
- dprintf("strange r%i: %06x @%06x", realsize, a&0xffffff, SekPc);\r
-\r
// for games with simple protection devices, discovered by Haze\r
// some dumb detection is used, but that should be enough to make things work\r
if ((a>>22) == 1 && Pico.romsize >= 512*1024) {\r
}\r
\r
end:\r
- dprintf("ret = %04x", d);\r
+ elprintf(EL_UIO, "strange r%i: [%06x] %04x @%06x", realsize, a&0xffffff, d, SekPc);\r
return d;\r
}\r
\r
static void OtherWrite8End(u32 a,u32 d,int realsize)\r
{\r
// sram\r
- //if(a==0x200000) dprintf("cc : %02x @ %06x [%i|%i]", d, SekPc, SekCyclesDoneT(), SekCyclesDone());\r
- //if(a==0x200001) dprintf("w8 : %02x @ %06x [%i]", d, SekPc, SekCyclesDoneT());\r
if(a >= SRam.start && a <= SRam.end) {\r
+ elprintf(EL_SRAMIO, "sram w8 [%06x] %02x @ %06x", a, d, SekPc);\r
SRAMWrite(a, d);\r
return;\r
}\r
#else\r
// sram access register\r
if(a == 0xA130F1) {\r
- dprintf("sram reg=%02x", d);\r
+ elprintf(EL_SRAMIO, "sram reg=%02x", d);\r
Pico.m.sram_reg &= ~3;\r
Pico.m.sram_reg |= (u8)(d&3);\r
return;\r
}\r
#endif\r
- dprintf("strange w%i: %06x, %08x @%06x", realsize, a&0xffffff, d, SekPc);\r
+ elprintf(EL_UIO, "strange w%i: %06x, %08x @%06x", realsize, a&0xffffff, d, SekPc);\r
\r
if(a >= 0xA13004 && a < 0xA13040) {\r
// dumb 12-in-1 or 4-in-1 banking support\r
// sram\r
if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {\r
d = SRAMRead(a);\r
+ elprintf(EL_SRAMIO, "sram r8 [%06x] %02x @ %06x", a, d, SekPc);\r
goto end;\r
}\r
#endif\r
\r
d=OtherRead16(a&~1, 8); if ((a&1)==0) d>>=8;\r
\r
- end:\r
-\r
- //if ((a&0xe0ffff)==0xe0AE57+0x69c)\r
- // dprintf("r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPc);\r
- //if ((a&0xe0ffff)==0xe0a9ba+0x69c)\r
- // dprintf("r8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);\r
-\r
- //if(a==0x200001||a==0x200000) printf("r8 : %02x [%06x] @ %06x [%i]\n", d, a, SekPc, SekCyclesDoneT());\r
- //dprintf("r8 : %06x, %02x @%06x [%03i]", a&0xffffff, (u8)d, SekPc, Pico.m.scanline);\r
+end:\r
#ifdef __debug_io\r
dprintf("r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPc);\r
#endif\r
if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {\r
d = SRAMRead(a);\r
d |= d<<8;\r
+ elprintf(EL_SRAMIO, "sram r16 [%06x] %04x @ %06x", a, d, SekPc);\r
goto end;\r
}\r
#endif\r
\r
d = OtherRead16(a, 16);\r
\r
- end:\r
- //if ((a&0xe0ffff)==0xe0AF0E+0x69c||(a&0xe0ffff)==0xe0A9A8+0x69c||(a&0xe0ffff)==0xe0A9AA+0x69c||(a&0xe0ffff)==0xe0A9AC+0x69c)\r
- // dprintf("r16: %06x, %04x @%06x", a&0xffffff, d, SekPc);\r
- //if(a==0x200000) printf("r16: %04x @ %06x [%i]\n", d, SekPc, SekCyclesDoneT());\r
-\r
+end:\r
#ifdef __debug_io\r
dprintf("r16: %06x, %04x @%06x", a&0xffffff, d, SekPc);\r
#endif\r
if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {\r
d = (SRAMRead(a)<<16)|SRAMRead(a+2);\r
d |= d<<8;\r
+ elprintf(EL_SRAMIO, "sram r32 [%06x] %08x @ %06x", a, d, SekPc);\r
goto end;\r
}\r
\r
\r
d = (OtherRead16(a, 32)<<16)|OtherRead16(a+2, 32);\r
\r
- end:\r
- //if(a==0x200000) printf("r32: %08x @ %06x [%i]\n", d, SekPc, SekCyclesDoneT());\r
+end:\r
#ifdef __debug_io\r
dprintf("r32: %06x, %08x @%06x", a&0xffffff, d, SekPc);\r
#endif\r
#if defined(EMU_C68K) && defined(EMU_M68K)\r
lastwrite_cyc_d[lwp_cyc++&15] = d;\r
#endif\r
- //if ((a&0xe0ffff)==0xe0AF0E+0x69c||(a&0xe0ffff)==0xe0A9A8+0x69c||(a&0xe0ffff)==0xe0A9AA+0x69c||(a&0xe0ffff)==0xe0A9AC+0x69c)\r
- // dprintf("w16: %06x, %04x @%06x", a&0xffffff, d, SekPc);\r
- //if(a==0x200000) printf("w16: %04x @ %06x [%i]\n", d, SekPc, SekCyclesDoneT());\r
\r
if ((a&0xe00000)==0xe00000) { *(u16 *)(Pico.ram+(a&0xfffe))=d; return; } // Ram\r
log_io(a, 16, 1);\r
#if defined(EMU_C68K) && defined(EMU_M68K)\r
lastwrite_cyc_d[lwp_cyc++&15] = d;\r
#endif\r
- //if(a==0x200000) printf("w32: %08x @ %06x [%i]\n", d, SekPc, SekCyclesDoneT());\r
\r
if ((a&0xe00000)==0xe00000)\r
{\r
void PicoWriteCD16w(unsigned int a, unsigned short d);\r
void PicoWriteCD32w(unsigned int a, unsigned int d);\r
\r
+/* it appears that Musashi doesn't always mask the unused bits */\r
unsigned int m68k_read_memory_8(unsigned int address)\r
{\r
- return (PicoMCD&1) ? PicoReadCD8w(address) : PicoRead8(address);\r
+ unsigned int d = (PicoMCD&1) ? PicoReadCD8w(address) : PicoRead8(address);\r
+ return d&0xff;\r
}\r
\r
unsigned int m68k_read_memory_16(unsigned int address)\r
{\r
- return (PicoMCD&1) ? PicoReadCD16w(address) : PicoRead16(address);\r
+ unsigned int d = (PicoMCD&1) ? PicoReadCD16w(address) : PicoRead16(address);\r
+ return d&0xffff;\r
}\r
\r
unsigned int m68k_read_memory_32(unsigned int address)\r
bx lr\r
\r
m_read8_above_rom:\r
+ @ might still be SRam (Micro Machines, HardBall '95)\r
+ ldr r2, =(SRam)\r
+ ldr r3, =(Pico+0x22200)\r
+ ldr r1, [r2, #8] @ SRam.end\r
+ cmp r0, r1\r
+ bgt m_read8_ar_nosram\r
+ ldr r1, [r2, #4] @ SRam.start\r
+ cmp r0, r1\r
+ blt m_read8_ar_nosram\r
+ ldrb r1, [r3, #0x11] @ Pico.m.sram_reg\r
+ tst r1, #5\r
+ bne SRAMRead\r
+m_read8_ar_nosram:\r
stmfd sp!,{r0,lr}\r
bic r0, r0, #1\r
mov r1, #8\r
bx lr\r
\r
m_read16_above_rom:\r
+ @ might still be SRam\r
+ ldr r2, =(SRam)\r
+ ldr r3, =(Pico+0x22200)\r
+ ldr r1, [r2, #8] @ SRam.end\r
bic r0, r0, #1\r
+ cmp r0, r1\r
+ bgt m_read16_ar_nosram\r
+ ldr r1, [r2, #4] @ SRam.start\r
+ cmp r0, r1\r
+ blt m_read16_ar_nosram\r
+ ldrb r1, [r3, #0x11] @ Pico.m.sram_reg\r
+ tst r1, #5\r
+ beq m_read16_ar_nosram\r
+ stmfd sp!,{lr}\r
+ bl SRAMRead\r
+ orr r0, r0, r0, lsl #8\r
+ ldmfd sp!,{pc}\r
+m_read16_ar_nosram:\r
mov r1, #16\r
b OtherRead16End\r
\r
#ifndef _CD_MEMORY_C
if (a >= SRam.start && a <= SRam.end) {
+ elprintf(EL_SRAMIO, "sram w16 [%06x] %04x @ %06x", a, d, SekPc);
if ((a&0x16)==0x10) { // detected, not EEPROM, write not disabled
u8 *pm=(u8 *)(SRam.data-SRam.start+a);
*pm++=d>>8;
SRam.changed = 1;
}
else
- SRAMWrite(a, d); // ??
+ SRAMWrite(a, d);
return;
}
#else
// rarely used EEPROM SRAM code\r
// known games which use this:\r
// Wonder Boy in Monster World, Megaman - The Wily Wars (X24C01, 128 bytes)\r
-// NFL Quarterback Club*, Frank Thomas Big Hurt Baseball (X24C04?)\r
-// College Slam, Blockbuster World Video Game Championship II, NBA Jam (X24C04?)\r
-// HardBall '95\r
\r
-// the above sports games use addr 0x200000 for SCL line (handled in Memory.c)\r
+// (see Genesis Plus for Wii/GC code and docs for info,\r
+// full game list and better code).\r
\r
unsigned int lastSSRamWrite = 0xffff0000;\r
\r
-// sram_reg: LAtd sela (L=pending SCL, A=pending SDA, t=type(1==uses 0x200000 for SCL and 2K bytes),\r
+// sram_reg: LAtd sela (L=pending SCL, A=pending SDA, t=(unused),\r
// d=SRAM was detected (header or by access), s=started, e=save is EEPROM, l=old SCL, a=old SDA)\r
PICO_INTERNAL void SRAMWriteEEPROM(unsigned int d) // ???? ??la (l=SCL, a=SDA)\r
{\r
- unsigned int sreg = Pico.m.sram_reg, saddr = Pico.m.sram_addr, scyc = Pico.m.sram_cycle, ssa = Pico.m.sram_slave;\r
+ unsigned int sreg = Pico.m.sram_reg, saddr = Pico.m.eeprom_addr, scyc = Pico.m.eeprom_cycle, ssa = Pico.m.eeprom_slave;\r
\r
- //printf("EEPROM write %i\n", d&3);\r
- sreg |= saddr&0xc000; // we store word count in add reg: dw?a aaaa ... (d=word count detected, w=words(0==use 2 words, else 1))\r
+ elprintf(EL_EEPROM, "eeprom: scl/sda: %i/%i -> %i/%i, newtime=%i", (sreg&2)>>1, sreg&1,\r
+ (d&2)>>1, d&1, SekCyclesDoneT()-lastSSRamWrite);\r
saddr&=0x1fff;\r
\r
if(sreg & d & 2) {\r
// SCL was and is still high..\r
if((sreg & 1) && !(d&1)) {\r
// ..and SDA went low, means it's a start command, so clear internal addr reg and clock counter\r
- //dprintf("-start-");\r
- if(!(sreg&0x8000) && scyc >= 9) {\r
- if(scyc != 28) sreg |= 0x4000; // 1 word\r
- //dprintf("detected word count: %i", scyc==28 ? 2 : 1);\r
- sreg |= 0x8000;\r
- }\r
+ elprintf(EL_EEPROM, "eeprom: -start-");\r
//saddr = 0;\r
scyc = 0;\r
sreg |= 8;\r
} else if(!(sreg & 1) && (d&1)) {\r
// SDA went high == stop command\r
- //dprintf("-stop-");\r
+ elprintf(EL_EEPROM, "eeprom: -stop-");\r
sreg &= ~8;\r
}\r
}\r
- else if((sreg & 8) && !(sreg & 2) && (d&2)) {\r
+ else if((sreg & 8) && !(sreg & 2) && (d&2))\r
+ {\r
// we are started and SCL went high - next cycle\r
scyc++; // pre-increment\r
- if(sreg & 0x20) {\r
+ if(SRam.eeprom_type) {\r
// X24C02+\r
if((ssa&1) && scyc == 18) {\r
scyc = 9;\r
saddr++; // next address in read mode\r
- if(sreg&0x4000) saddr&=0xff; else saddr&=0x1fff; // mask\r
+ /*if(SRam.eeprom_type==2) saddr&=0xff; else*/ saddr&=0x1fff; // mask\r
}\r
- else if((sreg&0x4000) && scyc == 27) scyc = 18;\r
+ else if(SRam.eeprom_type == 2 && scyc == 27) scyc = 18;\r
else if(scyc == 36) scyc = 27;\r
} else {\r
// X24C01\r
if(saddr&1) { saddr+=2; saddr&=0xff; } // next addr in read mode\r
}\r
}\r
- //dprintf("scyc: %i", scyc);\r
+ elprintf(EL_EEPROM, "eeprom: scyc: %i", scyc);\r
}\r
- else if((sreg & 8) && (sreg & 2) && !(d&2)) {\r
+ else if((sreg & 8) && (sreg & 2) && !(d&2))\r
+ {\r
// we are started and SCL went low (falling edge)\r
- if(sreg & 0x20) {\r
+ if(SRam.eeprom_type) {\r
// X24C02+\r
if(scyc == 9 || scyc == 18 || scyc == 27); // ACK cycles\r
- else if( (!(sreg&0x4000) && scyc > 27) || ((sreg&0x4000) && scyc > 18) ) {\r
+ else if( (SRam.eeprom_type == 3 && scyc > 27) || (SRam.eeprom_type == 2 && scyc > 18) ) {\r
if(!(ssa&1)) {\r
// data write\r
unsigned char *pm=SRam.data+saddr;\r
*pm <<= 1; *pm |= d&1;\r
if(scyc == 26 || scyc == 35) {\r
saddr=(saddr&~0xf)|((saddr+1)&0xf); // only 4 (?) lowest bits are incremented\r
- //dprintf("w done: %02x; addr inc: %x", *pm, saddr);\r
+ elprintf(EL_EEPROM, "eeprom: write done, addr inc to: %x, last byte=%02x", saddr, *pm);\r
}\r
SRam.changed = 1;\r
}\r
if(!(ssa&1)) {\r
// we latch another addr bit\r
saddr<<=1;\r
- if(sreg&0x4000) saddr&=0xff; else saddr&=0x1fff; // mask\r
+ if(SRam.eeprom_type == 2) saddr&=0xff; else saddr&=0x1fff; // mask\r
saddr|=d&1;\r
- //if(scyc==17||scyc==26) dprintf("addr reg done: %x", saddr);\r
+ if(scyc==17||scyc==26) {\r
+ elprintf(EL_EEPROM, "eeprom: addr reg done: %x", saddr);\r
+ if(scyc==17&&SRam.eeprom_type==2) { saddr&=0xff; saddr|=(ssa<<7)&0x700; } // add device bits too\r
+ }\r
}\r
} else {\r
// slave address\r
ssa<<=1; ssa|=d&1;\r
- //if(scyc==8) dprintf("slave done: %x", ssa);\r
+ if(scyc==8) elprintf(EL_EEPROM, "eeprom: slave done: %x", ssa);\r
}\r
} else {\r
// X24C01\r
*pm <<= 1; *pm |= d&1;\r
if(scyc == 17) {\r
saddr=(saddr&0xf9)|((saddr+2)&6); // only 2 lowest bits are incremented\r
- //dprintf("addr inc: %x", saddr>>1);\r
+ elprintf(EL_EEPROM, "eeprom: write done, addr inc to: %x, last byte=%02x", saddr>>1, *pm);\r
}\r
SRam.changed = 1;\r
}\r
} else {\r
// we latch another addr bit\r
saddr<<=1; saddr|=d&1; saddr&=0xff;\r
- //if(scyc==8) dprintf("addr done: %x", saddr>>1);\r
+ if(scyc==8) elprintf(EL_EEPROM, "eeprom: addr done: %x", saddr>>1);\r
}\r
}\r
}\r
\r
sreg &= ~3; sreg |= d&3; // remember SCL and SDA\r
- Pico.m.sram_reg = (unsigned char) sreg;\r
- Pico.m.sram_addr = (unsigned short)(saddr|(sreg&0xc000));\r
- Pico.m.sram_cycle= (unsigned char) scyc;\r
- Pico.m.sram_slave= (unsigned char) ssa;\r
+ Pico.m.sram_reg = (unsigned char) sreg;\r
+ Pico.m.eeprom_cycle= (unsigned char) scyc;\r
+ Pico.m.eeprom_slave= (unsigned char) ssa;\r
+ Pico.m.eeprom_addr = (unsigned short)saddr;\r
}\r
\r
PICO_INTERNAL_ASM unsigned int SRAMReadEEPROM(void)\r
{\r
- unsigned int shift, d=0;\r
- unsigned int sreg, saddr, scyc, ssa;\r
+ unsigned int shift, d;\r
+ unsigned int sreg, saddr, scyc, ssa, interval;\r
\r
// flush last pending write\r
SRAMWriteEEPROM(Pico.m.sram_reg>>6);\r
\r
- sreg = Pico.m.sram_reg; saddr = Pico.m.sram_addr&0x1fff; scyc = Pico.m.sram_cycle; ssa = Pico.m.sram_slave;\r
-// if(!(sreg & 2) && (sreg&0x80)) scyc++; // take care of raising edge now to compensate lag\r
+ sreg = Pico.m.sram_reg; saddr = Pico.m.eeprom_addr&0x1fff; scyc = Pico.m.eeprom_cycle; ssa = Pico.m.eeprom_slave;\r
+ interval = SekCyclesDoneT()-lastSSRamWrite;\r
+ d = (sreg>>6)&1; // use SDA as "open bus"\r
\r
- if(SekCyclesDoneT()-lastSSRamWrite < 46) {\r
- // data was just written, there was no time to respond (used by sports games)\r
- d = (sreg>>6)&1;\r
- } else if((sreg & 8) && scyc > 9 && scyc != 18 && scyc != 27) {\r
+ // NBA Jam is nasty enough to read <before> raising the SCL and starting the new cycle.\r
+ // this is probably valid because data changes occur while SCL is low and data can be read\r
+ // before it's actual cycle begins.\r
+ if (!(sreg&0x80) && interval >= 24) {\r
+ elprintf(EL_EEPROM, "eeprom: early read, cycles=%i", interval);\r
+ scyc++;\r
+ }\r
+\r
+ if (!(sreg & 8)); // not started, use open bus\r
+ else if (scyc == 9 || scyc == 18 || scyc == 27) {\r
+ elprintf(EL_EEPROM, "eeprom: r ack");\r
+ d = 0;\r
+ } else if (scyc > 9 && scyc < 18) {\r
// started and first command word received\r
shift = 17-scyc;\r
- if(sreg & 0x20) {\r
+ if (SRam.eeprom_type) {\r
// X24C02+\r
- if(ssa&1) {\r
- //dprintf("read: addr %02x, cycle %i, reg %02x", saddr, scyc, sreg);\r
+ if (ssa&1) {\r
+ elprintf(EL_EEPROM, "eeprom: read: addr %02x, cycle %i, reg %02x", saddr, scyc, sreg);\r
+ if (shift==0) elprintf(EL_EEPROM, "eeprom: read done, byte %02x", SRam.data[saddr]);\r
d = (SRam.data[saddr]>>shift)&1;\r
}\r
} else {\r
// X24C01\r
- if(saddr&1) {\r
+ if (saddr&1) {\r
+ elprintf(EL_EEPROM, "eeprom: read: addr %02x, cycle %i, reg %02x", saddr>>1, scyc, sreg);\r
+ if (shift==0) elprintf(EL_EEPROM, "eeprom: read done, byte %02x", SRam.data[saddr>>1]);\r
d = (SRam.data[saddr>>1]>>shift)&1;\r
}\r
}\r
}\r
- //else dprintf("r ack");\r
\r
- return d;\r
+ return (d << SRam.eeprom_bit_out);\r
}\r
\r
PICO_INTERNAL void SRAMUpdPending(unsigned int a, unsigned int d)\r
{\r
- unsigned int sreg = Pico.m.sram_reg;\r
-\r
- if(!(a&1)) sreg|=0x20;\r
-\r
- if(sreg&0x20) { // address through 0x200000\r
- if(!(a&1)) {\r
- sreg&=~0x80;\r
- sreg|=d<<7;\r
- } else {\r
- sreg&=~0x40;\r
- sreg|=(d<<6)&0x40;\r
- }\r
- } else {\r
- sreg&=~0xc0;\r
- sreg|=d<<6;\r
+ unsigned int d1, sreg = Pico.m.sram_reg;\r
+\r
+ if (!((SRam.eeprom_abits^a)&1))\r
+ {\r
+ // SCL\r
+ sreg &= ~0x80;\r
+ d1 = (d >> SRam.eeprom_bit_cl) & 1;\r
+ sreg |= d1<<7;\r
+ }\r
+ if (!(((SRam.eeprom_abits>>1)^a)&1))\r
+ {\r
+ // SDA in\r
+ sreg &= ~0x40;\r
+ d1 = (d >> SRam.eeprom_bit_in) & 1;\r
+ sreg |= d1<<6;\r
}\r
\r
Pico.m.sram_reg = (unsigned char) sreg;\r
int emustatus = 0;\r
void (*PicoWriteSound)(int len) = 0; // called once per frame at the best time to send sound buffer (PsndOut) to hardware\r
\r
-struct PicoSRAM SRam;\r
+struct PicoSRAM SRam = {0,};\r
int z80startCycle, z80stopCycle; // in 68k cycles\r
//int z80ExtraCycles = 0;\r
int PicoPad[2]; // Joypads, format is SACB RLDU\r
PicoInitMCD();\r
\r
SRam.data=0;\r
- SRam.resize=1;\r
\r
return 0;\r
}\r
unsigned int region=0;\r
int support=0,hw=0,i=0;\r
unsigned char pal=0;\r
+ unsigned char sram_reg=Pico.m.sram_reg; // must be preserved\r
\r
if (Pico.romsize<=0) return 1;\r
\r
- // setup correct memory map\r
- if (PicoMCD & 1)\r
- PicoMemSetupCD();\r
- else PicoMemSetup();\r
PicoMemReset();\r
SekReset();\r
// s68k doesn't have the TAS quirk, so we just globally set normal TAS handler in MCD mode (used by Batman games).\r
return 0;\r
}\r
\r
- if(SRam.resize) {\r
- int sram_size = 0;\r
- if(SRam.data) free(SRam.data); SRam.data=0;\r
- Pico.m.sram_reg = 0;\r
-\r
- if(*(Pico.rom+0x1B1) == 'R' && *(Pico.rom+0x1B0) == 'A') {\r
- if(*(Pico.rom+0x1B2) & 0x40) {\r
- // EEPROM\r
- // what kind of EEPROMs are actually used? X24C02? X24C04? (X24C01 has only 128), but we will support up to 8K\r
- SRam.start = PicoRead32(0x1B4) & ~1; // zero address is used for clock by some games\r
- SRam.end = PicoRead32(0x1B8);\r
- sram_size = 0x2000;\r
- Pico.m.sram_reg = 4;\r
- } else {\r
- // normal SRAM\r
- SRam.start = PicoRead32(0x1B4) & 0xFFFF00;\r
- SRam.end = PicoRead32(0x1B8) | 1;\r
- sram_size = SRam.end - SRam.start + 1;\r
- }\r
- Pico.m.sram_reg |= 0x10; // SRAM was detected\r
- }\r
- if(sram_size <= 0) {\r
- // some games may have bad headers, like S&K and Sonic3\r
- SRam.start = 0x200000;\r
- SRam.end = 0x203FFF;\r
- sram_size = 0x004000;\r
- }\r
+ // reset sram state; enable sram access by default if it doesn't overlap with ROM\r
+ Pico.m.sram_reg=sram_reg&0x14;\r
+ if (!(Pico.m.sram_reg&4) && Pico.romsize <= SRam.start) Pico.m.sram_reg |= 1;\r
\r
- // enable sram access by default if it doesn't overlap with ROM\r
- if(Pico.romsize <= SRam.start) Pico.m.sram_reg |= 1;\r
- SRam.reg_back = Pico.m.sram_reg;\r
-\r
- if(sram_size) {\r
- SRam.data = (unsigned char *) calloc(sram_size, 1);\r
- if(!SRam.data) return 1;\r
- }\r
- SRam.resize=0;\r
- // Dino Dini's Soccer malfunctions if SRAM is not filled with 0xff\r
- if (strncmp((char *)Pico.rom+0x150, "IDOND NI'I", 10) == 0)\r
- memset(SRam.data, 0xff, sram_size);\r
- elprintf(EL_STATUS, "sram: det: %i; eeprom: %i; start: %06x; end: %06x",\r
- (Pico.m.sram_reg>>4)&1, (Pico.m.sram_reg>>2)&1, SRam.start, SRam.end);\r
- }\r
-\r
- Pico.m.sram_reg = SRam.reg_back; // restore sram_reg\r
- SRam.changed = 0;\r
+ elprintf(EL_STATUS, "sram: det: %i; eeprom: %i; start: %06x; end: %06x",\r
+ (Pico.m.sram_reg>>4)&1, (Pico.m.sram_reg>>2)&1, SRam.start, SRam.end);\r
\r
return 0;\r
}\r
\r
+\r
// dma2vram settings are just hacks to unglitch Legend of Galahad (needs <= 104 to work)\r
// same for Outrunners (92-121, when active is set to 24)\r
static const int dma_timings[] = {\r
sprintf(dstrp, "mode set 4: %02x\n", (r=reg[0xC])); dstrp+=strlen(dstrp);\r
sprintf(dstrp, "interlace: %i%i, cells: %i, shadow: %i\n", bit(r,2), bit(r,1), (r&0x80) ? 40 : 32, bit(r,3));\r
dstrp+=strlen(dstrp);\r
- sprintf(dstrp, "scroll size: w: %i, h: %i SRAM: %i; eeprom: %i\n", reg[0x10]&3, (reg[0x10]&0x30)>>4,\r
- bit(Pico.m.sram_reg, 4), bit(Pico.m.sram_reg, 2)); dstrp+=strlen(dstrp);\r
+ sprintf(dstrp, "scroll size: w: %i, h: %i SRAM: %i; eeprom: %i (%i)\n", reg[0x10]&3, (reg[0x10]&0x30)>>4,\r
+ bit(Pico.m.sram_reg, 4), bit(Pico.m.sram_reg, 2), SRam.eeprom_type); dstrp+=strlen(dstrp);\r
sprintf(dstrp, "sram range: %06x-%06x, reg: %02x\n", SRam.start, SRam.end, Pico.m.sram_reg); dstrp+=strlen(dstrp);\r
sprintf(dstrp, "pend int: v:%i, h:%i, vdp status: %04x\n", bit(pv->pending_ints,5), bit(pv->pending_ints,4), pv->status);\r
dstrp+=strlen(dstrp);\r
// alt_renderer, 6button_gamepad, accurate_timing, accurate_sprites,\r
// draw_no_32col_border, external_ym2612, enable_cd_pcm, enable_cd_cdda\r
// enable_cd_gfx, cd_perfect_sync, soft_32col_scaling, enable_cd_ramcart\r
+// disable_vdp_fifo\r
extern int PicoOpt;\r
extern int PicoVer;\r
extern int PicoSkipFrame; // skip rendering frame, but still do sound (if enabled) and emulation stuff\r
unsigned char z80_fakeval;\r
unsigned char pad0;\r
unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
- unsigned short sram_addr; // EEPROM address register\r
- unsigned char sram_cycle; // EEPROM SRAM cycle number\r
- unsigned char sram_slave; // EEPROM slave word for X24C02 and better SRAMs\r
+ unsigned short eeprom_addr; // EEPROM address register\r
+ unsigned char eeprom_cycle; // EEPROM SRAM cycle number\r
+ unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
unsigned char prot_bytes[2]; // simple protection faking\r
unsigned short dma_xfers;\r
unsigned char pad[2];\r
unsigned char *data; // actual data\r
unsigned int start; // start address in 68k address space\r
unsigned int end;\r
- unsigned char resize; // 0c: 1=SRAM size changed and needs to be reallocated on PicoReset\r
- unsigned char reg_back; // copy of Pico.m.sram_reg to set after reset\r
+ unsigned char unused1; // 0c: unused\r
+ unsigned char unused2;\r
unsigned char changed;\r
- unsigned char pad;\r
+ unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: device with 2 addr words (X24C02+), 3: dev with 3 addr words\r
+ unsigned char eeprom_abits; // eeprom access must be odd addr for: bit0 ~ cl, bit1 ~ out\r
+ unsigned char eeprom_bit_cl; // bit number for cl\r
+ unsigned char eeprom_bit_in; // bit number for in\r
+ unsigned char eeprom_bit_out; // bit number for out\r
};\r
\r
// MCD\r
PICO_INTERNAL int PicoCdSaveState(void *file);\r
PICO_INTERNAL int PicoCdLoadState(void *file);\r
\r
+// Cart.c\r
+PICO_INTERNAL void PicoCartDetect(void);\r
+\r
// Draw.c\r
PICO_INTERNAL int PicoLine(int scan);\r
PICO_INTERNAL void PicoFrameStart(void);\r
#define EL_VDPDMA 0x0040 /* VDP DMA transfers and their timing */\r
#define EL_BUSREQ 0x0080 /* z80 busreq r/w */\r
#define EL_Z80BNK 0x0100 /* z80 i/o through bank area */\r
+#define EL_SRAMIO 0x0200 /* sram i/o */\r
+#define EL_EEPROM 0x0400 /* eeprom debug */\r
+#define EL_UIO 0x0800 /* unmapped i/o */\r
+#define EL_IO 0x1000 /* all i/o */\r
\r
#define EL_STATUS 0x4000 /* status messages */\r
#define EL_ANOMALY 0x8000 /* some unexpected conditions */\r
else\r
{\r
// preliminary FIFO emulation for Chaos Engine, The (E)\r
- if(!(pvid->status&8) && (pvid->reg[1]&0x40) && Pico.m.scanline!=-1) // active display, accurate mode?\r
+ if(!(pvid->status&8) && (pvid->reg[1]&0x40) && Pico.m.scanline!=-1 && !(PicoOpt&0x10000)) // active display, accurate mode?\r
{\r
pvid->status&=~0x200; // FIFO no longer empty\r
pvid->lwrite_cnt++;\r
endif\r
\r
DEFINC = -I../.. -I. -DARM -D__GP2X__ -D_UNZIP_SUPPORT # -DBENCHMARK\r
-COPT_COMMON = -static -Wall -O2 -ftracer -fstrength-reduce -fomit-frame-pointer -fstrict-aliasing -ffast-math -Winline\r
+COPT_COMMON = -static -Wall -Winline\r
+ifeq ($(DEBUG),)\r
+COPT_COMMON += -O2 -ftracer -fstrength-reduce -fomit-frame-pointer -fstrict-aliasing -ffast-math\r
+else\r
+COPT_COMMON += -ggdb\r
+endif\r
ifeq "$(profile)" "1"\r
COPT_COMMON += -fprofile-generate\r
endif\r
#include <Pico/Patch.h>\r
#include <zlib/zlib.h>\r
\r
+//#define PFRAMES\r
\r
#ifdef BENCHMARK\r
#define OSD_FPS_X 220\r
}\r
\r
// additional movie stuff\r
- if(movie_data) {\r
+ if (movie_data) {\r
if(movie_data[0x14] == '6')\r
PicoOpt |= 0x20; // 6 button pad\r
else PicoOpt &= ~0x20;\r
- PicoOpt |= 0x40; // accurate timing\r
+ PicoOpt |= 0x10040; // accurate timing, no VDP fifo timing\r
if(movie_data[0xF] >= 'A') {\r
if(movie_data[0x16] & 0x80) {\r
PicoRegionOverride = 8;\r
}\r
else\r
{\r
+ PicoOpt &= ~0x10000;\r
if(Pico.m.pal) {\r
strcpy(noticeMsg, "PAL SYSTEM / 50 FPS");\r
} else {\r
// prepare sound stuff\r
if(currentConfig.EmuOpt & 4) {\r
int snd_excess_add;\r
- if(PsndRate != PsndRate_old || (PicoOpt&0x20b) != (PicoOpt_old&0x20b) || Pico.m.pal != pal_old || crashed_940) {\r
+ if (PsndRate != PsndRate_old || (PicoOpt&0x20b) != (PicoOpt_old&0x20b) || Pico.m.pal != pal_old ||\r
+ ((PicoOpt&0x200) && crashed_940)) {\r
/* if 940 is turned off, we need it to be put back to sleep */\r
if (!(PicoOpt&0x200) && ((PicoOpt^PicoOpt_old)&0x200)) {\r
Reset940(1, 2);\r
Pause940(1);\r
}\r
- sound_rerate(1);\r
+ sound_rerate(Pico.m.frame_count ? 1 : 0);\r
}\r
- //excess_samples = PsndRate - PsndLen*target_fps;\r
snd_excess_add = ((PsndRate - PsndLen*target_fps)<<16) / target_fps;\r
- printf("starting audio: %i len: %i (ex: %04x) stereo: %i, pal: %i\n", PsndRate, PsndLen, snd_excess_add, (PicoOpt&8)>>3, Pico.m.pal);\r
+ printf("starting audio: %i len: %i (ex: %04x) stereo: %i, pal: %i\n",\r
+ PsndRate, PsndLen, snd_excess_add, (PicoOpt&8)>>3, Pico.m.pal);\r
gp2x_start_sound(PsndRate, 16, (PicoOpt&8)>>3);\r
gp2x_sound_volume(currentConfig.volume, currentConfig.volume);\r
PicoWriteSound = updateSound;\r
if (frames_shown > frames_done) frames_shown = frames_done;\r
}\r
}\r
+#ifdef PFRAMES\r
+ sprintf(fpsbuff, "%i", Pico.m.frame_count);\r
+#endif\r
\r
lim_time = (frames_done+1) * target_frametime + vsync_offset;\r
if(currentConfig.Frameskip >= 0) { // frameskip enabled\r
}\r
} else {\r
sram_size = SRam.end-SRam.start+1;\r
- if(SRam.reg_back & 4) sram_size=0x2000;\r
+ if(Pico.m.sram_reg & 4) sram_size=0x2000;\r
sram_data = SRam.data;\r
}\r
if (!sram_data) return 0; // SRam forcefully disabled for this game\r
#define CAN_HANDLE_240_LINES 1\r
\r
// logging emu events\r
-#define EL_LOGMASK 0 // (EL_STATUS|EL_ANOMALY) // xffff\r
+#define EL_LOGMASK 0 // (EL_STATUS|EL_ANOMALY|EL_UIO) // xffff\r
\r
//#define dprintf(f,...) printf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__)\r
#define dprintf(x...)\r
// pico.c
#define CAN_HANDLE_240_LINES 1
-#define EL_LOGMASK (EL_ANOMALY|EL_STATUS|EL_VDPDMA|EL_ASVDP|EL_SR) // |EL_BUSREQ|EL_Z80BNK)
+#define EL_LOGMASK (EL_ANOMALY|EL_STATUS|EL_SRAMIO|EL_EEPROM) // EL_VDPDMA|EL_ASVDP|EL_SR) // |EL_BUSREQ|EL_Z80BNK)
//#define dprintf(f,...) printf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__)
#define dprintf(x...)
\r
Changelog\r
---------\r
-1.332\r
+1.34\r
+ Some new optimizations in memory handlers, and for shadow/hilight mode.\r
+ Added some hacks to make more games work without enabling "accurate timing".\r
- * Fixed hang of NBA Jam (ingame saves do not work though).\r
* Adjusted timing for "accurate timing" mode and added preliminary VDP FIFO\r
emulation. Fixes Double Dragon 2, tearing in Chaos Engine and some other games.\r
* Fixed a few games not having sound at startup.\r
+ * Updated serial EEPROM code to support more games. Thanks to EkeEke for\r
+ providing info about additional EEPROM types and game mappers.\r
+ * The above change fixed hang of NBA Jam.\r
\r
1.33\r
* Updated Cyclone core to 0.0088.\r
notaz.gp2x.de / picodrive.git / commitdiff