updated EEPROM code, gmv fixed
[picodrive.git] / Pico / MemoryCmn.c
CommitLineData
6cadc2da 1// common code for Memory.c and cd/Memory.c
2// (c) Copyright 2006-2007, Grazvydas "notaz" Ignotas
fa1e5e29 3
eff55556 4#ifndef UTYPES_DEFINED
5typedef unsigned char u8;
6typedef unsigned short u16;
7typedef unsigned int u32;
8#define UTYPES_DEFINED
9#endif
10
11#ifdef _ASM_MEMORY_C
12u32 OtherRead16End(u32 a, int realsize);
13#endif
14#ifdef _ASM_CD_MEMORY_C
15static void OtherWrite8End(u32 a,u32 d,int realsize);
16#endif
17
fa1e5e29 18
19#ifndef _ASM_MEMORY_C
20static
21#endif
22u8 z80Read8(u32 a)
23{
24 if(Pico.m.z80Run&1) return 0;
25
26 a&=0x1fff;
27
28 if(!(PicoOpt&4)) {
29 // Z80 disabled, do some faking
30 static u8 zerosent = 0;
31 if(a == Pico.m.z80_lastaddr) { // probably polling something
32 u8 d = Pico.m.z80_fakeval;
33 if((d & 0xf) == 0xf && !zerosent) {
34 d = 0; zerosent = 1;
35 } else {
36 Pico.m.z80_fakeval++;
37 zerosent = 0;
38 }
39 return d;
40 } else {
41 Pico.m.z80_fakeval = 0;
42 }
43 }
44
45 Pico.m.z80_lastaddr = (u16) a;
46 return Pico.zram[a];
47}
48
fa1e5e29 49#ifndef _ASM_MEMORY_C
50static
51#endif
e5503e2f 52u32 z80ReadBusReq(void)
fa1e5e29 53{
e5503e2f 54 u32 d=Pico.m.z80Run&1;
f58f05d2 55 if (!d && Pico.m.scanline != -1) {
e5503e2f 56 // needed by buggy Terminator (Sega CD)
57 int stop_before = SekCyclesDone() - z80stopCycle;
69996cb7 58 //elprintf(EL_BUSREQ, "get_zrun: stop before: %i", stop_before);
59 // note: if we use 20 or more here, Barkley Shut Up and Jam! will purposedly crash itself.
60 // TODO: CD Terminator
61 if (stop_before > 0 && stop_before < 20) // Gens uses 16 here
e5503e2f 62 d = 1; // bus not yet available
63 }
64 // |=0x80 for Shadow of the Beast & Super Offroad
69996cb7 65 elprintf(EL_BUSREQ, "get_zrun: %02x [%i] @%06x", d|0x80, SekCyclesDone(), SekPc);
e5503e2f 66 return d|0x80;
67}
fa1e5e29 68
e5503e2f 69#ifndef _ASM_MEMORY_C
70static
71#endif
72void z80WriteBusReq(u32 d)
73{
74 d&=1; d^=1;
69996cb7 75 if (Pico.m.scanline != -1)
f58f05d2 76 {
77 if(!d) {
78 // this is for a nasty situation where Z80 was enabled and disabled in the same 68k timeslice (Golden Axe III)
79 if (Pico.m.z80Run) {
80 int lineCycles;
81 z80stopCycle = SekCyclesDone();
82 if (Pico.m.z80Run&2)
83 lineCycles=(488-SekCyclesLeft)&0x1ff;
84 else lineCycles=z80stopCycle-z80startCycle; // z80 was started at current line
85 if (lineCycles > 0 && lineCycles <= 488) {
69996cb7 86 //dprintf("zrun: %i/%i cycles", lineCycles, (lineCycles>>1)-(lineCycles>>5));
f58f05d2 87 lineCycles=(lineCycles>>1)-(lineCycles>>5);
88 z80_run(lineCycles);
89 }
e5503e2f 90 }
f58f05d2 91 } else {
69996cb7 92 if (!Pico.m.z80Run)
93 z80startCycle = SekCyclesDone();
94 else
95 d|=Pico.m.z80Run;
fa1e5e29 96 }
fa1e5e29 97 }
69996cb7 98 elprintf(EL_BUSREQ, "set_zrun: %i->%i [%i] @%06x", Pico.m.z80Run, d, SekCyclesDone(), SekPc);
e5503e2f 99 Pico.m.z80Run=(u8)d;
100}
101
102#ifndef _ASM_MEMORY_C
103static
104#endif
105u32 OtherRead16(u32 a, int realsize)
106{
107 u32 d=0;
fa1e5e29 108
109 if ((a&0xffffe0)==0xa10000) { // I/O ports
110 a=(a>>1)&0xf;
111 switch(a) {
112 case 0: d=Pico.m.hardware; break; // Hardware value (Version register)
e5503e2f 113 case 1: d=PadRead(0); break;
114 case 2: d=PadRead(1); break;
fa1e5e29 115 default: d=Pico.ioports[a]; break; // IO ports can be used as RAM
116 }
117 d|=d<<8;
118 goto end;
119 }
120
f58f05d2 121 // rotate fakes next fetched instruction for Time Killers
fa1e5e29 122 if (a==0xa11100) { // z80 busreq
e5503e2f 123 d=(z80ReadBusReq()<<8)|Pico.m.rotate++;
fa1e5e29 124 goto end;
125 }
126
e5503e2f 127 if ((a&0xff0000)==0xa00000) {
128 if ((a&0x4000)==0x0000) { d=z80Read8(a); d|=d<<8; goto end; } // Z80 ram (not byteswaped)
129 if ((a&0x6000)==0x4000) { // 0x4000-0x5fff, Fudge if disabled
130 if(PicoOpt&1) d=YM2612Read();
131 else d=Pico.m.rotate++&3;
69996cb7 132 elprintf(EL_YM2612R, "read ym2612: %02x", d);
e5503e2f 133 goto end;
134 }
135 d=0xffff;
136 goto end;
137 }
138
fa1e5e29 139#ifndef _ASM_MEMORY_C
140 if ((a&0xe700e0)==0xc00000) { d=PicoVideoRead(a); goto end; }
141#endif
142
143 d = OtherRead16End(a, realsize);
144
145end:
146 return d;
147}
148
e5503e2f 149static void IoWrite8(u32 a, u32 d)
150{
151 a=(a>>1)&0xf;
152 // 6 button gamepad: if TH went from 0 to 1, gamepad changes state
153 if(PicoOpt&0x20) {
154 if(a==1) {
155 Pico.m.padDelay[0] = 0;
156 if(!(Pico.ioports[1]&0x40) && (d&0x40)) Pico.m.padTHPhase[0]++;
157 }
158 else if(a==2) {
159 Pico.m.padDelay[1] = 0;
160 if(!(Pico.ioports[2]&0x40) && (d&0x40)) Pico.m.padTHPhase[1]++;
161 }
162 }
163 Pico.ioports[a]=(u8)d; // IO ports can be used as RAM
164}
fa1e5e29 165
4ff2d527 166#ifndef _ASM_CD_MEMORY_C
167static
168#endif
e5503e2f 169void OtherWrite8(u32 a,u32 d)
fa1e5e29 170{
e5503e2f 171#ifndef _ASM_MEMORY_C
fa1e5e29 172 if ((a&0xe700f9)==0xc00011||(a&0xff7ff9)==0xa07f11) { if(PicoOpt&2) SN76496Write(d); return; } // PSG Sound
173 if ((a&0xff4000)==0xa00000) { if(!(Pico.m.z80Run&1)) Pico.zram[a&0x1fff]=(u8)d; return; } // Z80 ram
174 if ((a&0xff6000)==0xa04000) { if(PicoOpt&1) emustatus|=YM2612Write(a&3, d); return; } // FM Sound
e5503e2f 175 if ((a&0xffffe0)==0xa10000) { IoWrite8(a, d); return; } // I/O ports
176#endif
177 if (a==0xa11100) { z80WriteBusReq(d); return; }
fa1e5e29 178 if (a==0xa11200) {
179 dprintf("write z80Reset: %02x", d);
180 if(!(d&1)) z80_reset();
181 return;
182 }
e5503e2f 183#ifndef _ASM_MEMORY_C
fa1e5e29 184 if ((a&0xff7f00)==0xa06000) // Z80 BANK register
185 {
186 Pico.m.z80_bank68k>>=1;
187 Pico.m.z80_bank68k|=(d&1)<<8;
188 Pico.m.z80_bank68k&=0x1ff; // 9 bits and filled in the new top one
189 return;
190 }
e5503e2f 191#endif
fa1e5e29 192 if ((a&0xe700e0)==0xc00000) {
f58f05d2 193 d&=0xff;
fa1e5e29 194 PicoVideoWrite(a,(u16)(d|(d<<8))); // Byte access gets mirrored
195 return;
196 }
197
e5503e2f 198 OtherWrite8End(a, d, 8);
fa1e5e29 199}
200
201
4ff2d527 202#ifndef _ASM_CD_MEMORY_C
203static
204#endif
205void OtherWrite16(u32 a,u32 d)
fa1e5e29 206{
207 if ((a&0xe700e0)==0xc00000) { PicoVideoWrite(a,(u16)d); return; }
e5503e2f 208 if (a==0xa11100) { z80WriteBusReq(d>>8); return; }
209 if (a==0xa11200) { dprintf("write z80reset: %04x", d); if(!(d&0x100)) z80_reset(); return; }
210 if ((a&0xffffe0)==0xa10000) { IoWrite8(a, d); return; } // I/O ports
fa1e5e29 211 if ((a&0xff4000)==0xa00000) { if(!(Pico.m.z80Run&1)) Pico.zram[a&0x1fff]=(u8)(d>>8); return; } // Z80 ram (MSB only)
e5503e2f 212 if ((a&0xe700f8)==0xc00010||(a&0xff7ff8)==0xa07f10) { if(PicoOpt&2) SN76496Write(d); return; } // PSG Sound
213 if ((a&0xff6000)==0xa04000) { if(PicoOpt&1) emustatus|=YM2612Write(a&3, d); return; } // FM Sound (??)
214 if ((a&0xff7f00)==0xa06000) // Z80 BANK register
215 {
216 Pico.m.z80_bank68k>>=1;
217 Pico.m.z80_bank68k|=(d&1)<<8;
218 Pico.m.z80_bank68k&=0x1ff; // 9 bits and filled in the new top one
fa1e5e29 219 return;
220 }
fa1e5e29 221
69996cb7 222#ifndef _CD_MEMORY_C
7969166e 223 if (a >= SRam.start && a <= SRam.end) {
1dceadae 224 elprintf(EL_SRAMIO, "sram w16 [%06x] %04x @ %06x", a, d, SekPc);
7969166e 225 if ((a&0x16)==0x10) { // detected, not EEPROM, write not disabled
226 u8 *pm=(u8 *)(SRam.data-SRam.start+a);
227 *pm++=d>>8;
228 *pm++=d;
229 SRam.changed = 1;
230 }
231 else
1dceadae 232 SRAMWrite(a, d);
7969166e 233 return;
234 }
69996cb7 235#else
236 OtherWrite8End(a, d>>8, 16);
237 OtherWrite8End(a+1,d&0xff, 16);
238#endif
fa1e5e29 239}
240
241