OBJS += plugins/dfsound/arm_utils.o
endif
ifeq "$(HAVE_C64_TOOLS)" "1"
-plugins/dfsound/spu.o: CFLAGS += -DC64X_DSP
+plugins/dfsound/%.o: CFLAGS += -DC64X_DSP -DWANT_THREAD_CODE
plugins/dfsound/spu.o: plugins/dfsound/spu_c64x.c
frontend/menu.o: CFLAGS += -DC64X_DSP
endif
frontend/libpicofe/linux/plat.o: CFLAGS += -DPANDORA
USE_PLUGIN_LIB = 1
USE_FRONTEND = 1
+CFLAGS += -gdwarf-3 -ffunction-sections -fdata-sections
+LDFLAGS += -Wl,--gc-sections
endif
ifeq "$(PLATFORM)" "caanoo"
OBJS += frontend/libpicofe/gp2x/in_gp2x.o frontend/warm/warm.o
static const char h_restore_def[] = "Switches back to default / recommended\n"
"configuration";
static const char h_frameskip[] = "Warning: frameskip sometimes causes glitches\n";
+static const char h_sputhr[] = "Warning: has some known bugs\n";
static menu_entry e_menu_options[] =
{
mee_enum ("Region", 0, region, men_region),
mee_range ("CPU clock", MA_OPT_CPU_CLOCKS, cpu_clock, 20, 5000),
#ifdef C64X_DSP
- mee_onoff ("Use C64x DSP for sound", MA_OPT_SPU_THREAD, spu_config.iUseThread, 1),
+ mee_onoff_h ("Use C64x DSP for sound", MA_OPT_SPU_THREAD, spu_config.iUseThread, 1, h_sputhr),
#else
- mee_onoff ("Threaded SPU", MA_OPT_SPU_THREAD, spu_config.iUseThread, 1),
+ mee_onoff_h ("Threaded SPU", MA_OPT_SPU_THREAD, spu_config.iUseThread, 1, h_sputhr),
#endif
mee_handler_id("[Display]", MA_OPT_DISP_OPTS, menu_loop_gfx_options),
mee_handler ("[BIOS/Plugins]", menu_loop_plugin_options),
doffs = xoffs + y * dstride;
if (dims_changed)
- flip_clear_counter = 2;
+ flip_clear_counter = 3;
if (flip_clear_counter > 0) {
if (pl_plat_clear)
ifndef C64_TOOLS_DSP_ROOT
$(error need C64_TOOLS_DSP_ROOT)
endif
+ifndef TI_CGTOOLS
+$(error need TI_CGTOOLS and stuff, source c64_tools/dsp/setenv.sh)
+endif
include $(C64_TOOLS_DSP_ROOT)/install.mk
\r
sample_buf sb[MAXCHAN];\r
int interpolation;\r
- sample_buf sb_thread[MAXCHAN];\r
+\r
+#if P_HAVE_PTHREAD || defined(WANT_THREAD_CODE)\r
+ sample_buf * sb_thread;\r
+ sample_buf sb_thread_[MAXCHAN];\r
+#endif\r
} SPUInfo;\r
\r
#define regAreaGet(offset) \\r
- spu.regArea[((offset) - 0xc00)>>1]\r
+ spu.regArea[((offset) - 0xc00) >> 1]\r
#define regAreaGetCh(ch, offset) \\r
- spu.regArea[((ch<<4)|(offset))>>1]\r
+ spu.regArea[(((ch) << 4) | (offset)) >> 1]\r
\r
///////////////////////////////////////////////////////////\r
// SPU.C globals\r
0xffffffff, 0x1307, 0x59b3, 0x12c7, \r
};\r
\r
-#endif
\ No newline at end of file
+#endif\r
{
int ret;
+ spu.sb_thread = spu.sb_thread_;
+
if (sysconf(_SC_NPROCESSORS_ONLN) <= 1)
return;
preload(work->SSumLR);
preload(work->SSumLR + 64/4);
- f.stale_caches = 1; // SB, spuMem
+ f.stale_caches = 1; // sb, spuMem
if (limit == 0)
printf("dsp: wait timeout\n");
static void thread_sync_caches(void)
{
if (f.stale_caches) {
- f.dsp_cache_inv_virt(spu.SB, sizeof(spu.SB[0]) * SB_SIZE * 24);
+ f.dsp_cache_inv_virt(spu.sb_thread, sizeof(spu.sb_thread[0]) * MAXCHAN);
f.dsp_cache_inv_virt(spu.spuMemC + 0x800, 0x800);
if (spu.rvb->StartAddr) {
int left = 0x40000 - spu.rvb->StartAddr;
// override default allocations
free(spu.spuMemC);
spu.spuMemC = mem->spu_ram;
- free(spu.SB);
- spu.SB = mem->SB;
+ spu.sb_thread = mem->sb_thread;
free(spu.s_chan);
spu.s_chan = mem->in.s_chan;
free(spu.rvb);
f.dsp_close();
spu.spuMemC = NULL;
- spu.SB = NULL;
+ spu.sb_thread = spu.sb_thread_;
spu.s_chan = NULL;
spu.rvb = NULL;
worker = NULL;
#ifndef __P_SPU_C64X_H__
#define __P_SPU_C64X_H__
+#include "externals.h"
+#include "spu_config.h"
+
#define COMPONENT_NAME "pcsxr_spu"
enum {
struct region_mem {
unsigned char spu_ram[512 * 1024];
- int SB[SB_SIZE * 24];
+ sample_buf sb_thread[MAXCHAN];
// careful not to lose ARM writes by DSP overwriting
// with old data when it's writing out neighbor cachelines
- int _pad1[128/4 - ((SB_SIZE * 24) & (128/4 - 1))];
+ int _pad1[128/4 - ((sizeof(sample_buf) * MAXCHAN / 4) & (128/4 - 1))];
struct spu_in {
// these are not to be modified by DSP
SPUCHAN s_chan[24 + 1];
// nothing to do? Write out non-critical caches
if (dirty) {
syscalls.cache_wb(spu.spuMemC + 0x800, 0x800, 1);
- syscalls.cache_wb(spu.SB, sizeof(spu.SB[0]) * SB_SIZE * 24, 1);
+ syscalls.cache_wb(spu.sb_thread, sizeof(spu.sb_thread[0]) * MAXCHAN, 1);
if (had_rvb) {
left = 0x40000 - spu.rvb->StartAddr;
syscalls.cache_wb(spu.spuMem + spu.rvb->StartAddr, left * 2, 1);
InitADSR();
spu.spuMemC = mem->spu_ram;
- spu.SB = mem->SB;
+ spu.sb_thread = mem->sb_thread;
spu.s_chan = mem->in.s_chan;
spu.rvb = &mem->in.rvb;
worker = &mem->worker;
do_processing();
- syscalls.cache_inv(&mem->SB, sizeof(mem->SB), 0);
+ syscalls.cache_inv(&mem->sb_thread, sizeof(mem->sb_thread), 0);
syscalls.cache_inv(&mem->in, sizeof(mem->in), 0);
break;
#define INLINE static inline
#endif
-#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+#if defined(__BYTE_ORDER__) && __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
#define HTOLE16(x) __builtin_bswap16(x)
#define LE16TOH(x) __builtin_bswap16(x)
#else