#ifndef __GPU_H__
#define __GPU_H__
-#define PSXGPU_LCF (1<<31)
-#define PSXGPU_nBUSY (1<<26)
-#define PSXGPU_ILACE (1<<22)
-#define PSXGPU_DHEIGHT (1<<19)
+#define PSXGPU_LCF (1u<<31)
+#define PSXGPU_nBUSY (1u<<26)
+#define PSXGPU_ILACE (1u<<22)
+#define PSXGPU_DHEIGHT (1u<<19)
+#define PSXGPU_FIELD (1u<<13)
// both must be set for interlace to work
-#define PSXGPU_ILACE_BITS (PSXGPU_ILACE | PSXGPU_DHEIGHT)
+#define PSXGPU_ILACE_BITS (PSXGPU_ILACE | PSXGPU_DHEIGHT | PSXGPU_FIELD)
#define HW_GPU_STATUS psxHu32ref(0x1814)
// TODO: handle com too
-#define PSXGPU_TIMING_BITS (PSXGPU_LCF | PSXGPU_nBUSY)
+#define PSXGPU_TIMING_BITS (PSXGPU_LCF | PSXGPU_nBUSY | PSXGPU_FIELD)
#define gpuSyncPluginSR() { \
HW_GPU_STATUS &= SWAP32(PSXGPU_TIMING_BITS); \
for (i = 0; i < sizeof(gpu_data_def) / sizeof(gpu_data_def[0]); i++)
GPU_writeData(gpu_data_def[i]);
+
+ HW_GPU_STATUS |= SWAP32(PSXGPU_nBUSY);
}
static void SetBootRegs(u32 pc, u32 gp, u32 sp)
// Update lace.
if( hSyncCount >= HSyncTotal[Config.PsxType] )
{
+ u32 status, field = 0;
rcnts[3].cycleStart += Config.PsxType ? PSXCLK / 50 : PSXCLK / 60;
hSyncCount = 0;
frame_counter++;
gpuSyncPluginSR();
- if ((HW_GPU_STATUS & SWAP32(PSXGPU_ILACE_BITS)) == SWAP32(PSXGPU_ILACE_BITS))
- HW_GPU_STATUS |= SWAP32(frame_counter << 31);
- GPU_vBlank(0, SWAP32(HW_GPU_STATUS) >> 31);
+ status = SWAP32(HW_GPU_STATUS) | PSXGPU_FIELD;
+ if ((status & PSXGPU_ILACE_BITS) == PSXGPU_ILACE_BITS) {
+ field = frame_counter & 1;
+ status |= field << 31;
+ status ^= field << 13;
+ }
+ HW_GPU_STATUS = SWAP32(status);
+ GPU_vBlank(0, field);
}
scheduleRcntBase();