{
struct psx_gpu *gpup = &gpu;
struct psx_gpu_async *agpu = gpup->async;
- int dirty = 0;
+ int renderer_dirty = 0;
assert(agpu);
slock_lock(agpu->lock);
int pos = agpu->pos_used & AGPU_BUF_MASK;
int done, cycles_dummy = 0, cmd = -1;
assert(len >= 0);
- if (len == 0 && !dirty) {
+ if (len == 0 && !renderer_dirty) {
switch (agpu->wait_mode) {
case waitmode_full:
case waitmode_target:
}
slock_unlock(agpu->lock);
- if (len == 0 && dirty) {
+ if (len == 0 && renderer_dirty) {
renderer_flush_queues();
- dirty = 0;
+ renderer_dirty = 0;
slock_lock(agpu->lock);
continue;
}
len = min(len, AGPU_BUF_LEN - pos);
done = renderer_do_cmd_list(agpu->cmd_buffer + pos, len, agpu->ex_regs,
&cycles_dummy, &cycles_dummy, &cmd);
+ renderer_dirty |= done;
if (done != len) {
const void *list = agpu->cmd_buffer + pos + done;
switch (cmd) {
break;
case FAKECMD_SET_INTERLACE:
done += do_set_interlace(gpup, list);
+ renderer_dirty = 0;
break;
case FAKECMD_DMA_WRITE:
done += do_dma_write(gpup, list, pos + done);
+ renderer_dirty = 0;
break;
case FAKECMD_BREAK:
done += sizeof(struct cmd_break) / 4;
+ renderer_flush_queues();
+ renderer_dirty = 0;
break;
default:
assert(0);
}
}
- dirty = 1;
assert(done > 0);
slock_lock(agpu->lock);
agpu->pos_used += done;
int stride = (w + 1) / 2;
int done = 0;
+ renderer_flush_queues();
+
pos += sizeof(*cmd) / 4u;
done += sizeof(*cmd) / 4u;
assert(pos <= AGPU_BUF_LEN);