+#ifndef __BLIT320_H__
+#define __BLIT320_H__
+
void blit320_640(void *dst, const void *src, int unused);
void blit320_512(void *dst, const void *src, int unused);
void blit320_368(void *dst, const void *src, int unused);
+
+#endif /* __BLIT320_H__ */
+#ifndef __CSPACE_H__
+#define __CSPACE_H__
+
#ifdef __cplusplus
extern "C"
{
#ifdef __cplusplus
}
#endif
+
+#endif /* __CSPACE_H__ */
+#ifndef __IN_TSBUTTON_H__
+#define __IN_TSBUTTON_H__
+
void in_tsbutton_init(void);
+
+#endif /* __IN_TSBUTTON_H__ */
+#ifndef __MENU_H__
+#define __MENU_H__
+
void menu_init(void);
void menu_prepare_emu(void);
void menu_loop(void);
extern int g_menuscreen_w;
extern int g_menuscreen_h;
+
+#endif /* __MENU_H__ */
+#ifndef __NOPIC_H__
+#define __NOPIC_H__
+
/* these are just deps, to be removed */
static const struct {
}
}
-
+#endif /* __NOPIC_H__ */
+#ifndef __PL_GUN_TS_H__
+#define __PL_GUN_TS_H__
+
#ifdef HAVE_TSLIB
struct tsdev;
#define pl_set_gun_rect(...) do {} while (0)
#endif
+
+#endif /* __PL_GUN_TS_H__ */
+#ifndef __PLAT_H__
+#define __PLAT_H__
+
void plat_init(void);
void plat_finish(void);
void plat_minimize(void);
void *plat_gvideo_set_mode(int *w, int *h, int *bpp);
void *plat_gvideo_flip(void);
void plat_gvideo_close(void);
+
+#endif /* __PLAT_H__ */
+#ifndef __PLAT_OMAP_H__
+#define __PLAT_OMAP_H__
void plat_omap_init(void);
void plat_omap_finish(void);
void plat_omap_gvideo_open(void);
+#endif /* __PLAT_OMAP_H__ */
+#ifndef __PLUGIN_H__
+#define __PLUGIN_H__
+
#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
#define PLUGIN_DL_BASE 0xfbad0000
void *plugin_link(enum builtint_plugins_e id, const char *sym);
void plugin_call_rearmed_cbs(void);
+
+#endif /* __PLUGIN_H__ */
+#ifndef __PLUGIN_LIB_H__
+#define __PLUGIN_LIB_H__
enum {
DKEY_SELECT = 0,
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
#endif
+
+#endif /* __PLUGIN_LIB_H__ */
+#ifndef __CONFIG_H__
+#define __CONFIG_H__
+
#define MAXPATHLEN 256
#define PCSX_VERSION "1.9"
+
+#endif /* __CONFIG_H__ */
+#ifndef __PCNT_H__
+#define __PCNT_H__
enum pcounters {
PCNT_ALL,
#define pcnt_print(fps)
#endif
+
+#endif /* __PCNT_H__ */
* that GPU plugin doesn't.
*/
+#ifndef __GPU_H__
+#define __GPU_H__
+
#define PSXGPU_LCF (1<<31)
#define PSXGPU_nBUSY (1<<26)
#define PSXGPU_ILACE (1<<22)
HW_GPU_STATUS &= PSXGPU_TIMING_BITS; \
HW_GPU_STATUS |= GPU_readStatus() & ~PSXGPU_TIMING_BITS; \
}
+
+#endif /* __GPU_H__ */
* along with this program; if not, see <http://www.gnu.org/licenses>.
*/
+#ifndef __GTE_ARM_H__
+#define __GTE_ARM_H__
+
void gteRTPS_nf_arm(void *cp2_regs, int opcode);
void gteRTPT_nf_arm(void *cp2_regs, int opcode);
void gteNCLIP_arm(void *cp2_regs, int opcode);
void gteMACtoIR_lm1(void *cp2_regs);
void gteMACtoIR_lm0_nf(void *cp2_regs);
void gteMACtoIR_lm1_nf(void *cp2_regs);
+
+#endif /* __GTE_ARM_H__ */
* along with this program; if not, see <http://www.gnu.org/licenses>.
*/
+#ifndef __GTE_DIVIDER_H__
+#define __GTE_DIVIDER_H__
+
u32 DIVIDE(s16 n, u16 d);
+
+#endif /* __GTE_DIVIDER_H__ */
* along with this program; if not, see <http://www.gnu.org/licenses>.
*/
+#ifndef __GTE_NEON_H__
+#define __GTE_NEON_H__
+
void gteRTPS_neon(void *cp2_regs, int opcode);
void gteRTPT_neon(void *cp2_regs, int opcode);
// after NEON call only, does not do gteIR
void gteMACtoIR_flags_neon(void *cp2_regs, int lm);
+
+#endif /* __GTE_NEON_H__ */
+#ifndef __ASSEM_ARM_H__
+#define __ASSEM_ARM_H__
+
#define HOST_REGS 13
#define HOST_CCREG 10
#define HOST_BTREG 8
extern char translation_cache[1 << TARGET_SIZE_2];
#define BASE_ADDR (u_int)translation_cache
#endif
+
+#endif /* __ASSEM_ARM_H__ */
+#ifndef __LINKAGE_OFFSETS_H__
+#define __LINKAGE_OFFSETS_H__
#define LO_next_interupt 64
#define LO_cycle_count (LO_next_interupt + 4)
#define LO_FCR31 (LO_align0)
#define LO_cop2_to_scratch_buf (LO_scratch_buf_ptr - LO_reg_cop2d)
+
+#endif /* __LINKAGE_OFFSETS_H__ */
+#ifndef __EMU_IF_H__
+#define __EMU_IF_H__
+
#include "../../new_dynarec.h"
#include "../../../r3000a.h"
#else
#define rdram ((u_int)psxM)
#endif
+
+#endif /* __EMU_IF_H__ */
+#ifndef __PCSXMEM_H__
+#define __PCSXMEM_H__
extern u8 zero_mem[0x1000];
void new_dyna_pcsx_mem_shutdown(void);
int pcsxmem_is_handler_dynamic(unsigned int addr);
+
+#endif /* __PCSXMEM_H__ */
+#ifndef __NEW_DYNAREC_H__
+#define __NEW_DYNAREC_H__
+
/* #define NEW_DYNAREC 1 */
extern int pcaddr;
void invalidate_all_pages(void);
void invalidate_block(unsigned int block);
+
+#endif /* __NEW_DYNAREC_H__ */
-
+#ifndef __NEW_DYNAREC_CONFIG_H__
+#define __NEW_DYNAREC_CONFIG_H__
#define CORTEX_A8_BRANCH_PREDICTION_HACK 1
#define USE_MINI_HT 1
#ifdef VITA
#define BASE_ADDR_DYNAMIC 1
#endif
+
+#endif /* __NEW_DYNAREC_CONFIG_H__ */
// Converted to binary format by Wei Mingzhi <whistler_wmz@users.sf.net>.
//
+#ifndef __SJISFONT_H__
+#define __SJISFONT_H__
+
const unsigned char font_8140[] = {
0x78, 0xda, 0xad, 0x3b, 0x3b, 0x90, 0x1b, 0xc9,
0x75, 0x3d, 0x9f, 0x05, 0x1a, 0xcb, 0xe1, 0x4e,
0xeb, 0xe7, 0xa8, 0x89, 0x0a, 0x11, 0xbc, 0xbc,
0x33, 0xf9, 0xff, 0xe8, 0xc4, 0x21, 0xbf
};
+
+#endif /* __SJISFONT_H__ */
+#ifndef __P_CDRCIMG_H__
+#define __P_CDRCIMG_H__
void cdrcimg_set_fname(const char *fname);
void *cdrcimg_get_sym(const char *sym);
+
+#endif /* __P_CDRCIMG_H__ */
+#ifndef __P_EXTERNALS_H__
+#define __P_EXTERNALS_H__
void dfinput_activate(void);
/* vibration trigger to frontend */
extern int in_enable_vibration;
extern void plat_trigger_vibrate(int pad, int low, int high);
+
+#endif /* __P_EXTERNALS_H__ */
+#ifndef __P_MAIN_H__
+#define __P_MAIN_H__
+
#include "psemu_plugin_defs.h"
#include "externals.h"
/* get button state and pad type from main emu */
extern long (*PAD1_readPort1)(PadDataS *pad);
extern long (*PAD2_readPort2)(PadDataS *pad);
+
+#endif /* __P_MAIN_H__ */
* *\r
***************************************************************************/\r
\r
+#ifndef __P_ADER_H__\r
+#define __P_ADER_H__\r
+\r
INLINE void StartADSR(int ch);\r
INLINE int MixADSR(int ch);\r
+\r
+#endif /* __P_ADER_H__ */\r
//\r
//*************************************************************************//\r
\r
+#ifndef __P_DMA_H__\r
+#define __P_DMA_H__\r
\r
unsigned short CALLBACK SPUreadDMA(void);\r
void CALLBACK SPUreadDMAMem(unsigned short * pusPSXMem,int iSize);\r
void CALLBACK SPUwriteDMA(unsigned short val);\r
void CALLBACK SPUwriteDMAMem(unsigned short * pusPSXMem,int iSize);\r
+\r
+#endif /* __P_DMA_H__ */\r
* *\r
***************************************************************************/\r
\r
+#ifndef __P_SOUND_EXTERNALS_H__\r
+#define __P_SOUND_EXTERNALS_H__\r
+\r
#include <stdint.h>\r
\r
/////////////////////////////////////////////////////////\r
\r
#endif\r
\r
+#endif /* __P_SOUND_EXTERNALS_H__ */\r
+#ifndef __P_OUT_H__
+#define __P_OUT_H__
struct out_driver {
const char *name;
extern struct out_driver *out_current;
void SetupSound(void);
+
+#endif /* __P_OUT_H__ */
* *\r
***************************************************************************/\r
\r
+#ifndef __P_REGISTERS_H__\r
+#define __P_REGISTERS_H__\r
+\r
#define H_SPUReverbAddr 0x0da2\r
#define H_SPUirqAddr 0x0da4\r
#define H_SPUaddr 0x0da6\r
\r
void CALLBACK SPUwriteRegister(unsigned long reg, unsigned short val, unsigned int cycles);\r
\r
+#endif /* __P_REGISTERS_H__ */\r
* *\r
***************************************************************************/\r
\r
+#ifndef __P_SPU_H__\r
+#define __P_SPU_H__\r
+\r
void ClearWorkingState(void);\r
void CALLBACK SPUplayADPCMchannel(xa_decode_t *xap);\r
int CALLBACK SPUplayCDDAchannel(short *pcm, int bytes);\r
+\r
+#endif /* __P_SPU_H__ */\r
+#ifndef __P_SPU_C64X_H__
+#define __P_SPU_C64X_H__
+
#define COMPONENT_NAME "pcsxr_spu"
enum {
};
#define ACTIVE_CNT 3
+
+#endif /* __P_SPU_C64X_H__ */
+#ifndef __P_SPU_CONFIG_H__
+#define __P_SPU_CONFIG_H__
+
// user settings
typedef struct
} SPUConfig;
extern SPUConfig spu_config;
+
+#endif /* __P_SPU_CONFIG_H__ */
* *
***************************************************************************/
+#ifndef __P_STDAFX_H__
+#define __P_STDAFX_H__
+
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#endif
#include "psemuxa.h"
+
+#endif /* __P_STDAFX_H__ */
* *\r
***************************************************************************/\r
\r
+#ifndef __P_XA_H__\r
+#define __P_XA_H__\r
+\r
INLINE void MixXA(void);\r
INLINE void FeedXA(xa_decode_t *xap);\r
-INLINE int FeedCDDA(unsigned char *pcm, int nBytes);
+INLINE int FeedCDDA(unsigned char *pcm, int nBytes);\r
+\r
+#endif /* __P_XA_H__ */\r
+#ifndef __P_PSX_GPU_OFFSETS_H__
+#define __P_PSX_GPU_OFFSETS_H__
+
#define psx_gpu_test_mask_offset 0x0
#define psx_gpu_uvrg_offset 0x10
#define psx_gpu_uvrg_dx_offset 0x20
#define psx_gpu_texture_4bpp_cache_offset 0x5a00
#define psx_gpu_texture_8bpp_even_cache_offset 0x205a00
#define psx_gpu_texture_8bpp_odd_cache_offset 0x305a00
+
+#endif /* __P_PSX_GPU_OFFSETS_H__ */
+#ifndef __GPU_UNAI_GPU_ARM_H__
+#define __GPU_UNAI_GPU_ARM_H__
+
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
+
+#endif /* __GPU_UNAI_GPU_ARM_H__ */
* 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
***************************************************************************/
+#ifndef __GPU_UNAI_GPU_COMMAND_H__
+#define __GPU_UNAI_GPU_COMMAND_H__
+
///////////////////////////////////////////////////////////////////////////////
void gpuSetTexture(u16 tpage)
{
///////////////////////////////////////////////////////////////////////////////
// End of code specific to non-gpulib standalone version of gpu_unai
///////////////////////////////////////////////////////////////////////////////
+
+#endif /* __GPU_UNAI_GPU_COMMAND_H__ */
* 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
***************************************************************************/
+#ifndef __GPU_UNAI_GPU_INNER_H__
+#define __GPU_UNAI_GPU_INNER_H__
+
///////////////////////////////////////////////////////////////////////////////
// Inner loop driver instantiation file
#undef TI
#undef TN
#undef TIBLOCK
+
+#endif /* __GPU_UNAI_GPU_INNER_H__ */
* 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
***************************************************************************/
+#ifndef __GPU_UNAI_GPU_RASTER_IMAGE_H__
+#define __GPU_UNAI_GPU_RASTER_IMAGE_H__
+
///////////////////////////////////////////////////////////////////////////////
#ifndef USE_GPULIB
void gpuLoadImage(PtrUnion packet)
}
}
}
+
+#endif /* __GPU_UNAI_GPU_RASTER_IMAGE_H__ */
* 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
***************************************************************************/
+#ifndef __GPU_UNAI_GPU_RASTER_LINE_H__
+#define __GPU_UNAI_GPU_RASTER_LINE_H__
+
///////////////////////////////////////////////////////////////////////////////
// GPU internal line drawing functions
//
// Final run of pixels
gpuPixelSpanDriver(dst, (uintptr_t)&gcol, incr_major, end_length);
}
+
+#endif /* __GPU_UNAI_GPU_RASTER_LINE_H__ */
* 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
***************************************************************************/
+#ifndef __GPU_UNAI_GPU_RASTER_POLYGON_H__
+#define __GPU_UNAI_GPU_RASTER_POLYGON_H__
+
//senquack - NOTE: GPU Unai poly routines have been rewritten/adapted
// from DrHell routines to fix multiple issues. See README_senquack.txt
}
} while (++cur_pass < total_passes);
}
+
+#endif /* __GPU_UNAI_GPU_RASTER_POLYGON_H__ */
* 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
***************************************************************************/
+#ifndef __GPU_UNAI_GPU_RASTER_SPRITE_H__
+#define __GPU_UNAI_GPU_RASTER_SPRITE_H__
+
///////////////////////////////////////////////////////////////////////////////
// GPU internal sprite drawing functions
Pixel += FRAME_WIDTH;
}
}
+
+#endif /* __GPU_UNAI_GPU_RASTER_SPRITE_H__ */
+#ifndef __GPU_UNAI_GPU_PORT_H__
+#define __GPU_UNAI_GPU_PORT_H__
+
#include <stddef.h>
#include <string.h>
#undef s32
}
+
+#endif /* __GPU_UNAI_GPU_PORT_H__ */
+#ifndef __GPU_UNAI_GPU_PROFILER_H__
+#define __GPU_UNAI_GPU_PROFILER_H__
+
#define pcsx4all_prof_pause(...)
#define pcsx4all_prof_start_with_pause(...)
#define pcsx4all_prof_end_with_resume(...)
#define pcsx4all_prof_resume(...)
+
+#endif /* __GPU_UNAI_GPU_PROFILER_H__ */
* See the COPYING file in the top-level directory.
*/
+#ifndef __GPULIB_GPU_H__
+#define __GPULIB_GPU_H__
+
#include <stdint.h>
#ifdef __cplusplus
#ifdef __cplusplus
}
#endif
+
+#endif /* __GPULIB_GPU_H__ */
+#ifndef __SPUNULL_REGISTER_H__\r
+#define __SPUNULL_REGISTER_H__\r
+\r
#define H_SPUirqAddr 0x0da4\r
#define H_SPUaddr 0x0da6\r
#define H_SPUdata 0x0da8\r
#define H_SPU_ADSRLevel22 0x0d68\r
#define H_SPU_ADSRLevel23 0x0d78\r
\r
+#endif /* __SPUNULL_REGISTER_H__ */\r