#define CDR_INT(eCycle) { \
psxRegs.interrupt |= 0x4; \
psxRegs.intCycle[2 + 1] = eCycle; \
- psxRegs.intCycle[2] = psxRegs.cycle; }
+ psxRegs.intCycle[2] = psxRegs.cycle; \
+ new_dyna_set_event(0, psxRegs.cycle + eCycle); \
+}
#define CDREAD_INT(eCycle) { \
psxRegs.interrupt |= 0x40000; \
psxRegs.intCycle[2 + 16 + 1] = eCycle; \
- psxRegs.intCycle[2 + 16] = psxRegs.cycle; }
+ psxRegs.intCycle[2 + 16] = psxRegs.cycle; \
+ new_dyna_set_event(2, psxRegs.cycle + eCycle); \
+}
#define StartReading(type, eCycle) { \
cdr.Reading = type; \
#include "../psxmem.h"
#include "../psxhle.h"
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
+
//#define memprintf printf
#define memprintf(...)
//#define evprintf printf
#define evprintf(...)
char invalid_code[0x100000];
+u32 event_cycles[6];
void MTC0_()
{
void gen_interupt()
{
+ u32 c, min;
+ int i;
+
evprintf("ari64_gen_interupt\n");
evprintf(" +ge %08x, %d->%d\n", psxRegs.pc, psxRegs.cycle, next_interupt);
#ifdef DRC_DBG
psxBranchTest();
- next_interupt = psxNextsCounter + psxNextCounter;
+ min = psxNextsCounter + psxNextCounter;
+ for (i = 0; i < ARRAY_SIZE(event_cycles); i++) {
+ c = event_cycles[i];
+ evprintf(" ev %d\n", c - psxRegs.cycle);
+ if (psxRegs.cycle < c && c < min)
+ min = c;
+ }
+ next_interupt = min;
+
+ //next_interupt = psxNextsCounter + psxNextCounter;
evprintf(" -ge %08x, %d->%d\n", psxRegs.pc, psxRegs.cycle, next_interupt);
pending_exception = 1; /* FIXME */
new_dynarec_init();
- for (i = 0; i < sizeof(readmem) / sizeof(readmem[0]); i++) {
+ for (i = 0; i < ARRAY_SIZE(readmem); i++) {
readmemb[i] = read_mem8;
readmemh[i] = read_mem16;
readmem[i] = read_mem32;
writemem[i] = write_mem32;
}
- for (i = 0; i < sizeof(gte_handlers) / sizeof(gte_handlers[0]); i++)
+ for (i = 0; i < ARRAY_SIZE(gte_handlers); i++)
if (psxCP2[i] != psxNULL)
gte_handlers[i] = psxCP2[i];
psxRegs.interrupt |= 0x01000000; \
psxRegs.intCycle[3 + 24 + 1] = eCycle; \
psxRegs.intCycle[3 + 24] = psxRegs.cycle; \
+ new_dyna_set_event(3, psxRegs.cycle + eCycle); \
}
#define SPUDMA_INT(eCycle) { \
psxRegs.interrupt |= 0x04000000; \
psxRegs.intCycle[1 + 24 + 1] = eCycle; \
psxRegs.intCycle[1 + 24] = psxRegs.cycle; \
+ new_dyna_set_event(5, psxRegs.cycle + eCycle); \
}
#define MDECOUTDMA_INT(eCycle) { \
psxRegs.interrupt |= 0x02000000; \
psxRegs.intCycle[5 + 24 + 1] = eCycle; \
psxRegs.intCycle[5 + 24] = psxRegs.cycle; \
+ new_dyna_set_event(4, psxRegs.cycle + eCycle); \
}
void psxDma2(u32 madr, u32 bcr, u32 chcr);
void psxMemWrite32(u32 mem, u32 value);
void *psxMemPointer(u32 mem);
+extern u32 event_cycles[6];
+extern u32 next_interupt;
+
+#define new_dyna_set_event(e, c) { \
+ u32 c_ = c; \
+ event_cycles[e] = c_; \
+ if (c_ < next_interupt) { \
+ /*printf("%u: next_interupt %d -> %d\n", psxRegs.cycle, \
+ next_interupt - psxRegs.cycle, c_ - psxRegs.cycle);*/ \
+ next_interupt = c_; \
+ } \
+}
+
#ifdef __cplusplus
}
#endif
psxRegs.interrupt |= 0x80;
psxRegs.intCycle[7 + 1] = 400;
psxRegs.intCycle[7] = psxRegs.cycle;
+ new_dyna_set_event(1, psxRegs.cycle + 400);
}
}