static unsigned int pppc, ops=0;\r
extern unsigned int lastread_a, lastread_d[16], lastwrite_cyc_d[16], lastwrite_mus_d[16];\r
extern int lrp_cyc, lrp_mus, lwp_cyc, lwp_mus;\r
-unsigned int old_regs[16], old_sr, ppop, have_illegal = 0, dbg_irq_level = 0;\r
+unsigned int old_regs[16], old_sr, ppop, have_illegal = 0;\r
+int dbg_irq_level = 0, dbg_irq_level_sub = 0;\r
\r
#undef dprintf\r
#define dprintf(f,...) printf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__)\r
#define other_is_stopped() (PicoCpuCM68k.state_flags&1)\r
#define other_is_tracing() ((PicoCpuCM68k.state_flags&2)?1:0)\r
#elif defined(EMU_F68K)\r
-#define other_get_sr() PicoCpuFM68k.sr\r
-#define other_dar(i) ((unsigned int*)PicoCpuFM68k.dreg)[i]\r
-#define other_osp PicoCpuFM68k.asp\r
-#define other_get_irq() PicoCpuFM68k.interrupts[0]\r
-#define other_set_irq(irq) PicoCpuFM68k.interrupts[0]=irq\r
-#define other_is_stopped() ((PicoCpuFM68k.execinfo&FM68K_HALTED)?1:0)\r
-#define other_is_tracing() ((PicoCpuFM68k.execinfo&FM68K_EMULATE_TRACE)?1:0)\r
+#define other_set_sub(s) g_m68kcontext=(s)?&PicoCpuFS68k:&PicoCpuFM68k;\r
+#define other_get_sr() g_m68kcontext->sr\r
+#define other_dar(i) ((unsigned int*)g_m68kcontext->dreg)[i]\r
+#define other_osp g_m68kcontext->asp\r
+#define other_get_irq() g_m68kcontext->interrupts[0]\r
+#define other_set_irq(irq) g_m68kcontext->interrupts[0]=irq\r
+#define other_is_stopped() ((g_m68kcontext->execinfo&FM68K_HALTED)?1:0)\r
+#define other_is_tracing() ((g_m68kcontext->execinfo&FM68K_EMULATE_TRACE)?1:0)\r
#else\r
#error other core missing, don't compile this file\r
#endif\r
}\r
\r
//static\r
-void dumpPCandExit()\r
+void dumpPCandExit(int is_sub)\r
{\r
char buff[128];\r
int i;\r
dprintf("d%i=%08x, a%i=%08x | d%i=%08x, a%i=%08x", i, other_dar(i), i, other_dar(i+8), i, old_regs[i], i, old_regs[i+8]);\r
dprintf("SR: %04x | %04x (??s? 0iii 000x nzvc)", other_get_sr(), old_sr);\r
dprintf("last_read: %08x @ %06x", lastread_d[--lrp_cyc&15], lastread_a);\r
- dprintf("ops done: %i", ops);\r
+ dprintf("ops done: %i, is_sub: %i", ops, is_sub);\r
exit(1);\r
}\r
\r
-int CM_compareRun(int cyc)\r
+int CM_compareRun(int cyc, int is_sub)\r
{\r
char *str;\r
- int cyc_done=0, cyc_other, cyc_musashi, err=0;\r
- unsigned int i, mu_sr;\r
+ int cyc_done=0, cyc_other, cyc_musashi, *irq_level, err=0;\r
+ unsigned int i, pc, mu_sr;\r
\r
+ m68ki_cpu_p=is_sub?&PicoCpuMS68k:&PicoCpuMM68k;\r
+ other_set_sub(is_sub);\r
lrp_cyc = lrp_mus = 0;\r
\r
- while(cyc > cyc_done)\r
+ while (cyc_done < cyc)\r
{\r
if (have_illegal && m68k_read_disassembler_16(m68ki_cpu.pc) != 0x4e73) // not rte\r
{\r
//PicoCpuCM68k.srh|=0x20;\r
}\r
\r
- pppc = SekPc;\r
+ pppc = is_sub ? SekPcS68k : SekPc;\r
ppop = m68k_read_disassembler_16(pppc);\r
memcpy(old_regs, &other_dar(0), 4*16);\r
old_sr = other_get_sr();\r
}\r
#endif\r
\r
- if (dbg_irq_level)\r
+ irq_level = is_sub ? &dbg_irq_level_sub : &dbg_irq_level;\r
+ if (*irq_level)\r
{\r
- other_set_irq(dbg_irq_level);\r
- m68k_set_irq(dbg_irq_level);\r
- dbg_irq_level=0;\r
+ other_set_irq(*irq_level);\r
+ m68k_set_irq(*irq_level);\r
+ *irq_level=0;\r
}\r
\r
cyc_other=otherRun();\r
}\r
\r
// compare PC\r
+ pc = is_sub ? SekPcS68k : SekPc;\r
m68ki_cpu.pc&=~1;\r
- if (SekPc != m68ki_cpu.pc) {\r
- dprintf("PC: %06x vs %06x", SekPc, m68ki_cpu.pc);\r
+ if (pc != m68ki_cpu.pc) {\r
+ dprintf("PC: %06x vs %06x", pc, m68ki_cpu.pc);\r
err=1;\r
}\r
\r
err=1;\r
}\r
\r
- if(err) dumpPCandExit();\r
+ if(err) dumpPCandExit(is_sub);\r
\r
#if 0\r
if (PicoCpuCM68k.a[7] < 0x00ff0000 || PicoCpuCM68k.a[7] >= 0x01000000)\r
// For commercial use, separate licencing terms must be obtained.\r
\r
\r
-#define __debug_io\r
+//#define __debug_io\r
\r
#include "PicoInt.h"\r
\r
\r
#ifndef EMU_CORE_DEBUG\r
// sram\r
- if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {\r
+ if (a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {\r
d = SRAMRead(a);\r
elprintf(EL_SRAMIO, "sram r8 [%06x] %02x @ %06x", a, d, SekPc);\r
goto end;\r
dprintf("r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPc);\r
#endif\r
#ifdef EMU_CORE_DEBUG\r
- if(a>=Pico.romsize/*&&(ppop&0x3f)!=0x3a&&(ppop&0x3f)!=0x3b*/) {\r
+ if (a>=Pico.romsize) {\r
lastread_a = a;\r
lastread_d[lrp_cyc++&15] = (u8)d;\r
}\r
\r
#ifndef EMU_CORE_DEBUG\r
// sram\r
- if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {\r
+ if (a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {\r
d = SRAMRead(a);\r
d |= d<<8;\r
elprintf(EL_SRAMIO, "sram r16 [%06x] %04x @ %06x", a, d, SekPc);\r
dprintf("r16: %06x, %04x @%06x", a&0xffffff, d, SekPc);\r
#endif\r
#ifdef EMU_CORE_DEBUG\r
- if(a>=Pico.romsize/*&&(ppop&0x3f)!=0x3a&&(ppop&0x3f)!=0x3b*/) {\r
+ if (a>=Pico.romsize) {\r
lastread_a = a;\r
lastread_d[lrp_cyc++&15] = d;\r
}\r
dprintf("r32: %06x, %08x @%06x", a&0xffffff, d, SekPc);\r
#endif\r
#ifdef EMU_CORE_DEBUG\r
- if(a>=Pico.romsize/*&&(ppop&0x3f)!=0x3a&&(ppop&0x3f)!=0x3b*/) {\r
+ if (a>=Pico.romsize) {\r
lastread_a = a;\r
lastread_d[lrp_cyc++&15] = d;\r
}\r
unsigned int m68k_read_pcrelative_CD32(unsigned int a);\r
\r
// these are allowed to access RAM\r
-static unsigned int m68k_read_8 (unsigned int a, int do_fake) {\r
+static unsigned int m68k_read_8 (unsigned int a, int do_fake)\r
+{\r
a&=0xffffff;\r
- if(PicoMCD&1) return m68k_read_pcrelative_CD8(a);\r
- if(a<Pico.romsize) return *(u8 *)(Pico.rom+(a^1)); // Rom\r
+ if(a<Pico.romsize && m68ki_cpu_p==&PicoCpuMM68k) return *(u8 *)(Pico.rom+(a^1)); // Rom\r
#ifdef EMU_CORE_DEBUG\r
if(do_fake&&((ppop&0x3f)==0x3a||(ppop&0x3f)==0x3b)) return lastread_d[lrp_mus++&15];\r
#endif\r
+ if(PicoMCD&1) return m68k_read_pcrelative_CD8(a);\r
if((a&0xe00000)==0xe00000) return *(u8 *)(Pico.ram+((a^1)&0xffff)); // Ram\r
return 0;\r
}\r
-static unsigned int m68k_read_16(unsigned int a, int do_fake) {\r
+static unsigned int m68k_read_16(unsigned int a, int do_fake)\r
+{\r
a&=0xffffff;\r
- if(PicoMCD&1) return m68k_read_pcrelative_CD16(a);\r
- if(a<Pico.romsize) return *(u16 *)(Pico.rom+(a&~1)); // Rom\r
+ if(a<Pico.romsize && m68ki_cpu_p==&PicoCpuMM68k) return *(u16 *)(Pico.rom+(a&~1)); // Rom\r
#ifdef EMU_CORE_DEBUG\r
if(do_fake&&((ppop&0x3f)==0x3a||(ppop&0x3f)==0x3b)) return lastread_d[lrp_mus++&15];\r
#endif\r
+ if(PicoMCD&1) return m68k_read_pcrelative_CD16(a);\r
if((a&0xe00000)==0xe00000) return *(u16 *)(Pico.ram+(a&0xfffe)); // Ram\r
return 0;\r
}\r
-static unsigned int m68k_read_32(unsigned int a, int do_fake) {\r
+static unsigned int m68k_read_32(unsigned int a, int do_fake)\r
+{\r
a&=0xffffff;\r
- if(PicoMCD&1) return m68k_read_pcrelative_CD32(a);\r
- if(a<Pico.romsize) { u16 *pm=(u16 *)(Pico.rom+(a&~1)); return (pm[0]<<16)|pm[1]; }\r
+ if(a<Pico.romsize && m68ki_cpu_p==&PicoCpuMM68k) { u16 *pm=(u16 *)(Pico.rom+(a&~1)); return (pm[0]<<16)|pm[1]; }\r
#ifdef EMU_CORE_DEBUG\r
if(do_fake&&((ppop&0x3f)==0x3a||(ppop&0x3f)==0x3b)) return lastread_d[lrp_mus++&15];\r
#endif\r
+ if(PicoMCD&1) return m68k_read_pcrelative_CD32(a);\r
if((a&0xe00000)==0xe00000) { u16 *pm=(u16 *)(Pico.ram+(a&0xfffe)); return (pm[0]<<16)|pm[1]; } // Ram\r
return 0;\r
}\r
unsigned int m68k_read_memory_8(unsigned int a)\r
{\r
u8 d;\r
- if(a<Pico.romsize) d = *(u8 *) (Pico.rom+(a^1));\r
+ if (a<Pico.romsize && m68ki_cpu_p==&PicoCpuMM68k)\r
+ d = *(u8 *) (Pico.rom+(a^1));\r
else d = (u8) lastread_d[lrp_mus++&15];\r
#ifdef __debug_io\r
dprintf("r8_mu : %06x, %02x @%06x", a&0xffffff, d, SekPc);\r
unsigned int m68k_read_memory_16(unsigned int a)\r
{\r
u16 d;\r
- if(a<Pico.romsize) d = *(u16 *)(Pico.rom+(a&~1));\r
+ if (a<Pico.romsize && m68ki_cpu_p==&PicoCpuMM68k)\r
+ d = *(u16 *)(Pico.rom+(a&~1));\r
else d = (u16) lastread_d[lrp_mus++&15];\r
#ifdef __debug_io\r
dprintf("r16_mu: %06x, %04x @%06x", a&0xffffff, d, SekPc);\r
unsigned int m68k_read_memory_32(unsigned int a)\r
{\r
u32 d;\r
- if(a<Pico.romsize) {u16 *pm=(u16 *)(Pico.rom+(a&~1));d=(pm[0]<<16)|pm[1];}\r
+ if (a<Pico.romsize && m68ki_cpu_p==&PicoCpuMM68k)\r
+ { u16 *pm=(u16 *)(Pico.rom+(a&~1));d=(pm[0]<<16)|pm[1]; }\r
+ else if (a <= 0x78) d = m68k_read_32(a, 0);\r
else d = lastread_d[lrp_mus++&15];\r
#ifdef __debug_io\r
dprintf("r32_mu: %06x, %08x @%06x", a&0xffffff, d, SekPc);\r
if((cyc_do=SekCycleAim-SekCycleCnt) <= 0) return;\r
#if defined(EMU_CORE_DEBUG)\r
// this means we do run-compare\r
- SekCycleCnt+=CM_compareRun(cyc_do);\r
+ SekCycleCnt+=CM_compareRun(cyc_do, 0);\r
#elif defined(EMU_C68K)\r
PicoCpuCM68k.cycles=cyc_do;\r
CycloneRun(&PicoCpuCM68k);\r
// this is required for timing sensitive stuff to work\r
int realaim=SekCycleAim; SekCycleAim=SekCycleCnt+1;\r
#if defined(EMU_CORE_DEBUG)\r
- SekCycleCnt+=CM_compareRun(1);\r
+ SekCycleCnt+=CM_compareRun(1, 0);\r
#elif defined(EMU_C68K)\r
PicoCpuCM68k.cycles=1;\r
CycloneRun(&PicoCpuCM68k);\r
PICO_INTERNAL void PicoCartDetect(void);\r
\r
// Debug.c\r
-int CM_compareRun(int cyc);\r
+int CM_compareRun(int cyc, int is_sub);\r
\r
// Draw.c\r
PICO_INTERNAL int PicoLine(int scan);\r
memset(&PicoCpuFM68k, 0, sizeof(PicoCpuFM68k));\r
fm68k_init();\r
PicoCpuFM68k.iack_handler = SekIntAckF68K;\r
+ PicoCpuFM68k.sr = 0x2704; // Z flag\r
g_m68kcontext = oldcontext;\r
}\r
#endif\r
{\r
#ifdef EMU_CORE_DEBUG\r
{\r
- extern unsigned int dbg_irq_level;\r
+ extern int dbg_irq_level;\r
dbg_irq_level=irq;\r
return 0;\r
}\r
// Loosely based on Gens code.\r
// (c) Copyright 2007, Grazvydas "notaz" Ignotas\r
\r
-// A68K no longer supported here\r
\r
//#define __debug_io\r
\r
//#define __debug_io\r
//#define __debug_io2\r
\r
-#define rdprintf dprintf\r
-//#define rdprintf(...)\r
+//#define rdprintf dprintf\r
+#define rdprintf(...)\r
//#define wrdprintf dprintf\r
#define wrdprintf(...)\r
#define plprintf dprintf\r
//#define plprintf(...)\r
\r
+#ifdef EMU_CORE_DEBUG\r
+extern u32 lastread_a, lastread_d[16], lastwrite_cyc_d[16];\r
+extern int lrp_cyc, lwp_cyc;\r
+#undef USE_POLL_DETECT\r
+#endif\r
+\r
// -----------------------------------------------------------------\r
\r
// poller detection\r
-//#undef USE_POLL_DETECT\r
#define POLL_LIMIT 16\r
#define POLL_CYCLES 124\r
// int m68k_poll_addr, m68k_poll_cnt;\r
{\r
//dprintf("s68k_regs w%2i: [%02x] %02x @ %06x", realsize, a, d, SekPcS68k);\r
\r
- // TODO: review against Gens\r
// Warning: d might have upper bits set\r
switch (a) {\r
case 2:\r
// -----------------------------------------------------------------\r
// Read Rom and read Ram\r
\r
-//u8 PicoReadM68k8_(u32 a);\r
#ifdef _ASM_CD_MEMORY_C\r
u32 PicoReadM68k8(u32 a);\r
#else\r
\r
#ifdef __debug_io\r
dprintf("r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPc);\r
+#endif\r
+#ifdef EMU_CORE_DEBUG\r
+ if (a>=Pico.romsize) {\r
+ lastread_a = a;\r
+ lastread_d[lrp_cyc++&15] = d;\r
+ }\r
#endif\r
return d;\r
}\r
\r
#ifdef __debug_io\r
dprintf("r16: %06x, %04x @%06x", a&0xffffff, d, SekPc);\r
+#endif\r
+#ifdef EMU_CORE_DEBUG\r
+ if (a>=Pico.romsize) {\r
+ lastread_a = a;\r
+ lastread_d[lrp_cyc++&15] = d;\r
+ }\r
#endif\r
return d;\r
}\r
end:\r
#ifdef __debug_io\r
dprintf("r32: %06x, %08x @%06x", a&0xffffff, d, SekPc);\r
+#endif\r
+#ifdef EMU_CORE_DEBUG\r
+ if (a>=Pico.romsize) {\r
+ lastread_a = a;\r
+ lastread_d[lrp_cyc++&15] = d;\r
+ }\r
#endif\r
return d;\r
}\r
#ifdef __debug_io\r
dprintf("w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);\r
#endif\r
- //if ((a&0xe0ffff)==0xe0a9ba+0x69c)\r
- // dprintf("w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);\r
-\r
+#ifdef EMU_CORE_DEBUG\r
+ lastwrite_cyc_d[lwp_cyc++&15] = d;\r
+#endif\r
\r
if ((a&0xe00000)==0xe00000) { // Ram\r
*(u8 *)(Pico.ram+((a^1)&0xffff)) = d;\r
#ifdef __debug_io\r
dprintf("w16: %06x, %04x", a&0xffffff, d);\r
#endif\r
- // dprintf("w16: %06x, %04x @%06x", a&0xffffff, d, SekPc);\r
+#ifdef EMU_CORE_DEBUG\r
+ lastwrite_cyc_d[lwp_cyc++&15] = d;\r
+#endif\r
\r
if ((a&0xe00000)==0xe00000) { // Ram\r
*(u16 *)(Pico.ram+(a&0xfffe))=d;\r
#ifdef __debug_io\r
dprintf("w32: %06x, %08x", a&0xffffff, d);\r
#endif\r
+#ifdef EMU_CORE_DEBUG\r
+ lastwrite_cyc_d[lwp_cyc++&15] = d;\r
+#endif\r
\r
if ((a&0xe00000)==0xe00000)\r
{\r
{\r
u32 d=0;\r
\r
+#ifdef EMU_CORE_DEBUG\r
+ u32 ab=a&0xfffffe;\r
+#endif\r
a&=0xffffff;\r
\r
// prg RAM\r
\r
#ifdef __debug_io2\r
dprintf("s68k r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPcS68k);\r
+#endif\r
+#ifdef EMU_CORE_DEBUG\r
+ lastread_a = ab;\r
+ lastread_d[lrp_cyc++&15] = d;\r
#endif\r
return d;\r
}\r
{\r
u32 d=0;\r
\r
+#ifdef EMU_CORE_DEBUG\r
+ u32 ab=a&0xfffffe;\r
+#endif\r
a&=0xfffffe;\r
\r
// prg RAM\r
\r
#ifdef __debug_io2\r
dprintf("s68k r16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);\r
+#endif\r
+#ifdef EMU_CORE_DEBUG\r
+ lastread_a = ab;\r
+ lastread_d[lrp_cyc++&15] = d;\r
#endif\r
return d;\r
}\r
{\r
u32 d=0;\r
\r
+#ifdef EMU_CORE_DEBUG\r
+ u32 ab=a&0xfffffe;\r
+#endif\r
a&=0xfffffe;\r
\r
// prg RAM\r
\r
#ifdef __debug_io2\r
dprintf("s68k r32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);\r
+#endif\r
+#ifdef EMU_CORE_DEBUG\r
+ if (ab > 0x78) { // not vectors and stuff\r
+ lastread_a = ab;\r
+ lastread_d[lrp_cyc++&15] = d;\r
+ }\r
#endif\r
return d;\r
}\r
\r
a&=0xffffff;\r
\r
+#ifdef EMU_CORE_DEBUG\r
+ lastwrite_cyc_d[lwp_cyc++&15] = d;\r
+#endif\r
+\r
// prg RAM\r
if (a < 0x80000) {\r
u8 *pm=(u8 *)(Pico_mcd->prg_ram+(a^1));\r
\r
a&=0xfffffe;\r
\r
+#ifdef EMU_CORE_DEBUG\r
+ lastwrite_cyc_d[lwp_cyc++&15] = d;\r
+#endif\r
+\r
// prg RAM\r
if (a < 0x80000) {\r
wrdprintf("s68k_prgram w16: [%06x] %04x @%06x", a, d, SekPcS68k);\r
\r
a&=0xfffffe;\r
\r
+#ifdef EMU_CORE_DEBUG\r
+ lastwrite_cyc_d[lwp_cyc++&15] = d;\r
+#endif\r
+\r
// prg RAM\r
if (a < 0x80000) {\r
if (a >= (Pico_mcd->s68k_regs[2]<<8)) {\r
}\r
\r
// these are allowed to access RAM\r
-unsigned int m68k_read_pcrelative_CD8 (unsigned int a) {\r
+unsigned int m68k_read_pcrelative_CD8 (unsigned int a)\r
+{\r
a&=0xffffff;\r
if(m68ki_cpu_p == &PicoCpuMS68k) {\r
if (a < 0x80000) return *(u8 *)(Pico_mcd->prg_ram+(a^1)); // PRG Ram\r
}\r
return 0;//(u8) lastread_d;\r
}\r
-unsigned int m68k_read_pcrelative_CD16(unsigned int a) {\r
+unsigned int m68k_read_pcrelative_CD16(unsigned int a)\r
+{\r
a&=0xffffff;\r
if(m68ki_cpu_p == &PicoCpuMS68k) {\r
if (a < 0x80000) return *(u16 *)(Pico_mcd->prg_ram+(a&~1)); // PRG Ram\r
}\r
return 0;\r
}\r
-unsigned int m68k_read_pcrelative_CD32(unsigned int a) {\r
+unsigned int m68k_read_pcrelative_CD32(unsigned int a)\r
+{\r
u16 *pm;\r
a&=0xffffff;\r
if(m68ki_cpu_p == &PicoCpuMS68k) {\r
int cyc_do;
SekCycleAim+=cyc;
if ((cyc_do=SekCycleAim-SekCycleCnt) <= 0) return;
-#if defined(EMU_C68K)
+#if defined(EMU_CORE_DEBUG)
+ SekCycleCnt+=CM_compareRun(cyc_do, 0);
+#elif defined(EMU_C68K)
PicoCpuCM68k.cycles=cyc_do;
CycloneRun(&PicoCpuCM68k);
SekCycleCnt+=cyc_do-PicoCpuCM68k.cycles;
int cyc_do;
SekCycleAimS68k+=cyc;
if ((cyc_do=SekCycleAimS68k-SekCycleCntS68k) <= 0) return;
-#if defined(EMU_C68K)
+#if defined(EMU_CORE_DEBUG)
+ SekCycleCntS68k+=CM_compareRun(cyc_do, 1);
+#elif defined(EMU_C68K)
PicoCpuCS68k.cycles=cyc_do;
CycloneRun(&PicoCpuCS68k);
SekCycleCntS68k+=cyc_do-PicoCpuCS68k.cycles;
#ifdef EMU_M68K
static int SekIntAckMS68k(int level)
{
+#ifndef EMU_CORE_DEBUG
int level_new = new_irq_level(level);
dprintf("s68kACK %i -> %i", level, level_new);
CPU_INT_LEVEL = level_new << 8;
+#else
+ CPU_INT_LEVEL = 0;
+#endif
return M68K_INT_ACK_AUTOVECTOR;
}
#endif
{
int level_new = new_irq_level(level);
dprintf("s68kACK %i -> %i", level, level_new);
+#ifndef EMU_CORE_DEBUG
PicoCpuFS68k.interrupts[0] = level_new;
+#else
+ {
+ extern int dbg_irq_level_sub;
+ dbg_irq_level_sub = level_new;
+ PicoCpuFS68k.interrupts[0] = 0;
+ }
+#endif
}
#endif
memset(&PicoCpuFS68k, 0, sizeof(PicoCpuFS68k));
fm68k_init();
PicoCpuFS68k.iack_handler = SekIntAckFS68k;
+ PicoCpuFS68k.sr = 0x2704; // Z flag
g_m68kcontext = oldcontext;
}
#endif
irqs = Pico_mcd->m.s68k_pend_ints >> 1;
while ((irqs >>= 1)) real_irq++;
+#ifdef EMU_CORE_DEBUG
+ {
+ extern int dbg_irq_level_sub;
+ dbg_irq_level_sub=real_irq;
+ elprintf(EL_ANOMALY, "s68k irq %i", real_irq);
+ return 0;
+ }
+#endif
#ifdef EMU_C68K
PicoCpuCS68k.irq=real_irq;
#endif
\r
#define USE_CYCLONE_TIMING\r
#define USE_CYCLONE_TIMING_DIV\r
+#define PICODRIVE_HACK\r
// Options //\r
\r
\r
\r
static u32 initialised = 0;\r
\r
+#ifdef PICODRIVE_HACK\r
+extern M68K_CONTEXT PicoCpuFS68k;\r
+#endif\r
+\r
/* Custom function handler */\r
typedef void (*opcode_func)(void);\r
\r
// won't emulate double fault\r
// if (m68kcontext.execinfo & M68K_FAULTED) return -1;\r
\r
+ // Cache PPL\r
+ flag_I = M68K_PPL;\r
+\r
if (m68kcontext.execinfo & FM68K_HALTED)\r
{\r
if (interrupt_chk__() <= 0)\r
// Cache SR\r
SET_SR(m68kcontext.sr)\r
\r
- // Cache PPL\r
- flag_I = M68K_PPL;\r
-\r
// Fijar PC\r
SET_PC(m68kcontext.pc)\r
\r
#endif\r
u32 i, j;\r
\r
- m68kcontext.sr = 0x2704; // Z flag\r
-\r
for(i = 0x0000; i <= 0xFFFF; i += 0x0001)\r
JumpTable[0x0000 + i] = CAST_OP(0x4AFC);\r
for(i = 0x0000; i <= 0x0007; i += 0x0001)\r
flag_V = 0;
flag_NotZ = res;
flag_N = res;
+#ifdef PICODRIVE_HACK
+ if (g_m68kcontext == &PicoCpuFS68k) {
+ res |= 0x80;
+ WRITE_BYTE_F(adr, res);
+ }
+#endif
+
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(18)
+#else
RET(8)
+#endif
}
// TAS
flag_V = 0;
flag_NotZ = res;
flag_N = res;
+
+#ifdef PICODRIVE_HACK
+ if (g_m68kcontext == &PicoCpuFS68k) {
+ res |= 0x80;
+ WRITE_BYTE_F(adr, res);
+ }
+#endif
+
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(18)
+#else
RET(8)
+#endif
}
// TAS
flag_V = 0;
flag_NotZ = res;
flag_N = res;
+
+#ifdef PICODRIVE_HACK
+ if (g_m68kcontext == &PicoCpuFS68k) {
+ res |= 0x80;
+ WRITE_BYTE_F(adr, res);
+ }
+#endif
+
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(20)
+#else
RET(10)
+#endif
}
// TAS
flag_V = 0;
flag_NotZ = res;
flag_N = res;
+
+#ifdef PICODRIVE_HACK
+ if (g_m68kcontext == &PicoCpuFS68k) {
+ res |= 0x80;
+ WRITE_BYTE_F(adr, res);
+ }
+#endif
+
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(22)
+#else
RET(12)
+#endif
}
// TAS
flag_V = 0;
flag_NotZ = res;
flag_N = res;
+
+#ifdef PICODRIVE_HACK
+ if (g_m68kcontext == &PicoCpuFS68k) {
+ res |= 0x80;
+ WRITE_BYTE_F(adr, res);
+ }
+#endif
+
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(24)
+#else
RET(14)
+#endif
}
// TAS
flag_V = 0;
flag_NotZ = res;
flag_N = res;
+
+#ifdef PICODRIVE_HACK
+ if (g_m68kcontext == &PicoCpuFS68k) {
+ res |= 0x80;
+ WRITE_BYTE_F(adr, res);
+ }
+#endif
+
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(22)
+#else
RET(12)
+#endif
}
// TAS
flag_V = 0;
flag_NotZ = res;
flag_N = res;
+
+#ifdef PICODRIVE_HACK
+ if (g_m68kcontext == &PicoCpuFS68k) {
+ res |= 0x80;
+ WRITE_BYTE_F(adr, res);
+ }
+#endif
+
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(26)
+#else
RET(16)
+#endif
}
// TAS
flag_V = 0;
flag_NotZ = res;
flag_N = res;
+
+#ifdef PICODRIVE_HACK
+ if (g_m68kcontext == &PicoCpuFS68k) {
+ res |= 0x80;
+ WRITE_BYTE_F(adr, res);
+ }
+#endif
+
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(18)
+#else
RET(8)
+#endif
}
// TAS
flag_V = 0;
flag_NotZ = res;
flag_N = res;
+
+#ifdef PICODRIVE_HACK
+ if (g_m68kcontext == &PicoCpuFS68k) {
+ res |= 0x80;
+ WRITE_BYTE_F(adr, res);
+ }
+#endif
+
POST_IO
-RET(10)
+#ifdef USE_CYCLONE_TIMING
+RET(20)
+#else
+RET(8)
+#endif
}
// ILLEGAL
FLAG_INT_MASK = int_level<<8;\r
\r
/* Get the new PC */\r
- new_pc = m68ki_read_data_32((vector<<2) + REG_VBR);\r
+ //new_pc = m68ki_read_data_32((vector<<2) + REG_VBR);\r
+ new_pc = m68k_read_immediate_32((vector<<2) + REG_VBR); // notaz hack\r
\r
/* If vector is uninitialized, call the uninitialized interrupt vector */\r
if(new_pc == 0)\r