}
}
+// MUST specify active_sh2 when called from sh2 memhandlers
void p32x_update_irls(SH2 *active_sh2, int m68k_cycles)
{
int irqs, mlvl = 0, slvl = 0;
slvl++;
slvl *= 2;
- mrun = sh2_irl_irq(&msh2, mlvl, active_sh2 != NULL);
- if (mrun)
+ mrun = sh2_irl_irq(&msh2, mlvl, active_sh2 == &msh2);
+ if (mrun) {
p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, m68k_cycles);
+ if (active_sh2 == &msh2)
+ sh2_end_run(active_sh2, 1);
+ }
- srun = sh2_irl_irq(&ssh2, slvl, active_sh2 != NULL);
- if (srun)
+ srun = sh2_irl_irq(&ssh2, slvl, active_sh2 == &ssh2);
+ if (srun) {
p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, m68k_cycles);
+ if (active_sh2 == &ssh2)
+ sh2_end_run(active_sh2, 1);
+ }
elprintf(EL_32X, "update_irls: m %d/%d, s %d/%d", mlvl, mrun, slvl, srun);
}
p32x_event_schedule(now, event, after);
left_to_next = (event_time_next - now) * 3;
- if (sh2_cycles_left(sh2) > left_to_next)
- sh2_end_run(sh2, left_to_next);
+ sh2_end_run(sh2, left_to_next);
}
static void run_events(unsigned int until)
}
if ((a & 0x30) == 0x30)
- return p32x_pwm_read16(a, SekCyclesDoneT());
+ return p32x_pwm_read16(a, NULL, SekCyclesDoneT());
out:
return Pico32x.regs[a / 2];
}
// PWM
else if ((a & 0x30) == 0x30) {
- p32x_pwm_write16(a, d, SekCyclesDoneT());
+ p32x_pwm_write16(a, d, NULL, SekCyclesDoneT());
return;
}
return r[a / 2];
}
if ((a & 0x30) == 0x30) {
- return p32x_pwm_read16(a, sh2_cycles_done_m68k(&sh2s[cpuid]));
+ return p32x_pwm_read16(a, &sh2s[cpuid], sh2_cycles_done_m68k(&sh2s[cpuid]));
}
return 0;
}
// PWM
else if ((a & 0x30) == 0x30) {
- p32x_pwm_write16(a, d, sh2_cycles_done_m68k(&sh2s[cpuid]));
+ p32x_pwm_write16(a, d, &sh2s[cpuid], sh2_cycles_done_m68k(&sh2s[cpuid]));
return;
}
Pico32x.pwm_irq_cnt = pwm_irq_reload;
}
-static void do_pwm_irq(unsigned int m68k_cycles)
+static void do_pwm_irq(SH2 *sh2, unsigned int m68k_cycles)
{
Pico32x.sh2irqs |= P32XI_PWM;
- p32x_update_irls(NULL, m68k_cycles);
+ p32x_update_irls(sh2, m68k_cycles);
if (Pico32x.regs[0x30 / 2] & P32XP_RTP) {
p32x_event_schedule(m68k_cycles, P32X_EVENT_PWM, pwm_cycles / 3 + 1);
}
}
-#define consume_fifo(m68k_cycles) { \
+#define consume_fifo(sh2, m68k_cycles) { \
int cycles_diff = ((m68k_cycles) * 3) - Pico32x.pwm_cycle_p; \
if (cycles_diff >= pwm_cycles) \
- consume_fifo_do(m68k_cycles, cycles_diff); \
+ consume_fifo_do(sh2, m68k_cycles, cycles_diff); \
}
-static void consume_fifo_do(unsigned int m68k_cycles, int sh2_cycles_diff)
+static void consume_fifo_do(SH2 *sh2, unsigned int m68k_cycles,
+ int sh2_cycles_diff)
{
int do_irq = 0;
Pico32x.pwm_cycle_p = m68k_cycles * 3 - sh2_cycles_diff;
if (do_irq)
- do_pwm_irq(m68k_cycles);
+ do_pwm_irq(sh2, m68k_cycles);
}
-static int p32x_pwm_schedule_(unsigned int m68k_now)
+static int p32x_pwm_schedule_(SH2 *sh2, unsigned int m68k_now)
{
unsigned int sh2_now = m68k_now * 3;
int cycles_diff_sh2;
cycles_diff_sh2 = sh2_now - Pico32x.pwm_cycle_p;
if (cycles_diff_sh2 >= pwm_cycles)
- consume_fifo_do(m68k_now, cycles_diff_sh2);
+ consume_fifo_do(sh2, m68k_now, cycles_diff_sh2);
if (Pico32x.sh2irqs & P32XI_PWM)
return 0; // previous not acked
void p32x_pwm_schedule(unsigned int m68k_now)
{
- int after = p32x_pwm_schedule_(m68k_now);
+ int after = p32x_pwm_schedule_(NULL, m68k_now);
if (after != 0)
p32x_event_schedule(m68k_now, P32X_EVENT_PWM, after);
}
void p32x_pwm_schedule_sh2(SH2 *sh2)
{
- int after = p32x_pwm_schedule_(sh2_cycles_done_m68k(sh2));
+ int after = p32x_pwm_schedule_(sh2, sh2_cycles_done_m68k(sh2));
if (after != 0)
p32x_event_schedule_sh2(sh2, P32X_EVENT_PWM, after);
}
p32x_pwm_schedule(m68k_now);
}
-unsigned int p32x_pwm_read16(unsigned int a, unsigned int m68k_cycles)
+unsigned int p32x_pwm_read16(unsigned int a, SH2 *sh2,
+ unsigned int m68k_cycles)
{
unsigned int d = 0;
- consume_fifo(m68k_cycles);
+ consume_fifo(sh2, m68k_cycles);
a &= 0x0e;
switch (a) {
}
void p32x_pwm_write16(unsigned int a, unsigned int d,
- unsigned int m68k_cycles)
+ SH2 *sh2, unsigned int m68k_cycles)
{
elprintf(EL_PWM, "pwm: %u: w16 %02x %04x (p %d %d)",
m68k_cycles, a & 0x0e, d, Pico32x.pwm_p[0], Pico32x.pwm_p[1]);
- consume_fifo(m68k_cycles);
+ consume_fifo(sh2, m68k_cycles);
a &= 0x0e;
if (a == 0) { // control
#ifndef DRC_SH2\r
# define sh2_end_run(sh2, after_) do { \\r
if ((sh2)->icount > (after_)) { \\r
- (sh2)->cycles_timeslice -= (sh2)->icount; \\r
+ (sh2)->cycles_timeslice -= (sh2)->icount - (after_); \\r
(sh2)->icount = after_; \\r
} \\r
} while (0)\r
# define sh2_end_run(sh2, after_) do { \\r
int left_ = (signed int)(sh2)->sr >> 12; \\r
if (left_ > (after_)) { \\r
- (sh2)->cycles_timeslice -= left_; \\r
+ (sh2)->cycles_timeslice -= left_ - (after_); \\r
(sh2)->sr &= 0xfff; \\r
(sh2)->sr |= (after_) << 12; \\r
} \\r
extern int Pico32xDrawMode;\r
\r
// 32x/pwm.c\r
-unsigned int p32x_pwm_read16(unsigned int a, unsigned int cycles);\r
-void p32x_pwm_write16(unsigned int a, unsigned int d, unsigned int cycles);\r
+unsigned int p32x_pwm_read16(unsigned int a, SH2 *sh2,\r
+ unsigned int m68k_cycles);\r
+void p32x_pwm_write16(unsigned int a, unsigned int d,\r
+ SH2 *sh2, unsigned int m68k_cycles);\r
void p32x_pwm_update(int *buf32, int length, int stereo);\r
void p32x_pwm_ctl_changed(void);\r
void p32x_pwm_schedule(unsigned int m68k_now);\r