libpcsxcore/decode_xa.o libpcsxcore/mdec.o \
libpcsxcore/misc.o libpcsxcore/plugins.o libpcsxcore/ppf.o libpcsxcore/psxbios.o \
libpcsxcore/psxcommon.o libpcsxcore/psxcounters.o libpcsxcore/psxdma.o \
- libpcsxcore/psxhw.o libpcsxcore/psxinterpreter.o libpcsxcore/psxmem.o libpcsxcore/r3000a.o \
+ libpcsxcore/psxhw.o libpcsxcore/psxinterpreter.o libpcsxcore/psxmem.o \
+ libpcsxcore/psxevents.o libpcsxcore/r3000a.o \
libpcsxcore/sio.o libpcsxcore/spu.o libpcsxcore/gpu.o
OBJS += libpcsxcore/gte.o libpcsxcore/gte_nf.o libpcsxcore/gte_divider.o
else
CFLAGS += -DDRC_DISABLE
endif
-OBJS += libpcsxcore/new_dynarec/emu_if.o libpcsxcore/new_dynarec/events.o
+OBJS += libpcsxcore/new_dynarec/emu_if.o
libpcsxcore/new_dynarec/new_dynarec.o: libpcsxcore/new_dynarec/pcsxmem_inline.c
ifdef DRC_DBG
libpcsxcore/new_dynarec/emu_if.o: CFLAGS += -D_FILE_OFFSET_BITS=64
$(CORE_DIR)/psxcommon.c \
$(CORE_DIR)/psxcounters.c \
$(CORE_DIR)/psxdma.c \
+ $(CORE_DIR)/psxevents.c \
$(CORE_DIR)/psxhw.c \
$(CORE_DIR)/psxinterpreter.c \
$(CORE_DIR)/psxmem.c \
endif
endif
SOURCES_C += $(DYNAREC_DIR)/emu_if.c
- SOURCES_C += $(DYNAREC_DIR)/events.c
ifeq ($(HAVE_LIGHTREC),1)
COREFLAGS += -DLIGHTREC -DLIGHTREC_STATIC
#include "misc.h"
#include "ppf.h"
#include "psxdma.h"
+#include "psxevents.h"
#include "arm_features.h"
/* logging */
msf[2] = s;
}
-// cdrInterrupt
-#define CDR_INT(eCycle) { \
- psxRegs.interrupt |= (1 << PSXINT_CDR); \
- psxRegs.intCycle[PSXINT_CDR].cycle = eCycle; \
- psxRegs.intCycle[PSXINT_CDR].sCycle = psxRegs.cycle; \
- new_dyna_set_event(PSXINT_CDR, eCycle); \
-}
-
// cdrPlayReadInterrupt
#define CDRPLAYREAD_INT(eCycle, isFirst) { \
u32 e_ = eCycle; \
else \
psxRegs.intCycle[PSXINT_CDREAD].sCycle += psxRegs.intCycle[PSXINT_CDREAD].cycle; \
psxRegs.intCycle[PSXINT_CDREAD].cycle = e_; \
- new_dyna_set_event_abs(PSXINT_CDREAD, psxRegs.intCycle[PSXINT_CDREAD].sCycle + e_); \
-}
-
-// cdrLidSeekInterrupt
-#define CDRLID_INT(eCycle) { \
- psxRegs.interrupt |= (1 << PSXINT_CDRLID); \
- psxRegs.intCycle[PSXINT_CDRLID].cycle = eCycle; \
- psxRegs.intCycle[PSXINT_CDRLID].sCycle = psxRegs.cycle; \
- new_dyna_set_event(PSXINT_CDRLID, eCycle); \
+ set_event_raw_abs(PSXINT_CDREAD, psxRegs.intCycle[PSXINT_CDREAD].sCycle + e_); \
}
#define StopReading() { \
{
memset(cdr.Prev, 0xff, sizeof(cdr.Prev));
cdr.DriveState = DRIVESTATE_LID_OPEN;
- CDRLID_INT(0x800);
+ set_event(PSXINT_CDRLID, 0x800);
}
break;
// only sometimes does that
// (not done when lots of commands are sent?)
- CDRLID_INT(cdReadTime * 30);
+ set_event(PSXINT_CDRLID, cdReadTime * 30);
break;
}
else if (cdr.StatP & STATUS_ROTATING) {
// and is only cleared by CdlNop
cdr.DriveState = DRIVESTATE_RESCAN_CD;
- CDRLID_INT(cdReadTime * 105);
+ set_event(PSXINT_CDRLID, cdReadTime * 105);
break;
}
// recheck for close
- CDRLID_INT(cdReadTime * 3);
+ set_event(PSXINT_CDRLID, cdReadTime * 3);
break;
case DRIVESTATE_RESCAN_CD:
// this is very long on real hardware, over 6 seconds
// make it a bit faster here...
- CDRLID_INT(cdReadTime * 150);
+ set_event(PSXINT_CDRLID, cdReadTime * 150);
break;
case DRIVESTATE_PREPARE_CD:
}
else {
SetPlaySeekRead(cdr.StatP, STATUS_SEEK);
- CDRLID_INT(cdReadTime * 26);
+ set_event(PSXINT_CDRLID, cdReadTime * 26);
}
break;
}
// yes, it really sets STATUS_SHELLOPEN
cdr.StatP |= STATUS_SHELLOPEN;
cdr.DriveState = DRIVESTATE_RESCAN_CD;
- CDRLID_INT(20480);
+ set_event(PSXINT_CDRLID, 20480);
start_rotating = 1;
break;
if (second_resp_time) {
cdr.CmdInProgress = Cmd | 0x100;
- CDR_INT(second_resp_time);
+ set_event(PSXINT_CDR, second_resp_time);
}
else if (cdr.Cmd && cdr.Cmd != (Cmd & 0xff)) {
cdr.CmdInProgress = cdr.Cmd;
if (!cdr.CmdInProgress) {
cdr.CmdInProgress = rt;
// should be something like 12k + controller delays
- CDR_INT(5000);
+ set_event(PSXINT_CDR, 5000);
}
else {
CDR_LOG_I("cmd while busy: %02x, prev %02x, busy %02x\n",
c = 2048 - (psxRegs.cycle - nextCycle);
c = MAX_VALUE(c, 512);
}
- CDR_INT(c);
+ set_event(PSXINT_CDR, c);
}
}
cdr.Stat &= ~rt;
}
psxCpu->Clear(madr, cdsize / 4);
- CDRDMA_INT((cdsize/4) * 24);
+ set_event(PSXINT_CDRDMA, (cdsize / 4) * 24);
HW_DMA3_CHCR &= SWAPu32(~0x10000000);
if (chcr & 0x100) {
break;
case PGS_PRIMITIVE_START:
HW_GPU_STATUS &= ~SWAP32(PSXGPU_nBUSY);
- GPUDMA_INT(200); // see gpuInterrupt
+ set_event(PSXINT_GPUDMA, 200); // see gpuInterrupt
break;
}
}
#include "../r3000a.h"
#include "../psxinterpreter.h"
#include "../psxhle.h"
-#include "../new_dynarec/events.h"
+#include "../psxevents.h"
#include "../frontend/main.h"
break;
}
- MDECINDMA_INT(size);
+ set_event(PSXINT_MDECINDMA, size);
}
void mdec0Interrupt()
}
/* define the power of mdec */
- MDECOUTDMA_INT(words * MDEC_BIAS);
+ set_event(PSXINT_MDECOUTDMA, words * MDEC_BIAS);
/* some CPU stalling */
psxRegs.cycle += words;
}
new_dyna_freeze(f, 0);
padFreeze(f, 0);
+ events_restore();
if (Config.HLE)
psxBiosCheckExe(biosBranchCheckOld, 0x60, 1);
#include "emu_if.h"
#include "pcsxmem.h"
-#include "events.h"
#include "../psxhle.h"
#include "../psxinterpreter.h"
#include "../psxcounters.h"
+#include "../psxevents.h"
#include "../r3000a.h"
#include "../gte_arm.h"
#include "../gte_neon.h"
MTC0(&psxRegs, reg, val);
}
-static void new_dyna_restore(void)
-{
- int i;
- for (i = 0; i < PSXINT_COUNT; i++)
- event_cycles[i] = psxRegs.intCycle[i].sCycle + psxRegs.intCycle[i].cycle;
-
- event_cycles[PSXINT_RCNT] = psxNextsCounter + psxNextCounter;
- psxRegs.interrupt |= 1 << PSXINT_RCNT;
- psxRegs.interrupt &= (1 << PSXINT_COUNT) - 1;
-
- new_dyna_pcsx_mem_load_state();
-}
-
void new_dyna_freeze(void *f, int mode)
{
const char header_save[8] = "ariblks";
SaveFuncs.write(f, addrs, size);
}
else {
- new_dyna_restore();
+ new_dyna_pcsx_mem_load_state();
bytes = SaveFuncs.read(f, header, sizeof(header));
if (bytes != sizeof(header) || strcmp(header, header_save)) {
{
new_dyna_pcsx_mem_reset();
new_dynarec_invalidate_all_pages();
- new_dyna_restore();
+ new_dyna_pcsx_mem_load_state();
pending_exception = 1;
}
+++ /dev/null
-#include "../psxcommon.h"
-
-extern int stop;
-
-union psxCP0Regs_;
-u32 schedule_timeslice(void);
-void gen_interupt(union psxCP0Regs_ *cp0);
#include "sio.h"
#include "psxhle.h"
#include "psxinterpreter.h"
-#include "new_dynarec/events.h"
+#include "psxevents.h"
#include <zlib.h>
#ifndef PSXBIOS_LOG
*/
#include "psxcounters.h"
+#include "psxevents.h"
#include "gpu.h"
//#include "debug.h"
#define DebugVSync()
}
}
- psxRegs.interrupt |= (1 << PSXINT_RCNT);
- new_dyna_set_event(PSXINT_RCNT, psxNextCounter);
+ set_event(PSXINT_RCNT, psxNextCounter);
}
/******************************************************************************/
// This should be much slower, like 12+ cycles/byte, it's like
// that because the CPU runs too fast and fifo is not emulated.
// See also set_dma_end().
- SPUDMA_INT(words * 4);
+ set_event(PSXINT_SPUDMA, words * 4);
return;
case 0x01000200: //spu to cpu transfer
psxCpu->Clear(madr, words_copy);
HW_DMA4_MADR = SWAPu32(madr + words_copy * 4);
- SPUDMA_INT(words * 4);
+ set_event(PSXINT_SPUDMA, words * 4);
return;
default:
// careful: gpu_state_change() also messes with this
HW_GPU_STATUS &= SWAP32(~PSXGPU_nBUSY);
// already 32-bit word size ((size * 4) / 4)
- GPUDMA_INT(words / 4);
+ set_event(PSXINT_GPUDMA, words / 4);
return;
case 0x01000201: // mem2vram
// careful: gpu_state_change() also messes with this
HW_GPU_STATUS &= SWAP32(~PSXGPU_nBUSY);
// already 32-bit word size ((size * 4) / 4)
- GPUDMA_INT(words / 4);
+ set_event(PSXINT_GPUDMA, words / 4);
return;
case 0x01000401: // dma chain
// Einhander = parse linked list in pieces (todo)
// Rebel Assault 2 = parse linked list in pieces (todo)
- GPUDMA_INT(size);
+ set_event(PSXINT_GPUDMA, size);
return;
default:
u32 size, madr_next = 0xffffff;
size = GPU_dmaChain((u32 *)psxM, HW_DMA2_MADR & 0x1fffff, &madr_next);
HW_DMA2_MADR = SWAPu32(madr_next);
- GPUDMA_INT(size);
+ set_event(PSXINT_GPUDMA, size);
return;
}
if (HW_DMA2_CHCR & SWAP32(0x01000000))
}
*++mem = SWAP32(0xffffff);
- //GPUOTCDMA_INT(size);
// halted
psxRegs.cycle += words;
- GPUOTCDMA_INT(16);
+ set_event(PSXINT_GPUOTCDMA, 16);
return;
}
else {
#include "r3000a.h"
#include "psxhw.h"
#include "psxmem.h"
-
-#define GPUDMA_INT(eCycle) { \
- psxRegs.interrupt |= (1 << PSXINT_GPUDMA); \
- psxRegs.intCycle[PSXINT_GPUDMA].cycle = eCycle; \
- psxRegs.intCycle[PSXINT_GPUDMA].sCycle = psxRegs.cycle; \
- new_dyna_set_event(PSXINT_GPUDMA, eCycle); \
-}
-
-#define SPUDMA_INT(eCycle) { \
- psxRegs.interrupt |= (1 << PSXINT_SPUDMA); \
- psxRegs.intCycle[PSXINT_SPUDMA].cycle = eCycle; \
- psxRegs.intCycle[PSXINT_SPUDMA].sCycle = psxRegs.cycle; \
- new_dyna_set_event(PSXINT_SPUDMA, eCycle); \
-}
-
-#define MDECOUTDMA_INT(eCycle) { \
- psxRegs.interrupt |= (1 << PSXINT_MDECOUTDMA); \
- psxRegs.intCycle[PSXINT_MDECOUTDMA].cycle = eCycle; \
- psxRegs.intCycle[PSXINT_MDECOUTDMA].sCycle = psxRegs.cycle; \
- new_dyna_set_event(PSXINT_MDECOUTDMA, eCycle); \
-}
-
-#define MDECINDMA_INT(eCycle) { \
- psxRegs.interrupt |= (1 << PSXINT_MDECINDMA); \
- psxRegs.intCycle[PSXINT_MDECINDMA].cycle = eCycle; \
- psxRegs.intCycle[PSXINT_MDECINDMA].sCycle = psxRegs.cycle; \
- new_dyna_set_event(PSXINT_MDECINDMA, eCycle); \
-}
-
-#define GPUOTCDMA_INT(eCycle) { \
- psxRegs.interrupt |= (1 << PSXINT_GPUOTCDMA); \
- psxRegs.intCycle[PSXINT_GPUOTCDMA].cycle = eCycle; \
- psxRegs.intCycle[PSXINT_GPUOTCDMA].sCycle = psxRegs.cycle; \
- new_dyna_set_event(PSXINT_GPUOTCDMA, eCycle); \
-}
-
-#define CDRDMA_INT(eCycle) { \
- psxRegs.interrupt |= (1 << PSXINT_CDRDMA); \
- psxRegs.intCycle[PSXINT_CDRDMA].cycle = eCycle; \
- psxRegs.intCycle[PSXINT_CDRDMA].sCycle = psxRegs.cycle; \
- new_dyna_set_event(PSXINT_CDRDMA, eCycle); \
-}
+#include "psxevents.h"
void psxDma2(u32 madr, u32 bcr, u32 chcr);
void psxDma3(u32 madr, u32 bcr, u32 chcr);
#include <stdio.h>
-#include "../r3000a.h"
-#include "../cdrom.h"
-#include "../psxdma.h"
-#include "../mdec.h"
-#include "events.h"
+#include "r3000a.h"
+#include "cdrom.h"
+#include "psxdma.h"
+#include "mdec.h"
+#include "psxevents.h"
extern int pending_exception;
return next_interupt;
}
+static void irqNoOp() {
+}
+
typedef void (irq_func)();
static irq_func * const irq_funcs[] = {
[PSXINT_MDECINDMA] = mdec0Interrupt,
[PSXINT_GPUOTCDMA] = gpuotcInterrupt,
[PSXINT_CDRDMA] = cdrDmaInterrupt,
+ [PSXINT_NEWDRC_CHECK] = irqNoOp,
[PSXINT_CDRLID] = cdrLidSeekInterrupt,
[PSXINT_IRQ10] = irq10Interrupt,
[PSXINT_SPU_UPDATE] = spuUpdate,
};
/* local dupe of psxBranchTest, using event_cycles */
-static void irq_test(psxCP0Regs *cp0)
+void irq_test(psxCP0Regs *cp0)
{
u32 cycle = psxRegs.cycle;
u32 irq, irq_bits;
next_interupt, next_interupt - psxRegs.cycle);
}
+void events_restore(void)
+{
+ int i;
+ for (i = 0; i < PSXINT_COUNT; i++)
+ event_cycles[i] = psxRegs.intCycle[i].sCycle + psxRegs.intCycle[i].cycle;
+ event_cycles[PSXINT_RCNT] = psxNextsCounter + psxNextCounter;
+ psxRegs.interrupt |= 1 << PSXINT_RCNT;
+ psxRegs.interrupt &= (1 << PSXINT_COUNT) - 1;
+}
--- /dev/null
+#ifndef __PSXEVENTS_H__
+#define __PSXEVENTS_H__
+
+#include "psxcommon.h"
+
+enum {
+ PSXINT_SIO = 0, // sioInterrupt
+ PSXINT_CDR, // cdrInterrupt
+ PSXINT_CDREAD, // cdrPlayReadInterrupt
+ PSXINT_GPUDMA, // gpuInterrupt
+ PSXINT_MDECOUTDMA, // mdec1Interrupt
+ PSXINT_SPUDMA, // spuInterrupt
+ PSXINT_UNUSED, //
+ PSXINT_MDECINDMA, // mdec0Interrupt
+ PSXINT_GPUOTCDMA, // gpuotcInterrupt
+ PSXINT_CDRDMA, // cdrDmaInterrupt
+ PSXINT_NEWDRC_CHECK, // (none)
+ PSXINT_RCNT, // psxRcntUpdate
+ PSXINT_CDRLID, // cdrLidSeekInterrupt
+ PSXINT_IRQ10, // irq10Interrupt
+ PSXINT_SPU_UPDATE, // spuUpdate
+ PSXINT_COUNT
+};
+
+extern u32 event_cycles[PSXINT_COUNT];
+extern u32 next_interupt;
+extern int stop;
+
+#define set_event_raw_abs(e, abs) { \
+ u32 abs_ = abs; \
+ s32 di_ = next_interupt - abs_; \
+ event_cycles[e] = abs_; \
+ if (di_ > 0) { \
+ /*printf("%u: next_interupt %u -> %u\n", psxRegs.cycle, next_interupt, abs_);*/ \
+ next_interupt = abs_; \
+ } \
+}
+
+#define set_event(e, c) do { \
+ psxRegs.interrupt |= (1 << (e)); \
+ psxRegs.intCycle[e].cycle = c; \
+ psxRegs.intCycle[e].sCycle = psxRegs.cycle; \
+ set_event_raw_abs(e, psxRegs.cycle + (c)) \
+} while (0)
+
+union psxCP0Regs_;
+u32 schedule_timeslice(void);
+void irq_test(union psxCP0Regs_ *cp0);
+void gen_interupt(union psxCP0Regs_ *cp0);
+void events_restore(void);
+
+#endif // __PSXEVENTS_H__
*/
#include "psxhw.h"
+#include "psxevents.h"
#include "mdec.h"
#include "cdrom.h"
#include "gpu.h"
if (stat & value) {
//if ((psxRegs.CP0.n.SR & 0x401) == 0x401)
// log_unhandled("irq on unmask @%08x\n", psxRegs.pc);
- new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
+ set_event(PSXINT_NEWDRC_CHECK, 1);
}
psxRegs.CP0.n.Cause &= ~0x400;
if (stat & value)
#include "gte.h"
#include "psxinterpreter.h"
#include "psxbios.h"
+#include "psxevents.h"
#include "../include/compiler_features.h"
R3000Acpu *psxCpu = NULL;
if ((psxRegs.cycle - psxNextsCounter) >= psxNextCounter)
psxRcntUpdate();
- if (psxRegs.interrupt) {
- if ((psxRegs.interrupt & (1 << PSXINT_SIO))) { // sio
- if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SIO].sCycle) >= psxRegs.intCycle[PSXINT_SIO].cycle) {
- psxRegs.interrupt &= ~(1 << PSXINT_SIO);
- sioInterrupt();
- }
- }
- if (psxRegs.interrupt & (1 << PSXINT_CDR)) { // cdr
- if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDR].sCycle) >= psxRegs.intCycle[PSXINT_CDR].cycle) {
- psxRegs.interrupt &= ~(1 << PSXINT_CDR);
- cdrInterrupt();
- }
- }
- if (psxRegs.interrupt & (1 << PSXINT_CDREAD)) { // cdr read
- if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDREAD].sCycle) >= psxRegs.intCycle[PSXINT_CDREAD].cycle) {
- psxRegs.interrupt &= ~(1 << PSXINT_CDREAD);
- cdrPlayReadInterrupt();
- }
- }
- if (psxRegs.interrupt & (1 << PSXINT_GPUDMA)) { // gpu dma
- if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUDMA].cycle) {
- psxRegs.interrupt &= ~(1 << PSXINT_GPUDMA);
- gpuInterrupt();
- }
- }
- if (psxRegs.interrupt & (1 << PSXINT_MDECOUTDMA)) { // mdec out dma
- if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECOUTDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECOUTDMA].cycle) {
- psxRegs.interrupt &= ~(1 << PSXINT_MDECOUTDMA);
- mdec1Interrupt();
- }
- }
- if (psxRegs.interrupt & (1 << PSXINT_SPUDMA)) { // spu dma
- if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_SPUDMA].cycle) {
- psxRegs.interrupt &= ~(1 << PSXINT_SPUDMA);
- spuInterrupt();
- }
- }
- if (psxRegs.interrupt & (1 << PSXINT_MDECINDMA)) { // mdec in
- if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECINDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECINDMA].cycle) {
- psxRegs.interrupt &= ~(1 << PSXINT_MDECINDMA);
- mdec0Interrupt();
- }
- }
- if (psxRegs.interrupt & (1 << PSXINT_GPUOTCDMA)) { // gpu otc
- if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUOTCDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUOTCDMA].cycle) {
- psxRegs.interrupt &= ~(1 << PSXINT_GPUOTCDMA);
- gpuotcInterrupt();
- }
- }
- if (psxRegs.interrupt & (1 << PSXINT_CDRDMA)) { // cdrom
- if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRDMA].sCycle) >= psxRegs.intCycle[PSXINT_CDRDMA].cycle) {
- psxRegs.interrupt &= ~(1 << PSXINT_CDRDMA);
- cdrDmaInterrupt();
- }
- }
- if (psxRegs.interrupt & (1 << PSXINT_CDRLID)) { // cdr lid states
- if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRLID].sCycle) >= psxRegs.intCycle[PSXINT_CDRLID].cycle) {
- psxRegs.interrupt &= ~(1 << PSXINT_CDRLID);
- cdrLidSeekInterrupt();
- }
- }
- if (psxRegs.interrupt & (1 << PSXINT_IRQ10)) { // irq10 - controller port pin8
- if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_IRQ10].sCycle) >= psxRegs.intCycle[PSXINT_IRQ10].cycle) {
- psxRegs.interrupt &= ~(1 << PSXINT_IRQ10);
- irq10Interrupt();
- }
- }
- if (psxRegs.interrupt & (1 << PSXINT_SPU_UPDATE)) { // scheduled spu update
- if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPU_UPDATE].sCycle) >= psxRegs.intCycle[PSXINT_SPU_UPDATE].cycle) {
- psxRegs.interrupt &= ~(1 << PSXINT_SPU_UPDATE);
- spuUpdate();
- }
- }
- }
+ irq_test(&psxRegs.CP0);
- psxRegs.CP0.n.Cause &= ~0x400;
- if (psxHu32(0x1070) & psxHu32(0x1074))
- psxRegs.CP0.n.Cause |= 0x400;
- if (((psxRegs.CP0.n.Cause | 1) & psxRegs.CP0.n.SR & 0x401) == 0x401)
- psxException(0, 0, &psxRegs.CP0);
- else if (unlikely(psxRegs.pc == psxRegs.biosBranchCheck))
+ if (unlikely(psxRegs.pc == psxRegs.biosBranchCheck))
psxBiosCheckBranch();
}
psxRegs.interrupt |= 1 << PSXINT_IRQ10;
psxRegs.intCycle[PSXINT_IRQ10].cycle = c;
psxRegs.intCycle[PSXINT_IRQ10].sCycle = rcnts[3].cycleStart;
- new_dyna_set_event_abs(PSXINT_IRQ10, cycles_abs);
+ set_event_raw_abs(PSXINT_IRQ10, cycles_abs);
}
void irq10Interrupt() {
PAIR p[32];
} psxCP2Ctrl;
-enum {
- PSXINT_SIO = 0,
- PSXINT_CDR,
- PSXINT_CDREAD,
- PSXINT_GPUDMA,
- PSXINT_MDECOUTDMA,
- PSXINT_SPUDMA,
- PSXINT_GPUBUSY,
- PSXINT_MDECINDMA,
- PSXINT_GPUOTCDMA,
- PSXINT_CDRDMA,
- PSXINT_NEWDRC_CHECK,
- PSXINT_RCNT,
- PSXINT_CDRLID,
- PSXINT_IRQ10,
- PSXINT_SPU_UPDATE,
- PSXINT_COUNT
-};
-
enum R3000Abdt {
// corresponds to bits 31,30 of Cause reg
R3000A_BRANCH_TAKEN = 3,
extern psxRegisters psxRegs;
/* new_dynarec stuff */
-extern u32 event_cycles[PSXINT_COUNT];
-extern u32 next_interupt;
-
void new_dyna_freeze(void *f, int mode);
-#define new_dyna_set_event_abs(e, abs) { \
- u32 abs_ = abs; \
- s32 di_ = next_interupt - abs_; \
- event_cycles[e] = abs_; \
- if (di_ > 0) { \
- /*printf("%u: next_interupt %u -> %u\n", psxRegs.cycle, next_interupt, abs_);*/ \
- next_interupt = abs_; \
- } \
-}
-
-#define new_dyna_set_event(e, c) \
- new_dyna_set_event_abs(e, psxRegs.cycle + (c))
-
int psxInit();
void psxReset();
void psxShutdown();
#include "misc.h"
#include "psxcounters.h"
+#include "psxevents.h"
#include "sio.h"
#include <sys/stat.h>
char Mcd1Data[MCD_SIZE], Mcd2Data[MCD_SIZE];
char McdDisable[2];
-#define SIO_INT(eCycle) { \
- psxRegs.interrupt |= (1 << PSXINT_SIO); \
- psxRegs.intCycle[PSXINT_SIO].cycle = eCycle; \
- psxRegs.intCycle[PSXINT_SIO].sCycle = psxRegs.cycle; \
- new_dyna_set_event(PSXINT_SIO, eCycle); \
-}
-
// clk cycle byte
// 4us * 8bits = (PSXCLK / 1000000) * 32; (linuzappz)
// TODO: add SioModePrescaler and BaudReg
if (more_data) {
bufcount = parp + 1;
- SIO_INT(SIO_CYCLES);
+ set_event(PSXINT_SIO, SIO_CYCLES);
}
}
else padst = 0;
if (more_data) {
bufcount = parp + 1;
- SIO_INT(SIO_CYCLES);
+ set_event(PSXINT_SIO, SIO_CYCLES);
}
return;
}
switch (mcdst) {
case 1:
- SIO_INT(SIO_CYCLES);
+ set_event(PSXINT_SIO, SIO_CYCLES);
if (rdwr) { parp++; return; }
parp = 1;
switch (value) {
}
return;
case 2: // address H
- SIO_INT(SIO_CYCLES);
+ set_event(PSXINT_SIO, SIO_CYCLES);
adrH = value;
*buf = 0;
parp = 0;
mcdst = 3;
return;
case 3: // address L
- SIO_INT(SIO_CYCLES);
+ set_event(PSXINT_SIO, SIO_CYCLES);
adrL = value;
*buf = adrH;
parp = 0;
mcdst = 4;
return;
case 4:
- SIO_INT(SIO_CYCLES);
+ set_event(PSXINT_SIO, SIO_CYCLES);
parp = 0;
switch (rdwr) {
case 1: // read
if (rdwr == 2) {
if (parp < 128) buf[parp + 1] = value;
}
- SIO_INT(SIO_CYCLES);
+ set_event(PSXINT_SIO, SIO_CYCLES);
return;
}
bufcount = 1;
parp = 0;
padst = 1;
- SIO_INT(SIO_CYCLES);
+ set_event(PSXINT_SIO, SIO_CYCLES);
return;
case 0x81: // start memcard
if (CtrlReg & 0x2000)
bufcount = 3;
mcdst = 1;
rdwr = 0;
- SIO_INT(SIO_CYCLES);
+ set_event(PSXINT_SIO, SIO_CYCLES);
return;
default:
no_device:
*/
#include "spu.h"
+#include "psxevents.h"
void CALLBACK SPUirq(void) {
psxHu32ref(0x1070) |= SWAPu32(0x200);
// spuUpdate
void CALLBACK SPUschedule(unsigned int cycles_after) {
- psxRegs.interrupt |= (1 << PSXINT_SPU_UPDATE);
- psxRegs.intCycle[PSXINT_SPU_UPDATE].cycle = cycles_after;
- psxRegs.intCycle[PSXINT_SPU_UPDATE].sCycle = psxRegs.cycle;
- new_dyna_set_event(PSXINT_SPU_UPDATE, cycles_after);
+ set_event(PSXINT_SPU_UPDATE, cycles_after);
}
void spuUpdate() {