git subrepo pull --force deps/lightrec

subrepo:
  subdir:   "deps/lightrec"
  merged:   "9d392272b2"
upstream:
  origin:   "https://github.com/pcercuei/lightrec.git"
  branch:   "master"
  commit:   "9d392272b2"
git-subrepo:
  version:  "0.4.6"
  origin:   "https://github.com/ingydotnet/git-subrepo.git"
  commit:   "110b9eb"

diff --git a/deps/lightrec/.gitrepo b/deps/lightrec/.gitrepo
index 94e769a..8552a07 100644 (file)
--- a/deps/lightrec/.gitrepo
+++ b/deps/lightrec/.gitrepo
@@ -6,7 +6,7 @@
 [subrepo]
        remote = https://github.com/pcercuei/lightrec.git
        branch = master
-       commit = 83b50408ae3eeeca408d3cc7ce05393e27dbe83b
-       parent = 537a9a8cd4c69a081dc1790099153a9a17da6e31
+       commit = 9d392272b26a4c9de71b0ccf8806c29fe4ced9ca
+       parent = 88e086706bbe2b1723072ad524bcf154c07eb9cb
        method = merge
        cmdver = 0.4.6

diff --git a/deps/lightrec/emitter.c b/deps/lightrec/emitter.c
index 2bd4dca..b8025aa 100644 (file)
--- a/deps/lightrec/emitter.c
+++ b/deps/lightrec/emitter.c
@@ -71,6 +71,7 @@ static void lightrec_emit_end_of_block(struct lightrec_cstate *state,
        const struct opcode *op = &block->opcode_list[offset],
                            *ds = get_delay_slot(block->opcode_list, offset);
        u32 cycles = state->cycles + lightrec_cycles_of_opcode(state->state, op->c);
+       bool has_ds = has_delay_slot(op->c);
 
        jit_note(__FILE__, __LINE__);
 
@@ -89,8 +90,7 @@ static void lightrec_emit_end_of_block(struct lightrec_cstate *state,
                update_ra_register(reg_cache, _jit, ra_reg, block->pc, link);
        }
 
-       if (has_delay_slot(op->c) &&
-           !op_flag_no_ds(op->flags) && !op_flag_local_branch(op->flags)) {
+       if (has_ds && !op_flag_no_ds(op->flags) && !op_flag_local_branch(op->flags)) {
                cycles += lightrec_cycles_of_opcode(state->state, ds->c);
 
                /* Recompile the delay slot */
@@ -106,7 +106,7 @@ static void lightrec_emit_end_of_block(struct lightrec_cstate *state,
                pr_debug("EOB: %u cycles\n", cycles);
        }
 
-       if (op_flag_load_delay(ds->flags)
+       if (has_ds && op_flag_load_delay(ds->flags)
            && opcode_is_load(ds->c) && !state->no_load_delay) {
                /* If the delay slot is a load opcode, its target register
                 * will be written after the first opcode of the target is