#define stop dynarec_local_var4(LO_stop)
#define psxRegs (*(psxRegisters *)((char *)dynarec_local + LO_psxRegs))
#define next_interupt dynarec_local_var4(LO_next_interupt)
-#define pending_exception dynarec_local_var4(LO_pending_exception)
#endif
static void ari64_thread_sync(void);
evprintf("MTC0 %d #%x @%08x %u\n", reg, val, psxRegs.pc, psxRegs.cycle);
MTC0(&psxRegs, reg, val);
gen_interupt(&psxRegs.CP0);
-
- //if (psxRegs.CP0.n.Cause & psxRegs.CP0.n.SR & 0x0300) // possible sw irq
- if ((psxRegs.pc & 0x803ffeff) == 0x80000080)
- pending_exception = 1;
}
void pcsx_mtc0_ds(u32 reg, u32 val)
new_dyna_pcsx_mem_reset();
new_dynarec_invalidate_all_pages();
new_dyna_pcsx_mem_load_state();
- pending_exception = 1;
}
// execute until predefined leave points
struct ndrc_globals ndrc_g; // dummy
unsigned int address;
-int pending_exception, stop;
+int stop;
u32 next_interupt;
void *psxH_ptr;
void *zeromem_ptr;
/* cycles/irqs */
extern u32 next_interupt;
-extern int pending_exception;
/* called by drc */
void pcsx_mtc0(u32 reg, u32 val);
DRC_VAR(next_interupt, 4)
DRC_VAR(cycle_count, 4)
DRC_VAR(last_count, 4)
-DRC_VAR(pending_exception, 4)
+@DRC_VAR(unused1, 4)
DRC_VAR(stop, 4)
DRC_VAR(branch_target, 4)
DRC_VAR(address, 4)
.align 2
FUNCTION(cc_interrupt):
ldr r0, [fp, #LO_last_count]
- mov r1, #0
- add r10, r0, r10
- str r1, [fp, #LO_pending_exception]
- str r10, [fp, #LO_cycle] /* PCSX cycles */
+ ldr r9, [fp, #LO_pcaddr]
+ add r1, r0, r10
+ str r1, [fp, #LO_cycle] /* PCSX cycles */
mov r10, lr
add r0, fp, #LO_reg_cop0 /* CP0 */
bl gen_interupt
mov lr, r10
ldr r10, [fp, #LO_cycle]
- ldr r0, [fp, #LO_next_interupt]
- ldr r1, [fp, #LO_pending_exception]
+ ldr r0, [fp, #LO_pcaddr]
+ ldr r1, [fp, #LO_next_interupt]
ldr r2, [fp, #LO_stop]
- str r0, [fp, #LO_last_count]
- sub r10, r10, r0
+ str r1, [fp, #LO_last_count]
+ sub r10, r10, r1
tst r2, r2
ldmfdne sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
- tst r1, r1
+ cmp r0, r9
moveq pc, lr
- ldr r0, [fp, #LO_pcaddr]
bl ndrc_get_addr_ht
mov pc, r0
.size cc_interrupt, .-cc_interrupt
DRC_VAR(next_interupt, 4)
DRC_VAR(cycle_count, 4)
DRC_VAR(last_count, 4)
-DRC_VAR(pending_exception, 4)
+@DRC_VAR(unused1, 4)
DRC_VAR(stop, 4)
DRC_VAR(branch_target, 4)
DRC_VAR(address, 4)
.align 2
FUNCTION(cc_interrupt):
ldr w0, [rFP, #LO_last_count]
+ ldr w22, [rFP, #LO_pcaddr]
add rCC, w0, rCC
- str wzr, [rFP, #LO_pending_exception]
str rCC, [rFP, #LO_cycle] /* PCSX cycles */
mov x21, lr
1:
bl gen_interupt
mov lr, x21
ldr rCC, [rFP, #LO_cycle]
- ldr w0, [rFP, #LO_next_interupt]
- ldr w1, [rFP, #LO_pending_exception]
+ ldr w0, [rFP, #LO_pcaddr]
+ ldr w1, [rFP, #LO_next_interupt]
ldr w2, [rFP, #LO_stop]
- str w0, [rFP, #LO_last_count]
- sub rCC, rCC, w0
+ str w1, [rFP, #LO_last_count]
+ sub rCC, rCC, w1
cbnz w2, new_dyna_leave
- cbnz w1, 2f
+ cmp w0, w22
+ bne 2f
ret
2:
- ldr w0, [rFP, #LO_pcaddr]
bl ndrc_get_addr_ht
br x0
ESIZE(cc_interrupt, .-cc_interrupt)
#define LO_next_interupt 64
#define LO_cycle_count (LO_next_interupt + 4)
#define LO_last_count (LO_cycle_count + 4)
-#define LO_pending_exception (LO_last_count + 4)
-#define LO_stop (LO_pending_exception + 4)
+#define LO_unused1 (LO_last_count + 4)
+#define LO_stop (LO_unused1 + 4)
#define LO_branch_target (LO_stop + 4)
#define LO_address (LO_branch_target + 4)
#define LO_hack_addr (LO_address + 4)
extern int cycle_count; // ... until end of the timeslice, counts -N -> 0 (CCREG)
extern int last_count; // last absolute target, often = next_interupt
extern int pcaddr;
-extern int pending_exception;
extern int branch_target;
/* same as psxRegs.CP0.n.* */
ofscase(next_interupt);
ofscase(cycle_count);
ofscase(last_count);
- ofscase(pending_exception);
ofscase(stop);
ofscase(address);
ofscase(lo);
}
emit_movimm(start+i*4+4,HOST_TEMPREG);
emit_writeword(HOST_TEMPREG,&pcaddr);
- emit_movimm(0,HOST_TEMPREG);
- emit_writeword(HOST_TEMPREG,&pending_exception);
}
if( s != 1)
emit_mov(s, 1);
emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
//emit_writeword(HOST_TEMPREG,&last_count);
assert(!is_delayslot);
- emit_readword(&pending_exception,HOST_TEMPREG);
- emit_test(HOST_TEMPREG,HOST_TEMPREG);
+ emit_readword(&pcaddr, 0);
+ emit_movimm(start+i*4+4, HOST_TEMPREG);
+ emit_cmp(HOST_TEMPREG, 0);
void *jaddr = out;
emit_jeq(0);
- emit_readword(&pcaddr, 0);
emit_far_call(ndrc_get_addr_ht);
emit_jmpreg(0);
set_jump_target(jaddr, out);
literal_pool(256);
assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4);
set_jump_target(stubs[n].addr, out);
- int i=stubs[n].b;
+ int i = stubs[n].b;
+ int r_pc = -1;
if (stubs[n].d != TAKEN) {
wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty);
}
if(stubs[n].c!=-1)
{
// Save PC as return address
- emit_movimm(stubs[n].c,0);
- emit_writeword(0,&pcaddr);
+ emit_movimm(stubs[n].c, (r_pc = 0));
}
else
{
else
emit_movimm((dops[i].opcode2 & 1) ? cinfo[i].ba : start + i*4 + 8, addr);
}
- emit_writeword(addr, &pcaddr);
+ r_pc = addr;
}
else
if(dops[i].itype==RJUMP)
{
- int r=get_reg(branch_regs[i].regmap,dops[i].rs1);
+ r_pc = get_reg(branch_regs[i].regmap, dops[i].rs1);
if (ds_writes_rjump_rs(i)) {
- r=get_reg(branch_regs[i].regmap,RTEMP);
+ r_pc = get_reg(branch_regs[i].regmap, RTEMP);
}
- emit_writeword(r,&pcaddr);
}
else {SysPrintf("Unknown branch type in do_ccstub\n");abort();}
}
+ emit_writeword(r_pc, &pcaddr);
// Update cycle count
assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
if(stubs[n].a) emit_addimm(HOST_CCREG,(int)stubs[n].a,HOST_CCREG);
mini_ht_clear();
copy=shadow;
expirep = EXPIRITY_OFFSET;
- pending_exception=0;
literalcount=0;
stop_after_jal=0;
inv_code_start=inv_code_end=~0;
#define MAXBLOCK 2048 // in mips instructions
-extern int pending_exception;
extern int stop;
#define NDHACK_NO_SMC_CHECK (1<<0)
#include "mdec.h"
#include "psxevents.h"
-extern int pending_exception;
-
//#define evprintf printf
#define evprintf(...)
cp0->n.Cause &= ~0x400;
if (psxHu32(0x1070) & psxHu32(0x1074))
cp0->n.Cause |= 0x400;
- if (((cp0->n.Cause | 1) & cp0->n.SR & 0x401) == 0x401) {
+ if (((cp0->n.Cause | 1) & cp0->n.SR & 0x401) == 0x401)
psxException(0, 0, cp0);
- pending_exception = 1;
- }
}
void gen_interupt(psxCP0Regs *cp0)
next_interupt, next_interupt - psxRegs.cycle);
irq_test(cp0);
- //pending_exception = 1;
schedule_timeslice();