#define rdprintf(...)\r
//#define wrdprintf dprintf\r
#define wrdprintf(...)\r
+//#define r3printf elprintf\r
#define r3printf(...)\r
#endif\r
\r
goto end;\r
case 2:\r
d = (Pico_mcd->s68k_regs[a]<<8) | (Pico_mcd->s68k_regs[a+1]&0xc7);\r
- // the DMNA delay must only be visible on s68k side (Lunar2, Silpheed)\r
- if (Pico_mcd->m.state_flags&2) { d &= ~1; d |= 2; }\r
r3printf(EL_STATUS, "m68k_regs r3: %02x @%06x", (u8)d, SekPc);\r
goto end;\r
case 4:\r
case 1:\r
d &= 3;\r
if (!(d&1)) Pico_mcd->m.state_flags |= 1; // reset pending, needed to be sure we fetch the right vectors on reset\r
- if ( (Pico_mcd->m.busreq&1) != (d&1)) dprintf("m68k: s68k reset %i", !(d&1));\r
- if ( (Pico_mcd->m.busreq&2) != (d&2)) dprintf("m68k: s68k brq %i", (d&2)>>1);\r
+ if ( (Pico_mcd->m.busreq&1) != (d&1)) elprintf(EL_INTSW, "m68k: s68k reset %i", !(d&1));\r
+ if ( (Pico_mcd->m.busreq&2) != (d&2)) elprintf(EL_INTSW, "m68k: s68k brq %i", (d&2)>>1);\r
if ((Pico_mcd->m.state_flags&1) && (d&3)==1) {\r
SekResetS68k(); // S68k comes out of RESET or BRQ state\r
Pico_mcd->m.state_flags&=~1;\r
//if ((Pico_mcd->s68k_regs[3]&4) != (d&4)) dprintf("m68k: ram mode %i mbit", (d&4) ? 1 : 2);\r
//if ((Pico_mcd->s68k_regs[3]&2) != (d&2)) dprintf("m68k: %s", (d&4) ? ((d&2) ? "word swap req" : "noop?") :\r
// ((d&2) ? "word ram to s68k" : "word ram to m68k"));\r
- if (dold & 4) {\r
- d ^= 2; // writing 0 to DMNA actually sets it, 1 does nothing\r
+ if (dold & 4) { // 1M mode\r
+ d ^= 2; // writing 0 to DMNA actually sets it, 1 does nothing\r
} else {\r
- //dold &= ~2; // ??\r
-#if 1\r
- if (d & (d ^ dold) & 2) { // DMNA is being set\r
- Pico_mcd->m.state_flags |= 2; // we must delay setting DMNA bit (needed for Silpheed)\r
- d &= ~2;\r
- }\r
- else\r
- Pico_mcd->m.state_flags &= ~2;\r
-#else\r
- if (d & 2) dold &= ~1; // return word RAM to s68k in 2M mode\r
-#endif\r
+ if ((d ^ dold) & d & 2) { // DMNA is being set\r
+ dold &= ~1; // return word RAM to s68k\r
+ /* Silpheed hack: bset(w3), r3, btst, bne, r3 */\r
+ SekEndRun(20+16+10+12+16);\r
+ }\r
}\r
Pico_mcd->s68k_regs[3] = d | dold; // really use s68k side register\r
#ifdef USE_POLL_DETECT\r
}\r
else\r
d |= dold&1;\r
+ // s68k can only set RET, writing 0 has no effect\r
if (d&1) d &= ~2; // return word RAM to m68k in 2M mode\r
}\r
- Pico_mcd->m.state_flags &= ~2;\r
break;\r
}\r
case 4:\r
// update gfx chip
if (Pico_mcd->rot_comp.Reg_58 & 0x8000)
gfx_cd_update();
-
- // delayed setting of DMNA bit (needed for Silpheed)
- if (Pico_mcd->m.state_flags & 2) {
- Pico_mcd->m.state_flags &= ~2;
- if (!(Pico_mcd->s68k_regs[3] & 4)) {
- Pico_mcd->s68k_regs[3] |= 2;
- Pico_mcd->s68k_regs[3] &= ~1;
-#ifdef USE_POLL_DETECT
- if ((s68k_poll_adclk&0xfe) == 2) {
- SekSetStopS68k(0); s68k_poll_adclk = 0;
- }
-#endif
- }
- }
}
(((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
#define SekCyclesLeftS68k \\r
((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)\r
-#define SekSetCyclesLeftNoMCD(c) PicoCpuCM68k.cycles=c\r
-#define SekSetCyclesLeft(c) { \\r
- if ((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) SekCycleCnt=SekCycleAim-(c); else SekSetCyclesLeftNoMCD(c); \\r
-}\r
+#define SekEndTimeslice(after) PicoCpuCM68k.cycles=after\r
#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
(((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
#define SekCyclesLeftS68k \\r
((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)\r
-#define SekSetCyclesLeftNoMCD(c) PicoCpuFM68k.io_cycle_counter=c\r
-#define SekSetCyclesLeft(c) { \\r
- if ((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) SekCycleCnt=SekCycleAim-(c); else SekSetCyclesLeftNoMCD(c); \\r
-}\r
+#define SekEndTimeslice(after) PicoCpuFM68k.io_cycle_counter=after\r
#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
#define SekSetStop(x) { \\r
(((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
#define SekCyclesLeftS68k \\r
((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)\r
-#define SekSetCyclesLeftNoMCD(c) SET_CYCLES(c)\r
-#define SekSetCyclesLeft(c) { \\r
- if ((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) SekCycleCnt=SekCycleAim-(c); else SET_CYCLES(c); \\r
-}\r
+#define SekEndTimeslice(after) SET_CYCLES(after)\r
#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
#define SekSetStop(x) { \\r
}\r
\r
#endif\r
-#endif\r
+#endif // EMU_M68K\r
\r
extern int SekCycleCnt; // cycles done in this frame\r
extern int SekCycleAim; // cycle aim\r
#define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r
\r
#define SekEndRun(after) { \\r
- SekCycleCnt -= SekCyclesLeft - after; \\r
- if(SekCycleCnt < 0) SekCycleCnt = 0; \\r
- SekSetCyclesLeft(after); \\r
+ SekCycleCnt -= SekCyclesLeft - (after); \\r
+ if (SekCycleCnt < 0) SekCycleCnt = 0; \\r
+ SekEndTimeslice(after); \\r
}\r
\r
extern int SekCycleCntS68k;\r
\r
#ifdef EMU_CORE_DEBUG\r
extern int dbg_irq_level;\r
-#undef SekSetCyclesLeftNoMCD\r
-#undef SekSetCyclesLeft\r
+#undef SekEndTimeslice\r
#undef SekCyclesBurn\r
#undef SekEndRun\r
#undef SekInterrupt\r
-#define SekSetCyclesLeftNoMCD(c)\r
-#define SekSetCyclesLeft(c)\r
+#define SekEndTimeslice(c)\r
#define SekCyclesBurn(c) c\r
#define SekEndRun(c)\r
#define SekInterrupt(irq) dbg_irq_level=irq\r
unsigned short hint_vector;\r
unsigned char busreq;\r
unsigned char s68k_pend_ints;\r
- unsigned int state_flags; // 04: emu state: reset_pending, dmna_pending\r
+ unsigned int state_flags; // 04: emu state: reset_pending\r
unsigned int counter75hz;\r
unsigned int pad0;\r
int timer_int3; // 10\r
\r
Pico.m.dma_xfers += len;\r
if ((PicoAHW & PAHW_MCD) && (PicoOpt & POPT_EN_MCD_PSYNC)) SekCyclesBurn(CheckDMA());\r
- else SekSetCyclesLeftNoMCD(SekCyclesLeftNoMCD - CheckDMA());\r
+ else SekEndTimeslice(SekCyclesLeftNoMCD - CheckDMA());\r
\r
if ((source&0xe00000)==0xe00000) { // Ram\r
pd=(u16 *)(Pico.ram+(source&0xfffe));\r
ifeq "$(use_musashi)" "1"
DEFINES += EMU_M68K
OBJS += cpu/musashi/m68kops.o cpu/musashi/m68kcpu.o
+OBJS += cpu/musashi/m68kdasm.o
endif
ifeq "$(use_fame)" "1"
DEFINES += EMU_F68K
ifeq "$(use_fame)" "1"
ifeq "$(use_musashi)" "1"
OBJS += pico/debugCPU.o
-OBJS += cpu/musashi/m68kdasm.o
endif
endif
-OBJS += cpu/musashi/m68kdasm.o
CFLAGS += $(addprefix -D,$(DEFINES))