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switch DMNA Silpheed hack to timeslice hack
[picodrive.git] / pico / pico_int.h
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eff55556 1// Pico Library - Internal Header File\r
cc68a136 2\r
3// (c) Copyright 2004 Dave, All rights reserved.\r
4936aac1 4// (c) Copyright 2006-2008 Grazvydas "notaz" Ignotas, all rights reserved.\r
cc68a136 5// Free for non-commercial use.\r
6\r
7// For commercial use, separate licencing terms must be obtained.\r
8\r
eff55556 9#ifndef PICO_INTERNAL_INCLUDED\r
10#define PICO_INTERNAL_INCLUDED\r
cc68a136 11\r
12#include <stdio.h>\r
13#include <stdlib.h>\r
14#include <string.h>\r
efcba75f 15#include "pico.h"\r
f53f286a 16#include "carthw/carthw.h"\r
cc68a136 17\r
89fa852d 18//\r
19#define USE_POLL_DETECT\r
20\r
eff55556 21#ifndef PICO_INTERNAL\r
22#define PICO_INTERNAL\r
23#endif\r
24#ifndef PICO_INTERNAL_ASM\r
25#define PICO_INTERNAL_ASM\r
26#endif\r
cc68a136 27\r
70357ce5 28// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
cc68a136 29\r
30#ifdef __cplusplus\r
31extern "C" {\r
32#endif\r
33\r
34\r
35// ----------------------- 68000 CPU -----------------------\r
36#ifdef EMU_C68K\r
37#include "../cpu/Cyclone/Cyclone.h"\r
3aa1e148 38extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
39#define SekCyclesLeftNoMCD PicoCpuCM68k.cycles // cycles left for this run\r
7336a99a 40#define SekCyclesLeft \\r
602133e1 41 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
7a1f6e45 42#define SekCyclesLeftS68k \\r
602133e1 43 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)\r
ef090115 44#define SekEndTimeslice(after) PicoCpuCM68k.cycles=after\r
3aa1e148 45#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
46#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
47#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
48#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
ca61ee42 49#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
03e4f2a3 50#define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
b542be46 51\r
52#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
53\r
03e4f2a3 54#ifdef EMU_M68K\r
55#define EMU_CORE_DEBUG\r
56#endif\r
cc68a136 57#endif\r
58\r
70357ce5 59#ifdef EMU_F68K\r
60#include "../cpu/fame/fame.h"\r
b542be46 61extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
3aa1e148 62#define SekCyclesLeftNoMCD PicoCpuFM68k.io_cycle_counter\r
70357ce5 63#define SekCyclesLeft \\r
602133e1 64 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
70357ce5 65#define SekCyclesLeftS68k \\r
602133e1 66 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)\r
ef090115 67#define SekEndTimeslice(after) PicoCpuFM68k.io_cycle_counter=after\r
03e4f2a3 68#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
69#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
70357ce5 70#define SekSetStop(x) { \\r
03e4f2a3 71 PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
72 if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
70357ce5 73}\r
74#define SekSetStopS68k(x) { \\r
03e4f2a3 75 PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r
76 if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
70357ce5 77}\r
ca61ee42 78#define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r
03e4f2a3 79#define SekShouldInterrupt fm68k_would_interrupt()\r
b542be46 80\r
81#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
82\r
03e4f2a3 83#ifdef EMU_M68K\r
84#define EMU_CORE_DEBUG\r
85#endif\r
cc68a136 86#endif\r
87\r
88#ifdef EMU_M68K\r
89#include "../cpu/musashi/m68kcpu.h"\r
3aa1e148 90extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
cc68a136 91#ifndef SekCyclesLeft\r
3aa1e148 92#define SekCyclesLeftNoMCD PicoCpuMM68k.cyc_remaining_cycles\r
7336a99a 93#define SekCyclesLeft \\r
602133e1 94 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
7a1f6e45 95#define SekCyclesLeftS68k \\r
602133e1 96 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)\r
ef090115 97#define SekEndTimeslice(after) SET_CYCLES(after)\r
3aa1e148 98#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
99#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
7a1f6e45 100#define SekSetStop(x) { \\r
3aa1e148 101 if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
102 else PicoCpuMM68k.stopped=0; \\r
7a1f6e45 103}\r
104#define SekSetStopS68k(x) { \\r
3aa1e148 105 if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
106 else PicoCpuMS68k.stopped=0; \\r
7a1f6e45 107}\r
ca61ee42 108#define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r
03e4f2a3 109#define SekShouldInterrupt (CPU_INT_LEVEL > FLAG_INT_MASK)\r
b542be46 110\r
71de3cd9 111#define SekInterrupt(irq) { \\r
b542be46 112 void *oldcontext = m68ki_cpu_p; \\r
113 m68k_set_context(&PicoCpuMM68k); \\r
114 m68k_set_irq(irq); \\r
115 m68k_set_context(oldcontext); \\r
116}\r
117\r
cc68a136 118#endif\r
ef090115 119#endif // EMU_M68K\r
cc68a136 120\r
121extern int SekCycleCnt; // cycles done in this frame\r
122extern int SekCycleAim; // cycle aim\r
123extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r
124\r
b8cbd802 125#define SekCyclesReset() { \\r
126 SekCycleCntT+=SekCycleAim; \\r
127 SekCycleCnt-=SekCycleAim; \\r
128 SekCycleAim=0; \\r
129}\r
cc68a136 130#define SekCyclesBurn(c) SekCycleCnt+=c\r
4b9c5888 131#define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // number of cycles done in this frame (can be checked anywhere)\r
cc68a136 132#define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r
133\r
134#define SekEndRun(after) { \\r
ef090115 135 SekCycleCnt -= SekCyclesLeft - (after); \\r
136 if (SekCycleCnt < 0) SekCycleCnt = 0; \\r
137 SekEndTimeslice(after); \\r
cc68a136 138}\r
139\r
140extern int SekCycleCntS68k;\r
141extern int SekCycleAimS68k;\r
142\r
bf5fbbb4 143#define SekCyclesResetS68k() { \\r
144 SekCycleCntS68k-=SekCycleAimS68k; \\r
145 SekCycleAimS68k=0; \\r
146}\r
7a1f6e45 147#define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)\r
cc68a136 148\r
03e4f2a3 149#ifdef EMU_CORE_DEBUG\r
99464b62 150extern int dbg_irq_level;\r
ef090115 151#undef SekEndTimeslice\r
2d0b15bb 152#undef SekCyclesBurn\r
153#undef SekEndRun\r
99464b62 154#undef SekInterrupt\r
ef090115 155#define SekEndTimeslice(c)\r
2270612a 156#define SekCyclesBurn(c) c\r
2d0b15bb 157#define SekEndRun(c)\r
99464b62 158#define SekInterrupt(irq) dbg_irq_level=irq\r
2d0b15bb 159#endif\r
cc68a136 160\r
b542be46 161// ----------------------- Z80 CPU -----------------------\r
162\r
163#if defined(_USE_MZ80)\r
dca310c4 164#include "../cpu/mz80/mz80.h"\r
b542be46 165\r
4b9c5888 166#define z80_run(cycles) { mz80GetElapsedTicks(1); mz80_run(cycles) }\r
b542be46 167#define z80_run_nr(cycles) mz80_run(cycles)\r
168#define z80_int() mz80int(0)\r
b542be46 169\r
170#elif defined(_USE_DRZ80)\r
dca310c4 171#include "../cpu/DrZ80/drz80.h"\r
b542be46 172\r
173extern struct DrZ80 drZ80;\r
174\r
175#define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r
176#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
4936aac1 177#define z80_int() drZ80.Z80_IRQ = 1\r
4b9c5888 178\r
179#define z80_cyclesLeft drZ80.cycles\r
b542be46 180\r
181#elif defined(_USE_CZ80)\r
dca310c4 182#include "../cpu/cz80/cz80.h"\r
b542be46 183\r
184#define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r
185#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r
186#define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r
4b9c5888 187\r
188#define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)\r
b542be46 189\r
190#else\r
191\r
192#define z80_run(cycles) (cycles)\r
193#define z80_run_nr(cycles)\r
194#define z80_int()\r
b542be46 195\r
196#endif\r
197\r
4b9c5888 198extern int z80stopCycle; /* in 68k cycles */\r
199extern int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */\r
200extern int z80_cycle_aim;\r
201extern int z80_scanline;\r
202extern int z80_scanline_cycles; /* cycles done until z80_scanline */\r
203\r
204#define z80_resetCycles() \\r
205 z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;\r
206\r
207#define z80_cyclesDone() \\r
208 (z80_cycle_aim - z80_cyclesLeft)\r
209\r
210#define cycles_68k_to_z80(x) ((x)*957 >> 11)\r
211\r
cc68a136 212// ---------------------------------------------------------\r
213\r
214// main oscillator clock which controls timing\r
215#define OSC_NTSC 53693100\r
b8cbd802 216// seems to be accurate, see scans from http://www.hot.ee/tmeeco/\r
217#define OSC_PAL 53203424\r
cc68a136 218\r
219struct PicoVideo\r
220{\r
221 unsigned char reg[0x20];\r
b8cbd802 222 unsigned int command; // 32-bit Command\r
223 unsigned char pending; // 1 if waiting for second half of 32-bit command\r
224 unsigned char type; // Command type (v/c/vsram read/write)\r
225 unsigned short addr; // Read/Write address\r
226 int status; // Status bits\r
cc68a136 227 unsigned char pending_ints; // pending interrupts: ??VH????\r
b8cbd802 228 signed char lwrite_cnt; // VDP write count during active display line\r
9761a7d0 229 unsigned short v_counter; // V-counter\r
230 unsigned char pad[0x10];\r
cc68a136 231};\r
232\r
233struct PicoMisc\r
234{\r
235 unsigned char rotate;\r
236 unsigned char z80Run;\r
e5503e2f 237 unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
2aa27095 238 unsigned short scanline; // 04 0 to 261||311\r
e5503e2f 239 char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
240 unsigned char hardware; // 07 Hardware value for country\r
241 unsigned char pal; // 08 1=PAL 0=NTSC\r
242 unsigned char sram_reg; // SRAM mode register. bit0: allow read? bit1: deny write? bit2: EEPROM? bit4: detected? (header or by access)\r
243 unsigned short z80_bank68k; // 0a\r
cc68a136 244 unsigned short z80_lastaddr; // this is for Z80 faking\r
245 unsigned char z80_fakeval;\r
bd613473 246 unsigned char z80_reset; // z80 reset held\r
e5503e2f 247 unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
1dceadae 248 unsigned short eeprom_addr; // EEPROM address register\r
249 unsigned char eeprom_cycle; // EEPROM SRAM cycle number\r
250 unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
721cd396 251 unsigned char prot_bytes[2]; // simple protection faking\r
053fd9b4 252 unsigned short dma_xfers; // 18\r
312e9ce1 253 unsigned char pad[2];\r
053fd9b4 254 unsigned int frame_count; // 1c for movies and idle det\r
cc68a136 255};\r
256\r
257// some assembly stuff depend on these, do not touch!\r
258struct Pico\r
259{\r
260 unsigned char ram[0x10000]; // 0x00000 scratch ram\r
261 unsigned short vram[0x8000]; // 0x10000\r
262 unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
263 unsigned char ioports[0x10];\r
264 unsigned int pad[0x3c]; // unused\r
265 unsigned short cram[0x40]; // 0x22100\r
266 unsigned short vsram[0x40]; // 0x22180\r
267\r
268 unsigned char *rom; // 0x22200\r
269 unsigned int romsize; // 0x22204\r
270\r
271 struct PicoMisc m;\r
272 struct PicoVideo video;\r
273};\r
274\r
275// sram\r
276struct PicoSRAM\r
277{\r
4ff2d527 278 unsigned char *data; // actual data\r
279 unsigned int start; // start address in 68k address space\r
cc68a136 280 unsigned int end;\r
1dceadae 281 unsigned char unused1; // 0c: unused\r
282 unsigned char unused2;\r
cc68a136 283 unsigned char changed;\r
1dceadae 284 unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: device with 2 addr words (X24C02+), 3: dev with 3 addr words\r
285 unsigned char eeprom_abits; // eeprom access must be odd addr for: bit0 ~ cl, bit1 ~ out\r
286 unsigned char eeprom_bit_cl; // bit number for cl\r
287 unsigned char eeprom_bit_in; // bit number for in\r
288 unsigned char eeprom_bit_out; // bit number for out\r
cc68a136 289};\r
290\r
291// MCD\r
292#include "cd/cd_sys.h"\r
293#include "cd/LC89510.h"\r
d1df8786 294#include "cd/gfx_cd.h"\r
cc68a136 295\r
4f265db7 296struct mcd_pcm\r
297{\r
298 unsigned char control; // reg7\r
299 unsigned char enabled; // reg8\r
300 unsigned char cur_ch;\r
301 unsigned char bank;\r
302 int pad1;\r
303\r
4ff2d527 304 struct pcm_chan // 08, size 0x10\r
4f265db7 305 {\r
306 unsigned char regs[8];\r
4ff2d527 307 unsigned int addr; // .08: played sample address\r
4f265db7 308 int pad;\r
309 } ch[8];\r
310};\r
311\r
c459aefd 312struct mcd_misc\r
313{\r
314 unsigned short hint_vector;\r
315 unsigned char busreq;\r
51a902ae 316 unsigned char s68k_pend_ints;\r
ef090115 317 unsigned int state_flags; // 04: emu state: reset_pending\r
51a902ae 318 unsigned int counter75hz;\r
c9e1affc 319 unsigned int pad0;\r
4ff2d527 320 int timer_int3; // 10\r
4f265db7 321 unsigned int timer_stopwatch;\r
6cadc2da 322 unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
323 unsigned char pad2;\r
324 unsigned short pad3;\r
325 int pad[9];\r
c459aefd 326};\r
327\r
cc68a136 328typedef struct\r
329{\r
4ff2d527 330 unsigned char bios[0x20000]; // 000000: 128K\r
331 union { // 020000: 512K\r
fa1e5e29 332 unsigned char prg_ram[0x80000];\r
cc68a136 333 unsigned char prg_ram_b[4][0x20000];\r
334 };\r
4ff2d527 335 union { // 0a0000: 256K\r
fa1e5e29 336 struct {\r
337 unsigned char word_ram2M[0x40000];\r
dca310c4 338 unsigned char unused0[0x20000];\r
fa1e5e29 339 };\r
340 struct {\r
dca310c4 341 unsigned char unused1[0x20000];\r
fa1e5e29 342 unsigned char word_ram1M[2][0x20000];\r
343 };\r
344 };\r
4ff2d527 345 union { // 100000: 64K\r
fa1e5e29 346 unsigned char pcm_ram[0x10000];\r
4f265db7 347 unsigned char pcm_ram_b[0x10][0x1000];\r
348 };\r
4ff2d527 349 unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
350 unsigned char bram[0x2000]; // 110200: 8K\r
351 struct mcd_misc m; // 112200: misc\r
352 struct mcd_pcm pcm; // 112240:\r
75736070 353 _scd_toc TOC; // not to be saved\r
cc68a136 354 CDD cdd;\r
355 CDC cdc;\r
356 _scd scd;\r
d1df8786 357 Rot_Comp rot_comp;\r
cc68a136 358} mcd_state;\r
359\r
360#define Pico_mcd ((mcd_state *)Pico.rom)\r
361\r
d49b10c2 362\r
51a902ae 363// Area.c\r
2aa27095 364PICO_INTERNAL void PicoAreaPackCpu(unsigned char *cpu, int is_sub);\r
365PICO_INTERNAL void PicoAreaUnpackCpu(unsigned char *cpu, int is_sub);\r
fad24893 366extern void (*PicoLoadStateHook)(void);\r
51a902ae 367\r
368// cd/Area.c\r
eff55556 369PICO_INTERNAL int PicoCdSaveState(void *file);\r
370PICO_INTERNAL int PicoCdLoadState(void *file);\r
cc68a136 371\r
945c2fdc 372typedef struct {\r
373 int chunk;\r
374 int size;\r
375 void *ptr;\r
376} carthw_state_chunk;\r
377extern carthw_state_chunk *carthw_chunks;\r
378#define CHUNK_CARTHW 64\r
379\r
bcc9eda0 380// area.c\r
381typedef size_t (arearw)(void *p, size_t _size, size_t _n, void *file);\r
382typedef size_t (areaeof)(void *file);\r
383typedef int (areaseek)(void *file, long offset, int whence);\r
384typedef int (areaclose)(void *file);\r
385extern arearw *areaRead; // external read and write function pointers for\r
386extern arearw *areaWrite; // gzip save state ability\r
387extern areaeof *areaEof;\r
388extern areaseek *areaSeek;\r
389extern areaclose *areaClose;\r
390\r
1dceadae 391// Cart.c\r
e807ac75 392extern void (*PicoCartUnloadHook)(void);\r
1dceadae 393\r
03e4f2a3 394// Debug.c\r
b5e5172d 395int CM_compareRun(int cyc, int is_sub);\r
03e4f2a3 396\r
cc68a136 397// Draw.c\r
eff55556 398PICO_INTERNAL void PicoFrameStart(void);\r
b6d7ac70 399void PicoDrawSync(int to, int blank_last_line);\r
400extern int DrawScanline;\r
f579f7b8 401#define MAX_LINE_SPRITES 29\r
402extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];\r
cc68a136 403\r
404// Draw2.c\r
eff55556 405PICO_INTERNAL void PicoFrameFull();\r
cc68a136 406\r
407// Memory.c\r
2aa27095 408PICO_INTERNAL void PicoInitPc(unsigned int pc);\r
406c96c5 409PICO_INTERNAL unsigned int PicoCheckPc(unsigned int pc);\r
8ab3e3c1 410PICO_INTERNAL_ASM unsigned int PicoRead32(unsigned int a);\r
eff55556 411PICO_INTERNAL void PicoMemSetup(void);\r
412PICO_INTERNAL_ASM void PicoMemReset(void);\r
f8ef8ff7 413PICO_INTERNAL void PicoMemResetHooks(void);\r
e5503e2f 414PICO_INTERNAL int PadRead(int i);\r
eff55556 415PICO_INTERNAL unsigned char z80_read(unsigned short a);\r
a4221917 416#ifndef _USE_CZ80\r
eff55556 417PICO_INTERNAL_ASM void z80_write(unsigned char data, unsigned short a);\r
418PICO_INTERNAL void z80_write16(unsigned short data, unsigned short a);\r
a4221917 419PICO_INTERNAL unsigned short z80_read16(unsigned short a);\r
420#else\r
421PICO_INTERNAL_ASM void z80_write(unsigned int a, unsigned char data);\r
422#endif\r
4b9c5888 423PICO_INTERNAL int ym2612_write_local(unsigned int a, unsigned int d, int is_from_z80);\r
f53f286a 424extern unsigned int (*PicoRead16Hook)(unsigned int a, int realsize);\r
f8ef8ff7 425extern void (*PicoWrite8Hook) (unsigned int a,unsigned int d,int realsize);\r
426extern void (*PicoWrite16Hook)(unsigned int a,unsigned int d,int realsize);\r
cc68a136 427\r
428// cd/Memory.c\r
eff55556 429PICO_INTERNAL void PicoMemSetupCD(void);\r
430PICO_INTERNAL_ASM void PicoMemResetCD(int r3);\r
431PICO_INTERNAL_ASM void PicoMemResetCDdecode(int r3);\r
cc68a136 432\r
9037e45d 433// Pico/Memory.c\r
434PICO_INTERNAL void PicoMemSetupPico(void);\r
43e6eaad 435PICO_INTERNAL unsigned int ym2612_read_local_68k(void);\r
9037e45d 436\r
cc68a136 437// Pico.c\r
438extern struct Pico Pico;\r
439extern struct PicoSRAM SRam;\r
5f9a0d16 440extern int PicoPadInt[2];\r
cc68a136 441extern int emustatus;\r
f8ef8ff7 442extern void (*PicoResetHook)(void);\r
b0677887 443extern void (*PicoLineHook)(void);\r
1e6b5e39 444PICO_INTERNAL int CheckDMA(void);\r
445PICO_INTERNAL void PicoDetectRegion(void);\r
4b9c5888 446PICO_INTERNAL void PicoSyncZ80(int m68k_cycles_done);\r
cc68a136 447\r
448// cd/Pico.c\r
2aa27095 449PICO_INTERNAL void PicoInitMCD(void);\r
e5f426aa 450PICO_INTERNAL void PicoExitMCD(void);\r
1cb1584b 451PICO_INTERNAL void PicoPowerMCD(void);\r
2aa27095 452PICO_INTERNAL int PicoResetMCD(void);\r
453PICO_INTERNAL void PicoFrameMCD(void);\r
cc68a136 454\r
9037e45d 455// Pico/Pico.c\r
2aa27095 456PICO_INTERNAL void PicoInitPico(void);\r
ed367a3f 457PICO_INTERNAL void PicoReratePico(void);\r
9037e45d 458\r
ef4eb506 459// Pico/xpcm.c\r
460PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);\r
461PICO_INTERNAL void PicoPicoPCMReset(void);\r
213c16ad 462PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);\r
ef4eb506 463\r
cc68a136 464// Sek.c\r
2aa27095 465PICO_INTERNAL void SekInit(void);\r
466PICO_INTERNAL int SekReset(void);\r
3aa1e148 467PICO_INTERNAL void SekState(int *data);\r
eff55556 468PICO_INTERNAL void SekSetRealTAS(int use_real);\r
5f9a0d16 469void SekStepM68k(void);\r
053fd9b4 470void SekInitIdleDet(void);\r
471void SekFinishIdleDet(void);\r
cc68a136 472\r
473// cd/Sek.c\r
2aa27095 474PICO_INTERNAL void SekInitS68k(void);\r
475PICO_INTERNAL int SekResetS68k(void);\r
476PICO_INTERNAL int SekInterruptS68k(int irq);\r
cc68a136 477\r
7a93adeb 478// sound/sound.c\r
c9e1affc 479PICO_INTERNAL void cdda_start_play();\r
480extern short cdda_out_buffer[2*1152];\r
7a93adeb 481extern int PsndLen_exc_cnt;\r
482extern int PsndLen_exc_add;\r
48dc74f2 483extern int timer_a_next_oflow, timer_a_step; // in z80 cycles\r
484extern int timer_b_next_oflow, timer_b_step;\r
43e6eaad 485\r
486void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);\r
d2721b08 487void ym2612_pack_state(void);\r
453d2a6e 488void ym2612_unpack_state(void);\r
4b9c5888 489\r
e53704e6 490#define TIMER_NO_OFLOW 0x70000000\r
45a1ef71 491// tA = 72 * (1024 - NA) / M\r
492#define TIMER_A_TICK_ZCYCLES 17203\r
493// tB = 1152 * (256 - NA) / M\r
494#define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura\r
e53704e6 495\r
4b9c5888 496#define timers_cycle() \\r
e53704e6 497 if (timer_a_next_oflow > 0 && timer_a_next_oflow < TIMER_NO_OFLOW) \\r
43e6eaad 498 timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
e53704e6 499 if (timer_b_next_oflow > 0 && timer_b_next_oflow < TIMER_NO_OFLOW) \\r
43e6eaad 500 timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
501 ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);\r
4b9c5888 502\r
503#define timers_reset() \\r
e53704e6 504 timer_a_next_oflow = timer_b_next_oflow = TIMER_NO_OFLOW; \\r
48dc74f2 505 timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \\r
506 timer_b_step = TIMER_B_TICK_ZCYCLES * 256;\r
43e6eaad 507\r
7a93adeb 508\r
cc68a136 509// VideoPort.c\r
eff55556 510PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
511PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
9761a7d0 512PICO_INTERNAL_ASM unsigned int PicoVideoRead8(unsigned int a);\r
5de27868 513extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **srcp, unsigned short **limitp);\r
cc68a136 514\r
515// Misc.c\r
eff55556 516PICO_INTERNAL void SRAMWriteEEPROM(unsigned int d);\r
517PICO_INTERNAL void SRAMUpdPending(unsigned int a, unsigned int d);\r
518PICO_INTERNAL_ASM unsigned int SRAMReadEEPROM(void);\r
519PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r
520PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
521PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r
522PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r
cc68a136 523\r
fa1e5e29 524// cd/Misc.c\r
eff55556 525PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
526PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
527\r
528// cd/buffering.c\r
529PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r
530\r
531// sound/sound.c\r
9d917eea 532PICO_INTERNAL void PsndReset(void);\r
4b9c5888 533PICO_INTERNAL void PsndDoDAC(int line_to);\r
9d917eea 534PICO_INTERNAL void PsndClear(void);\r
7b3f44c6 535PICO_INTERNAL void PsndGetSamples(int y);\r
eff55556 536// z80 functionality wrappers\r
537PICO_INTERNAL void z80_init(void);\r
eff55556 538PICO_INTERNAL void z80_pack(unsigned char *data);\r
539PICO_INTERNAL void z80_unpack(unsigned char *data);\r
540PICO_INTERNAL void z80_reset(void);\r
541PICO_INTERNAL void z80_exit(void);\r
4b9c5888 542extern int PsndDacLine;\r
cc68a136 543\r
b8cbd802 544// emulation event logging\r
545#ifndef EL_LOGMASK\r
546#define EL_LOGMASK 0\r
547#endif\r
548\r
017512f2 549#define EL_HVCNT 0x00000001 /* hv counter reads */\r
550#define EL_SR 0x00000002 /* SR reads */\r
551#define EL_INTS 0x00000004 /* ints and acks */\r
43e6eaad 552#define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */\r
017512f2 553#define EL_INTSW 0x00000010 /* log irq switching on/off */\r
554#define EL_ASVDP 0x00000020 /* VDP accesses during active scan */\r
555#define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */\r
556#define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */\r
557#define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */\r
558#define EL_SRAMIO 0x00000200 /* sram i/o */\r
559#define EL_EEPROM 0x00000400 /* eeprom debug */\r
560#define EL_UIO 0x00000800 /* unmapped i/o */\r
561#define EL_IO 0x00001000 /* all i/o */\r
562#define EL_CDPOLL 0x00002000 /* MCD: log poll detection */\r
563#define EL_SVP 0x00004000 /* SVP stuff */\r
fa22af4c 564#define EL_PICOHW 0x00008000 /* Pico stuff */\r
053fd9b4 565#define EL_IDLE 0x00010000 /* idle loop det. */\r
017512f2 566\r
567#define EL_STATUS 0x40000000 /* status messages */\r
568#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
b8cbd802 569\r
570#if EL_LOGMASK\r
7d0143a2 571extern void lprintf(const char *fmt, ...);\r
b8cbd802 572#define elprintf(w,f,...) \\r
573{ \\r
574 if ((w) & EL_LOGMASK) \\r
7d0143a2 575 lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
b8cbd802 576}\r
dca310c4 577#elif defined(_MSC_VER)\r
578#define elprintf\r
b8cbd802 579#else\r
580#define elprintf(w,f,...)\r
581#endif\r
582\r
dca310c4 583#ifdef _MSC_VER\r
584#define cdprintf\r
585#else\r
586#define cdprintf(x...)\r
587#endif\r
588\r
f8af9634 589#ifdef __cplusplus\r
590} // End of extern "C"\r
591#endif\r
592\r
eff55556 593#endif // PICO_INTERNAL_INCLUDED\r
594\r
fast MegaDrive/MegaCD/32X emulator