switch (state)
{
case PGS_VRAM_TRANSFER_START:
- HW_GPU_STATUS &= ~SWAP32(PSXGPU_nBUSY);
+ psxRegs.gpuIdleAfter = psxRegs.cycle + PSXCLK / 50;
break;
case PGS_VRAM_TRANSFER_END:
- HW_GPU_STATUS |= SWAP32(PSXGPU_nBUSY);
+ psxRegs.gpuIdleAfter = psxRegs.cycle;
break;
case PGS_PRIMITIVE_START:
- HW_GPU_STATUS &= ~SWAP32(PSXGPU_nBUSY);
- set_event(PSXINT_GPUDMA, 200); // see gpuInterrupt
+ psxRegs.gpuIdleAfter = psxRegs.cycle + 200;
break;
}
}
SaveFuncs.read(f, &psxRegs, offsetof(psxRegisters, gteBusyCycle));
psxRegs.gteBusyCycle = psxRegs.cycle;
psxRegs.biosBranchCheck = ~0;
+ psxRegs.gpuIdleAfter = psxRegs.cycle - 1;
+ HW_GPU_STATUS &= SWAP32(~PSXGPU_nBUSY);
psxCpu->Notify(R3000ACPU_NOTIFY_AFTER_LOAD, NULL);
SaveFuncs.read(f, gpufP, sizeof(GPUFreeze_t));
GPU_freeze(0, gpufP);
free(gpufP);
- if (HW_GPU_STATUS == 0)
- HW_GPU_STATUS = SWAP32(GPU_readStatus());
+ gpuSyncPluginSR();
// spu
SaveFuncs.read(f, &Size, 4);
GPU_writeStatus(gpu_ctl_def[i]);
for (i = 0; i < sizeof(gpu_data_def) / sizeof(gpu_data_def[0]); i++)
GPU_writeData(gpu_data_def[i]);
- HW_GPU_STATUS |= SWAP32(PSXGPU_nBUSY);
// spu
for (i = 0x1f801d80; i < sizeof(spu_config) / sizeof(spu_config[0]); i++)
}
HW_GPU_STATUS = SWAP32(status);
GPU_vBlank(0, field);
+ if ((s32)(psxRegs.gpuIdleAfter - psxRegs.cycle) < 0)
+ psxRegs.gpuIdleAfter = psxRegs.cycle - 1; // prevent overflow
if ((rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) ||
(rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2))
HW_DMA2_MADR = SWAPu32(madr + words_copy * 4);
// careful: gpu_state_change() also messes with this
- HW_GPU_STATUS &= SWAP32(~PSXGPU_nBUSY);
+ psxRegs.gpuIdleAfter = psxRegs.cycle + words / 4 + 16;
// already 32-bit word size ((size * 4) / 4)
set_event(PSXINT_GPUDMA, words / 4);
return;
HW_DMA2_MADR = SWAPu32(madr);
// careful: gpu_state_change() also messes with this
- HW_GPU_STATUS &= SWAP32(~PSXGPU_nBUSY);
+ psxRegs.gpuIdleAfter = psxRegs.cycle + words / 4 + 16;
// already 32-bit word size ((size * 4) / 4)
set_event(PSXINT_GPUDMA, words / 4);
return;
if ((int)size <= 0)
size = gpuDmaChainSize(madr);
- HW_GPU_STATUS &= SWAP32(~PSXGPU_nBUSY);
HW_DMA2_MADR = SWAPu32(madr_next);
// Tekken 3 = use 1.0 only (not 1.5x)
// Einhander = parse linked list in pieces (todo)
// Rebel Assault 2 = parse linked list in pieces (todo)
+ psxRegs.gpuIdleAfter = psxRegs.cycle + size + 16;
set_event(PSXINT_GPUDMA, size);
return;
DMA_INTERRUPT(2);
}
-// note: this is also (ab)used for non-dma prim command
-// to delay gpu returning to idle state, see gpu_state_change()
void gpuInterrupt() {
if (HW_DMA2_CHCR == SWAP32(0x01000401) && !(HW_DMA2_MADR & SWAP32(0x800000)))
{
u32 size, madr_next = 0xffffff;
size = GPU_dmaChain((u32 *)psxM, HW_DMA2_MADR & 0x1fffff, &madr_next);
HW_DMA2_MADR = SWAPu32(madr_next);
+ psxRegs.gpuIdleAfter = psxRegs.cycle + size + 64;
set_event(PSXINT_GPUDMA, size);
return;
}
HW_DMA2_CHCR &= SWAP32(~0x01000000);
DMA_INTERRUPT(2);
}
- HW_GPU_STATUS |= SWAP32(PSXGPU_nBUSY); // GPU no longer busy
}
void psxDma6(u32 madr, u32 bcr, u32 chcr) {
mdecInit(); // initialize mdec decoder
cdrReset();
psxRcntInit();
- HW_GPU_STATUS = SWAP32(0x14802000);
+ HW_GPU_STATUS = SWAP32(0x10802000);
psxHwReadGpuSRptr = Config.hacks.gpu_busy_hack
? psxHwReadGpuSRbusyHack : psxHwReadGpuSR;
}
u32 psxHwReadGpuSR(void)
{
- u32 v;
+ u32 v, c = psxRegs.cycle;
// meh2, syncing for img bit, might want to avoid it..
gpuSyncPluginSR();
v = SWAP32(HW_GPU_STATUS);
+ v |= ((s32)(psxRegs.gpuIdleAfter - c) >> 31) & PSXGPU_nBUSY;
// XXX: because of large timeslices can't use hSyncCount, using rough
// approximization instead. Perhaps better use hcounter code here or something.
if (hSyncCount < 240 && (v & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
- v |= PSXGPU_LCF & (psxRegs.cycle << 20);
+ v |= PSXGPU_LCF & (c << 20);
return v;
}
u32 dloadVal[2];
u32 biosBranchCheck;
u32 cpuInRecursion;
- u32 reserved[2];
+ u32 gpuIdleAfter;
+ u32 reserved[1];
// warning: changing anything in psxRegisters requires update of all
// asm in libpcsxcore/new_dynarec/
} psxRegisters;