added copyright line to top of source files next to license information

[cyclone68000.git] / Cyclone / OpLogic.cpp

\r
// This file is part of the Cyclone 68000 Emulator\r
\r
// Copyright (c) 2011 FinalDave (emudave (at) gmail.com)\r
\r
// This code is licensed under the GNU General Public License version 2.0 and the MAME License.\r
// You can choose the license that has the most advantages for you.\r
\r
// SVN repository can be found at http://code.google.com/p/cyclone68000/\r
\r
#include "app.h"\r
\r
// --------------------- Opcodes 0x0100+ ---------------------\r
// Emit a Btst (Register) opcode 0000nnn1 00aaaaaa\r
int OpBtstReg(int op)\r
{\r
  int use=0;\r
  int type=0,sea=0,tea=0;\r
  int size=0;\r
\r
  type=(op>>6)&3;\r
  // Get source and target EA\r
  sea=(op>>9)&7;\r
  tea=op&0x003f;\r
  if (tea<0x10) size=2; // For registers, 32-bits\r
\r
  if ((tea&0x38)==0x08) return 1; // movep\r
\r
  // See if we can do this opcode:\r
  if (EaCanRead(tea,0)==0) return 1;\r
  if (type>0)\r
  {\r
    if (EaCanWrite(tea)==0) return 1;\r
  }\r
\r
  use=OpBase(op);\r
  use&=~0x0e00; // Use same handler for all registers\r
  if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
  OpStart(op); Cycles=4;\r
  if (tea<0x10) Cycles+=2;\r
  if (type>0) Cycles+=4;\r
\r
  ot("  mov r10,#1\n");\r
\r
  EaCalc (0,0x0e00,sea,0);\r
  EaRead (0,     0,sea,0);\r
  ot("  bic r9,r9,#0x40000000 ;@ Blank Z flag\n");\r
  ot("  mov r10,r10,lsl r0 ;@ Make bit mask\n");\r
  ot("\n");\r
\r
  EaCalc(11,0x003f,tea,size);\r
  EaRead(11,     0,tea,size);\r
  ot("  tst r0,r10 ;@ Do arithmetic\n");\r
  ot("  orreq r9,r9,#0x40000000 ;@ Get Z flag\n");\r
  ot("\n");\r
\r
  if (type>0)\r
  {\r
    if (type==1) ot("  eor r1,r0,r10 ;@ Toggle bit\n");\r
    if (type==2) ot("  bic r1,r0,r10 ;@ Clear bit\n");\r
    if (type==3) ot("  orr r1,r0,r10 ;@ Set bit\n");\r
    ot("\n");\r
    EaWrite(11,   1,tea,size);\r
  }\r
  OpEnd();\r
\r
  return 0;\r
}\r
\r
// --------------------- Opcodes 0x0800+ ---------------------\r
// Emit a Btst/Bchg/Bclr/Bset (Immediate) opcode 00001000 ttaaaaaa nn\r
int OpBtstImm(int op)\r
{\r
  int type=0,sea=0,tea=0;\r
  int use=0;\r
  int size=0;\r
\r
  type=(op>>6)&3;\r
  // Get source and target EA\r
  sea=   0x003c;\r
  tea=op&0x003f;\r
  if (tea<0x10) size=2; // For registers, 32-bits\r
\r
  // See if we can do this opcode:\r
  if (EaCanRead(tea,0)==0) return 1;\r
  if (type>0)\r
  {\r
    if (EaCanWrite(tea)==0) return 1;\r
  }\r
\r
  use=OpBase(op);\r
  if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
  OpStart(op); Cycles=4;\r
  if (type<3 && tea<0x10) Cycles+=2;\r
  if (type>0) Cycles+=4;\r
\r
  ot("  mov r10,#1\n");\r
  ot("\n");\r
  EaCalc ( 0,0x0000,sea,0);\r
  EaRead ( 0,     0,sea,0);\r
  ot("  bic r9,r9,#0x40000000 ;@ Blank Z flag\n");\r
  ot("  mov r10,r10,lsl r0 ;@ Make bit mask\n");\r
  ot("\n");\r
\r
  EaCalc (11,0x003f,tea,size);\r
  EaRead (11,     0,tea,size);\r
  ot("  tst r0,r10 ;@ Do arithmetic\n");\r
  ot("  orreq r9,r9,#0x40000000 ;@ Get Z flag\n");\r
  ot("\n");\r
\r
  if (type>0)\r
  {\r
    if (type==1) ot("  eor r1,r0,r10 ;@ Toggle bit\n");\r
    if (type==2) ot("  bic r1,r0,r10 ;@ Clear bit\n");\r
    if (type==3) ot("  orr r1,r0,r10 ;@ Set bit\n");\r
    ot("\n");\r
    EaWrite(11,   1,tea,size);\r
  }\r
\r
  OpEnd();\r
\r
  return 0;\r
}\r
\r
// --------------------- Opcodes 0x4000+ ---------------------\r
int OpNeg(int op)\r
{\r
  // 01000tt0 xxeeeeee (tt=negx/clr/neg/not, xx=size, eeeeee=EA)\r
  int type=0,size=0,ea=0,use=0;\r
\r
  type=(op>>9)&3;\r
  ea  =op&0x003f;\r
  size=(op>>6)&3; if (size>=3) return 1;\r
\r
  switch (type)\r
  {\r
    case 1: case 2: case 3: break;\r
    default: return 1; // todo\r
  }\r
\r
  // See if we can do this opcode:\r
  if (EaCanRead (ea,size)==0) return 1;\r
  if (EaCanWrite(ea     )==0) return 1;\r
\r
  use=OpBase(op);\r
  if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
  OpStart(op); Cycles=size<2?4:6;\r
\r
  EaCalc (10,0x003f,ea,size);\r
\r
  if (type!=1) EaRead (10,0,ea,size); // Don't need to read for 'clr'\r
  if (type==1) ot("\n");\r
\r
  if (type==1)\r
  {\r
    ot(";@ Clear:\n");\r
    ot("  mov r1,#0\n");\r
    ot("  mov r9,#0x40000000 ;@ NZCV=0100\n");\r
    ot("\n");\r
  }\r
\r
  if (type==2)\r
  {\r
    ot(";@ Neg:\n");\r
    ot("  rsbs r1,r0,#0\n");\r
    OpGetFlags(1,1);\r
    ot("\n");\r
  }\r
\r
  if (type==3)\r
  {\r
    ot(";@ Not:\n");\r
    ot("  mvn r1,r0\n");\r
    ot("  adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
    OpGetFlags(0,0);\r
    ot("\n");\r
  }\r
\r
  EaWrite(10,     1,ea,size);\r
\r
  OpEnd();\r
\r
  return 0;\r
}\r
\r
// --------------------- Opcodes 0x4840+ ---------------------\r
// Swap, 01001000 01000nnn swap Dn\r
int OpSwap(int op)\r
{\r
  int ea=0,use=0;\r
\r
  ea=op&7;\r
  use=op&~0x0007; // Use same opcode for all An\r
\r
  if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
  OpStart(op); Cycles=4;\r
\r
  EaCalc (10,0x0007,ea,2);\r
  EaRead (10,     0,ea,2);\r
\r
  ot("  mov r1,r0,ror #16\n");\r
  ot("  adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
  OpGetFlags(0,0);\r
\r
  EaWrite(10,     1,8,2);\r
\r
  OpEnd();\r
\r
  return 0;\r
}\r
\r
// --------------------- Opcodes 0x4a00+ ---------------------\r
// Emit a Tst opcode, 01001010 xxeeeeee\r
int OpTst(int op)\r
{\r
  int sea=0;\r
  int size=0,use=0;\r
\r
  sea=op&0x003f;\r
  size=(op>>6)&3; if (size>=3) return 1;\r
\r
  // See if we can do this opcode:\r
  if (EaCanWrite(sea)==0) return 1;\r
\r
  use=OpBase(op);\r
  if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
  OpStart(op); Cycles=4;\r
\r
  EaCalc ( 0,0x003f,sea,size);\r
  EaRead ( 0,     0,sea,size);\r
\r
  ot("  adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
  ot("  mrs r9,cpsr ;@ r9=flags\n");\r
  ot("\n");\r
\r
  OpEnd();\r
  return 0;\r
}\r
\r
// --------------------- Opcodes 0x4880+ ---------------------\r
// Emit an Ext opcode, 01001000 1x000nnn\r
int OpExt(int op)\r
{\r
  int ea=0;\r
  int size=0,use=0;\r
  int shift=0;\r
\r
  ea=op&0x0007;\r
  size=(op>>6)&1;\r
  shift=32-(8<<size);\r
\r
  use=OpBase(op);\r
  if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
  OpStart(op); Cycles=4;\r
\r
  EaCalc (10,0x0007,ea,size+1);\r
  EaRead (10,     0,ea,size+1);\r
\r
  ot("  mov r0,r0,asl #%d\n",shift);\r
  ot("  adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
  ot("  mrs r9,cpsr ;@ r9=flags\n");\r
  ot("  mov r1,r0,asr #%d\n",shift);\r
  ot("\n");\r
\r
  EaWrite(10,     1,ea,size+1);\r
\r
  OpEnd();\r
  return 0;\r
}\r
\r
// --------------------- Opcodes 0x50c0+ ---------------------\r
// Emit a Set cc opcode, 0101cccc 11eeeeee\r
int OpSet(int op)\r
{\r
  int cc=0,ea=0;\r
  int size=0,use=0;\r
  char *cond[16]=\r
  {\r
    "al","", "hi","ls","cc","cs","ne","eq",\r
    "vc","vs","pl","mi","ge","lt","gt","le"\r
  };\r
\r
  cc=(op>>8)&15;\r
  ea=op&0x003f;\r
\r
  if ((ea&0x38)==0x08) return 1; // dbra, not scc\r
  \r
  // See if we can do this opcode:\r
  if (EaCanWrite(ea)==0) return 1;\r
\r
  use=OpBase(op);\r
  if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
  OpStart(op); Cycles=8;\r
\r
  if (ea<0x10) Cycles=4;\r
\r
  ot("  mov r1,#0\n");\r
\r
  if (cc!=1)\r
  {\r
    ot(";@ Is the condition true?\n");\r
    if ((cc&~1)==2) ot("  eor r9,r9,#0x20000000 ;@ Invert carry for hi/ls\n");\r
    ot("  msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");\r
    if ((cc&~1)==2) ot("  eor r9,r9,#0x20000000 ;@ Invert carry for hi/ls\n");\r
    ot("  mvn%s r1,r1\n",cond[cc]);\r
  }\r
\r
  if (ea<0x10) ot("  sub%s r5,r5,#2 ;@ Extra cycles\n",cond[cc]);\r
  ot("\n");\r
\r
  EaCalc (0,0x003f, ea,size);\r
  EaWrite(0,     1, ea,size);\r
\r
  OpEnd();\r
  return 0;\r
}\r
\r
// Emit a Asr/Lsr/Roxr/Ror opcode\r
static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)\r
{\r
  char pct[8]="";\r
  int shift=32-(8<<size);\r
\r
  if (count>=1) sprintf(pct,"#%d",count); // Fixed count\r
\r
  if (count<0)\r
  {\r
    ot("  mov r2,r8,lsr #9 ;@ Get 'n'\n");\r
    ot("  and r2,r2,#7\n\n"); strcpy(pct,"r2");\r
  }\r
\r
  if (usereg)\r
  {\r
    ot(";@ Use Dn for count:\n");\r
    ot("  ldr r2,[r7,r2,lsl #2]\n");\r
    ot("  and r2,r2,#63\n");\r
    ot("\n");\r
  }\r
\r
  // Take 2*n cycles:\r
  if (count<0) ot("  sub r5,r5,r2,asl #1 ;@ Take 2*n cycles\n\n");\r
  else Cycles+=count<<1;\r
\r
  if (type<2)\r
  {\r
    // Asr/Lsr\r
    if (dir==0 && size<2)\r
    {\r
      ot(";@ For shift right, also copy to lowest bits (to get carry bit):\n");\r
      ot("  orr r0,r0,r0,lsr #%d\n",32-(8<<size));\r
      ot("\n");\r
    }\r
\r
    ot(";@ Shift register:\n");\r
    if (type==0) ot("  movs r0,r0,%s %s\n",dir?"asl":"asr",pct);\r
    if (type==1) ot("  movs r0,r0,%s %s\n",dir?"lsl":"lsr",pct);\r
    OpGetFlags(0,1);\r
    ot("\n");\r
\r
    if (size<2)\r
    {\r
      ot(";@ Check if result is zero:\n");\r
      ot("  movs r2,r0,lsr #%d\n",shift);\r
      ot("  orreq r9,r9,#0x40000000\n");\r
      ot("\n");\r
    }\r
  }\r
\r
  // --------------------------------------\r
  if (type==2)\r
  {\r
    // Roxr\r
    int wide=8<<size;\r
\r
    if (shift) ot("  mov r0,r0,lsr #%d ;@ Shift down\n",shift);\r
\r
    ot(";@ Rotate register through X:\n");\r
    if (strcmp("r2",pct)!=0) { ot("  mov r2,%s\n",pct); strcpy(pct,"r2"); } // Get into register\r
\r
    if (count!=8)\r
    {\r
      ot(";@ Reduce r2 until <0:\n");\r
      ot("Reduce_%.4x%s\n",op,ms?"":":");\r
      ot("  subs r2,r2,#%d\n",wide+1);\r
      ot("  bpl Reduce_%.4x\n",op);\r
      ot("  add r2,r2,#%d ;@ Now r2=0-%d\n",wide+1,wide);\r
      ot("\n");\r
    }\r
\r
    if (dir) ot("  rsb r2,r2,#%d ;@ Reverse direction\n",wide+1);\r
\r
    ot(";@ Rotate bits:\n");\r
    ot("  mov r3,r0,lsr r2 ;@ Get right part\n");\r
    ot("  rsb r2,r2,#%d\n",wide+1);\r
    ot("  movs r0,r0,lsl r2 ;@ Get left part\n");\r
    ot("  orr r0,r3,r0 ;@ r0=Rotated value\n");\r
\r
    ot(";@ Insert X bit into r2-1:\n");\r
    ot("  ldrb r3,[r7,#0x45]\n");\r
    ot("  sub r2,r2,#1\n");\r
    ot("  and r3,r3,#2\n");\r
    ot("  mov r3,r3,lsr #1\n");\r
    ot("  orr r0,r0,r3,lsl r2\n");\r
    ot("\n");\r
\r
    if (shift) ot("  movs r0,r0,lsl #%d ;@ Shift up and get correct NC flags\n",shift);\r
    OpGetFlags(0,1);\r
    ot("\n");\r
  }\r
\r
  // --------------------------------------\r
  if (type==3)\r
  {\r
    // Ror\r
    if (size<2)\r
    {\r
      ot(";@ Mirror value in whole 32 bits:\n");\r
      if (size<=0) ot("  orr r0,r0,r0,lsr #8\n");\r
      if (size<=1) ot("  orr r0,r0,r0,lsr #16\n");\r
      ot("\n");\r
    }\r
\r
    ot(";@ Rotate register:\n");\r
    if (count<0)\r
    {\r
      if (dir) ot("  rsb r2,%s,#32\n",pct);\r
      ot("  movs r0,r0,ror %s\n",pct);\r
    }\r
    else\r
    {\r
      int ror=count;\r
      if (dir) ror=32-ror;\r
      if (ror&31) ot("  movs r0,r0,ror #%d\n",ror);\r
    }\r
\r
    if (dir)\r
    {\r
      ot(";@ Get carry bit from bit 0:\n");\r
      ot("  mov r9,#0\n");\r
      ot("  ands r2,r0,#1\n");\r
      ot("  orrne r9,r9,#0x20000000\n");\r
    }\r
    else\r
    {\r
      OpGetFlags(0,0);\r
    }\r
    ot("\n");\r
\r
  }\r
  // --------------------------------------\r
  \r
  return 0;\r
}\r
\r
// Emit a Asr/Lsr/Roxr/Ror opcode - 1110cccd xxuttnnn\r
// (ccc=count, d=direction xx=size extension, u=use reg for count, tt=type, nnn=register Dn)\r
int OpAsr(int op)\r
{\r
  int ea=0,use=0;\r
  int count=0,dir=0;\r
  int size=0,usereg=0,type=0;\r
\r
  ea=0;\r
  count =(op>>9)&7;\r
  dir   =(op>>8)&1;\r
  size  =(op>>6)&3;\r
  if (size>=3) return 1; // todo Asr EA\r
  usereg=(op>>5)&1;\r
  type  =(op>>3)&3;\r
\r
  if (usereg==0) count=((count-1)&7)+1; // because ccc=000 means 8\r
\r
  // Use the same opcode for target registers:\r
  use=op&~0x0007;\r
\r
  // As long as count is not 8, use the same opcode for all shift counts::\r
  if (usereg==0 && count!=8) { use|=0x0e00; count=-1; }\r
  if (usereg) { use&=~0x0e00; count=-1; } // Use same opcode for all Dn\r
\r
  if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
  OpStart(op); Cycles=size<2?6:8;\r
\r
  EaCalc(10,0x0007, ea,size);\r
  EaRead(10,     0, ea,size,1);\r
\r
  EmitAsr(op,type,dir,count, size,usereg);\r
\r
  EaWrite(10,    0, ea,size,1);\r
\r
  OpEnd();\r
\r
  return 0;\r
}\r
\r
// Asr/l/Ror/l etc EA - 11100ttd 11eeeeee \r
int OpAsrEa(int op)\r
{\r
  int use=0,type=0,dir=0,ea=0,size=1;\r
\r
  type=(op>>9)&3;\r
  dir =(op>>8)&1;\r
  ea  = op&0x3f;\r
\r
  if (ea<0x10) return 1;\r
  // See if we can do this opcode:\r
  if (EaCanRead(ea,0)==0) return 1;\r
  if (EaCanWrite(ea)==0) return 1;\r
\r
  use=OpBase(op);\r
  if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
  OpStart(op); Cycles=8;\r
\r
  EaCalc (10,0x003f,ea,size);\r
  EaRead (10,     0,ea,size,1);\r
\r
  EmitAsr(op,type,dir,1, size,0);\r
\r
  ot(";@ Save shifted value back to EA:\n");\r
  ot("  mov r1,r0\n");\r
  EaWrite(10,     1,ea,size,1);\r
\r
  OpEnd();\r
  return 0;\r
}\r