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don't pass trash in MSB bits to write8 and write16 handlers
[cyclone68000.git] / Ea.cpp
CommitLineData
6003a768 1\r
619b1824 2// This file is part of the Cyclone 68000 Emulator\r
3\r
d9d77995 4// Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)\r
5// Copyright (c) 2005-2011 GraÅžvydas "notaz" Ignotas (notasas (at) gmail.com)\r
c41b9b97 6\r
619b1824 7// This code is licensed under the GNU General Public License version 2.0 and the MAME License.\r
8// You can choose the license that has the most advantages for you.\r
9\r
10// SVN repository can be found at http://code.google.com/p/cyclone68000/\r
11\r
d9d77995 12\r
6003a768 13#include "app.h"\r
14\r
d9d77995 15int earead_check_addrerr = 1, eawrite_check_addrerr = 0;\r
16\r
17// some ops use non-standard cycle counts for EAs, so are listed here.\r
18// all constants borrowed from the MUSASHI core by Karl Stenerud.\r
19\r
20/* Extra cycles for JMP instruction (000, 010) */\r
21int g_jmp_cycle_table[8] =\r
22{\r
23 4, /* EA_MODE_AI */\r
24 6, /* EA_MODE_DI */\r
25 10, /* EA_MODE_IX */\r
26 6, /* EA_MODE_AW */\r
27 8, /* EA_MODE_AL */\r
28 6, /* EA_MODE_PCDI */\r
29 10, /* EA_MODE_PCIX */\r
30 0, /* EA_MODE_I */\r
31};\r
32\r
33/* Extra cycles for JSR instruction (000, 010) */\r
34int g_jsr_cycle_table[8] =\r
35{\r
36 4, /* EA_MODE_AI */\r
37 6, /* EA_MODE_DI */\r
38 10, /* EA_MODE_IX */\r
39 6, /* EA_MODE_AW */\r
40 8, /* EA_MODE_AL */\r
41 6, /* EA_MODE_PCDI */\r
42 10, /* EA_MODE_PCIX */\r
43 0, /* EA_MODE_I */\r
44};\r
45\r
46/* Extra cycles for LEA instruction (000, 010) */\r
47int g_lea_cycle_table[8] =\r
48{\r
49 4, /* EA_MODE_AI */\r
50 8, /* EA_MODE_DI */\r
51 12, /* EA_MODE_IX */\r
52 8, /* EA_MODE_AW */\r
53 12, /* EA_MODE_AL */\r
54 8, /* EA_MODE_PCDI */\r
55 12, /* EA_MODE_PCIX */\r
56 0, /* EA_MODE_I */\r
57};\r
58\r
59/* Extra cycles for PEA instruction (000, 010) */\r
60int g_pea_cycle_table[8] =\r
61{\r
62 6, /* EA_MODE_AI */\r
63 10, /* EA_MODE_DI */\r
64 14, /* EA_MODE_IX */\r
65 10, /* EA_MODE_AW */\r
66 14, /* EA_MODE_AL */\r
67 10, /* EA_MODE_PCDI */\r
68 14, /* EA_MODE_PCIX */\r
69 0, /* EA_MODE_I */\r
70};\r
71\r
72/* Extra cycles for MOVEM instruction (000, 010) */\r
73int g_movem_cycle_table[8] =\r
74{\r
75 0, /* EA_MODE_AI */\r
76 4, /* EA_MODE_DI */\r
77 6, /* EA_MODE_IX */\r
78 4, /* EA_MODE_AW */\r
79 8, /* EA_MODE_AL */\r
80 0, /* EA_MODE_PCDI */\r
81 0, /* EA_MODE_PCIX */\r
82 0, /* EA_MODE_I */\r
83};\r
84\r
85// add nonstandard EA\r
86int Ea_add_ns(int *tab, int ea)\r
87{\r
88 if(ea<0x10) return 0;\r
89 if((ea&0x38)==0x10) return tab[0]; // (An) (ai)\r
90 if(ea<0x28) return 0;\r
91 if(ea<0x30) return tab[1]; // ($nn,An) (di)\r
92 if(ea<0x38) return tab[2]; // ($nn,An,Rn) (ix)\r
93 if(ea==0x38) return tab[3]; // (aw)\r
94 if(ea==0x39) return tab[4]; // (al)\r
95 if(ea==0x3a) return tab[5]; // ($nn,PC) (pcdi)\r
96 if(ea==0x3b) return tab[6]; // ($nn,pc,Rn) (pcix)\r
97 if(ea==0x3c) return tab[7]; // #$nnnn (i)\r
98 return 0;\r
99}\r
100\r
101\r
6003a768 102// ---------------------------------------------------------------------------\r
103// Gets the offset of a register for an ea, and puts it in 'r'\r
104// Shifted left by 'shift'\r
105// Doesn't trash anything\r
d9d77995 106static int EaCalcReg(int r,int ea,int mask,int forceor,int shift,int noshift=0)\r
6003a768 107{\r
108 int i=0,low=0,needor=0;\r
109 int lsl=0;\r
110\r
111 for (i=mask|0x8000; (i&1)==0; i>>=1) low++; // Find out how high up the EA mask is\r
112 mask&=0xf<<low; // This is the max we can do\r
113\r
d9d77995 114 if (ea>=8)\r
115 {\r
116 needor=1; // Need to OR to access A0-7\r
117 if ((g_op>>low)&8) { needor=0; mask|=8<<low; } // Ah - no we don't actually need to or, since the bit is high in r8\r
118 if (forceor) needor=1; // Special case for 0x30-0x38 EAs ;)\r
119 }\r
6003a768 120\r
121 ot(" and r%d,r8,#0x%.4x\n",r,mask);\r
d9d77995 122 if (needor) ot(" orr r%d,r%d,#0x%x ;@ A0-7\n",r,r,8<<low);\r
6003a768 123\r
124 // Find out amount to shift left:\r
125 lsl=shift-low;\r
126\r
d9d77995 127 if (lsl&&!noshift)\r
6003a768 128 {\r
129 ot(" mov r%d,r%d,",r,r);\r
130 if (lsl>0) ot("lsl #%d\n", lsl);\r
131 else ot("lsr #%d\n",-lsl);\r
132 }\r
133\r
6003a768 134 return 0;\r
135}\r
136\r
137// EaCalc - ARM Register 'a' = Effective Address\r
d9d77995 138// If ea>=0x10, trashes r0,r2 and r3, else nothing\r
139// size values 0, 1, 2 ~ byte, word, long\r
140// mask shows usable bits in r8\r
65044ba9 141int EaCalc(int a,int mask,int ea,int size,EaRWType type)\r
6003a768 142{\r
143 char text[32]="";\r
6003a768 144\r
145 DisaPc=2; DisaGetEa(text,ea,size); // Get text version of the effective address\r
6003a768 146\r
147 if (ea<0x10)\r
148 {\r
65044ba9 149 // Saves one opcode as we can shift in ldr/str\r
d9d77995 150 int noshift=0;\r
65044ba9 151 if (size >= 2 || (size == 0 && type != earwt_sign_extend)) noshift=1;\r
6003a768 152\r
153 ot(";@ EaCalc : Get register index into r%d:\n",a);\r
154\r
d9d77995 155 EaCalcReg(a,ea,mask,0,2,noshift);\r
6003a768 156 return 0;\r
157 }\r
d9d77995 158\r
6003a768 159 ot(";@ EaCalc : Get '%s' into r%d:\n",text,a);\r
d9d77995 160 // (An), (An)+, -(An)\r
6003a768 161 if (ea<0x28)\r
162 {\r
d9d77995 163 int step=1<<size, strr=a;\r
164 int low=0,lsl=0,i;\r
6003a768 165\r
166 if ((ea&7)==7 && step<2) step=2; // move.b (a7)+ or -(a7) steps by 2 not 1\r
167\r
d9d77995 168 if (ea==0x1f||ea==0x27) // A7 handlers are always separate\r
169 {\r
170 ot(" ldr r%d,[r7,#0x3c] ;@ A7\n",a);\r
171 }\r
172 else\r
173 {\r
174 EaCalcReg(2,ea,mask,0,0,1);\r
175 if(mask)\r
176 for (i=mask|0x8000; (i&1)==0; i>>=1) low++; // Find out how high up the EA mask is\r
177 lsl=2-low; // Having a lsl #x here saves one opcode\r
178 if (lsl>=0) ot(" ldr r%d,[r7,r2,lsl #%i]\n",a,lsl);\r
179 else if (lsl<0) ot(" ldr r%d,[r7,r2,lsr #%i]\n",a,-lsl);\r
180 }\r
6003a768 181\r
d9d77995 182 if ((ea&0x38)==0x18) // (An)+\r
6003a768 183 {\r
184 ot(" add r3,r%d,#%d ;@ Post-increment An\n",a,step);\r
d9d77995 185 strr=3;\r
6003a768 186 }\r
187\r
d9d77995 188 if ((ea&0x38)==0x20) // -(An)\r
6003a768 189 ot(" sub r%d,r%d,#%d ;@ Pre-decrement An\n",a,a,step);\r
d9d77995 190\r
191 if ((ea&0x38)==0x18||(ea&0x38)==0x20)\r
192 {\r
193 if (ea==0x1f||ea==0x27)\r
194 {\r
195 ot(" str r%d,[r7,#0x3c] ;@ A7\n",strr);\r
196 }\r
197 else\r
198 {\r
199 if (lsl>=0) ot(" str r%d,[r7,r2,lsl #%i]\n",strr,lsl);\r
200 else if (lsl<0) ot(" str r%d,[r7,r2,lsr #%i]\n",strr,-lsl);\r
201 }\r
6003a768 202 }\r
203\r
204 if ((ea&0x38)==0x20) Cycles+=size<2 ? 6:10; // -(An) Extra cycles\r
205 else Cycles+=size<2 ? 4:8; // (An),(An)+ Extra cycles\r
206 return 0;\r
207 }\r
208\r
d9d77995 209 if (ea<0x30) // ($nn,An) (di)\r
6003a768 210 {\r
d9d77995 211 ot(" ldrsh r0,[r4],#2 ;@ Fetch offset\n"); pc_dirty=1;\r
212 EaCalcReg(2,8,mask,0,0);\r
213 ot(" ldr r2,[r7,r2,lsl #2]\n");\r
6003a768 214 ot(" add r%d,r0,r2 ;@ Add on offset\n",a);\r
215 Cycles+=size<2 ? 8:12; // Extra cycles\r
216 return 0;\r
217 }\r
218\r
d9d77995 219 if (ea<0x38) // ($nn,An,Rn) (ix)\r
6003a768 220 {\r
221 ot(";@ Get extension word into r3:\n");\r
d9d77995 222 ot(" ldrh r3,[r4],#2 ;@ ($Disp,PC,Rn)\n"); pc_dirty=1;\r
6003a768 223 ot(" mov r2,r3,lsr #10\n");\r
224 ot(" tst r3,#0x0800 ;@ Is Rn Word or Long\n");\r
225 ot(" and r2,r2,#0x3c ;@ r2=Index of Rn\n");\r
6003a768 226 ot(" ldreqsh r2,[r7,r2] ;@ r2=Rn.w\n");\r
227 ot(" ldrne r2,[r7,r2] ;@ r2=Rn.l\n");\r
d9d77995 228 ot(" mov r0,r3,asl #24 ;@ r0=Get 8-bit signed Disp\n");\r
6003a768 229 ot(" add r3,r2,r0,asr #24 ;@ r3=Disp+Rn\n");\r
230\r
d9d77995 231 EaCalcReg(2,8,mask,1,0);\r
232 ot(" ldr r2,[r7,r2,lsl #2]\n");\r
6003a768 233 ot(" add r%d,r2,r3 ;@ r%d=Disp+An+Rn\n",a,a);\r
234 Cycles+=size<2 ? 10:14; // Extra cycles\r
235 return 0;\r
236 }\r
237\r
d9d77995 238 if (ea==0x38) // (aw)\r
6003a768 239 {\r
d9d77995 240 ot(" ldrsh r%d,[r4],#2 ;@ Fetch Absolute Short address\n",a); pc_dirty=1;\r
6003a768 241 Cycles+=size<2 ? 8:12; // Extra cycles\r
242 return 0;\r
243 }\r
244\r
d9d77995 245 if (ea==0x39) // (al)\r
6003a768 246 {\r
247 ot(" ldrh r2,[r4],#2 ;@ Fetch Absolute Long address\n");\r
d9d77995 248 ot(" ldrh r0,[r4],#2\n"); pc_dirty=1;\r
6003a768 249 ot(" orr r%d,r0,r2,lsl #16\n",a);\r
250 Cycles+=size<2 ? 12:16; // Extra cycles\r
251 return 0;\r
252 }\r
253\r
d9d77995 254 if (ea==0x3a) // ($nn,PC) (pcdi)\r
6003a768 255 {\r
256 ot(" ldr r0,[r7,#0x60] ;@ Get Memory base\n");\r
257 ot(" sub r0,r4,r0 ;@ Real PC\n");\r
d9d77995 258 ot(" ldrsh r2,[r4],#2 ;@ Fetch extension\n"); pc_dirty=1;\r
2fc3c6ff 259 ot(" add r%d,r2,r0 ;@ ($nn,PC)\n",a);\r
6003a768 260 Cycles+=size<2 ? 8:12; // Extra cycles\r
261 return 0;\r
262 }\r
263\r
d9d77995 264 if (ea==0x3b) // ($nn,pc,Rn) (pcix)\r
6003a768 265 {\r
d9d77995 266 ot(" ldr r0,[r7,#0x60] ;@ Get Memory base\n");\r
267 ot(" ldrh r3,[r4] ;@ Get extension word\n");\r
268 ot(" sub r0,r4,r0 ;@ r0=PC\n");\r
269 ot(" add r4,r4,#2\n"); pc_dirty=1;\r
6003a768 270 ot(" mov r2,r3,lsr #10\n");\r
271 ot(" tst r3,#0x0800 ;@ Is Rn Word or Long\n");\r
272 ot(" and r2,r2,#0x3c ;@ r2=Index of Rn\n");\r
6003a768 273 ot(" ldreqsh r2,[r7,r2] ;@ r2=Rn.w\n");\r
274 ot(" ldrne r2,[r7,r2] ;@ r2=Rn.l\n");\r
d9d77995 275 ot(" mov r3,r3,asl #24 ;@ r3=Get 8-bit signed Disp\n");\r
276 ot(" add r2,r2,r3,asr #24 ;@ r2=Disp+Rn\n");\r
2fc3c6ff 277 ot(" add r%d,r2,r0 ;@ r%d=Disp+PC+Rn\n",a,a);\r
6003a768 278 Cycles+=size<2 ? 10:14; // Extra cycles\r
279 return 0;\r
280 }\r
281\r
d9d77995 282 if (ea==0x3c) // #$nnnn (i)\r
6003a768 283 {\r
284 if (size<2)\r
285 {\r
d9d77995 286 ot(" ldr%s r%d,[r4],#2 ;@ Fetch immediate value\n",Sarm[size&3],a); pc_dirty=1;\r
6003a768 287 Cycles+=4; // Extra cycles\r
288 return 0;\r
289 }\r
290\r
291 ot(" ldrh r2,[r4],#2 ;@ Fetch immediate value\n");\r
d9d77995 292 ot(" ldrh r3,[r4],#2\n"); pc_dirty=1;\r
293 ot(" orr r%d,r3,r2,lsl #16\n",a);\r
6003a768 294 Cycles+=8; // Extra cycles\r
295 return 0;\r
296 }\r
297\r
298 return 1;\r
299}\r
300\r
301// ---------------------------------------------------------------------------\r
302// Read effective address in (ARM Register 'a') to ARM register 'v'\r
303// 'a' and 'v' can be anything but 0 is generally best (for both)\r
65044ba9 304// If (ea<0x10) nothing is trashed, else r0-r3,r12 is trashed\r
305int EaRead(int a,int v,int ea,int size,int mask,EaRWType type,int set_nz)\r
6003a768 306{\r
307 char text[32]="";\r
3504ce94 308 const char *s="";\r
309 int flags_set=0;\r
6003a768 310 int shift=0;\r
d9d77995 311\r
65044ba9 312 if (set_nz) {\r
313 if (type == earwt_msb_dont_care || type == earwt_zero_extend) {\r
314 fprintf(stderr, "set_nz on msb_dont_care/zero_extend?\n");\r
315 exit(1);\r
316 }\r
317 s="s";\r
318 }\r
3504ce94 319\r
6003a768 320 shift=32-(8<<size);\r
321\r
322 DisaPc=2; DisaGetEa(text,ea,size); // Get text version of the effective address\r
323\r
324 if (ea<0x10)\r
325 {\r
d9d77995 326 int lsl=0,low=0,nsarm=size&3,i;\r
65044ba9 327 if (size >= 2 || (size == 0 && type != earwt_sign_extend)) {\r
328 if (mask)\r
d9d77995 329 for (i=mask|0x8000; (i&1)==0; i>>=1) low++; // Find out how high up the EA mask is\r
330 lsl=2-low; // Having a lsl #2 here saves one opcode\r
331 }\r
332\r
65044ba9 333 if (type == earwt_shifted_up || type == earwt_msb_dont_care)\r
334 // use plain ldr\r
335 nsarm = 3;\r
6003a768 336\r
337 ot(";@ EaRead : Read register[r%d] into r%d:\n",a,v);\r
338\r
d9d77995 339 if (lsl>0) ot(" ldr%s r%d,[r7,r%d,lsl #%i]\n",Narm[nsarm],v,a,lsl);\r
340 else if (lsl<0) ot(" ldr%s r%d,[r7,r%d,lsr #%i]\n",Narm[nsarm],v,a,-lsl);\r
ba3db9e7 341 else ot(" ldr%s r%d,[r7,r%d]\n",type==earwt_sign_extend?Sarm[nsarm]:Narm[nsarm],v,a);\r
6003a768 342\r
65044ba9 343 if (type == earwt_shifted_up && shift)\r
344 ot(" mov%s r%d,r%d,asl #%d\n",s,v,v,shift);\r
345 else if (set_nz)\r
346 ot(" tst r%d,r%d\n",v,v);\r
6003a768 347\r
348 ot("\n"); return 0;\r
349 }\r
350\r
351 ot(";@ EaRead : Read '%s' (address in r%d) into r%d:\n",text,a,v);\r
352\r
353 if (ea==0x3c)\r
354 {\r
355 int asl=0;\r
356\r
65044ba9 357 if (type == earwt_shifted_up) asl = shift;\r
6003a768 358\r
3504ce94 359 if (asl) ot(" mov%s r%d,r%d,asl #%d\n",s,v,a,asl);\r
360 else if (v!=a) ot(" mov%s r%d,r%d\n",s,v,a);\r
361 else if (set_nz) ot(" tst r%d,r%d\n",v,v);\r
6003a768 362 ot("\n"); return 0;\r
363 }\r
364\r
d9d77995 365 if (ea>=0x3a && ea<=0x3b) MemHandler(2,size,a,earead_check_addrerr); // Fetch\r
366 else MemHandler(0,size,a,earead_check_addrerr); // Read\r
6003a768 367\r
d9d77995 368 // defaults to 1, as most things begins with a read\r
369 earead_check_addrerr=1;\r
6003a768 370\r
65044ba9 371 if (type == earwt_sign_extend)\r
d9d77995 372 {\r
373 int d_reg=0;\r
374 if (shift) {\r
65044ba9 375 ot(" mov r%d,r%d,asl #%d\n",v,d_reg,shift);\r
376 ot(" mov%s r%d,r%d,asr #%d\n",s,v,v,shift);\r
d9d77995 377 d_reg=v;\r
3504ce94 378 flags_set=1;\r
379 }\r
380 if (d_reg != v) {\r
381 ot(" mov%s r%d,r%d\n",s,v,d_reg);\r
382 flags_set=1;\r
d9d77995 383 }\r
d9d77995 384 }\r
385 else\r
386 {\r
65044ba9 387 if (type == earwt_shifted_up && shift) {\r
3504ce94 388 ot(" mov%s r%d,r0,asl #%d\n",s,v,shift);\r
389 flags_set=1;\r
390 }\r
391 else if (v!=0) {\r
392 ot(" mov%s r%d,r0\n",s,v);\r
393 flags_set=1;\r
394 }\r
d9d77995 395 }\r
6003a768 396\r
3504ce94 397 if (set_nz&&!flags_set)\r
398 ot(" tst r%d,r%d\n",v,v);\r
399\r
6003a768 400 ot("\n"); return 0;\r
401}\r
402\r
d9d77995 403// calculate EA and read\r
404// if (ea < 0x10) nothing is trashed\r
405// if (ea == 0x3c) r2 and r3 are trashed\r
406// else r0-r3 are trashed\r
407// size values 0, 1, 2 ~ byte, word, long\r
408// r_ea is reg to store ea in (-1 means ea is not needed), r is dst reg\r
65044ba9 409int EaCalcRead(int r_ea,int r,int ea,int size,int mask,EaRWType type,int set_nz)\r
d9d77995 410{\r
411 if (ea<0x10)\r
412 {\r
413 if (r_ea==-1)\r
414 {\r
415 r_ea=r;\r
65044ba9 416 if (type == earwt_msb_dont_care) size=2;\r
d9d77995 417 }\r
418 }\r
419 else if (ea==0x3c) // #imm\r
420 {\r
421 r_ea=r;\r
422 }\r
423 else\r
424 {\r
425 if (r_ea==-1) r_ea=0;\r
426 }\r
427\r
65044ba9 428 EaCalc (r_ea,mask,ea,size,type);\r
429 EaRead (r_ea, r,ea,size,mask,type,set_nz);\r
d9d77995 430\r
431 return 0;\r
432}\r
433\r
6003a768 434// Return 1 if we can read this ea\r
435int EaCanRead(int ea,int size)\r
436{\r
437 if (size<0)\r
438 {\r
439 // LEA:\r
440 // These don't make sense?:\r
d9d77995 441 if (ea< 0x10) return 0; // Register\r
6003a768 442 if (ea==0x3c) return 0; // Immediate\r
443 if (ea>=0x18 && ea<0x28) return 0; // Pre/Post inc/dec An\r
444 }\r
445\r
446 if (ea<=0x3c) return 1;\r
447 return 0;\r
448}\r
449\r
450// ---------------------------------------------------------------------------\r
451// Write effective address (ARM Register 'a') with ARM register 'v'\r
d9d77995 452// Trashes r0-r3,r12,lr; 'a' can be 0 or 2+, 'v' can be 1 or higher\r
6003a768 453// If a==0 and v==1 it's faster though.\r
65044ba9 454int EaWrite(int a,int v,int ea,int size,int mask,EaRWType type)\r
6003a768 455{\r
456 char text[32]="";\r
457 int shift=0;\r
458\r
d9d77995 459 if(a == 1) { printf("Error! EaWrite a==1 !\n"); return 1; }\r
460\r
65044ba9 461 if (type == earwt_shifted_up) shift=32-(8<<size);\r
6003a768 462\r
463 DisaPc=2; DisaGetEa(text,ea,size); // Get text version of the effective address\r
464\r
465 if (ea<0x10)\r
466 {\r
d9d77995 467 int lsl=0,low=0,i;\r
65044ba9 468 if (size >= 2 || (size == 0 && type != earwt_sign_extend)) {\r
d9d77995 469 if(mask)\r
470 for (i=mask|0x8000; (i&1)==0; i>>=1) low++; // Find out how high up the EA mask is\r
471 lsl=2-low; // Having a lsl #x here saves one opcode\r
472 }\r
6003a768 473\r
474 ot(";@ EaWrite: r%d into register[r%d]:\n",v,a);\r
ba3db9e7 475 if (shift) ot(" mov r%d,r%d,lsr #%d\n",v,v,shift);\r
6003a768 476\r
d9d77995 477 if (lsl>0) ot(" str%s r%d,[r7,r%d,lsl #%i]\n",Narm[size&3],v,a,lsl);\r
478 else if (lsl<0) ot(" str%s r%d,[r7,r%d,lsr #%i]\n",Narm[size&3],v,a,-lsl);\r
479 else ot(" str%s r%d,[r7,r%d]\n",Narm[size&3],v,a);\r
6003a768 480\r
481 ot("\n"); return 0;\r
482 }\r
483\r
484 ot(";@ EaWrite: Write r%d into '%s' (address in r%d):\n",v,text,a);\r
485\r
486 if (ea==0x3c) { ot("Error! Write EA=0x%x\n\n",ea); return 1; }\r
487\r
ba3db9e7 488 if (shift)\r
489 {\r
490 ot(" mov r1,r%d,lsr #%d\n",v,shift);\r
491 }\r
492 else if (v != 1 || (size < 2 && type != earwt_zero_extend))\r
493 {\r
494 switch (size) {\r
495 case 0:\r
496 ot(" and r1,r%d,#0xff\n",v);\r
497 break;\r
498 case 1:\r
499 if (type != earwt_zero_extend)\r
500 {\r
501 ot(" mov r1,r%d,lsl #16\n",v);\r
502 ot(" mov r1,r1,lsr #16\n");\r
503 break;\r
504 }\r
505 // fallthrough\r
506 case 2:\r
507 default:\r
508 ot(" mov r1,r%d\n",v);\r
509 break;\r
510 }\r
511 }\r
6003a768 512\r
d9d77995 513 MemHandler(1,size,a,eawrite_check_addrerr); // Call write handler\r
514\r
515 // not check by default, because most cases are rmw and\r
516 // address was already checked before reading\r
517 eawrite_check_addrerr = 0;\r
6003a768 518\r
519 ot("\n"); return 0;\r
520}\r
521\r
522// Return 1 if we can write this ea\r
523int EaCanWrite(int ea)\r
524{\r
d9d77995 525 if (ea<=0x39) return 1; // 3b?\r
6003a768 526 return 0;\r
527}\r
528// ---------------------------------------------------------------------------\r
d9d77995 529\r
530// Return 1 if EA is An reg\r
531int EaAn(int ea)\r
532{\r
533 if((ea&0x38)==8) return 1;\r
534 return 0;\r
535}\r
536\r
68000 emulator written in ARM 32-bit assembly