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fix bcd instructions
[cyclone68000.git] / Main.cpp
CommitLineData
6003a768 1\r
619b1824 2// This file is part of the Cyclone 68000 Emulator\r
3\r
d9d77995 4// Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)\r
5// Copyright (c) 2005-2011 Gražvydas "notaz" Ignotas (notasas (at) gmail.com)\r
c41b9b97 6\r
619b1824 7// This code is licensed under the GNU General Public License version 2.0 and the MAME License.\r
8// You can choose the license that has the most advantages for you.\r
9\r
10// SVN repository can be found at http://code.google.com/p/cyclone68000/\r
11\r
d9d77995 12\r
6003a768 13#include "app.h"\r
14\r
15static FILE *AsmFile=NULL;\r
16\r
d9d77995 17static int CycloneVer=0x0099; // Version number of library\r
6003a768 18int *CyJump=NULL; // Jump table\r
d9d77995 19int ms=USE_MS_SYNTAX; // If non-zero, output in Microsoft ARMASM format\r
20const char * const Narm[4]={ "b", "h","",""}; // Normal ARM Extensions for operand sizes 0,1,2\r
21const char * const Sarm[4]={"sb","sh","",""}; // Sign-extend ARM Extensions for operand sizes 0,1,2\r
22int Cycles; // Current cycles for opcode\r
23int pc_dirty; // something changed PC during processing\r
24int arm_op_count;\r
25\r
26// opcodes often used by games\r
27static const unsigned short hot_opcodes[] = {\r
c6237d9e 28 0x6702, // beq $3\r
29 0x6602, // bne $3\r
d9d77995 30 0x51c8, // dbra Dn, $2\r
31 0x4a38, // tst.b $0.w\r
32 0xd040, // add.w Dn, Dn\r
33 0x4a79, // tst.w $0.l\r
34 0x0240, // andi.w #$0, D0\r
35 0x2038, // move.l $0.w, D0\r
36 0xb0b8, // cmp.l $0.w, D0\r
c6237d9e 37 0x6002, // bra $3\r
d9d77995 38 0x30c0, // move.w D0, (A0)+\r
39 0x3028, // move.w ($0,A0), D0\r
40 0x0c40, // cmpi.w #$0, D0\r
41 0x0c79, // cmpi.w #$0, $0.l\r
42 0x4e75, // rts\r
43 0x4e71, // nop\r
44 0x3000, // move.w D0, D0\r
45 0x0839, // btst #$0, $0.l\r
46 0x7000, // moveq #$0, D0\r
47 0x3040, // movea.w D0, A0\r
48 0x0838, // btst #$0, $0.w\r
49 0x4a39, // tst.b $0.l\r
50 0x33d8, // move.w (A0)+, $0.l\r
51 0x6700, // beq $2\r
52 0xb038, // cmp.b $0.w, D0\r
53 0x3039, // move.w $0.l, D0\r
54 0x4840, // swap D0\r
c6237d9e 55 0x6102, // bsr $3\r
d9d77995 56 0x6100, // bsr $2\r
57 0x5e40, // addq.w #7, D0\r
58 0x1039, // move.b $0.l, D0\r
59 0x20c0, // move.l D0, (A0)+\r
60 0x1018, // move.b (A0)+, D0\r
61 0x30d0, // move.w (A0), (A0)+\r
62 0x3080, // move.w D0, (A0)\r
63 0x3018, // move.w (A0)+, D0\r
64 0xc040, // and.w D0, D0\r
65 0x3180, // move.w D0, (A0,D0.w)\r
66 0x1198, // move.b (A0)+, (A0,D0.w)\r
c6237d9e 67 0x6502, // bcs $3\r
d9d77995 68 0x6500, // bcs $2\r
c6237d9e 69 0x6402, // bcc $3\r
70 0x6a02, // bpl $3\r
d9d77995 71 0x41f0, // lea (A0,D0.w), A0\r
72 0x4a28, // tst.b ($0,A0)\r
73 0x0828, // btst #$0, ($0,A0)\r
74 0x0640, // addi.w #$0, D0\r
75 0x10c0, // move.b D0, (A0)+\r
76 0x10d8, // move.b (A0)+, (A0)+\r
77};\r
78#define hot_opcode_count (int)(sizeof(hot_opcodes) / sizeof(hot_opcodes[0]))\r
79\r
80static int is_op_hot(int op)\r
81{\r
82 int i;\r
83 for (i = 0; i < hot_opcode_count; i++)\r
84 if (op == hot_opcodes[i])\r
85 return 1;\r
86 return 0;\r
87}\r
6003a768 88\r
c30e2e2d 89void ot(const char *format, ...)\r
6003a768 90{\r
c30e2e2d 91 va_list valist;\r
d9d77995 92 int i, len;\r
93\r
94 // notaz: stop me from leaving newlines in the middle of format string\r
95 // and generating bad code\r
96 for(i=0, len=strlen(format); i < len && format[i] != '\n'; i++);\r
97 if(i < len-1 && format[len-1] != '\n') printf("\nWARNING: possible improper newline placement:\n%s\n", format);\r
98\r
99 if (format[0] == ' ' && format[1] == ' ' && format[2] != ' ' && format[2] != '.')\r
100 arm_op_count++;\r
101\r
6003a768 102 va_start(valist,format);\r
103 if (AsmFile) vfprintf(AsmFile,format,valist);\r
104 va_end(valist);\r
105}\r
106\r
107void ltorg()\r
108{\r
109 if (ms) ot(" LTORG\n");\r
110 else ot(" .ltorg\n");\r
111}\r
112\r
d9d77995 113#if (CYCLONE_FOR_GENESIS == 2)\r
66dda842 114static const char *tas_ops[] = {\r
115 "Op4ad0", "Op4ad8", "Op4adf",\r
116 "Op4ae0", "Op4ae7", "Op4ae8",\r
117 "Op4af0", "Op4af8", "Op4af9",\r
118};\r
119\r
120// get handler address in r0, OT (offset table) in r2\r
121static void ChangeTASGet(unsigned int i)\r
6003a768 122{\r
66dda842 123 if (i >= sizeof(tas_ops) / sizeof(tas_ops[0]))\r
124 abort();\r
125 ot(" ldr r0,[r2,#%d*4] ;@ %s\n",i,tas_ops[i]);\r
126 ot(" add r0,r0,r2\n");\r
6003a768 127}\r
d9d77995 128#endif\r
6003a768 129\r
66dda842 130static void LoadCycloneJumpTab(int reg, int tmp)\r
131{\r
132 ot(" adr r%d,CycloneOT_JT\n", tmp);\r
133 ot(" ldr r%d,[r%d] ;@ CycloneJumpTab-CycloneOT_JT\n", reg, tmp);\r
134 ot(" add r%d,r%d,r%d ;@ =CycloneJumpTab\n", reg, reg, tmp);\r
135}\r
136\r
d9d77995 137#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
138static void AddressErrorWrapper(char rw, const char *dataprg, int iw)\r
6003a768 139{\r
d9d77995 140 ot("ExceptionAddressError_%c_%s%s\n", rw, dataprg, ms?"":":");\r
141 ot(" ldr r1,[r7,#0x44]\n");\r
142 ot(" mov r6,#0x%02x\n", iw);\r
143 ot(" mov r11,r0\n");\r
144 ot(" tst r1,#0x20\n");\r
145 ot(" orrne r6,r6,#4\n");\r
146 ot(" b ExceptionAddressError\n");\r
6003a768 147 ot("\n");\r
148}\r
d9d77995 149#endif\r
150\r
355815eb 151void FlushPC(int force)\r
d9d77995 152{\r
153#if MEMHANDLERS_NEED_PC\r
355815eb 154 force |= pc_dirty;\r
d9d77995 155 pc_dirty = 0;\r
355815eb 156#endif\r
157 if (force)\r
158 ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
d9d77995 159}\r
6003a768 160\r
161static void PrintFramework()\r
162{\r
d9d77995 163 int state_flags_to_check = 1; // stopped\r
164#if EMULATE_TRACE\r
165 state_flags_to_check |= 2; // tracing\r
166#endif\r
167#if EMULATE_HALT\r
168 state_flags_to_check |= 0x10; // halted\r
169#endif\r
170\r
6003a768 171 ot(";@ --------------------------- Framework --------------------------\n");\r
172 if (ms) ot("CycloneRun\n");\r
173 else ot("CycloneRun:\n");\r
174\r
d9d77995 175 ot(" stmdb sp!,{r4-r8,r10,r11,lr}\n");\r
6003a768 176\r
177 ot(" mov r7,r0 ;@ r7 = Pointer to Cpu Context\n");\r
178 ot(" ;@ r0-3 = Temporary registers\n");\r
d9d77995 179 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Flags (NZCV)\n");\r
66dda842 180 ot(" ldr r6,[r7,#0x54] ;@ r6 = Opcode Jump table (from reset)\n");\r
6003a768 181 ot(" ldr r5,[r7,#0x5c] ;@ r5 = Cycles\n");\r
182 ot(" ldr r4,[r7,#0x40] ;@ r4 = Current PC + Memory Base\n");\r
183 ot(" ;@ r8 = Current Opcode\n");\r
d9d77995 184 ot(" ldr r1,[r7,#0x44] ;@ Get SR high T_S__III and irq level\n");\r
185 ot(" mov r10,r10,lsl #28;@ r10 = Flags 0xf0000000, cpsr format\n");\r
186 ot(" ;@ r11 = Source value / Memory Base\n");\r
d9d77995 187 ot("\n");\r
188#if (CYCLONE_FOR_GENESIS == 2) || EMULATE_TRACE\r
189 ot(" mov r2,#0\n");\r
190 ot(" str r2,[r7,#0x98] ;@ clear custom CycloneEnd\n");\r
191#endif\r
192 ot(";@ CheckInterrupt:\n");\r
193 ot(" movs r0,r1,lsr #24 ;@ Get IRQ level\n"); // same as ldrb r0,[r7,#0x47]\r
194 ot(" beq NoInts0\n");\r
195 ot(" cmp r0,#6 ;@ irq>6 ?\n");\r
196 ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");\r
197 ot(" cmple r0,r1 ;@ irq<=6: Is irq<=mask ?\n");\r
198 ot(" bgt CycloneDoInterrupt\n");\r
199 ot("NoInts0%s\n", ms?"":":");\r
200 ot("\n");\r
201 ot(";@ Check if our processor is in special state\n");\r
202 ot(";@ and jump to opcode handler if not\n");\r
203 ot(" ldr r0,[r7,#0x58] ;@ state_flags\n");\r
204 ot(" ldrh r8,[r4],#2 ;@ Fetch first opcode\n");\r
205 ot(" tst r0,#0x%02x ;@ special state?\n", state_flags_to_check);\r
206 ot(" ldreq pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
207 ot("\n");\r
208 ot("CycloneSpecial%s\n", ms?"":":");\r
209#if EMULATE_TRACE\r
210 ot(" tst r0,#2 ;@ tracing?\n");\r
211 ot(" bne CycloneDoTrace\n");\r
212#endif\r
213 ot(";@ stopped or halted\n");\r
214 ot(" mov r5,#0\n");\r
215 ot(" str r5,[r7,#0x5C] ;@ eat all cycles\n");\r
216 ot(" ldmia sp!,{r4-r8,r10,r11,pc} ;@ we are stopped, do nothing!\n");\r
6003a768 217 ot("\n");\r
6003a768 218 ot("\n");\r
219\r
220 ot(";@ We come back here after execution\n");\r
221 ot("CycloneEnd%s\n", ms?"":":");\r
222 ot(" sub r4,r4,#2\n");\r
223 ot("CycloneEndNoBack%s\n", ms?"":":");\r
d9d77995 224#if (CYCLONE_FOR_GENESIS == 2) || EMULATE_TRACE\r
225 ot(" ldr r1,[r7,#0x98]\n");\r
226 ot(" mov r10,r10,lsr #28\n");\r
227 ot(" tst r1,r1\n");\r
228 ot(" bxne r1 ;@ jump to alternative CycloneEnd\n");\r
229#else\r
230 ot(" mov r10,r10,lsr #28\n");\r
231#endif\r
6003a768 232 ot(" str r4,[r7,#0x40] ;@ Save Current PC + Memory Base\n");\r
233 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
d9d77995 234 ot(" strb r10,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
235 ot(" ldmia sp!,{r4-r8,r10,r11,pc}\n");\r
236 ltorg();\r
6003a768 237 ot("\n");\r
6003a768 238 ot("\n");\r
d9d77995 239\r
240 ot("CycloneInit%s\n", ms?"":":");\r
241#if COMPRESS_JUMPTABLE\r
242 ot(";@ decompress jump table\n");\r
66dda842 243 LoadCycloneJumpTab(12, 1);\r
d9d77995 244 ot(" add r0,r12,#0xe000*4 ;@ ctrl code pointer\n");\r
245 ot(" ldr r1,[r0,#-4]\n");\r
246 ot(" tst r1,r1\n");\r
247 ot(" movne pc,lr ;@ already uncompressed\n");\r
248 ot(" add r3,r12,#0xa000*4 ;@ handler table pointer, r12=dest\n");\r
249 ot("unc_loop%s\n", ms?"":":");\r
250 ot(" ldrh r1,[r0],#2\n");\r
251 ot(" and r2,r1,#0xf\n");\r
252 ot(" bic r1,r1,#0xf\n");\r
253 ot(" ldr r1,[r3,r1,lsr #2] ;@ r1=handler\n");\r
254 ot(" cmp r2,#0xf\n");\r
255 ot(" addeq r2,r2,#1 ;@ 0xf is really 0x10\n");\r
256 ot(" tst r2,r2\n");\r
257 ot(" ldreqh r2,[r0],#2 ;@ counter is in next word\n");\r
258 ot(" tst r2,r2\n");\r
259 ot(" beq unc_finish ;@ done decompressing\n");\r
260 ot(" tst r1,r1\n");\r
261 ot(" addeq r12,r12,r2,lsl #2 ;@ 0 handler means we should skip those bytes\n");\r
262 ot(" beq unc_loop\n");\r
263 ot("unc_loop_in%s\n", ms?"":":");\r
264 ot(" subs r2,r2,#1\n");\r
265 ot(" str r1,[r12],#4\n");\r
266 ot(" bgt unc_loop_in\n");\r
267 ot(" b unc_loop\n");\r
268 ot("unc_finish%s\n", ms?"":":");\r
66dda842 269 LoadCycloneJumpTab(12, 1);\r
d9d77995 270 ot(" ;@ set a-line and f-line handlers\n");\r
271 ot(" add r0,r12,#0xa000*4\n");\r
272 ot(" ldr r1,[r0,#4] ;@ a-line handler\n");\r
273 ot(" ldr r3,[r0,#8] ;@ f-line handler\n");\r
274 ot(" mov r2,#0x1000\n");\r
275 ot("unc_fill3%s\n", ms?"":":");\r
276 ot(" subs r2,r2,#1\n");\r
277 ot(" str r1,[r0],#4\n");\r
278 ot(" bgt unc_fill3\n");\r
279 ot(" add r0,r12,#0xf000*4\n");\r
280 ot(" mov r2,#0x1000\n");\r
281 ot("unc_fill4%s\n", ms?"":":");\r
282 ot(" subs r2,r2,#1\n");\r
283 ot(" str r3,[r0],#4\n");\r
284 ot(" bgt unc_fill4\n");\r
285 ot(" bx lr\n");\r
286 ltorg();\r
287#else\r
590d780f 288 ot(";@ fix final jumptable entries\n");\r
66dda842 289 LoadCycloneJumpTab(12, 0);\r
590d780f 290 ot(" add r12,r12,#0x10000*4\n");\r
291 ot(" ldr r0,[r12,#-3*4]\n");\r
292 ot(" str r0,[r12,#-2*4]\n");\r
293 ot(" str r0,[r12,#-1*4]\n");\r
d9d77995 294 ot(" bx lr\n");\r
295#endif\r
6003a768 296 ot("\n");\r
d9d77995 297\r
298 // --------------\r
299 ot("CycloneReset%s\n", ms?"":":");\r
300 ot(" stmfd sp!,{r7,lr}\n");\r
66dda842 301 LoadCycloneJumpTab(12, 1);\r
d9d77995 302 ot(" mov r7,r0\n");\r
66dda842 303 ot(" str r12,[r7,#0x54] ;@ save CycloneJumpTab avoid literal pools\n");\r
d9d77995 304 ot(" mov r0,#0\n");\r
305 ot(" str r0,[r7,#0x58] ;@ state_flags\n");\r
306 ot(" str r0,[r7,#0x48] ;@ OSP\n");\r
307 ot(" mov r1,#0x27 ;@ Supervisor mode\n");\r
308 ot(" strb r1,[r7,#0x44] ;@ set SR high\n");\r
309 ot(" strb r0,[r7,#0x47] ;@ IRQ\n");\r
6003a768 310 MemHandler(0,2);\r
d9d77995 311 ot(" str r0,[r7,#0x3c] ;@ Stack pointer\n");\r
312 ot(" mov r0,#0\n");\r
313 ot(" str r0,[r7,#0x60] ;@ Membase\n");\r
314 ot(" mov r0,#4\n");\r
315 MemHandler(0,2);\r
316#ifdef MEMHANDLERS_DIRECT_PREFIX\r
317 ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);\r
318#else\r
6003a768 319 ot(" mov lr,pc\n");\r
320 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
d9d77995 321#endif\r
322 ot(" str r0,[r7,#0x40] ;@ PC + base\n");\r
323 ot(" ldmfd sp!,{r7,pc}\n");\r
324 ot("\n");\r
325\r
66dda842 326 // --------------\r
327 ot("CycloneSetRealTAS%s\n", ms?"":":");\r
328#if (CYCLONE_FOR_GENESIS == 2)\r
329 LoadCycloneJumpTab(12, 1);\r
330 ot(" tst r0,r0\n");\r
331 ot(" add r12,r12,#0x4a00*4\n");\r
332 ot(" add r12,r12,#0x00d0*4\n");\r
333 ot(" adr r2,CycloneOT_TAS_\n");\r
334 ot(" addeq r2,r2,#%lu*4\n", sizeof(tas_ops) / sizeof(tas_ops[0]));\r
335\r
336 ChangeTASGet(0);\r
337 ot(" mov r1,#8\n");\r
338 ot("setrtas_loop0%s ;@ 4ad0-4ad7\n",ms?"":":");\r
339 ot(" subs r1,r1,#1\n");\r
340 ot(" str r0,[r12],#4\n");\r
341 ot(" bne setrtas_loop0\n");\r
342\r
343 ChangeTASGet(1);\r
344 ot(" mov r1,#7\n");\r
345 ot("setrtas_loop1%s ;@ 4ad8-4ade\n",ms?"":":");\r
346 ot(" subs r1,r1,#1\n");\r
347 ot(" str r0,[r12],#4\n");\r
348 ot(" bne setrtas_loop1\n");\r
349\r
350 ChangeTASGet(2);\r
351 ot(" str r0,[r12],#4\n");\r
352 ChangeTASGet(3);\r
353 ot(" mov r1,#7\n");\r
354 ot("setrtas_loop2%s ;@ 4ae0-4ae6\n",ms?"":":");\r
355 ot(" subs r1,r1,#1\n");\r
356 ot(" str r0,[r12],#4\n");\r
357 ot(" bne setrtas_loop2\n");\r
358\r
359 ChangeTASGet(4);\r
360 ot(" str r0,[r12],#4\n");\r
361 ChangeTASGet(5);\r
362 ot(" mov r1,#8\n");\r
363 ot("setrtas_loop3%s ;@ 4ae8-4aef\n",ms?"":":");\r
364 ot(" subs r1,r1,#1\n");\r
365 ot(" str r0,[r12],#4\n");\r
366 ot(" bne setrtas_loop3\n");\r
367\r
368 ChangeTASGet(6);\r
369 ot(" mov r1,#8\n");\r
370 ot("setrtas_loop4%s ;@ 4af0-4af7\n",ms?"":":");\r
371 ot(" subs r1,r1,#1\n");\r
372 ot(" str r0,[r12],#4\n");\r
373 ot(" bne setrtas_loop4\n");\r
374\r
375 ChangeTASGet(7);\r
376 ot(" str r0,[r12],#4\n");\r
377 ChangeTASGet(8);\r
378 ot(" str r0,[r12],#4\n");\r
379#endif\r
380 ot(" bx lr\n");\r
381 ot("\n");\r
382\r
383 // --------------\r
384 // offset table to avoid .text relocations (forbidden by Android and iOS)\r
385 ot("CycloneOT_JT%s\n", ms?"":":");\r
386 ot(" %s %s-CycloneOT_JT\n", ms?"dcd":".long", "CycloneJumpTab");\r
387#if (CYCLONE_FOR_GENESIS == 2)\r
388 ot("CycloneOT_TAS_%s\n", ms?"":":"); // working TAS (no MD bug)\r
389 for (size_t i = 0; i < sizeof(tas_ops) / sizeof(tas_ops[0]); i++)\r
390 ot(" %s %s_-CycloneOT_TAS_\n", ms?"dcd":".long", tas_ops[i]);\r
391 ot("CycloneOT_TAS%s\n", ms?"":":"); // broken TAS\r
392 for (size_t i = 0; i < sizeof(tas_ops) / sizeof(tas_ops[0]); i++)\r
393 ot(" %s %s-CycloneOT_TAS\n", ms?"dcd":".long", tas_ops[i]);\r
394 ot("\n");\r
395#endif\r
396\r
d9d77995 397 // --------------\r
398 // 68k: XNZVC, ARM: NZCV\r
399 ot("CycloneSetSr%s\n", ms?"":":");\r
400 ot(" mov r2,r1,lsr #8\n");\r
401// ot(" ldrb r3,[r0,#0x44] ;@ get SR high\n");\r
402// ot(" eor r3,r3,r2\n");\r
403// ot(" tst r3,#0x20\n");\r
404#if EMULATE_TRACE\r
405 ot(" and r2,r2,#0xa7 ;@ only defined bits\n");\r
406#else\r
407 ot(" and r2,r2,#0x27 ;@ only defined bits\n");\r
408#endif\r
409 ot(" strb r2,[r0,#0x44] ;@ set SR high\n");\r
410 ot(" mov r2,r1,lsl #25\n");\r
411 ot(" str r2,[r0,#0x4c] ;@ the X flag\n");\r
412 ot(" bic r2,r1,#0xf3\n");\r
413 ot(" tst r1,#1\n");\r
414 ot(" orrne r2,r2,#2\n");\r
415 ot(" tst r1,#2\n");\r
416 ot(" orrne r2,r2,#1\n");\r
417 ot(" strb r2,[r0,#0x46] ;@ flags\n");\r
418 ot(" bx lr\n");\r
419 ot("\n");\r
420\r
421 // --------------\r
422 ot("CycloneGetSr%s\n", ms?"":":");\r
423 ot(" ldrb r1,[r0,#0x46] ;@ flags\n");\r
424 ot(" bic r2,r1,#0xf3\n");\r
425 ot(" tst r1,#1\n");\r
426 ot(" orrne r2,r2,#2\n");\r
427 ot(" tst r1,#2\n");\r
428 ot(" orrne r2,r2,#1\n");\r
429 ot(" ldr r1,[r0,#0x4c] ;@ the X flag\n");\r
430 ot(" tst r1,#0x20000000\n");\r
431 ot(" orrne r2,r2,#0x10\n");\r
432 ot(" ldrb r1,[r0,#0x44] ;@ the SR high\n");\r
433 ot(" orr r0,r2,r1,lsl #8\n");\r
434 ot(" bx lr\n");\r
435 ot("\n");\r
436\r
437 // --------------\r
438 ot("CyclonePack%s\n", ms?"":":");\r
439 ot(" stmfd sp!,{r4,r5,lr}\n");\r
6003a768 440 ot(" mov r4,r0\n");\r
d9d77995 441 ot(" mov r5,r1\n");\r
442 ot(" mov r3,#16\n");\r
443 ot(";@ 0x00-0x3f: DA registers\n");\r
444 ot("c_pack_loop%s\n",ms?"":":");\r
445 ot(" ldr r1,[r0],#4\n");\r
446 ot(" subs r3,r3,#1\n");\r
447 ot(" str r1,[r5],#4\n");\r
448 ot(" bne c_pack_loop\n");\r
449 ot(";@ 0x40: PC\n");\r
450 ot(" ldr r0,[r4,#0x40] ;@ PC + Memory Base\n");\r
451 ot(" ldr r1,[r4,#0x60] ;@ Memory base\n");\r
452 ot(" sub r0,r0,r1\n");\r
453 ot(" str r0,[r5],#4\n");\r
454 ot(";@ 0x44: SR\n");\r
455 ot(" mov r0,r4\n");\r
456 ot(" bl CycloneGetSr\n");\r
457 ot(" strh r0,[r5],#2\n");\r
458 ot(";@ 0x46: IRQ level\n");\r
459 ot(" ldrb r0,[r4,#0x47]\n");\r
460 ot(" strb r0,[r5],#2\n");\r
461 ot(";@ 0x48: other SP\n");\r
462 ot(" ldr r0,[r4,#0x48]\n");\r
463 ot(" str r0,[r5],#4\n");\r
464 ot(";@ 0x4c: CPU state flags\n");\r
465 ot(" ldr r0,[r4,#0x58]\n");\r
466 ot(" str r0,[r5],#4\n");\r
467 ot(" ldmfd sp!,{r4,r5,pc}\n");\r
468 ot("\n");\r
469\r
470 // --------------\r
471 ot("CycloneUnpack%s\n", ms?"":":");\r
472 ot(" stmfd sp!,{r5,r7,lr}\n");\r
473 ot(" mov r7,r0\n");\r
474 ot(" movs r5,r1\n");\r
475 ot(" beq c_unpack_do_pc\n");\r
476 ot(" mov r3,#16\n");\r
477 ot(";@ 0x00-0x3f: DA registers\n");\r
478 ot("c_unpack_loop%s\n",ms?"":":");\r
479 ot(" ldr r1,[r5],#4\n");\r
480 ot(" subs r3,r3,#1\n");\r
481 ot(" str r1,[r0],#4\n");\r
482 ot(" bne c_unpack_loop\n");\r
483 ot(";@ 0x40: PC\n");\r
484 ot(" ldr r0,[r5],#4 ;@ PC\n");\r
485 ot(" str r0,[r7,#0x40] ;@ handle later\n");\r
486 ot(";@ 0x44: SR\n");\r
487 ot(" ldrh r1,[r5],#2\n");\r
488 ot(" mov r0,r7\n");\r
489 ot(" bl CycloneSetSr\n");\r
490 ot(";@ 0x46: IRQ level\n");\r
491 ot(" ldrb r0,[r5],#2\n");\r
492 ot(" strb r0,[r7,#0x47]\n");\r
493 ot(";@ 0x48: other SP\n");\r
494 ot(" ldr r0,[r5],#4\n");\r
495 ot(" str r0,[r7,#0x48]\n");\r
496 ot(";@ 0x4c: CPU state flags\n");\r
497 ot(" ldr r0,[r5],#4\n");\r
498 ot(" str r0,[r7,#0x58]\n");\r
499 ot("c_unpack_do_pc%s\n",ms?"":":");\r
500 ot(" ldr r0,[r7,#0x40] ;@ unbased PC\n");\r
501#if USE_CHECKPC_CALLBACK\r
502 ot(" mov r1,#0\n");\r
503 ot(" str r1,[r7,#0x60] ;@ Memory base\n");\r
504 #ifdef MEMHANDLERS_DIRECT_PREFIX\r
505 ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);\r
506 #else\r
507 ot(" mov lr,pc\n");\r
508 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
509 #endif\r
510#else\r
511 ot(" ldr r1,[r7,#0x60] ;@ Memory base\n");\r
512 ot(" add r0,r0,r1 ;@ r0 = Memory Base + New PC\n");\r
513#endif\r
514 ot(" str r0,[r7,#0x40] ;@ PC + Memory Base\n");\r
515 ot(" ldmfd sp!,{r5,r7,pc}\n");\r
516 ot("\n");\r
517\r
518 // --------------\r
519 ot("CycloneFlushIrq%s\n", ms?"":":");\r
520 ot(" ldr r1,[r0,#0x44] ;@ Get SR high T_S__III and irq level\n");\r
521 ot(" mov r2,r1,lsr #24 ;@ Get IRQ level\n"); // same as ldrb r0,[r7,#0x47]\r
522 ot(" cmp r2,#6 ;@ irq>6 ?\n");\r
523 ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");\r
524 ot(" cmple r2,r1 ;@ irq<=6: Is irq<=mask ?\n");\r
525 ot(" movle r0,#0\n");\r
526 ot(" bxle lr ;@ no ints\n");\r
527 ot("\n");\r
528 ot(" stmdb sp!,{r4,r5,r7,r8,r10,r11,lr}\n");\r
529 ot(" mov r7,r0\n");\r
530 ot(" mov r0,r2\n");\r
531 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Flags (NZCV)\n");\r
532 ot(" mov r5,#0\n");\r
533 ot(" ldr r4,[r7,#0x40] ;@ r4 = Current PC + Memory Base\n");\r
534 ot(" mov r10,r10,lsl #28 ;@ r10 = Flags 0xf0000000, cpsr format\n");\r
535 ot(" adr r2,CycloneFlushIrqEnd\n");\r
536 ot(" str r2,[r7,#0x98] ;@ set custom CycloneEnd\n");\r
537 ot(" b CycloneDoInterrupt\n");\r
538 ot("\n");\r
539 ot("CycloneFlushIrqEnd%s\n", ms?"":":");\r
540 ot(" rsb r0,r5,#0\n");\r
541 ot(" str r4,[r7,#0x40] ;@ Save Current PC + Memory Base\n");\r
542 ot(" strb r10,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
543 ot(" ldmia sp!,{r4,r5,r7,r8,r10,r11,lr}\n");\r
544 ot(" bx lr\n");\r
545 ot("\n");\r
546 ot("\n");\r
547\r
d9d77995 548 // --------------\r
549 ot(";@ DoInterrupt - r0=IRQ level\n");\r
550 ot("CycloneDoInterruptGoBack%s\n", ms?"":":");\r
551 ot(" sub r4,r4,#2\n");\r
552 ot("CycloneDoInterrupt%s\n", ms?"":":");\r
553 ot(" bic r8,r8,#0xff000000\n");\r
554 ot(" orr r8,r8,r0,lsl #29 ;@ abuse r8\n");\r
555\r
556 // Steps are from "M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL", p. 6-4\r
557 // but their order is based on http://pasti.fxatari.com/68kdocs/68kPrefetch.html\r
558 // 1. Make a temporary copy of the status register and set the status register for exception processing.\r
559 ot(" ldr r2,[r7,#0x58] ;@ state flags\n");\r
560 ot(" and r0,r0,#7\n");\r
561 ot(" orr r3,r0,#0x20 ;@ Supervisor mode + IRQ level\n");\r
562 ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");\r
563#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
564 ot(" orr r2,r2,#4 ;@ set activity bit: 'not processing instruction'\n");\r
565#endif\r
566 ot(" str r2,[r7,#0x58]\n");\r
567 ot(" ldrb r6,[r7,#0x44] ;@ Get old SR high, abuse r6\n");\r
568 ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");\r
6003a768 569 ot("\n");\r
d9d77995 570\r
571 // 3. Save the current processor context.\r
572 ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");\r
573 ot(" ldr r11,[r7,#0x3c] ;@ Get A7\n");\r
574 ot(" tst r6,#0x20\n");\r
575 ot(";@ get our SP:\n");\r
576 ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");\r
577 ot(" streq r11,[r7,#0x48]\n");\r
578 ot(" moveq r11,r2\n");\r
579 ot(";@ Push old PC onto stack\n");\r
580 ot(" sub r0,r11,#4 ;@ Predecremented A7\n");\r
581 ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");\r
582 MemHandler(1,2);\r
583 ot(";@ Push old SR:\n");\r
584 ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");\r
585 ot(" mov r1,r10,lsr #28 ;@ ____NZCV\n");\r
586 ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");\r
587 ot(" tst r2,#1 ;@ 1 if C!=V\n");\r
588 ot(" eorne r1,r1,#3 ;@ ____NZVC\n");\r
589 ot(" and r0,r0,#0x20000000\n");\r
590 ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");\r
591 ot(" orr r1,r1,r6,lsl #8 ;@ Include old SR high\n");\r
592 ot(" sub r0,r11,#6 ;@ Predecrement A7\n");\r
593 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
594 MemHandler(1,1,0,0); // already checked for address error by prev MemHandler\r
6003a768 595 ot("\n");\r
d9d77995 596\r
597 // 2. Obtain the exception vector.\r
598 ot(" mov r11,r8,lsr #29\n");\r
599 ot(" mov r0,r11\n");\r
600#if USE_INT_ACK_CALLBACK\r
601 ot(";@ call IrqCallback if it is defined\n");\r
602#if INT_ACK_NEEDS_STUFF\r
603 ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
604 ot(" mov r1,r10,lsr #28\n");\r
605 ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
606 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
607#endif\r
608 ot(" ldr r3,[r7,#0x8c] ;@ IrqCallback\n");\r
609 ot(" add lr,pc,#4*3\n");\r
610 ot(" tst r3,r3\n");\r
611 ot(" streqb r3,[r7,#0x47] ;@ just clear IRQ if there is no callback\n");\r
612 ot(" mvneq r0,#0 ;@ and simulate -1 return\n");\r
613 ot(" bxne r3\n");\r
614#if INT_ACK_CHANGES_CYCLES\r
615 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
616#endif\r
617 ot(";@ get IRQ vector address:\n");\r
618 ot(" cmn r0,#1 ;@ returned -1?\n");\r
619 ot(" addeq r0,r11,#0x18 ;@ use autovector then\n");\r
620 ot(" cmn r0,#2 ;@ returned -2?\n"); // should be safe as above add should never result in -2\r
621 ot(" moveq r0,#0x18 ;@ use spurious interrupt then\n");\r
622#else // !USE_INT_ACK_CALLBACK\r
6003a768 623 ot(";@ Clear irq:\n");\r
d9d77995 624 ot(" mov r2,#0\n");\r
625 ot(" strb r2,[r7,#0x47]\n");\r
626 ot(" add r0,r0,#0x18 ;@ use autovector\n");\r
627#endif\r
628 ot(" mov r0,r0,lsl #2 ;@ get vector address\n");\r
629 ot("\n");\r
630 ot(" ldr r11,[r7,#0x60] ;@ Get Memory base\n");\r
631 ot(";@ Read IRQ Vector:\n");\r
632 MemHandler(0,2,0,0);\r
633 ot(" tst r0,r0 ;@ uninitialized int vector?\n");\r
634 ot(" moveq r0,#0x3c\n");\r
635 #ifdef MEMHANDLERS_DIRECT_PREFIX\r
636 ot(" bleq %sread32 ;@ Call read32(r0) handler\n", MEMHANDLERS_DIRECT_PREFIX);\r
637 #else\r
638 ot(" moveq lr,pc\n");\r
639 ot(" ldreq pc,[r7,#0x70] ;@ Call read32(r0) handler\n");\r
640 #endif\r
641#if USE_CHECKPC_CALLBACK\r
642 ot(" add lr,pc,#4\n");\r
643 ot(" add r0,r0,r11 ;@ r0 = Memory Base + New PC\n");\r
644 #ifdef MEMHANDLERS_DIRECT_PREFIX\r
645 ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);\r
646 #else\r
647 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
648 #endif\r
649 #if EMULATE_ADDRESS_ERRORS_JUMP\r
650 ot(" mov r4,r0\n");\r
651 #else\r
652 ot(" bic r4,r0,#1\n");\r
653 #endif\r
654#else\r
655 ot(" add r4,r0,r11 ;@ r4 = Memory Base + New PC\n");\r
656 #if EMULATE_ADDRESS_ERRORS_JUMP\r
657 ot(" bic r4,r4,#1\n");\r
658 #endif\r
659#endif\r
6003a768 660 ot("\n");\r
661\r
d9d77995 662 // 4. Obtain a new context and resume instruction processing.\r
663 // note: the obtain part was already done in previous steps\r
664#if EMULATE_ADDRESS_ERRORS_JUMP\r
665 ot(" tst r4,#1\n");\r
666 ot(" bne ExceptionAddressError_r_prg_r4\n");\r
667#endif\r
668 ot(" ldr r6,[r7,#0x54]\n");\r
669 ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
670 ot(" subs r5,r5,#44 ;@ Subtract cycles\n");\r
c204973a 671 ot(" ldrgt pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
d9d77995 672 ot(" b CycloneEnd\n");\r
6003a768 673 ot("\n");\r
d9d77995 674\r
675 // --------------\r
676 // trashes all temp regs\r
677 ot("Exception%s\n", ms?"":":");\r
678 ot(" ;@ Cause an Exception - Vector number in r0\n");\r
6003a768 679 ot(" mov r11,lr ;@ Preserve ARM return address\n");\r
d9d77995 680 ot(" bic r8,r8,#0xff000000\n");\r
681 ot(" orr r8,r8,r0,lsl #24 ;@ abuse r8\n");\r
682\r
683 // 1. Make a temporary copy of the status register and set the status register for exception processing.\r
684 ot(" ldr r6,[r7,#0x44] ;@ Get old SR high, abuse r6\n");\r
685 ot(" ldr r2,[r7,#0x58] ;@ state flags\n");\r
686 ot(" and r3,r6,#0x27 ;@ clear trace and unused flags\n");\r
687 ot(" orr r3,r3,#0x20 ;@ set supervisor mode\n");\r
688 ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");\r
689 ot(" str r2,[r7,#0x58]\n");\r
690 ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");\r
691 ot("\n");\r
692\r
693 // 3. Save the current processor context.\r
694 ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");\r
695 ot(" tst r6,#0x20\n");\r
696 ot(";@ get our SP:\n");\r
697 ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");\r
698 ot(" streq r0,[r7,#0x48]\n");\r
699 ot(" moveq r0,r2\n");\r
700 ot(";@ Push old PC onto stack\n");\r
701 ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");\r
702 ot(" sub r0,r0,#4 ;@ Predecremented A7\n");\r
703 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
704 ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");\r
705 MemHandler(1,2);\r
706 ot(";@ Push old SR:\n");\r
707 ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");\r
708 ot(" mov r1,r10,lsr #28 ;@ ____NZCV\n");\r
709 ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");\r
710 ot(" tst r2,#1 ;@ 1 if C!=V\n");\r
711 ot(" eorne r1,r1,#3 ;@ ____NZVC\n");\r
712 ot(" and r0,r0,#0x20000000\n");\r
713 ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");\r
714 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
715 ot(" orr r1,r1,r6,lsl #8 ;@ Include SR high\n");\r
716 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
717 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
718 MemHandler(1,1,0,0);\r
719 ot("\n");\r
720\r
721 // 2. Obtain the exception vector\r
722 ot(";@ Read Exception Vector:\n");\r
723 ot(" mov r0,r8,lsr #24\n");\r
724 ot(" mov r0,r0,lsl #2\n");\r
725 MemHandler(0,2,0,0);\r
726 ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");\r
727#if USE_CHECKPC_CALLBACK\r
728 ot(" add lr,pc,#4\n");\r
729 ot(" add r0,r0,r3 ;@ r0 = Memory Base + New PC\n");\r
730 #ifdef MEMHANDLERS_DIRECT_PREFIX\r
731 ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);\r
732 #else\r
733 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
734 #endif\r
735 #if EMULATE_ADDRESS_ERRORS_JUMP\r
736 ot(" mov r4,r0\n");\r
737 #else\r
738 ot(" bic r4,r0,#1\n");\r
739 #endif\r
740#else\r
741 ot(" add r4,r0,r3 ;@ r4 = Memory Base + New PC\n");\r
742 #if EMULATE_ADDRESS_ERRORS_JUMP\r
743 ot(" bic r4,r4,#1\n");\r
744 #endif\r
745#endif\r
6003a768 746 ot("\n");\r
d9d77995 747\r
748 // 4. Resume execution.\r
749#if EMULATE_ADDRESS_ERRORS_JUMP\r
750 ot(" tst r4,#1\n");\r
751 ot(" bne ExceptionAddressError_r_prg_r4\n");\r
752#endif\r
753 ot(" ldr r6,[r7,#0x54]\n");\r
754 ot(" bx r11 ;@ Return\n");\r
755 ot("\n");\r
756\r
757 // --------------\r
758#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
759 // first some wrappers: I see no point inlining this code,\r
760 // as it will be executed in really rare cases.\r
761 AddressErrorWrapper('r', "data", 0x11);\r
762 AddressErrorWrapper('r', "prg", 0x12);\r
763 AddressErrorWrapper('w', "data", 0x01);\r
764 // there are no program writes\r
765 // cpu space is only for bus errors?\r
766 ot("ExceptionAddressError_r_prg_r4%s\n", ms?"":":");\r
767 ot(" ldr r1,[r7,#0x44]\n");\r
768 ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");\r
769 ot(" mov r6,#0x12\n");\r
770 ot(" sub r11,r4,r3\n");\r
771 ot(" tst r1,#0x20\n");\r
772 ot(" orrne r6,r6,#4\n");\r
773 ot("\n");\r
774\r
775 ot("ExceptionAddressError%s\n", ms?"":":");\r
776 ot(";@ r6 - info word (without instruction/not bit), r11 - faulting address\n");\r
777\r
778 // 1. Make a temporary copy of the status register and set the status register for exception processing.\r
779 ot(" ldrb r0,[r7,#0x44] ;@ Get old SR high\n");\r
780 ot(" ldr r2,[r7,#0x58] ;@ state flags\n");\r
781 ot(" and r3,r0,#0x27 ;@ clear trace and unused flags\n");\r
782 ot(" orr r3,r3,#0x20 ;@ set supervisor mode\n");\r
783 ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");\r
784 ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");\r
785 ot(" tst r2,#4\n");\r
786 ot(" orrne r6,r6,#8 ;@ complete info word\n");\r
787 ot(" orr r2,r2,#4 ;@ set activity bit: 'not processing instruction'\n");\r
788#if EMULATE_HALT\r
789 ot(" tst r2,#8\n");\r
790 ot(" orrne r2,r2,#0x10 ;@ HALT\n");\r
791 ot(" orr r2,r2,#8 ;@ processing address error\n");\r
792 ot(" str r2,[r7,#0x58]\n");\r
793 ot(" movne r5,#0\n");\r
794 ot(" bne CycloneEndNoBack ;@ bye bye\n");\r
795#else\r
796 ot(" str r2,[r7,#0x58]\n");\r
797#endif\r
798 ot(" and r10,r10,#0xf0000000\n");\r
799 ot(" orr r10,r10,r0,lsl #4 ;@ some preparations for SR push\n");\r
800 ot("\n");\r
801\r
802 // 3. Save the current processor context + additional information.\r
803 ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");\r
804 ot(" tst r10,#0x200\n");\r
805 ot(";@ get our SP:\n");\r
806 ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");\r
807 ot(" streq r0,[r7,#0x48]\n");\r
808 ot(" moveq r0,r2\n");\r
809 // PC\r
810 ot(";@ Push old PC onto stack\n");\r
811 ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");\r
812 ot(" sub r0,r0,#4 ;@ Predecremented A7\n");\r
813 ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");\r
814 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
815 MemHandler(1,2,0,EMULATE_HALT);\r
816 // SR\r
817 ot(";@ Push old SR:\n");\r
818 ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");\r
819 ot(" mov r1,r10,ror #28 ;@ ____NZCV\n");\r
820 ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");\r
821 ot(" tst r2,#1 ;@ 1 if C!=V\n");\r
822 ot(" eorne r1,r1,#3 ;@ ____NZVC\n");\r
823 ot(" and r0,r0,#0x20000000\n");\r
824 ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");\r
825 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
826 ot(" and r10,r10,#0xf0000000\n");\r
827 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
828 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
829 MemHandler(1,1,0,0);\r
830 // IR (instruction register)\r
831 ot(";@ Push IR:\n");\r
832 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
833 ot(" mov r1,r8\n");\r
834 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
835 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
836 MemHandler(1,1,0,0);\r
837 // access address\r
838 ot(";@ Push address:\n");\r
839 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
840 ot(" mov r1,r11\n");\r
841 ot(" sub r0,r0,#4 ;@ Predecrement A7\n");\r
842 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
843 MemHandler(1,2,0,0);\r
844 // information word\r
845 ot(";@ Push info word:\n");\r
846 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
847 ot(" mov r1,r6\n");\r
848 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
849 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
850 MemHandler(1,1,0,0);\r
851 ot("\n");\r
852\r
853 // 2. Obtain the exception vector\r
854 ot(";@ Read Exception Vector:\n");\r
855 ot(" mov r0,#0x0c\n");\r
856 MemHandler(0,2,0,0);\r
857 ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");\r
858#if USE_CHECKPC_CALLBACK\r
859 ot(" add lr,pc,#4\n");\r
860 ot(" add r0,r0,r3 ;@ r0 = Memory Base + New PC\n");\r
861 #ifdef MEMHANDLERS_DIRECT_PREFIX\r
862 ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);\r
863 #else\r
864 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
865 #endif\r
866 ot(" mov r4,r0\n");\r
867#else\r
868 ot(" add r4,r0,r3 ;@ r4 = Memory Base + New PC\n");\r
869#endif\r
870 ot("\n");\r
871\r
872#if EMULATE_ADDRESS_ERRORS_JUMP && EMULATE_HALT\r
873 ot(" tst r4,#1\n");\r
874 ot(" bne ExceptionAddressError_r_prg_r4\n");\r
875#else\r
876 ot(" bic r4,r4,#1\n");\r
877#endif\r
878\r
879 // 4. Resume execution.\r
880 ot(" ldr r6,[r7,#0x54]\n");\r
881 ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
882 ot(" subs r5,r5,#50 ;@ Subtract cycles\n");\r
c204973a 883 ot(" ldrgt pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
d9d77995 884 ot(" b CycloneEnd\n");\r
885 ot("\n");\r
886#endif\r
887\r
888 // --------------\r
889#if EMULATE_TRACE\r
890 // expects srh and irq level in r1, next opcode already fetched to r8\r
891 ot("CycloneDoTraceWithChecks%s\n", ms?"":":");\r
892 ot(" ldr r0,[r7,#0x58]\n");\r
893 ot(" cmp r5,#0\n");\r
894 ot(" orr r0,r0,#2 ;@ go to trace mode\n");\r
895 ot(" str r0,[r7,#0x58]\n");\r
c204973a 896 ot(" ble CycloneEnd\n"); // should take care of situation where we come here when already tracing\r
d9d77995 897 ot(";@ CheckInterrupt:\n");\r
898 ot(" movs r0,r1,lsr #24 ;@ Get IRQ level\n");\r
899 ot(" beq CycloneDoTrace\n");\r
900 ot(" cmp r0,#6 ;@ irq>6 ?\n");\r
901 ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");\r
902 ot(" cmple r0,r1 ;@ irq<=6: Is irq<=mask ?\n");\r
903 ot(" bgt CycloneDoInterruptGoBack\n");\r
904 ot("\n");\r
905\r
906 // expects next opcode to be already fetched to r8\r
907 ot("CycloneDoTrace%s\n", ms?"":":");\r
908 ot(" str r5,[r7,#0x9c] ;@ save cycles\n");\r
909 ot(" ldr r1,[r7,#0x98]\n");\r
910 ot(" mov r5,#0\n");\r
911 ot(" str r1,[r7,#0xa0]\n");\r
912 ot(" adr r0,TraceEnd\n");\r
913 ot(" str r0,[r7,#0x98] ;@ store TraceEnd as CycloneEnd hadler\n");\r
914 ot(" ldr pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
915 ot("\n");\r
916\r
917 ot("TraceEnd%s\n", ms?"":":");\r
918 ot(" ldr r2,[r7,#0x58]\n");\r
919 ot(" ldr r0,[r7,#0x9c] ;@ restore cycles\n");\r
920 ot(" ldr r1,[r7,#0xa0] ;@ old CycloneEnd handler\n");\r
921 ot(" mov r10,r10,lsl #28\n");\r
922 ot(" add r5,r0,r5\n");\r
923 ot(" str r1,[r7,#0x98]\n");\r
924 ot(";@ still tracing?\n"); // exception might have happend\r
925 ot(" tst r2,#2\n");\r
926 ot(" beq TraceDisabled\n");\r
927 ot(";@ trace exception\n");\r
928#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
929 ot(" ldr r1,[r7,#0x58]\n");\r
930 ot(" mov r0,#9\n");\r
931 ot(" orr r1,r1,#4 ;@ set activity bit: 'not processing instruction'\n");\r
932 ot(" str r1,[r7,#0x58]\n");\r
933#else\r
934 ot(" mov r0,#9\n");\r
935#endif\r
936 ot(" bl Exception\n");\r
937 ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
938 ot(" subs r5,r5,#34 ;@ Subtract cycles\n");\r
c204973a 939 ot(" ldrgt pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
d9d77995 940 ot(" b CycloneEnd\n");\r
941 ot("\n");\r
942 ot("TraceDisabled%s\n", ms?"":":");\r
943 ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
944 ot(" cmp r5,#0\n");\r
c204973a 945 ot(" ldrgt pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
d9d77995 946 ot(" b CycloneEnd\n");\r
947 ot("\n");\r
948#endif\r
6003a768 949}\r
950\r
951// ---------------------------------------------------------------------------\r
952// Call Read(r0), Write(r0,r1) or Fetch(r0)\r
d9d77995 953// Trashes r0-r3,r12,lr\r
954int MemHandler(int type,int size,int addrreg,int need_addrerr_check)\r
6003a768 955{\r
d9d77995 956 int func=0x68+type*0xc+(size<<2); // Find correct offset\r
957 char what[32];\r
6003a768 958\r
d9d77995 959#if MEMHANDLERS_NEED_FLAGS\r
960 ot(" mov r3,r10,lsr #28\n");\r
961 ot(" strb r3,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
962#endif\r
963 FlushPC();\r
6003a768 964\r
d9d77995 965#if (MEMHANDLERS_ADDR_MASK & 0xff000000)\r
966 ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0xff000000);\r
967 addrreg=0;\r
968#endif\r
969#if (MEMHANDLERS_ADDR_MASK & 0x00ff0000)\r
970 ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0x00ff0000);\r
971 addrreg=0;\r
972#endif\r
973#if (MEMHANDLERS_ADDR_MASK & 0x0000ff00)\r
974 ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0x0000ff00);\r
975 addrreg=0;\r
976#endif\r
977#if (MEMHANDLERS_ADDR_MASK & 0x000000ff)\r
978 ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0x000000ff);\r
979 addrreg=0;\r
980#endif\r
981\r
982#if EMULATE_ADDRESS_ERRORS_IO\r
983 if (size > 0 && need_addrerr_check)\r
984 {\r
985 ot(" add lr,pc,#4*%i\n", addrreg==0?2:3); // helps to prevent interlocks\r
986 if (addrreg != 0) ot(" mov r0,r%i\n", addrreg);\r
987 ot(" tst r0,#1 ;@ address error?\n");\r
988 switch (type) {\r
989 case 0: ot(" bne ExceptionAddressError_r_data\n"); break;\r
990 case 1: ot(" bne ExceptionAddressError_w_data\n"); break;\r
991 case 2: ot(" bne ExceptionAddressError_r_prg\n"); break;\r
992 }\r
993 }\r
994 else\r
995#endif\r
996\r
997 sprintf(what, "%s%d", type==0 ? "read" : (type==1 ? "write" : "fetch"), 8<<size);\r
998#ifdef MEMHANDLERS_DIRECT_PREFIX\r
999 if (addrreg != 0)\r
1000 ot(" mov r0,r%i\n", addrreg);\r
1001 ot(" bl %s%s ;@ Call ", MEMHANDLERS_DIRECT_PREFIX, what);\r
1002 (void)func; // avoid warning\r
1003#else\r
1004 if (addrreg != 0)\r
1005 {\r
1006 ot(" add lr,pc,#4\n");\r
1007 ot(" mov r0,r%i\n", addrreg);\r
1008 }\r
1009 else\r
1010 ot(" mov lr,pc\n");\r
6003a768 1011 ot(" ldr pc,[r7,#0x%x] ;@ Call ",func);\r
d9d77995 1012#endif\r
6003a768 1013\r
1014 // Document what we are calling:\r
d9d77995 1015 if (type==1) ot("%s(r0,r1)",what);\r
1016 else ot("%s(r0)", what);\r
6003a768 1017 ot(" handler\n");\r
1018\r
d9d77995 1019#if MEMHANDLERS_CHANGE_FLAGS\r
1020 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");\r
1021 ot(" mov r10,r10,lsl #28\n");\r
1022#endif\r
1023#if MEMHANDLERS_CHANGE_PC\r
1024 ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
1025#endif\r
1026\r
6003a768 1027 return 0;\r
1028}\r
1029\r
1030static void PrintOpcodes()\r
1031{\r
1032 int op=0;\r
d9d77995 1033\r
6003a768 1034 printf("Creating Opcodes: [");\r
1035\r
1036 ot(";@ ---------------------------- Opcodes ---------------------------\n");\r
1037\r
1038 // Emit null opcode:\r
1039 ot("Op____%s ;@ Called if an opcode is not recognised\n", ms?"":":");\r
d9d77995 1040#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
1041 ot(" ldr r1,[r7,#0x58]\n");\r
1042 ot(" sub r4,r4,#2\n");\r
1043 ot(" orr r1,r1,#4 ;@ set activity bit: 'not processing instruction'\n");\r
1044 ot(" str r1,[r7,#0x58]\n");\r
1045#else\r
1046 ot(" sub r4,r4,#2\n");\r
1047#endif\r
1048#if USE_UNRECOGNIZED_CALLBACK\r
1049 ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
1050 ot(" mov r1,r10,lsr #28\n");\r
1051 ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
1052 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
1053 ot(" ldr r11,[r7,#0x94] ;@ UnrecognizedCallback\n");\r
1054 ot(" tst r11,r11\n");\r
1055 ot(" movne lr,pc\n");\r
1056 ot(" movne pc,r11 ;@ call UnrecognizedCallback if it is defined\n");\r
1057 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");\r
1058 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
1059 ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
1060 ot(" mov r10,r10,lsl #28\n");\r
1061 ot(" tst r0,r0\n");\r
1062 ot(" moveq r0,#4\n");\r
1063 ot(" bleq Exception\n");\r
1064#else\r
1065 ot(" mov r0,#4\n");\r
1066 ot(" bl Exception\n");\r
1067#endif\r
1068 ot("\n");\r
1069 Cycles=34;\r
1070 OpEnd();\r
1071\r
1072 // Unrecognised a-line and f-line opcodes throw an exception:\r
1073 ot("Op__al%s ;@ Unrecognised a-line opcode\n", ms?"":":");\r
1074 ot(" sub r4,r4,#2\n");\r
1075#if USE_AFLINE_CALLBACK\r
1076 ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
1077 ot(" mov r1,r10,lsr #28\n");\r
1078 ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
1079 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
1080 ot(" ldr r11,[r7,#0x94] ;@ UnrecognizedCallback\n");\r
1081 ot(" tst r11,r11\n");\r
1082 ot(" movne lr,pc\n");\r
1083 ot(" movne pc,r11 ;@ call UnrecognizedCallback if it is defined\n");\r
1084 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");\r
1085 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
1086 ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
1087 ot(" mov r10,r10,lsl #28\n");\r
1088 ot(" tst r0,r0\n");\r
1089 ot(" moveq r0,#0x0a\n");\r
1090 ot(" bleq Exception\n");\r
1091#else\r
1092 ot(" mov r0,#0x0a\n");\r
1093 ot(" bl Exception\n");\r
1094#endif\r
1095 ot("\n");\r
1096 Cycles=4;\r
1097 OpEnd();\r
1098\r
1099 ot("Op__fl%s ;@ Unrecognised f-line opcode\n", ms?"":":");\r
1100 ot(" sub r4,r4,#2\n");\r
1101#if USE_AFLINE_CALLBACK\r
1102 ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
1103 ot(" mov r1,r10,lsr #28\n");\r
1104 ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
1105 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
1106 ot(" ldr r11,[r7,#0x94] ;@ UnrecognizedCallback\n");\r
1107 ot(" tst r11,r11\n");\r
1108 ot(" movne lr,pc\n");\r
1109 ot(" movne pc,r11 ;@ call UnrecognizedCallback if it is defined\n");\r
1110 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");\r
1111 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
1112 ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
1113 ot(" mov r10,r10,lsl #28\n");\r
1114 ot(" tst r0,r0\n");\r
1115 ot(" moveq r0,#0x0b\n");\r
1116 ot(" bleq Exception\n");\r
1117#else\r
1118 ot(" mov r0,#0x0b\n");\r
1119 ot(" bl Exception\n");\r
1120#endif\r
1121 ot("\n");\r
1122 Cycles=4;\r
1123 OpEnd();\r
1124\r
6003a768 1125\r
d9d77995 1126 for (op=0;op<hot_opcode_count;op++)\r
1127 OpAny(hot_opcodes[op]);\r
6003a768 1128\r
1129 for (op=0;op<0x10000;op++)\r
1130 {\r
1131 if ((op&0xfff)==0) { printf("%x",op>>12); fflush(stdout); } // Update progress\r
1132\r
d9d77995 1133 if (!is_op_hot(op))\r
1134 OpAny(op);\r
6003a768 1135 }\r
1136\r
1137 ot("\n");\r
1138\r
1139 printf("]\n");\r
1140}\r
1141\r
d9d77995 1142// helper\r
1143static void ott(const char *str, int par, const char *nl, int nlp, int counter, int size)\r
1144{\r
1145 switch(size) {\r
1146 case 0: if((counter&7)==0) ot(ms?" dcb ":" .byte "); break;\r
1147 case 1: if((counter&7)==0) ot(ms?" dcw ":" .hword "); break;\r
1148 case 2: if((counter&7)==0) ot(ms?" dcd ":" .long "); break;\r
1149 }\r
1150 ot(str, par);\r
1151 if((counter&7)==7) ot(nl,nlp); else ot(",");\r
1152}\r
1153\r
6003a768 1154static void PrintJumpTable()\r
1155{\r
1156 int i=0,op=0,len=0;\r
1157\r
1158 ot(";@ -------------------------- Jump Table --------------------------\n");\r
6003a768 1159\r
d9d77995 1160 // space for decompressed table\r
1161 ot(ms?" area |.data|, data\n":" .data\n .align 4\n\n");\r
6003a768 1162\r
d9d77995 1163#if COMPRESS_JUMPTABLE\r
1164 int handlers=0,reps=0,*indexes,ip,u,out;\r
1165 // use some weird compression on the jump table\r
1166 indexes=(int *)malloc(0x10000*4);\r
1167 if(!indexes) { printf("ERROR: out of memory\n"); exit(1); }\r
1168 len=0x10000;\r
6003a768 1169\r
d9d77995 1170 ot("CycloneJumpTab%s\n", ms?"":":");\r
1171 if(ms) {\r
1172 for(i = 0; i < 0xa000/8; i++)\r
1173 ot(" dcd 0,0,0,0,0,0,0,0\n");\r
1174 } else\r
1175 ot(" .rept 0x%x\n .long 0,0,0,0,0,0,0,0\n .endr\n", 0xa000/8);\r
1176\r
1177 // hanlers live in "a-line" part of the table\r
1178 // first output nop,a-line,f-line handlers\r
1179 ot(ms?" dcd Op____,Op__al,Op__fl,":" .long Op____,Op__al,Op__fl,");\r
1180 handlers=3;\r
1181\r
1182 for(i=0;i<len;i++)\r
1183 {\r
1184 op=CyJump[i];\r
1185\r
1186 for(u=i-1; u>=0; u--) if(op == CyJump[u]) break; // already done with this op?\r
1187 if(u==-1 && op >= 0) {\r
1188 ott("Op%.4x",op," ;@ %.4x\n",i,handlers,2);\r
1189 indexes[op] = handlers;\r
1190 handlers++;\r
1191 }\r
1192 }\r
1193 if(handlers&7) {\r
1194 fseek(AsmFile, -1, SEEK_CUR); // remove last comma\r
1195 for(i = 8-(handlers&7); i > 0; i--)\r
1196 ot(",000000");\r
1197 ot("\n");\r
1198 }\r
1199 if(ms) {\r
1200 for(i = (0x4000-handlers)/8; i > 0; i--)\r
1201 ot(" dcd 0,0,0,0,0,0,0,0\n");\r
1202 } else {\r
1203 ot(ms?"":" .rept 0x%x\n .long 0,0,0,0,0,0,0,0\n .endr\n", (0x4000-handlers)/8);\r
1204 }\r
1205 printf("total distinct hanlers: %i\n",handlers);\r
1206 // output data\r
1207 for(i=0,ip=0; i < 0xf000; i++, ip++) {\r
1208 op=CyJump[i];\r
1209 if(op == -2) {\r
1210 // it must skip a-line area, because we keep our data there\r
1211 ott("0x%.4x", handlers<<4, "\n",0,ip++,1);\r
1212 ott("0x%.4x", 0x1000, "\n",0,ip,1);\r
1213 i+=0xfff;\r
1214 continue;\r
1215 }\r
1216 for(reps=1; i < 0xf000; i++, reps++) if(op != CyJump[i+1]) break;\r
1217 if(op>=0) out=indexes[op]<<4; else out=0; // unrecognised\r
1218 if(reps <= 0xe || reps==0x10) {\r
1219 if(reps!=0x10) out|=reps; else out|=0xf; // 0xf means 0x10 (0xf appeared to be unused anyway)\r
1220 ott("0x%.4x", out, "\n",0,ip,1);\r
1221 } else {\r
1222 ott("0x%.4x", out, "\n",0,ip++,1);\r
1223 ott("0x%.4x", reps,"\n",0,ip,1);\r
1224 }\r
1225 }\r
1226 if(ip&1) ott("0x%.4x", 0, "\n",0,ip++,1);\r
1227 if(ip&7) fseek(AsmFile, -1, SEEK_CUR); // remove last comma\r
1228 if(ip&7) {\r
1229 for(i = 8-(ip&7); i > 0; i--)\r
1230 ot(",0x0000");\r
1231 }\r
1232 ot("\n");\r
1233 if(ms) {\r
1234 for(i = (0x2000-ip/2)/8+1; i > 0; i--)\r
1235 ot(" dcd 0,0,0,0,0,0,0,0\n");\r
1236 } else {\r
1237 ot(" .rept 0x%x\n .long 0,0,0,0,0,0,0,0\n .endr\n", (0x2000-ip/2)/8+1);\r
1238 }\r
1239 ot("\n");\r
1240 free(indexes);\r
1241#else\r
1242 ot("CycloneJumpTab%s\n", ms?"":":");\r
1243 len=0xfffe; // Hmmm, armasm 2.50.8684 messes up with a 0x10000 long jump table\r
1244 // notaz: same thing with GNU as 2.9-psion-98r2 (reloc overflow)\r
1245 // this is due to COFF objects using only 2 bytes for reloc count\r
1246\r
1247 for (i=0;i<len;i++)\r
1248 {\r
1249 op=CyJump[i];\r
1250\r
1251 if(op>=0) ott("Op%.4x",op," ;@ %.4x\n",i-7,i,2);\r
1252 else if(op==-2) ott("Op__al",0, " ;@ %.4x\n",i-7,i,2);\r
1253 else if(op==-3) ott("Op__fl",0, " ;@ %.4x\n",i-7,i,2);\r
1254 else ott("Op____",0, " ;@ %.4x\n",i-7,i,2);\r
1255 }\r
1256 if(i&7) fseek(AsmFile, -1, SEEK_CUR); // remove last comma\r
1257\r
1258 ot("\n");\r
1259 ot(";@ notaz: we don't want to crash if we run into those 2 missing opcodes\n");\r
1260 ot(";@ so we leave this pattern to patch it later\n");\r
1261 ot("%s 0x78563412\n", ms?" dcd":" .long");\r
1262 ot("%s 0x56341290\n", ms?" dcd":" .long");\r
1263#endif\r
6003a768 1264}\r
1265\r
1266static int CycloneMake()\r
1267{\r
d9d77995 1268 int i;\r
1269 const char *name="Cyclone.s";\r
1270 const char *globl=ms?"export":".global";\r
1271\r
6003a768 1272 // Open the assembly file\r
1273 if (ms) name="Cyclone.asm";\r
1274 AsmFile=fopen(name,"wt"); if (AsmFile==NULL) return 1;\r
d9d77995 1275\r
6003a768 1276 printf("Making %s...\n",name);\r
1277\r
1278 ot("\n;@ Cyclone 68000 Emulator v%x.%.3x - Assembler Output\n\n",CycloneVer>>12,CycloneVer&0xfff);\r
1279\r
d9d77995 1280 ot(";@ Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)\n");\r
1281 ot(";@ Copyright (c) 2005-2011 Gražvydas \"notaz\" Ignotas (notasas (at) gmail.com)\n\n");\r
c41b9b97 1282\r
6003a768 1283 ot(";@ This code is licensed under the GNU General Public License version 2.0 and the MAME License.\n");\r
1284 ot(";@ You can choose the license that has the most advantages for you.\n\n");\r
1285 ot(";@ SVN repository can be found at http://code.google.com/p/cyclone68000/\n\n");\r
1286\r
1287 CyJump=(int *)malloc(0x40000); if (CyJump==NULL) return 1;\r
1288 memset(CyJump,0xff,0x40000); // Init to -1\r
d9d77995 1289 for(i=0xa000; i<0xb000; i++) CyJump[i] = -2; // a-line emulation\r
1290 for(i=0xf000; i<0x10000; i++) CyJump[i] = -3; // f-line emulation\r
6003a768 1291\r
d9d77995 1292 ot(ms?" area |.text|, code\n":" .text\n .align 4\n\n");\r
1293 ot(" %s CycloneInit\n",globl);\r
1294 ot(" %s CycloneReset\n",globl);\r
1295 ot(" %s CycloneRun\n",globl);\r
1296 ot(" %s CycloneSetSr\n",globl);\r
1297 ot(" %s CycloneGetSr\n",globl);\r
1298 ot(" %s CycloneFlushIrq\n",globl);\r
1299 ot(" %s CyclonePack\n",globl);\r
1300 ot(" %s CycloneUnpack\n",globl);\r
1301 ot(" %s CycloneVer\n",globl);\r
1302#if (CYCLONE_FOR_GENESIS == 2)\r
1303 ot(" %s CycloneSetRealTAS\n",globl);\r
1304 ot(" %s CycloneDoInterrupt\n",globl);\r
1305 ot(" %s CycloneDoTrace\n",globl);\r
1306 ot(" %s CycloneJumpTab\n",globl);\r
1307 ot(" %s Op____\n",globl);\r
c6237d9e 1308 ot(" %s Op6002\n",globl);\r
1309 ot(" %s Op6602\n",globl);\r
1310 ot(" %s Op6702\n",globl);\r
d9d77995 1311#endif\r
1312 ot("\n");\r
1313 ot(ms?"CycloneVer dcd 0x":"CycloneVer: .long 0x");\r
1314 ot("%.4x\n",CycloneVer);\r
6003a768 1315 ot("\n");\r
1316\r
1317 PrintFramework();\r
d9d77995 1318 arm_op_count = 0;\r
6003a768 1319 PrintOpcodes();\r
d9d77995 1320 printf("~%i ARM instructions used for opcode handlers\n", arm_op_count);\r
6003a768 1321 PrintJumpTable();\r
1322\r
1323 if (ms) ot(" END\n");\r
1324\r
d9d77995 1325 ot("\n\n;@ vim:filetype=armasm\n");\r
1326\r
6003a768 1327 fclose(AsmFile); AsmFile=NULL;\r
1328\r
d9d77995 1329#if 0\r
6003a768 1330 printf("Assembling...\n");\r
1331 // Assemble the file\r
1332 if (ms) system("armasm Cyclone.asm");\r
1333 else system("as -o Cyclone.o Cyclone.s");\r
1334 printf("Done!\n\n");\r
d9d77995 1335#endif\r
6003a768 1336\r
1337 free(CyJump);\r
1338 return 0;\r
1339}\r
1340\r
1341int main()\r
1342{\r
1343 printf("\n Cyclone 68000 Emulator v%x.%.3x - Core Creator\n\n",CycloneVer>>12,CycloneVer&0xfff);\r
1344\r
d9d77995 1345 // Make GAS or ARMASM version\r
1346 CycloneMake();\r
6003a768 1347 return 0;\r
1348}\r
d9d77995 1349\r
68000 emulator written in ARM 32-bit assembly