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fix compatibility with ancient gas
[cyclone68000.git] / Main.cpp
CommitLineData
6003a768 1\r
619b1824 2// This file is part of the Cyclone 68000 Emulator\r
3\r
d9d77995 4// Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)\r
5// Copyright (c) 2005-2011 Gražvydas "notaz" Ignotas (notasas (at) gmail.com)\r
c41b9b97 6\r
619b1824 7// This code is licensed under the GNU General Public License version 2.0 and the MAME License.\r
8// You can choose the license that has the most advantages for you.\r
9\r
10// SVN repository can be found at http://code.google.com/p/cyclone68000/\r
11\r
d9d77995 12\r
6003a768 13#include "app.h"\r
14\r
15static FILE *AsmFile=NULL;\r
16\r
d9d77995 17static int CycloneVer=0x0099; // Version number of library\r
6003a768 18int *CyJump=NULL; // Jump table\r
d9d77995 19int ms=USE_MS_SYNTAX; // If non-zero, output in Microsoft ARMASM format\r
20const char * const Narm[4]={ "b", "h","",""}; // Normal ARM Extensions for operand sizes 0,1,2\r
21const char * const Sarm[4]={"sb","sh","",""}; // Sign-extend ARM Extensions for operand sizes 0,1,2\r
22int Cycles; // Current cycles for opcode\r
23int pc_dirty; // something changed PC during processing\r
24int arm_op_count;\r
25\r
26// opcodes often used by games\r
27static const unsigned short hot_opcodes[] = {\r
c6237d9e 28 0x6702, // beq $3\r
29 0x6602, // bne $3\r
d9d77995 30 0x51c8, // dbra Dn, $2\r
31 0x4a38, // tst.b $0.w\r
32 0xd040, // add.w Dn, Dn\r
33 0x4a79, // tst.w $0.l\r
34 0x0240, // andi.w #$0, D0\r
35 0x2038, // move.l $0.w, D0\r
36 0xb0b8, // cmp.l $0.w, D0\r
c6237d9e 37 0x6002, // bra $3\r
d9d77995 38 0x30c0, // move.w D0, (A0)+\r
39 0x3028, // move.w ($0,A0), D0\r
40 0x0c40, // cmpi.w #$0, D0\r
41 0x0c79, // cmpi.w #$0, $0.l\r
42 0x4e75, // rts\r
43 0x4e71, // nop\r
44 0x3000, // move.w D0, D0\r
45 0x0839, // btst #$0, $0.l\r
46 0x7000, // moveq #$0, D0\r
47 0x3040, // movea.w D0, A0\r
48 0x0838, // btst #$0, $0.w\r
49 0x4a39, // tst.b $0.l\r
50 0x33d8, // move.w (A0)+, $0.l\r
51 0x6700, // beq $2\r
52 0xb038, // cmp.b $0.w, D0\r
53 0x3039, // move.w $0.l, D0\r
54 0x4840, // swap D0\r
c6237d9e 55 0x6102, // bsr $3\r
d9d77995 56 0x6100, // bsr $2\r
57 0x5e40, // addq.w #7, D0\r
58 0x1039, // move.b $0.l, D0\r
59 0x20c0, // move.l D0, (A0)+\r
60 0x1018, // move.b (A0)+, D0\r
61 0x30d0, // move.w (A0), (A0)+\r
62 0x3080, // move.w D0, (A0)\r
63 0x3018, // move.w (A0)+, D0\r
64 0xc040, // and.w D0, D0\r
65 0x3180, // move.w D0, (A0,D0.w)\r
66 0x1198, // move.b (A0)+, (A0,D0.w)\r
c6237d9e 67 0x6502, // bcs $3\r
d9d77995 68 0x6500, // bcs $2\r
c6237d9e 69 0x6402, // bcc $3\r
70 0x6a02, // bpl $3\r
d9d77995 71 0x41f0, // lea (A0,D0.w), A0\r
72 0x4a28, // tst.b ($0,A0)\r
73 0x0828, // btst #$0, ($0,A0)\r
74 0x0640, // addi.w #$0, D0\r
75 0x10c0, // move.b D0, (A0)+\r
76 0x10d8, // move.b (A0)+, (A0)+\r
77};\r
78#define hot_opcode_count (int)(sizeof(hot_opcodes) / sizeof(hot_opcodes[0]))\r
79\r
80static int is_op_hot(int op)\r
81{\r
82 int i;\r
83 for (i = 0; i < hot_opcode_count; i++)\r
84 if (op == hot_opcodes[i])\r
85 return 1;\r
86 return 0;\r
87}\r
6003a768 88\r
c30e2e2d 89void ot(const char *format, ...)\r
6003a768 90{\r
c30e2e2d 91 va_list valist;\r
d9d77995 92 int i, len;\r
93\r
94 // notaz: stop me from leaving newlines in the middle of format string\r
95 // and generating bad code\r
96 for(i=0, len=strlen(format); i < len && format[i] != '\n'; i++);\r
97 if(i < len-1 && format[len-1] != '\n') printf("\nWARNING: possible improper newline placement:\n%s\n", format);\r
98\r
99 if (format[0] == ' ' && format[1] == ' ' && format[2] != ' ' && format[2] != '.')\r
100 arm_op_count++;\r
101\r
6003a768 102 va_start(valist,format);\r
103 if (AsmFile) vfprintf(AsmFile,format,valist);\r
104 va_end(valist);\r
105}\r
106\r
107void ltorg()\r
108{\r
109 if (ms) ot(" LTORG\n");\r
110 else ot(" .ltorg\n");\r
111}\r
112\r
d9d77995 113#if (CYCLONE_FOR_GENESIS == 2)\r
66dda842 114static const char *tas_ops[] = {\r
115 "Op4ad0", "Op4ad8", "Op4adf",\r
116 "Op4ae0", "Op4ae7", "Op4ae8",\r
117 "Op4af0", "Op4af8", "Op4af9",\r
118};\r
119\r
120// get handler address in r0, OT (offset table) in r2\r
121static void ChangeTASGet(unsigned int i)\r
6003a768 122{\r
66dda842 123 if (i >= sizeof(tas_ops) / sizeof(tas_ops[0]))\r
124 abort();\r
125 ot(" ldr r0,[r2,#%d*4] ;@ %s\n",i,tas_ops[i]);\r
126 ot(" add r0,r0,r2\n");\r
6003a768 127}\r
d9d77995 128#endif\r
6003a768 129\r
d9d77995 130#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
131static void AddressErrorWrapper(char rw, const char *dataprg, int iw)\r
6003a768 132{\r
d9d77995 133 ot("ExceptionAddressError_%c_%s%s\n", rw, dataprg, ms?"":":");\r
134 ot(" ldr r1,[r7,#0x44]\n");\r
135 ot(" mov r6,#0x%02x\n", iw);\r
136 ot(" mov r11,r0\n");\r
137 ot(" tst r1,#0x20\n");\r
138 ot(" orrne r6,r6,#4\n");\r
139 ot(" b ExceptionAddressError\n");\r
6003a768 140 ot("\n");\r
141}\r
d9d77995 142#endif\r
143\r
355815eb 144void FlushPC(int force)\r
d9d77995 145{\r
146#if MEMHANDLERS_NEED_PC\r
355815eb 147 force |= pc_dirty;\r
d9d77995 148 pc_dirty = 0;\r
355815eb 149#endif\r
150 if (force)\r
151 ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
d9d77995 152}\r
6003a768 153\r
154static void PrintFramework()\r
155{\r
d9d77995 156 int state_flags_to_check = 1; // stopped\r
157#if EMULATE_TRACE\r
158 state_flags_to_check |= 2; // tracing\r
159#endif\r
160#if EMULATE_HALT\r
161 state_flags_to_check |= 0x10; // halted\r
162#endif\r
163\r
6003a768 164 ot(";@ --------------------------- Framework --------------------------\n");\r
165 if (ms) ot("CycloneRun\n");\r
166 else ot("CycloneRun:\n");\r
167\r
d9d77995 168 ot(" stmdb sp!,{r4-r8,r10,r11,lr}\n");\r
6003a768 169\r
170 ot(" mov r7,r0 ;@ r7 = Pointer to Cpu Context\n");\r
171 ot(" ;@ r0-3 = Temporary registers\n");\r
d9d77995 172 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Flags (NZCV)\n");\r
66dda842 173 ot(" ldr r6,[r7,#0x54] ;@ r6 = Opcode Jump table (from reset)\n");\r
6003a768 174 ot(" ldr r5,[r7,#0x5c] ;@ r5 = Cycles\n");\r
175 ot(" ldr r4,[r7,#0x40] ;@ r4 = Current PC + Memory Base\n");\r
176 ot(" ;@ r8 = Current Opcode\n");\r
d9d77995 177 ot(" ldr r1,[r7,#0x44] ;@ Get SR high T_S__III and irq level\n");\r
178 ot(" mov r10,r10,lsl #28;@ r10 = Flags 0xf0000000, cpsr format\n");\r
179 ot(" ;@ r11 = Source value / Memory Base\n");\r
d9d77995 180 ot("\n");\r
181#if (CYCLONE_FOR_GENESIS == 2) || EMULATE_TRACE\r
182 ot(" mov r2,#0\n");\r
183 ot(" str r2,[r7,#0x98] ;@ clear custom CycloneEnd\n");\r
184#endif\r
185 ot(";@ CheckInterrupt:\n");\r
186 ot(" movs r0,r1,lsr #24 ;@ Get IRQ level\n"); // same as ldrb r0,[r7,#0x47]\r
187 ot(" beq NoInts0\n");\r
188 ot(" cmp r0,#6 ;@ irq>6 ?\n");\r
189 ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");\r
190 ot(" cmple r0,r1 ;@ irq<=6: Is irq<=mask ?\n");\r
191 ot(" bgt CycloneDoInterrupt\n");\r
192 ot("NoInts0%s\n", ms?"":":");\r
193 ot("\n");\r
194 ot(";@ Check if our processor is in special state\n");\r
195 ot(";@ and jump to opcode handler if not\n");\r
196 ot(" ldr r0,[r7,#0x58] ;@ state_flags\n");\r
197 ot(" ldrh r8,[r4],#2 ;@ Fetch first opcode\n");\r
198 ot(" tst r0,#0x%02x ;@ special state?\n", state_flags_to_check);\r
199 ot(" ldreq pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
200 ot("\n");\r
201 ot("CycloneSpecial%s\n", ms?"":":");\r
202#if EMULATE_TRACE\r
203 ot(" tst r0,#2 ;@ tracing?\n");\r
204 ot(" bne CycloneDoTrace\n");\r
205#endif\r
206 ot(";@ stopped or halted\n");\r
207 ot(" mov r5,#0\n");\r
208 ot(" str r5,[r7,#0x5C] ;@ eat all cycles\n");\r
209 ot(" ldmia sp!,{r4-r8,r10,r11,pc} ;@ we are stopped, do nothing!\n");\r
6003a768 210 ot("\n");\r
6003a768 211 ot("\n");\r
212\r
213 ot(";@ We come back here after execution\n");\r
214 ot("CycloneEnd%s\n", ms?"":":");\r
215 ot(" sub r4,r4,#2\n");\r
216 ot("CycloneEndNoBack%s\n", ms?"":":");\r
d9d77995 217#if (CYCLONE_FOR_GENESIS == 2) || EMULATE_TRACE\r
218 ot(" ldr r1,[r7,#0x98]\n");\r
219 ot(" mov r10,r10,lsr #28\n");\r
220 ot(" tst r1,r1\n");\r
221 ot(" bxne r1 ;@ jump to alternative CycloneEnd\n");\r
222#else\r
223 ot(" mov r10,r10,lsr #28\n");\r
224#endif\r
6003a768 225 ot(" str r4,[r7,#0x40] ;@ Save Current PC + Memory Base\n");\r
226 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
d9d77995 227 ot(" strb r10,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
228 ot(" ldmia sp!,{r4-r8,r10,r11,pc}\n");\r
229 ltorg();\r
6003a768 230 ot("\n");\r
6003a768 231 ot("\n");\r
d9d77995 232\r
b889883d 233 ot("CycloneInitJT%s\n", ms?"":":");\r
d9d77995 234#if COMPRESS_JUMPTABLE\r
235 ot(";@ decompress jump table\n");\r
b889883d 236 ot(" mov r12,r0 ;@ jump table\n");\r
d9d77995 237 ot(" add r0,r12,#0xe000*4 ;@ ctrl code pointer\n");\r
238 ot(" ldr r1,[r0,#-4]\n");\r
239 ot(" tst r1,r1\n");\r
240 ot(" movne pc,lr ;@ already uncompressed\n");\r
b889883d 241 ot(" stmfd sp!,{r7,lr}\n");\r
242 ot(" mov r7,r12 ;@ jump table\n");\r
d9d77995 243 ot(" add r3,r12,#0xa000*4 ;@ handler table pointer, r12=dest\n");\r
244 ot("unc_loop%s\n", ms?"":":");\r
245 ot(" ldrh r1,[r0],#2\n");\r
246 ot(" and r2,r1,#0xf\n");\r
247 ot(" bic r1,r1,#0xf\n");\r
248 ot(" ldr r1,[r3,r1,lsr #2] ;@ r1=handler\n");\r
249 ot(" cmp r2,#0xf\n");\r
250 ot(" addeq r2,r2,#1 ;@ 0xf is really 0x10\n");\r
251 ot(" tst r2,r2\n");\r
252 ot(" ldreqh r2,[r0],#2 ;@ counter is in next word\n");\r
253 ot(" tst r2,r2\n");\r
254 ot(" beq unc_finish ;@ done decompressing\n");\r
255 ot(" tst r1,r1\n");\r
256 ot(" addeq r12,r12,r2,lsl #2 ;@ 0 handler means we should skip those bytes\n");\r
257 ot(" beq unc_loop\n");\r
258 ot("unc_loop_in%s\n", ms?"":":");\r
259 ot(" subs r2,r2,#1\n");\r
260 ot(" str r1,[r12],#4\n");\r
261 ot(" bgt unc_loop_in\n");\r
262 ot(" b unc_loop\n");\r
263 ot("unc_finish%s\n", ms?"":":");\r
d9d77995 264 ot(" ;@ set a-line and f-line handlers\n");\r
b889883d 265 ot(" add r0,r7,#0xa000*4\n");\r
d9d77995 266 ot(" ldr r1,[r0,#4] ;@ a-line handler\n");\r
267 ot(" ldr r3,[r0,#8] ;@ f-line handler\n");\r
268 ot(" mov r2,#0x1000\n");\r
269 ot("unc_fill3%s\n", ms?"":":");\r
270 ot(" subs r2,r2,#1\n");\r
271 ot(" str r1,[r0],#4\n");\r
272 ot(" bgt unc_fill3\n");\r
b889883d 273 ot(" add r0,r7,#0xf000*4\n");\r
d9d77995 274 ot(" mov r2,#0x1000\n");\r
275 ot("unc_fill4%s\n", ms?"":":");\r
276 ot(" subs r2,r2,#1\n");\r
277 ot(" str r3,[r0],#4\n");\r
278 ot(" bgt unc_fill4\n");\r
b889883d 279 ot(" ldmfd sp!,{r7,pc}\n");\r
d9d77995 280 ltorg();\r
281#else\r
590d780f 282 ot(";@ fix final jumptable entries\n");\r
b889883d 283 ot(" add r0,r0,#0x10000*4\n");\r
284 ot(" ldr r1,[r0,#-3*4]\n");\r
285 ot(" str r1,[r0,#-2*4]\n");\r
286 ot(" str r1,[r0,#-1*4]\n");\r
d9d77995 287 ot(" bx lr\n");\r
288#endif\r
6003a768 289 ot("\n");\r
d9d77995 290\r
291 // --------------\r
b889883d 292 ot("CycloneResetJT%s\n", ms?"":":");\r
d9d77995 293 ot(" stmfd sp!,{r7,lr}\n");\r
294 ot(" mov r7,r0\n");\r
b889883d 295 ot(" str r1,[r7,#0x54] ;@ save CycloneJumpTab avoid literal pools\n");\r
d9d77995 296 ot(" mov r0,#0\n");\r
297 ot(" str r0,[r7,#0x58] ;@ state_flags\n");\r
298 ot(" str r0,[r7,#0x48] ;@ OSP\n");\r
299 ot(" mov r1,#0x27 ;@ Supervisor mode\n");\r
300 ot(" strb r1,[r7,#0x44] ;@ set SR high\n");\r
301 ot(" strb r0,[r7,#0x47] ;@ IRQ\n");\r
6003a768 302 MemHandler(0,2);\r
d9d77995 303 ot(" str r0,[r7,#0x3c] ;@ Stack pointer\n");\r
304 ot(" mov r0,#0\n");\r
305 ot(" str r0,[r7,#0x60] ;@ Membase\n");\r
306 ot(" mov r0,#4\n");\r
307 MemHandler(0,2);\r
308#ifdef MEMHANDLERS_DIRECT_PREFIX\r
309 ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);\r
310#else\r
6003a768 311 ot(" mov lr,pc\n");\r
312 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
d9d77995 313#endif\r
314 ot(" str r0,[r7,#0x40] ;@ PC + base\n");\r
315 ot(" ldmfd sp!,{r7,pc}\n");\r
316 ot("\n");\r
317\r
66dda842 318 // --------------\r
b889883d 319 ot("CycloneSetRealTAS_JT%s\n", ms?"":":");\r
66dda842 320#if (CYCLONE_FOR_GENESIS == 2)\r
66dda842 321 ot(" tst r0,r0\n");\r
b889883d 322 ot(" add r12,r1,#0x4a00*4\n");\r
66dda842 323 ot(" add r12,r12,#0x00d0*4\n");\r
324 ot(" adr r2,CycloneOT_TAS_\n");\r
325 ot(" addeq r2,r2,#%lu*4\n", sizeof(tas_ops) / sizeof(tas_ops[0]));\r
326\r
327 ChangeTASGet(0);\r
328 ot(" mov r1,#8\n");\r
329 ot("setrtas_loop0%s ;@ 4ad0-4ad7\n",ms?"":":");\r
330 ot(" subs r1,r1,#1\n");\r
331 ot(" str r0,[r12],#4\n");\r
332 ot(" bne setrtas_loop0\n");\r
333\r
334 ChangeTASGet(1);\r
335 ot(" mov r1,#7\n");\r
336 ot("setrtas_loop1%s ;@ 4ad8-4ade\n",ms?"":":");\r
337 ot(" subs r1,r1,#1\n");\r
338 ot(" str r0,[r12],#4\n");\r
339 ot(" bne setrtas_loop1\n");\r
340\r
341 ChangeTASGet(2);\r
342 ot(" str r0,[r12],#4\n");\r
343 ChangeTASGet(3);\r
344 ot(" mov r1,#7\n");\r
345 ot("setrtas_loop2%s ;@ 4ae0-4ae6\n",ms?"":":");\r
346 ot(" subs r1,r1,#1\n");\r
347 ot(" str r0,[r12],#4\n");\r
348 ot(" bne setrtas_loop2\n");\r
349\r
350 ChangeTASGet(4);\r
351 ot(" str r0,[r12],#4\n");\r
352 ChangeTASGet(5);\r
353 ot(" mov r1,#8\n");\r
354 ot("setrtas_loop3%s ;@ 4ae8-4aef\n",ms?"":":");\r
355 ot(" subs r1,r1,#1\n");\r
356 ot(" str r0,[r12],#4\n");\r
357 ot(" bne setrtas_loop3\n");\r
358\r
359 ChangeTASGet(6);\r
360 ot(" mov r1,#8\n");\r
361 ot("setrtas_loop4%s ;@ 4af0-4af7\n",ms?"":":");\r
362 ot(" subs r1,r1,#1\n");\r
363 ot(" str r0,[r12],#4\n");\r
364 ot(" bne setrtas_loop4\n");\r
365\r
366 ChangeTASGet(7);\r
367 ot(" str r0,[r12],#4\n");\r
368 ChangeTASGet(8);\r
369 ot(" str r0,[r12],#4\n");\r
370#endif\r
371 ot(" bx lr\n");\r
372 ot("\n");\r
373\r
374 // --------------\r
375 // offset table to avoid .text relocations (forbidden by Android and iOS)\r
66dda842 376#if (CYCLONE_FOR_GENESIS == 2)\r
377 ot("CycloneOT_TAS_%s\n", ms?"":":"); // working TAS (no MD bug)\r
378 for (size_t i = 0; i < sizeof(tas_ops) / sizeof(tas_ops[0]); i++)\r
379 ot(" %s %s_-CycloneOT_TAS_\n", ms?"dcd":".long", tas_ops[i]);\r
380 ot("CycloneOT_TAS%s\n", ms?"":":"); // broken TAS\r
381 for (size_t i = 0; i < sizeof(tas_ops) / sizeof(tas_ops[0]); i++)\r
382 ot(" %s %s-CycloneOT_TAS\n", ms?"dcd":".long", tas_ops[i]);\r
383 ot("\n");\r
384#endif\r
385\r
d9d77995 386 // --------------\r
387 // 68k: XNZVC, ARM: NZCV\r
388 ot("CycloneSetSr%s\n", ms?"":":");\r
389 ot(" mov r2,r1,lsr #8\n");\r
390// ot(" ldrb r3,[r0,#0x44] ;@ get SR high\n");\r
391// ot(" eor r3,r3,r2\n");\r
392// ot(" tst r3,#0x20\n");\r
393#if EMULATE_TRACE\r
394 ot(" and r2,r2,#0xa7 ;@ only defined bits\n");\r
395#else\r
396 ot(" and r2,r2,#0x27 ;@ only defined bits\n");\r
397#endif\r
398 ot(" strb r2,[r0,#0x44] ;@ set SR high\n");\r
399 ot(" mov r2,r1,lsl #25\n");\r
400 ot(" str r2,[r0,#0x4c] ;@ the X flag\n");\r
401 ot(" bic r2,r1,#0xf3\n");\r
402 ot(" tst r1,#1\n");\r
403 ot(" orrne r2,r2,#2\n");\r
404 ot(" tst r1,#2\n");\r
405 ot(" orrne r2,r2,#1\n");\r
406 ot(" strb r2,[r0,#0x46] ;@ flags\n");\r
407 ot(" bx lr\n");\r
408 ot("\n");\r
409\r
410 // --------------\r
411 ot("CycloneGetSr%s\n", ms?"":":");\r
412 ot(" ldrb r1,[r0,#0x46] ;@ flags\n");\r
413 ot(" bic r2,r1,#0xf3\n");\r
414 ot(" tst r1,#1\n");\r
415 ot(" orrne r2,r2,#2\n");\r
416 ot(" tst r1,#2\n");\r
417 ot(" orrne r2,r2,#1\n");\r
418 ot(" ldr r1,[r0,#0x4c] ;@ the X flag\n");\r
419 ot(" tst r1,#0x20000000\n");\r
420 ot(" orrne r2,r2,#0x10\n");\r
421 ot(" ldrb r1,[r0,#0x44] ;@ the SR high\n");\r
422 ot(" orr r0,r2,r1,lsl #8\n");\r
423 ot(" bx lr\n");\r
424 ot("\n");\r
425\r
426 // --------------\r
427 ot("CyclonePack%s\n", ms?"":":");\r
428 ot(" stmfd sp!,{r4,r5,lr}\n");\r
6003a768 429 ot(" mov r4,r0\n");\r
d9d77995 430 ot(" mov r5,r1\n");\r
431 ot(" mov r3,#16\n");\r
432 ot(";@ 0x00-0x3f: DA registers\n");\r
433 ot("c_pack_loop%s\n",ms?"":":");\r
434 ot(" ldr r1,[r0],#4\n");\r
435 ot(" subs r3,r3,#1\n");\r
436 ot(" str r1,[r5],#4\n");\r
437 ot(" bne c_pack_loop\n");\r
438 ot(";@ 0x40: PC\n");\r
439 ot(" ldr r0,[r4,#0x40] ;@ PC + Memory Base\n");\r
440 ot(" ldr r1,[r4,#0x60] ;@ Memory base\n");\r
441 ot(" sub r0,r0,r1\n");\r
442 ot(" str r0,[r5],#4\n");\r
443 ot(";@ 0x44: SR\n");\r
444 ot(" mov r0,r4\n");\r
445 ot(" bl CycloneGetSr\n");\r
446 ot(" strh r0,[r5],#2\n");\r
447 ot(";@ 0x46: IRQ level\n");\r
448 ot(" ldrb r0,[r4,#0x47]\n");\r
449 ot(" strb r0,[r5],#2\n");\r
450 ot(";@ 0x48: other SP\n");\r
451 ot(" ldr r0,[r4,#0x48]\n");\r
452 ot(" str r0,[r5],#4\n");\r
453 ot(";@ 0x4c: CPU state flags\n");\r
454 ot(" ldr r0,[r4,#0x58]\n");\r
455 ot(" str r0,[r5],#4\n");\r
456 ot(" ldmfd sp!,{r4,r5,pc}\n");\r
457 ot("\n");\r
458\r
459 // --------------\r
460 ot("CycloneUnpack%s\n", ms?"":":");\r
461 ot(" stmfd sp!,{r5,r7,lr}\n");\r
462 ot(" mov r7,r0\n");\r
463 ot(" movs r5,r1\n");\r
464 ot(" beq c_unpack_do_pc\n");\r
465 ot(" mov r3,#16\n");\r
466 ot(";@ 0x00-0x3f: DA registers\n");\r
467 ot("c_unpack_loop%s\n",ms?"":":");\r
468 ot(" ldr r1,[r5],#4\n");\r
469 ot(" subs r3,r3,#1\n");\r
470 ot(" str r1,[r0],#4\n");\r
471 ot(" bne c_unpack_loop\n");\r
472 ot(";@ 0x40: PC\n");\r
473 ot(" ldr r0,[r5],#4 ;@ PC\n");\r
474 ot(" str r0,[r7,#0x40] ;@ handle later\n");\r
475 ot(";@ 0x44: SR\n");\r
476 ot(" ldrh r1,[r5],#2\n");\r
477 ot(" mov r0,r7\n");\r
478 ot(" bl CycloneSetSr\n");\r
479 ot(";@ 0x46: IRQ level\n");\r
480 ot(" ldrb r0,[r5],#2\n");\r
481 ot(" strb r0,[r7,#0x47]\n");\r
482 ot(";@ 0x48: other SP\n");\r
483 ot(" ldr r0,[r5],#4\n");\r
484 ot(" str r0,[r7,#0x48]\n");\r
485 ot(";@ 0x4c: CPU state flags\n");\r
486 ot(" ldr r0,[r5],#4\n");\r
487 ot(" str r0,[r7,#0x58]\n");\r
488 ot("c_unpack_do_pc%s\n",ms?"":":");\r
489 ot(" ldr r0,[r7,#0x40] ;@ unbased PC\n");\r
490#if USE_CHECKPC_CALLBACK\r
491 ot(" mov r1,#0\n");\r
492 ot(" str r1,[r7,#0x60] ;@ Memory base\n");\r
493 #ifdef MEMHANDLERS_DIRECT_PREFIX\r
494 ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);\r
495 #else\r
496 ot(" mov lr,pc\n");\r
497 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
498 #endif\r
499#else\r
500 ot(" ldr r1,[r7,#0x60] ;@ Memory base\n");\r
501 ot(" add r0,r0,r1 ;@ r0 = Memory Base + New PC\n");\r
502#endif\r
503 ot(" str r0,[r7,#0x40] ;@ PC + Memory Base\n");\r
504 ot(" ldmfd sp!,{r5,r7,pc}\n");\r
505 ot("\n");\r
506\r
507 // --------------\r
508 ot("CycloneFlushIrq%s\n", ms?"":":");\r
509 ot(" ldr r1,[r0,#0x44] ;@ Get SR high T_S__III and irq level\n");\r
510 ot(" mov r2,r1,lsr #24 ;@ Get IRQ level\n"); // same as ldrb r0,[r7,#0x47]\r
511 ot(" cmp r2,#6 ;@ irq>6 ?\n");\r
512 ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");\r
513 ot(" cmple r2,r1 ;@ irq<=6: Is irq<=mask ?\n");\r
514 ot(" movle r0,#0\n");\r
515 ot(" bxle lr ;@ no ints\n");\r
516 ot("\n");\r
517 ot(" stmdb sp!,{r4,r5,r7,r8,r10,r11,lr}\n");\r
518 ot(" mov r7,r0\n");\r
519 ot(" mov r0,r2\n");\r
520 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Flags (NZCV)\n");\r
521 ot(" mov r5,#0\n");\r
522 ot(" ldr r4,[r7,#0x40] ;@ r4 = Current PC + Memory Base\n");\r
523 ot(" mov r10,r10,lsl #28 ;@ r10 = Flags 0xf0000000, cpsr format\n");\r
524 ot(" adr r2,CycloneFlushIrqEnd\n");\r
525 ot(" str r2,[r7,#0x98] ;@ set custom CycloneEnd\n");\r
526 ot(" b CycloneDoInterrupt\n");\r
527 ot("\n");\r
528 ot("CycloneFlushIrqEnd%s\n", ms?"":":");\r
529 ot(" rsb r0,r5,#0\n");\r
530 ot(" str r4,[r7,#0x40] ;@ Save Current PC + Memory Base\n");\r
531 ot(" strb r10,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
532 ot(" ldmia sp!,{r4,r5,r7,r8,r10,r11,lr}\n");\r
533 ot(" bx lr\n");\r
534 ot("\n");\r
535 ot("\n");\r
536\r
d9d77995 537 // --------------\r
538 ot(";@ DoInterrupt - r0=IRQ level\n");\r
539 ot("CycloneDoInterruptGoBack%s\n", ms?"":":");\r
540 ot(" sub r4,r4,#2\n");\r
541 ot("CycloneDoInterrupt%s\n", ms?"":":");\r
542 ot(" bic r8,r8,#0xff000000\n");\r
543 ot(" orr r8,r8,r0,lsl #29 ;@ abuse r8\n");\r
544\r
545 // Steps are from "M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL", p. 6-4\r
546 // but their order is based on http://pasti.fxatari.com/68kdocs/68kPrefetch.html\r
547 // 1. Make a temporary copy of the status register and set the status register for exception processing.\r
548 ot(" ldr r2,[r7,#0x58] ;@ state flags\n");\r
549 ot(" and r0,r0,#7\n");\r
550 ot(" orr r3,r0,#0x20 ;@ Supervisor mode + IRQ level\n");\r
551 ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");\r
552#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
553 ot(" orr r2,r2,#4 ;@ set activity bit: 'not processing instruction'\n");\r
554#endif\r
555 ot(" str r2,[r7,#0x58]\n");\r
556 ot(" ldrb r6,[r7,#0x44] ;@ Get old SR high, abuse r6\n");\r
557 ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");\r
6003a768 558 ot("\n");\r
d9d77995 559\r
560 // 3. Save the current processor context.\r
561 ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");\r
562 ot(" ldr r11,[r7,#0x3c] ;@ Get A7\n");\r
563 ot(" tst r6,#0x20\n");\r
564 ot(";@ get our SP:\n");\r
565 ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");\r
566 ot(" streq r11,[r7,#0x48]\n");\r
567 ot(" moveq r11,r2\n");\r
568 ot(";@ Push old PC onto stack\n");\r
569 ot(" sub r0,r11,#4 ;@ Predecremented A7\n");\r
570 ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");\r
571 MemHandler(1,2);\r
572 ot(";@ Push old SR:\n");\r
573 ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");\r
574 ot(" mov r1,r10,lsr #28 ;@ ____NZCV\n");\r
575 ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");\r
576 ot(" tst r2,#1 ;@ 1 if C!=V\n");\r
577 ot(" eorne r1,r1,#3 ;@ ____NZVC\n");\r
578 ot(" and r0,r0,#0x20000000\n");\r
579 ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");\r
580 ot(" orr r1,r1,r6,lsl #8 ;@ Include old SR high\n");\r
581 ot(" sub r0,r11,#6 ;@ Predecrement A7\n");\r
582 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
583 MemHandler(1,1,0,0); // already checked for address error by prev MemHandler\r
6003a768 584 ot("\n");\r
d9d77995 585\r
586 // 2. Obtain the exception vector.\r
587 ot(" mov r11,r8,lsr #29\n");\r
588 ot(" mov r0,r11\n");\r
589#if USE_INT_ACK_CALLBACK\r
590 ot(";@ call IrqCallback if it is defined\n");\r
591#if INT_ACK_NEEDS_STUFF\r
592 ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
593 ot(" mov r1,r10,lsr #28\n");\r
594 ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
595 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
596#endif\r
597 ot(" ldr r3,[r7,#0x8c] ;@ IrqCallback\n");\r
598 ot(" add lr,pc,#4*3\n");\r
599 ot(" tst r3,r3\n");\r
600 ot(" streqb r3,[r7,#0x47] ;@ just clear IRQ if there is no callback\n");\r
601 ot(" mvneq r0,#0 ;@ and simulate -1 return\n");\r
602 ot(" bxne r3\n");\r
603#if INT_ACK_CHANGES_CYCLES\r
604 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
605#endif\r
606 ot(";@ get IRQ vector address:\n");\r
607 ot(" cmn r0,#1 ;@ returned -1?\n");\r
608 ot(" addeq r0,r11,#0x18 ;@ use autovector then\n");\r
609 ot(" cmn r0,#2 ;@ returned -2?\n"); // should be safe as above add should never result in -2\r
610 ot(" moveq r0,#0x18 ;@ use spurious interrupt then\n");\r
611#else // !USE_INT_ACK_CALLBACK\r
6003a768 612 ot(";@ Clear irq:\n");\r
d9d77995 613 ot(" mov r2,#0\n");\r
614 ot(" strb r2,[r7,#0x47]\n");\r
615 ot(" add r0,r0,#0x18 ;@ use autovector\n");\r
616#endif\r
617 ot(" mov r0,r0,lsl #2 ;@ get vector address\n");\r
618 ot("\n");\r
619 ot(" ldr r11,[r7,#0x60] ;@ Get Memory base\n");\r
620 ot(";@ Read IRQ Vector:\n");\r
621 MemHandler(0,2,0,0);\r
622 ot(" tst r0,r0 ;@ uninitialized int vector?\n");\r
623 ot(" moveq r0,#0x3c\n");\r
624 #ifdef MEMHANDLERS_DIRECT_PREFIX\r
625 ot(" bleq %sread32 ;@ Call read32(r0) handler\n", MEMHANDLERS_DIRECT_PREFIX);\r
626 #else\r
627 ot(" moveq lr,pc\n");\r
628 ot(" ldreq pc,[r7,#0x70] ;@ Call read32(r0) handler\n");\r
629 #endif\r
630#if USE_CHECKPC_CALLBACK\r
631 ot(" add lr,pc,#4\n");\r
632 ot(" add r0,r0,r11 ;@ r0 = Memory Base + New PC\n");\r
633 #ifdef MEMHANDLERS_DIRECT_PREFIX\r
634 ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);\r
635 #else\r
636 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
637 #endif\r
638 #if EMULATE_ADDRESS_ERRORS_JUMP\r
639 ot(" mov r4,r0\n");\r
640 #else\r
641 ot(" bic r4,r0,#1\n");\r
642 #endif\r
643#else\r
644 ot(" add r4,r0,r11 ;@ r4 = Memory Base + New PC\n");\r
645 #if EMULATE_ADDRESS_ERRORS_JUMP\r
646 ot(" bic r4,r4,#1\n");\r
647 #endif\r
648#endif\r
6003a768 649 ot("\n");\r
650\r
d9d77995 651 // 4. Obtain a new context and resume instruction processing.\r
652 // note: the obtain part was already done in previous steps\r
653#if EMULATE_ADDRESS_ERRORS_JUMP\r
654 ot(" tst r4,#1\n");\r
655 ot(" bne ExceptionAddressError_r_prg_r4\n");\r
656#endif\r
657 ot(" ldr r6,[r7,#0x54]\n");\r
658 ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
659 ot(" subs r5,r5,#44 ;@ Subtract cycles\n");\r
c204973a 660 ot(" ldrgt pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
d9d77995 661 ot(" b CycloneEnd\n");\r
6003a768 662 ot("\n");\r
d9d77995 663\r
664 // --------------\r
665 // trashes all temp regs\r
666 ot("Exception%s\n", ms?"":":");\r
667 ot(" ;@ Cause an Exception - Vector number in r0\n");\r
6003a768 668 ot(" mov r11,lr ;@ Preserve ARM return address\n");\r
d9d77995 669 ot(" bic r8,r8,#0xff000000\n");\r
670 ot(" orr r8,r8,r0,lsl #24 ;@ abuse r8\n");\r
671\r
672 // 1. Make a temporary copy of the status register and set the status register for exception processing.\r
673 ot(" ldr r6,[r7,#0x44] ;@ Get old SR high, abuse r6\n");\r
674 ot(" ldr r2,[r7,#0x58] ;@ state flags\n");\r
675 ot(" and r3,r6,#0x27 ;@ clear trace and unused flags\n");\r
676 ot(" orr r3,r3,#0x20 ;@ set supervisor mode\n");\r
677 ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");\r
678 ot(" str r2,[r7,#0x58]\n");\r
679 ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");\r
680 ot("\n");\r
681\r
682 // 3. Save the current processor context.\r
683 ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");\r
684 ot(" tst r6,#0x20\n");\r
685 ot(";@ get our SP:\n");\r
686 ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");\r
687 ot(" streq r0,[r7,#0x48]\n");\r
688 ot(" moveq r0,r2\n");\r
689 ot(";@ Push old PC onto stack\n");\r
690 ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");\r
691 ot(" sub r0,r0,#4 ;@ Predecremented A7\n");\r
692 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
693 ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");\r
694 MemHandler(1,2);\r
695 ot(";@ Push old SR:\n");\r
696 ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");\r
697 ot(" mov r1,r10,lsr #28 ;@ ____NZCV\n");\r
698 ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");\r
699 ot(" tst r2,#1 ;@ 1 if C!=V\n");\r
700 ot(" eorne r1,r1,#3 ;@ ____NZVC\n");\r
701 ot(" and r0,r0,#0x20000000\n");\r
702 ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");\r
703 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
704 ot(" orr r1,r1,r6,lsl #8 ;@ Include SR high\n");\r
705 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
706 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
707 MemHandler(1,1,0,0);\r
708 ot("\n");\r
709\r
710 // 2. Obtain the exception vector\r
711 ot(";@ Read Exception Vector:\n");\r
712 ot(" mov r0,r8,lsr #24\n");\r
713 ot(" mov r0,r0,lsl #2\n");\r
714 MemHandler(0,2,0,0);\r
715 ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");\r
716#if USE_CHECKPC_CALLBACK\r
717 ot(" add lr,pc,#4\n");\r
718 ot(" add r0,r0,r3 ;@ r0 = Memory Base + New PC\n");\r
719 #ifdef MEMHANDLERS_DIRECT_PREFIX\r
720 ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);\r
721 #else\r
722 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
723 #endif\r
724 #if EMULATE_ADDRESS_ERRORS_JUMP\r
725 ot(" mov r4,r0\n");\r
726 #else\r
727 ot(" bic r4,r0,#1\n");\r
728 #endif\r
729#else\r
730 ot(" add r4,r0,r3 ;@ r4 = Memory Base + New PC\n");\r
731 #if EMULATE_ADDRESS_ERRORS_JUMP\r
732 ot(" bic r4,r4,#1\n");\r
733 #endif\r
734#endif\r
6003a768 735 ot("\n");\r
d9d77995 736\r
737 // 4. Resume execution.\r
738#if EMULATE_ADDRESS_ERRORS_JUMP\r
739 ot(" tst r4,#1\n");\r
740 ot(" bne ExceptionAddressError_r_prg_r4\n");\r
741#endif\r
742 ot(" ldr r6,[r7,#0x54]\n");\r
743 ot(" bx r11 ;@ Return\n");\r
744 ot("\n");\r
745\r
746 // --------------\r
747#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
748 // first some wrappers: I see no point inlining this code,\r
749 // as it will be executed in really rare cases.\r
750 AddressErrorWrapper('r', "data", 0x11);\r
751 AddressErrorWrapper('r', "prg", 0x12);\r
752 AddressErrorWrapper('w', "data", 0x01);\r
753 // there are no program writes\r
754 // cpu space is only for bus errors?\r
755 ot("ExceptionAddressError_r_prg_r4%s\n", ms?"":":");\r
756 ot(" ldr r1,[r7,#0x44]\n");\r
757 ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");\r
758 ot(" mov r6,#0x12\n");\r
759 ot(" sub r11,r4,r3\n");\r
760 ot(" tst r1,#0x20\n");\r
761 ot(" orrne r6,r6,#4\n");\r
762 ot("\n");\r
763\r
764 ot("ExceptionAddressError%s\n", ms?"":":");\r
765 ot(";@ r6 - info word (without instruction/not bit), r11 - faulting address\n");\r
766\r
767 // 1. Make a temporary copy of the status register and set the status register for exception processing.\r
768 ot(" ldrb r0,[r7,#0x44] ;@ Get old SR high\n");\r
769 ot(" ldr r2,[r7,#0x58] ;@ state flags\n");\r
770 ot(" and r3,r0,#0x27 ;@ clear trace and unused flags\n");\r
771 ot(" orr r3,r3,#0x20 ;@ set supervisor mode\n");\r
772 ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");\r
773 ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");\r
774 ot(" tst r2,#4\n");\r
775 ot(" orrne r6,r6,#8 ;@ complete info word\n");\r
776 ot(" orr r2,r2,#4 ;@ set activity bit: 'not processing instruction'\n");\r
777#if EMULATE_HALT\r
778 ot(" tst r2,#8\n");\r
779 ot(" orrne r2,r2,#0x10 ;@ HALT\n");\r
780 ot(" orr r2,r2,#8 ;@ processing address error\n");\r
781 ot(" str r2,[r7,#0x58]\n");\r
782 ot(" movne r5,#0\n");\r
783 ot(" bne CycloneEndNoBack ;@ bye bye\n");\r
784#else\r
785 ot(" str r2,[r7,#0x58]\n");\r
786#endif\r
787 ot(" and r10,r10,#0xf0000000\n");\r
788 ot(" orr r10,r10,r0,lsl #4 ;@ some preparations for SR push\n");\r
789 ot("\n");\r
790\r
791 // 3. Save the current processor context + additional information.\r
792 ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");\r
793 ot(" tst r10,#0x200\n");\r
794 ot(";@ get our SP:\n");\r
795 ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");\r
796 ot(" streq r0,[r7,#0x48]\n");\r
797 ot(" moveq r0,r2\n");\r
798 // PC\r
799 ot(";@ Push old PC onto stack\n");\r
800 ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");\r
801 ot(" sub r0,r0,#4 ;@ Predecremented A7\n");\r
802 ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");\r
803 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
804 MemHandler(1,2,0,EMULATE_HALT);\r
805 // SR\r
806 ot(";@ Push old SR:\n");\r
807 ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");\r
808 ot(" mov r1,r10,ror #28 ;@ ____NZCV\n");\r
809 ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");\r
810 ot(" tst r2,#1 ;@ 1 if C!=V\n");\r
811 ot(" eorne r1,r1,#3 ;@ ____NZVC\n");\r
812 ot(" and r0,r0,#0x20000000\n");\r
813 ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");\r
814 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
815 ot(" and r10,r10,#0xf0000000\n");\r
816 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
817 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
818 MemHandler(1,1,0,0);\r
819 // IR (instruction register)\r
820 ot(";@ Push IR:\n");\r
821 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
822 ot(" mov r1,r8\n");\r
823 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
824 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
825 MemHandler(1,1,0,0);\r
826 // access address\r
827 ot(";@ Push address:\n");\r
828 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
829 ot(" mov r1,r11\n");\r
830 ot(" sub r0,r0,#4 ;@ Predecrement A7\n");\r
831 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
832 MemHandler(1,2,0,0);\r
833 // information word\r
834 ot(";@ Push info word:\n");\r
835 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
836 ot(" mov r1,r6\n");\r
837 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
838 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
839 MemHandler(1,1,0,0);\r
840 ot("\n");\r
841\r
842 // 2. Obtain the exception vector\r
843 ot(";@ Read Exception Vector:\n");\r
844 ot(" mov r0,#0x0c\n");\r
845 MemHandler(0,2,0,0);\r
846 ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");\r
847#if USE_CHECKPC_CALLBACK\r
848 ot(" add lr,pc,#4\n");\r
849 ot(" add r0,r0,r3 ;@ r0 = Memory Base + New PC\n");\r
850 #ifdef MEMHANDLERS_DIRECT_PREFIX\r
851 ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);\r
852 #else\r
853 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
854 #endif\r
855 ot(" mov r4,r0\n");\r
856#else\r
857 ot(" add r4,r0,r3 ;@ r4 = Memory Base + New PC\n");\r
858#endif\r
859 ot("\n");\r
860\r
861#if EMULATE_ADDRESS_ERRORS_JUMP && EMULATE_HALT\r
862 ot(" tst r4,#1\n");\r
863 ot(" bne ExceptionAddressError_r_prg_r4\n");\r
864#else\r
865 ot(" bic r4,r4,#1\n");\r
866#endif\r
867\r
868 // 4. Resume execution.\r
869 ot(" ldr r6,[r7,#0x54]\n");\r
870 ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
871 ot(" subs r5,r5,#50 ;@ Subtract cycles\n");\r
c204973a 872 ot(" ldrgt pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
d9d77995 873 ot(" b CycloneEnd\n");\r
874 ot("\n");\r
875#endif\r
876\r
877 // --------------\r
878#if EMULATE_TRACE\r
879 // expects srh and irq level in r1, next opcode already fetched to r8\r
880 ot("CycloneDoTraceWithChecks%s\n", ms?"":":");\r
881 ot(" ldr r0,[r7,#0x58]\n");\r
882 ot(" cmp r5,#0\n");\r
883 ot(" orr r0,r0,#2 ;@ go to trace mode\n");\r
884 ot(" str r0,[r7,#0x58]\n");\r
c204973a 885 ot(" ble CycloneEnd\n"); // should take care of situation where we come here when already tracing\r
d9d77995 886 ot(";@ CheckInterrupt:\n");\r
887 ot(" movs r0,r1,lsr #24 ;@ Get IRQ level\n");\r
888 ot(" beq CycloneDoTrace\n");\r
889 ot(" cmp r0,#6 ;@ irq>6 ?\n");\r
890 ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");\r
891 ot(" cmple r0,r1 ;@ irq<=6: Is irq<=mask ?\n");\r
892 ot(" bgt CycloneDoInterruptGoBack\n");\r
893 ot("\n");\r
894\r
895 // expects next opcode to be already fetched to r8\r
896 ot("CycloneDoTrace%s\n", ms?"":":");\r
897 ot(" str r5,[r7,#0x9c] ;@ save cycles\n");\r
898 ot(" ldr r1,[r7,#0x98]\n");\r
899 ot(" mov r5,#0\n");\r
900 ot(" str r1,[r7,#0xa0]\n");\r
901 ot(" adr r0,TraceEnd\n");\r
902 ot(" str r0,[r7,#0x98] ;@ store TraceEnd as CycloneEnd hadler\n");\r
903 ot(" ldr pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
904 ot("\n");\r
905\r
906 ot("TraceEnd%s\n", ms?"":":");\r
907 ot(" ldr r2,[r7,#0x58]\n");\r
908 ot(" ldr r0,[r7,#0x9c] ;@ restore cycles\n");\r
909 ot(" ldr r1,[r7,#0xa0] ;@ old CycloneEnd handler\n");\r
910 ot(" mov r10,r10,lsl #28\n");\r
911 ot(" add r5,r0,r5\n");\r
912 ot(" str r1,[r7,#0x98]\n");\r
913 ot(";@ still tracing?\n"); // exception might have happend\r
914 ot(" tst r2,#2\n");\r
915 ot(" beq TraceDisabled\n");\r
916 ot(";@ trace exception\n");\r
917#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
918 ot(" ldr r1,[r7,#0x58]\n");\r
919 ot(" mov r0,#9\n");\r
920 ot(" orr r1,r1,#4 ;@ set activity bit: 'not processing instruction'\n");\r
921 ot(" str r1,[r7,#0x58]\n");\r
922#else\r
923 ot(" mov r0,#9\n");\r
924#endif\r
925 ot(" bl Exception\n");\r
926 ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
927 ot(" subs r5,r5,#34 ;@ Subtract cycles\n");\r
c204973a 928 ot(" ldrgt pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
d9d77995 929 ot(" b CycloneEnd\n");\r
930 ot("\n");\r
931 ot("TraceDisabled%s\n", ms?"":":");\r
932 ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
933 ot(" cmp r5,#0\n");\r
c204973a 934 ot(" ldrgt pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
d9d77995 935 ot(" b CycloneEnd\n");\r
936 ot("\n");\r
937#endif\r
6003a768 938}\r
939\r
940// ---------------------------------------------------------------------------\r
941// Call Read(r0), Write(r0,r1) or Fetch(r0)\r
d9d77995 942// Trashes r0-r3,r12,lr\r
943int MemHandler(int type,int size,int addrreg,int need_addrerr_check)\r
6003a768 944{\r
d9d77995 945 int func=0x68+type*0xc+(size<<2); // Find correct offset\r
946 char what[32];\r
6003a768 947\r
d9d77995 948#if MEMHANDLERS_NEED_FLAGS\r
949 ot(" mov r3,r10,lsr #28\n");\r
950 ot(" strb r3,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
951#endif\r
952 FlushPC();\r
6003a768 953\r
d9d77995 954#if (MEMHANDLERS_ADDR_MASK & 0xff000000)\r
955 ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0xff000000);\r
956 addrreg=0;\r
957#endif\r
958#if (MEMHANDLERS_ADDR_MASK & 0x00ff0000)\r
959 ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0x00ff0000);\r
960 addrreg=0;\r
961#endif\r
962#if (MEMHANDLERS_ADDR_MASK & 0x0000ff00)\r
963 ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0x0000ff00);\r
964 addrreg=0;\r
965#endif\r
966#if (MEMHANDLERS_ADDR_MASK & 0x000000ff)\r
967 ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0x000000ff);\r
968 addrreg=0;\r
969#endif\r
970\r
971#if EMULATE_ADDRESS_ERRORS_IO\r
972 if (size > 0 && need_addrerr_check)\r
973 {\r
974 ot(" add lr,pc,#4*%i\n", addrreg==0?2:3); // helps to prevent interlocks\r
975 if (addrreg != 0) ot(" mov r0,r%i\n", addrreg);\r
976 ot(" tst r0,#1 ;@ address error?\n");\r
977 switch (type) {\r
978 case 0: ot(" bne ExceptionAddressError_r_data\n"); break;\r
979 case 1: ot(" bne ExceptionAddressError_w_data\n"); break;\r
980 case 2: ot(" bne ExceptionAddressError_r_prg\n"); break;\r
981 }\r
982 }\r
983 else\r
984#endif\r
985\r
986 sprintf(what, "%s%d", type==0 ? "read" : (type==1 ? "write" : "fetch"), 8<<size);\r
987#ifdef MEMHANDLERS_DIRECT_PREFIX\r
988 if (addrreg != 0)\r
989 ot(" mov r0,r%i\n", addrreg);\r
990 ot(" bl %s%s ;@ Call ", MEMHANDLERS_DIRECT_PREFIX, what);\r
991 (void)func; // avoid warning\r
992#else\r
993 if (addrreg != 0)\r
994 {\r
995 ot(" add lr,pc,#4\n");\r
996 ot(" mov r0,r%i\n", addrreg);\r
997 }\r
998 else\r
999 ot(" mov lr,pc\n");\r
6003a768 1000 ot(" ldr pc,[r7,#0x%x] ;@ Call ",func);\r
d9d77995 1001#endif\r
6003a768 1002\r
1003 // Document what we are calling:\r
d9d77995 1004 if (type==1) ot("%s(r0,r1)",what);\r
1005 else ot("%s(r0)", what);\r
6003a768 1006 ot(" handler\n");\r
1007\r
d9d77995 1008#if MEMHANDLERS_CHANGE_FLAGS\r
1009 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");\r
1010 ot(" mov r10,r10,lsl #28\n");\r
1011#endif\r
1012#if MEMHANDLERS_CHANGE_PC\r
1013 ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
1014#endif\r
1015\r
6003a768 1016 return 0;\r
1017}\r
1018\r
1019static void PrintOpcodes()\r
1020{\r
1021 int op=0;\r
d9d77995 1022\r
6003a768 1023 printf("Creating Opcodes: [");\r
1024\r
1025 ot(";@ ---------------------------- Opcodes ---------------------------\n");\r
1026\r
1027 // Emit null opcode:\r
1028 ot("Op____%s ;@ Called if an opcode is not recognised\n", ms?"":":");\r
d9d77995 1029#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
1030 ot(" ldr r1,[r7,#0x58]\n");\r
1031 ot(" sub r4,r4,#2\n");\r
1032 ot(" orr r1,r1,#4 ;@ set activity bit: 'not processing instruction'\n");\r
1033 ot(" str r1,[r7,#0x58]\n");\r
1034#else\r
1035 ot(" sub r4,r4,#2\n");\r
1036#endif\r
1037#if USE_UNRECOGNIZED_CALLBACK\r
1038 ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
1039 ot(" mov r1,r10,lsr #28\n");\r
1040 ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
1041 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
1042 ot(" ldr r11,[r7,#0x94] ;@ UnrecognizedCallback\n");\r
1043 ot(" tst r11,r11\n");\r
1044 ot(" movne lr,pc\n");\r
1045 ot(" movne pc,r11 ;@ call UnrecognizedCallback if it is defined\n");\r
1046 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");\r
1047 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
1048 ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
1049 ot(" mov r10,r10,lsl #28\n");\r
1050 ot(" tst r0,r0\n");\r
1051 ot(" moveq r0,#4\n");\r
1052 ot(" bleq Exception\n");\r
1053#else\r
1054 ot(" mov r0,#4\n");\r
1055 ot(" bl Exception\n");\r
1056#endif\r
1057 ot("\n");\r
1058 Cycles=34;\r
1059 OpEnd();\r
1060\r
1061 // Unrecognised a-line and f-line opcodes throw an exception:\r
1062 ot("Op__al%s ;@ Unrecognised a-line opcode\n", ms?"":":");\r
1063 ot(" sub r4,r4,#2\n");\r
1064#if USE_AFLINE_CALLBACK\r
1065 ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
1066 ot(" mov r1,r10,lsr #28\n");\r
1067 ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
1068 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
1069 ot(" ldr r11,[r7,#0x94] ;@ UnrecognizedCallback\n");\r
1070 ot(" tst r11,r11\n");\r
1071 ot(" movne lr,pc\n");\r
1072 ot(" movne pc,r11 ;@ call UnrecognizedCallback if it is defined\n");\r
1073 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");\r
1074 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
1075 ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
1076 ot(" mov r10,r10,lsl #28\n");\r
1077 ot(" tst r0,r0\n");\r
1078 ot(" moveq r0,#0x0a\n");\r
1079 ot(" bleq Exception\n");\r
1080#else\r
1081 ot(" mov r0,#0x0a\n");\r
1082 ot(" bl Exception\n");\r
1083#endif\r
1084 ot("\n");\r
1085 Cycles=4;\r
1086 OpEnd();\r
1087\r
1088 ot("Op__fl%s ;@ Unrecognised f-line opcode\n", ms?"":":");\r
1089 ot(" sub r4,r4,#2\n");\r
1090#if USE_AFLINE_CALLBACK\r
1091 ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
1092 ot(" mov r1,r10,lsr #28\n");\r
1093 ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
1094 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
1095 ot(" ldr r11,[r7,#0x94] ;@ UnrecognizedCallback\n");\r
1096 ot(" tst r11,r11\n");\r
1097 ot(" movne lr,pc\n");\r
1098 ot(" movne pc,r11 ;@ call UnrecognizedCallback if it is defined\n");\r
1099 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");\r
1100 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
1101 ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
1102 ot(" mov r10,r10,lsl #28\n");\r
1103 ot(" tst r0,r0\n");\r
1104 ot(" moveq r0,#0x0b\n");\r
1105 ot(" bleq Exception\n");\r
1106#else\r
1107 ot(" mov r0,#0x0b\n");\r
1108 ot(" bl Exception\n");\r
1109#endif\r
1110 ot("\n");\r
1111 Cycles=4;\r
1112 OpEnd();\r
1113\r
6003a768 1114\r
d9d77995 1115 for (op=0;op<hot_opcode_count;op++)\r
1116 OpAny(hot_opcodes[op]);\r
6003a768 1117\r
1118 for (op=0;op<0x10000;op++)\r
1119 {\r
1120 if ((op&0xfff)==0) { printf("%x",op>>12); fflush(stdout); } // Update progress\r
1121\r
d9d77995 1122 if (!is_op_hot(op))\r
1123 OpAny(op);\r
6003a768 1124 }\r
1125\r
1126 ot("\n");\r
1127\r
1128 printf("]\n");\r
1129}\r
1130\r
d9d77995 1131// helper\r
1132static void ott(const char *str, int par, const char *nl, int nlp, int counter, int size)\r
1133{\r
1134 switch(size) {\r
1135 case 0: if((counter&7)==0) ot(ms?" dcb ":" .byte "); break;\r
1136 case 1: if((counter&7)==0) ot(ms?" dcw ":" .hword "); break;\r
1137 case 2: if((counter&7)==0) ot(ms?" dcd ":" .long "); break;\r
1138 }\r
1139 ot(str, par);\r
1140 if((counter&7)==7) ot(nl,nlp); else ot(",");\r
1141}\r
1142\r
6003a768 1143static void PrintJumpTable()\r
1144{\r
1145 int i=0,op=0,len=0;\r
1146\r
1147 ot(";@ -------------------------- Jump Table --------------------------\n");\r
6003a768 1148\r
d9d77995 1149 // space for decompressed table\r
1150 ot(ms?" area |.data|, data\n":" .data\n .align 4\n\n");\r
6003a768 1151\r
d9d77995 1152#if COMPRESS_JUMPTABLE\r
1153 int handlers=0,reps=0,*indexes,ip,u,out;\r
1154 // use some weird compression on the jump table\r
1155 indexes=(int *)malloc(0x10000*4);\r
1156 if(!indexes) { printf("ERROR: out of memory\n"); exit(1); }\r
1157 len=0x10000;\r
6003a768 1158\r
d9d77995 1159 ot("CycloneJumpTab%s\n", ms?"":":");\r
1160 if(ms) {\r
1161 for(i = 0; i < 0xa000/8; i++)\r
1162 ot(" dcd 0,0,0,0,0,0,0,0\n");\r
1163 } else\r
1164 ot(" .rept 0x%x\n .long 0,0,0,0,0,0,0,0\n .endr\n", 0xa000/8);\r
1165\r
1166 // hanlers live in "a-line" part of the table\r
1167 // first output nop,a-line,f-line handlers\r
1168 ot(ms?" dcd Op____,Op__al,Op__fl,":" .long Op____,Op__al,Op__fl,");\r
1169 handlers=3;\r
1170\r
1171 for(i=0;i<len;i++)\r
1172 {\r
1173 op=CyJump[i];\r
1174\r
1175 for(u=i-1; u>=0; u--) if(op == CyJump[u]) break; // already done with this op?\r
1176 if(u==-1 && op >= 0) {\r
1177 ott("Op%.4x",op," ;@ %.4x\n",i,handlers,2);\r
1178 indexes[op] = handlers;\r
1179 handlers++;\r
1180 }\r
1181 }\r
1182 if(handlers&7) {\r
1183 fseek(AsmFile, -1, SEEK_CUR); // remove last comma\r
1184 for(i = 8-(handlers&7); i > 0; i--)\r
1185 ot(",000000");\r
1186 ot("\n");\r
1187 }\r
1188 if(ms) {\r
1189 for(i = (0x4000-handlers)/8; i > 0; i--)\r
1190 ot(" dcd 0,0,0,0,0,0,0,0\n");\r
1191 } else {\r
1192 ot(ms?"":" .rept 0x%x\n .long 0,0,0,0,0,0,0,0\n .endr\n", (0x4000-handlers)/8);\r
1193 }\r
1194 printf("total distinct hanlers: %i\n",handlers);\r
1195 // output data\r
1196 for(i=0,ip=0; i < 0xf000; i++, ip++) {\r
1197 op=CyJump[i];\r
1198 if(op == -2) {\r
1199 // it must skip a-line area, because we keep our data there\r
1200 ott("0x%.4x", handlers<<4, "\n",0,ip++,1);\r
1201 ott("0x%.4x", 0x1000, "\n",0,ip,1);\r
1202 i+=0xfff;\r
1203 continue;\r
1204 }\r
1205 for(reps=1; i < 0xf000; i++, reps++) if(op != CyJump[i+1]) break;\r
1206 if(op>=0) out=indexes[op]<<4; else out=0; // unrecognised\r
1207 if(reps <= 0xe || reps==0x10) {\r
1208 if(reps!=0x10) out|=reps; else out|=0xf; // 0xf means 0x10 (0xf appeared to be unused anyway)\r
1209 ott("0x%.4x", out, "\n",0,ip,1);\r
1210 } else {\r
1211 ott("0x%.4x", out, "\n",0,ip++,1);\r
1212 ott("0x%.4x", reps,"\n",0,ip,1);\r
1213 }\r
1214 }\r
1215 if(ip&1) ott("0x%.4x", 0, "\n",0,ip++,1);\r
1216 if(ip&7) fseek(AsmFile, -1, SEEK_CUR); // remove last comma\r
1217 if(ip&7) {\r
1218 for(i = 8-(ip&7); i > 0; i--)\r
1219 ot(",0x0000");\r
1220 }\r
1221 ot("\n");\r
1222 if(ms) {\r
1223 for(i = (0x2000-ip/2)/8+1; i > 0; i--)\r
1224 ot(" dcd 0,0,0,0,0,0,0,0\n");\r
1225 } else {\r
1226 ot(" .rept 0x%x\n .long 0,0,0,0,0,0,0,0\n .endr\n", (0x2000-ip/2)/8+1);\r
1227 }\r
1228 ot("\n");\r
1229 free(indexes);\r
1230#else\r
1231 ot("CycloneJumpTab%s\n", ms?"":":");\r
1232 len=0xfffe; // Hmmm, armasm 2.50.8684 messes up with a 0x10000 long jump table\r
1233 // notaz: same thing with GNU as 2.9-psion-98r2 (reloc overflow)\r
1234 // this is due to COFF objects using only 2 bytes for reloc count\r
1235\r
1236 for (i=0;i<len;i++)\r
1237 {\r
1238 op=CyJump[i];\r
1239\r
1240 if(op>=0) ott("Op%.4x",op," ;@ %.4x\n",i-7,i,2);\r
1241 else if(op==-2) ott("Op__al",0, " ;@ %.4x\n",i-7,i,2);\r
1242 else if(op==-3) ott("Op__fl",0, " ;@ %.4x\n",i-7,i,2);\r
1243 else ott("Op____",0, " ;@ %.4x\n",i-7,i,2);\r
1244 }\r
1245 if(i&7) fseek(AsmFile, -1, SEEK_CUR); // remove last comma\r
1246\r
1247 ot("\n");\r
1248 ot(";@ notaz: we don't want to crash if we run into those 2 missing opcodes\n");\r
1249 ot(";@ so we leave this pattern to patch it later\n");\r
1250 ot("%s 0x78563412\n", ms?" dcd":" .long");\r
1251 ot("%s 0x56341290\n", ms?" dcd":" .long");\r
1252#endif\r
6003a768 1253}\r
1254\r
1255static int CycloneMake()\r
1256{\r
d9d77995 1257 int i;\r
1258 const char *name="Cyclone.s";\r
1259 const char *globl=ms?"export":".global";\r
1260\r
6003a768 1261 // Open the assembly file\r
1262 if (ms) name="Cyclone.asm";\r
1263 AsmFile=fopen(name,"wt"); if (AsmFile==NULL) return 1;\r
d9d77995 1264\r
6003a768 1265 printf("Making %s...\n",name);\r
1266\r
1267 ot("\n;@ Cyclone 68000 Emulator v%x.%.3x - Assembler Output\n\n",CycloneVer>>12,CycloneVer&0xfff);\r
1268\r
d9d77995 1269 ot(";@ Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)\n");\r
1270 ot(";@ Copyright (c) 2005-2011 Gražvydas \"notaz\" Ignotas (notasas (at) gmail.com)\n\n");\r
c41b9b97 1271\r
6003a768 1272 ot(";@ This code is licensed under the GNU General Public License version 2.0 and the MAME License.\n");\r
1273 ot(";@ You can choose the license that has the most advantages for you.\n\n");\r
1274 ot(";@ SVN repository can be found at http://code.google.com/p/cyclone68000/\n\n");\r
1275\r
1276 CyJump=(int *)malloc(0x40000); if (CyJump==NULL) return 1;\r
1277 memset(CyJump,0xff,0x40000); // Init to -1\r
d9d77995 1278 for(i=0xa000; i<0xb000; i++) CyJump[i] = -2; // a-line emulation\r
1279 for(i=0xf000; i<0x10000; i++) CyJump[i] = -3; // f-line emulation\r
6003a768 1280\r
d9d77995 1281 ot(ms?" area |.text|, code\n":" .text\n .align 4\n\n");\r
b889883d 1282 ot(" %s CycloneInitJT\n",globl);\r
1283 ot(" %s CycloneResetJT\n",globl);\r
d9d77995 1284 ot(" %s CycloneRun\n",globl);\r
1285 ot(" %s CycloneSetSr\n",globl);\r
1286 ot(" %s CycloneGetSr\n",globl);\r
1287 ot(" %s CycloneFlushIrq\n",globl);\r
1288 ot(" %s CyclonePack\n",globl);\r
1289 ot(" %s CycloneUnpack\n",globl);\r
1290 ot(" %s CycloneVer\n",globl);\r
5fc93bdd 1291 ot(" %s CycloneJumpTab\n",globl);\r
d9d77995 1292#if (CYCLONE_FOR_GENESIS == 2)\r
b889883d 1293 ot(" %s CycloneSetRealTAS_JT\n",globl);\r
d9d77995 1294 ot(" %s CycloneDoInterrupt\n",globl);\r
1295 ot(" %s CycloneDoTrace\n",globl);\r
d9d77995 1296 ot(" %s Op____\n",globl);\r
c6237d9e 1297 ot(" %s Op6002\n",globl);\r
1298 ot(" %s Op6602\n",globl);\r
1299 ot(" %s Op6702\n",globl);\r
d9d77995 1300#endif\r
1301 ot("\n");\r
1302 ot(ms?"CycloneVer dcd 0x":"CycloneVer: .long 0x");\r
1303 ot("%.4x\n",CycloneVer);\r
6003a768 1304 ot("\n");\r
1305\r
1306 PrintFramework();\r
d9d77995 1307 arm_op_count = 0;\r
6003a768 1308 PrintOpcodes();\r
d9d77995 1309 printf("~%i ARM instructions used for opcode handlers\n", arm_op_count);\r
6003a768 1310 PrintJumpTable();\r
1311\r
1312 if (ms) ot(" END\n");\r
1313\r
d9d77995 1314 ot("\n\n;@ vim:filetype=armasm\n");\r
1315\r
6003a768 1316 fclose(AsmFile); AsmFile=NULL;\r
1317\r
d9d77995 1318#if 0\r
6003a768 1319 printf("Assembling...\n");\r
1320 // Assemble the file\r
1321 if (ms) system("armasm Cyclone.asm");\r
1322 else system("as -o Cyclone.o Cyclone.s");\r
1323 printf("Done!\n\n");\r
d9d77995 1324#endif\r
6003a768 1325\r
1326 free(CyJump);\r
1327 return 0;\r
1328}\r
1329\r
1330int main()\r
1331{\r
1332 printf("\n Cyclone 68000 Emulator v%x.%.3x - Core Creator\n\n",CycloneVer>>12,CycloneVer&0xfff);\r
1333\r
d9d77995 1334 // Make GAS or ARMASM version\r
1335 CycloneMake();\r
6003a768 1336 return 0;\r
1337}\r
d9d77995 1338\r
68000 emulator written in ARM 32-bit assembly