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add fixup for uncompressed jumptable
[cyclone68000.git] / Main.cpp
CommitLineData
6003a768 1\r
619b1824 2// This file is part of the Cyclone 68000 Emulator\r
3\r
d9d77995 4// Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)\r
5// Copyright (c) 2005-2011 Gražvydas "notaz" Ignotas (notasas (at) gmail.com)\r
c41b9b97 6\r
619b1824 7// This code is licensed under the GNU General Public License version 2.0 and the MAME License.\r
8// You can choose the license that has the most advantages for you.\r
9\r
10// SVN repository can be found at http://code.google.com/p/cyclone68000/\r
11\r
d9d77995 12\r
6003a768 13#include "app.h"\r
14\r
15static FILE *AsmFile=NULL;\r
16\r
d9d77995 17static int CycloneVer=0x0099; // Version number of library\r
6003a768 18int *CyJump=NULL; // Jump table\r
d9d77995 19int ms=USE_MS_SYNTAX; // If non-zero, output in Microsoft ARMASM format\r
20const char * const Narm[4]={ "b", "h","",""}; // Normal ARM Extensions for operand sizes 0,1,2\r
21const char * const Sarm[4]={"sb","sh","",""}; // Sign-extend ARM Extensions for operand sizes 0,1,2\r
22int Cycles; // Current cycles for opcode\r
23int pc_dirty; // something changed PC during processing\r
24int arm_op_count;\r
25\r
26// opcodes often used by games\r
27static const unsigned short hot_opcodes[] = {\r
c6237d9e 28 0x6702, // beq $3\r
29 0x6602, // bne $3\r
d9d77995 30 0x51c8, // dbra Dn, $2\r
31 0x4a38, // tst.b $0.w\r
32 0xd040, // add.w Dn, Dn\r
33 0x4a79, // tst.w $0.l\r
34 0x0240, // andi.w #$0, D0\r
35 0x2038, // move.l $0.w, D0\r
36 0xb0b8, // cmp.l $0.w, D0\r
c6237d9e 37 0x6002, // bra $3\r
d9d77995 38 0x30c0, // move.w D0, (A0)+\r
39 0x3028, // move.w ($0,A0), D0\r
40 0x0c40, // cmpi.w #$0, D0\r
41 0x0c79, // cmpi.w #$0, $0.l\r
42 0x4e75, // rts\r
43 0x4e71, // nop\r
44 0x3000, // move.w D0, D0\r
45 0x0839, // btst #$0, $0.l\r
46 0x7000, // moveq #$0, D0\r
47 0x3040, // movea.w D0, A0\r
48 0x0838, // btst #$0, $0.w\r
49 0x4a39, // tst.b $0.l\r
50 0x33d8, // move.w (A0)+, $0.l\r
51 0x6700, // beq $2\r
52 0xb038, // cmp.b $0.w, D0\r
53 0x3039, // move.w $0.l, D0\r
54 0x4840, // swap D0\r
c6237d9e 55 0x6102, // bsr $3\r
d9d77995 56 0x6100, // bsr $2\r
57 0x5e40, // addq.w #7, D0\r
58 0x1039, // move.b $0.l, D0\r
59 0x20c0, // move.l D0, (A0)+\r
60 0x1018, // move.b (A0)+, D0\r
61 0x30d0, // move.w (A0), (A0)+\r
62 0x3080, // move.w D0, (A0)\r
63 0x3018, // move.w (A0)+, D0\r
64 0xc040, // and.w D0, D0\r
65 0x3180, // move.w D0, (A0,D0.w)\r
66 0x1198, // move.b (A0)+, (A0,D0.w)\r
c6237d9e 67 0x6502, // bcs $3\r
d9d77995 68 0x6500, // bcs $2\r
c6237d9e 69 0x6402, // bcc $3\r
70 0x6a02, // bpl $3\r
d9d77995 71 0x41f0, // lea (A0,D0.w), A0\r
72 0x4a28, // tst.b ($0,A0)\r
73 0x0828, // btst #$0, ($0,A0)\r
74 0x0640, // addi.w #$0, D0\r
75 0x10c0, // move.b D0, (A0)+\r
76 0x10d8, // move.b (A0)+, (A0)+\r
77};\r
78#define hot_opcode_count (int)(sizeof(hot_opcodes) / sizeof(hot_opcodes[0]))\r
79\r
80static int is_op_hot(int op)\r
81{\r
82 int i;\r
83 for (i = 0; i < hot_opcode_count; i++)\r
84 if (op == hot_opcodes[i])\r
85 return 1;\r
86 return 0;\r
87}\r
6003a768 88\r
c30e2e2d 89void ot(const char *format, ...)\r
6003a768 90{\r
c30e2e2d 91 va_list valist;\r
d9d77995 92 int i, len;\r
93\r
94 // notaz: stop me from leaving newlines in the middle of format string\r
95 // and generating bad code\r
96 for(i=0, len=strlen(format); i < len && format[i] != '\n'; i++);\r
97 if(i < len-1 && format[len-1] != '\n') printf("\nWARNING: possible improper newline placement:\n%s\n", format);\r
98\r
99 if (format[0] == ' ' && format[1] == ' ' && format[2] != ' ' && format[2] != '.')\r
100 arm_op_count++;\r
101\r
6003a768 102 va_start(valist,format);\r
103 if (AsmFile) vfprintf(AsmFile,format,valist);\r
104 va_end(valist);\r
105}\r
106\r
107void ltorg()\r
108{\r
109 if (ms) ot(" LTORG\n");\r
110 else ot(" .ltorg\n");\r
111}\r
112\r
d9d77995 113#if (CYCLONE_FOR_GENESIS == 2)\r
114// r12=ptr to tas in table, trashes r0,r1\r
115static void ChangeTAS(int norm)\r
6003a768 116{\r
d9d77995 117 ot(" ldr r0,=Op4ad0%s\n",norm?"_":"");\r
118 ot(" mov r1,#8\n");\r
119 ot("setrtas_loop%i0%s ;@ 4ad0-4ad7\n",norm,ms?"":":");\r
120 ot(" subs r1,r1,#1\n");\r
121 ot(" str r0,[r12],#4\n");\r
122 ot(" bne setrtas_loop%i0\n",norm);\r
123 ot(" ldr r0,=Op4ad8%s\n",norm?"_":"");\r
124 ot(" mov r1,#7\n");\r
125 ot("setrtas_loop%i1%s ;@ 4ad8-4ade\n",norm,ms?"":":");\r
126 ot(" subs r1,r1,#1\n");\r
127 ot(" str r0,[r12],#4\n");\r
128 ot(" bne setrtas_loop%i1\n",norm);\r
129 ot(" ldr r0,=Op4adf%s\n",norm?"_":"");\r
130 ot(" str r0,[r12],#4\n");\r
131 ot(" ldr r0,=Op4ae0%s\n",norm?"_":"");\r
132 ot(" mov r1,#7\n");\r
133 ot("setrtas_loop%i2%s ;@ 4ae0-4ae6\n",norm,ms?"":":");\r
134 ot(" subs r1,r1,#1\n");\r
135 ot(" str r0,[r12],#4\n");\r
136 ot(" bne setrtas_loop%i2\n",norm);\r
137 ot(" ldr r0,=Op4ae7%s\n",norm?"_":"");\r
138 ot(" str r0,[r12],#4\n");\r
139 ot(" ldr r0,=Op4ae8%s\n",norm?"_":"");\r
140 ot(" mov r1,#8\n");\r
141 ot("setrtas_loop%i3%s ;@ 4ae8-4aef\n",norm,ms?"":":");\r
142 ot(" subs r1,r1,#1\n");\r
143 ot(" str r0,[r12],#4\n");\r
144 ot(" bne setrtas_loop%i3\n",norm);\r
145 ot(" ldr r0,=Op4af0%s\n",norm?"_":"");\r
146 ot(" mov r1,#8\n");\r
147 ot("setrtas_loop%i4%s ;@ 4af0-4af7\n",norm,ms?"":":");\r
148 ot(" subs r1,r1,#1\n");\r
149 ot(" str r0,[r12],#4\n");\r
150 ot(" bne setrtas_loop%i4\n",norm);\r
151 ot(" ldr r0,=Op4af8%s\n",norm?"_":"");\r
152 ot(" str r0,[r12],#4\n");\r
153 ot(" ldr r0,=Op4af9%s\n",norm?"_":"");\r
154 ot(" str r0,[r12],#4\n");\r
6003a768 155}\r
d9d77995 156#endif\r
6003a768 157\r
d9d77995 158#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
159static void AddressErrorWrapper(char rw, const char *dataprg, int iw)\r
6003a768 160{\r
d9d77995 161 ot("ExceptionAddressError_%c_%s%s\n", rw, dataprg, ms?"":":");\r
162 ot(" ldr r1,[r7,#0x44]\n");\r
163 ot(" mov r6,#0x%02x\n", iw);\r
164 ot(" mov r11,r0\n");\r
165 ot(" tst r1,#0x20\n");\r
166 ot(" orrne r6,r6,#4\n");\r
167 ot(" b ExceptionAddressError\n");\r
6003a768 168 ot("\n");\r
169}\r
d9d77995 170#endif\r
171\r
172void FlushPC(void)\r
173{\r
174#if MEMHANDLERS_NEED_PC\r
175 if (pc_dirty)\r
176 ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
177#endif\r
178 pc_dirty = 0;\r
179}\r
6003a768 180\r
181static void PrintFramework()\r
182{\r
d9d77995 183 int state_flags_to_check = 1; // stopped\r
184#if EMULATE_TRACE\r
185 state_flags_to_check |= 2; // tracing\r
186#endif\r
187#if EMULATE_HALT\r
188 state_flags_to_check |= 0x10; // halted\r
189#endif\r
190\r
6003a768 191 ot(";@ --------------------------- Framework --------------------------\n");\r
192 if (ms) ot("CycloneRun\n");\r
193 else ot("CycloneRun:\n");\r
194\r
d9d77995 195 ot(" stmdb sp!,{r4-r8,r10,r11,lr}\n");\r
6003a768 196\r
197 ot(" mov r7,r0 ;@ r7 = Pointer to Cpu Context\n");\r
198 ot(" ;@ r0-3 = Temporary registers\n");\r
d9d77995 199 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Flags (NZCV)\n");\r
200 ot(" ldr r6,=CycloneJumpTab ;@ r6 = Opcode Jump table\n");\r
6003a768 201 ot(" ldr r5,[r7,#0x5c] ;@ r5 = Cycles\n");\r
202 ot(" ldr r4,[r7,#0x40] ;@ r4 = Current PC + Memory Base\n");\r
203 ot(" ;@ r8 = Current Opcode\n");\r
d9d77995 204 ot(" ldr r1,[r7,#0x44] ;@ Get SR high T_S__III and irq level\n");\r
205 ot(" mov r10,r10,lsl #28;@ r10 = Flags 0xf0000000, cpsr format\n");\r
206 ot(" ;@ r11 = Source value / Memory Base\n");\r
207 ot(" str r6,[r7,#0x54] ;@ make a copy to avoid literal pools\n");\r
208 ot("\n");\r
209#if (CYCLONE_FOR_GENESIS == 2) || EMULATE_TRACE\r
210 ot(" mov r2,#0\n");\r
211 ot(" str r2,[r7,#0x98] ;@ clear custom CycloneEnd\n");\r
212#endif\r
213 ot(";@ CheckInterrupt:\n");\r
214 ot(" movs r0,r1,lsr #24 ;@ Get IRQ level\n"); // same as ldrb r0,[r7,#0x47]\r
215 ot(" beq NoInts0\n");\r
216 ot(" cmp r0,#6 ;@ irq>6 ?\n");\r
217 ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");\r
218 ot(" cmple r0,r1 ;@ irq<=6: Is irq<=mask ?\n");\r
219 ot(" bgt CycloneDoInterrupt\n");\r
220 ot("NoInts0%s\n", ms?"":":");\r
221 ot("\n");\r
222 ot(";@ Check if our processor is in special state\n");\r
223 ot(";@ and jump to opcode handler if not\n");\r
224 ot(" ldr r0,[r7,#0x58] ;@ state_flags\n");\r
225 ot(" ldrh r8,[r4],#2 ;@ Fetch first opcode\n");\r
226 ot(" tst r0,#0x%02x ;@ special state?\n", state_flags_to_check);\r
227 ot(" ldreq pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
228 ot("\n");\r
229 ot("CycloneSpecial%s\n", ms?"":":");\r
230#if EMULATE_TRACE\r
231 ot(" tst r0,#2 ;@ tracing?\n");\r
232 ot(" bne CycloneDoTrace\n");\r
233#endif\r
234 ot(";@ stopped or halted\n");\r
235 ot(" mov r5,#0\n");\r
236 ot(" str r5,[r7,#0x5C] ;@ eat all cycles\n");\r
237 ot(" ldmia sp!,{r4-r8,r10,r11,pc} ;@ we are stopped, do nothing!\n");\r
6003a768 238 ot("\n");\r
6003a768 239 ot("\n");\r
240\r
241 ot(";@ We come back here after execution\n");\r
242 ot("CycloneEnd%s\n", ms?"":":");\r
243 ot(" sub r4,r4,#2\n");\r
244 ot("CycloneEndNoBack%s\n", ms?"":":");\r
d9d77995 245#if (CYCLONE_FOR_GENESIS == 2) || EMULATE_TRACE\r
246 ot(" ldr r1,[r7,#0x98]\n");\r
247 ot(" mov r10,r10,lsr #28\n");\r
248 ot(" tst r1,r1\n");\r
249 ot(" bxne r1 ;@ jump to alternative CycloneEnd\n");\r
250#else\r
251 ot(" mov r10,r10,lsr #28\n");\r
252#endif\r
6003a768 253 ot(" str r4,[r7,#0x40] ;@ Save Current PC + Memory Base\n");\r
254 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
d9d77995 255 ot(" strb r10,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
256 ot(" ldmia sp!,{r4-r8,r10,r11,pc}\n");\r
257 ltorg();\r
6003a768 258 ot("\n");\r
6003a768 259 ot("\n");\r
d9d77995 260\r
261 ot("CycloneInit%s\n", ms?"":":");\r
262#if COMPRESS_JUMPTABLE\r
263 ot(";@ decompress jump table\n");\r
264 ot(" ldr r12,=CycloneJumpTab\n");\r
265 ot(" add r0,r12,#0xe000*4 ;@ ctrl code pointer\n");\r
266 ot(" ldr r1,[r0,#-4]\n");\r
267 ot(" tst r1,r1\n");\r
268 ot(" movne pc,lr ;@ already uncompressed\n");\r
269 ot(" add r3,r12,#0xa000*4 ;@ handler table pointer, r12=dest\n");\r
270 ot("unc_loop%s\n", ms?"":":");\r
271 ot(" ldrh r1,[r0],#2\n");\r
272 ot(" and r2,r1,#0xf\n");\r
273 ot(" bic r1,r1,#0xf\n");\r
274 ot(" ldr r1,[r3,r1,lsr #2] ;@ r1=handler\n");\r
275 ot(" cmp r2,#0xf\n");\r
276 ot(" addeq r2,r2,#1 ;@ 0xf is really 0x10\n");\r
277 ot(" tst r2,r2\n");\r
278 ot(" ldreqh r2,[r0],#2 ;@ counter is in next word\n");\r
279 ot(" tst r2,r2\n");\r
280 ot(" beq unc_finish ;@ done decompressing\n");\r
281 ot(" tst r1,r1\n");\r
282 ot(" addeq r12,r12,r2,lsl #2 ;@ 0 handler means we should skip those bytes\n");\r
283 ot(" beq unc_loop\n");\r
284 ot("unc_loop_in%s\n", ms?"":":");\r
285 ot(" subs r2,r2,#1\n");\r
286 ot(" str r1,[r12],#4\n");\r
287 ot(" bgt unc_loop_in\n");\r
288 ot(" b unc_loop\n");\r
289 ot("unc_finish%s\n", ms?"":":");\r
290 ot(" ldr r12,=CycloneJumpTab\n");\r
291 ot(" ;@ set a-line and f-line handlers\n");\r
292 ot(" add r0,r12,#0xa000*4\n");\r
293 ot(" ldr r1,[r0,#4] ;@ a-line handler\n");\r
294 ot(" ldr r3,[r0,#8] ;@ f-line handler\n");\r
295 ot(" mov r2,#0x1000\n");\r
296 ot("unc_fill3%s\n", ms?"":":");\r
297 ot(" subs r2,r2,#1\n");\r
298 ot(" str r1,[r0],#4\n");\r
299 ot(" bgt unc_fill3\n");\r
300 ot(" add r0,r12,#0xf000*4\n");\r
301 ot(" mov r2,#0x1000\n");\r
302 ot("unc_fill4%s\n", ms?"":":");\r
303 ot(" subs r2,r2,#1\n");\r
304 ot(" str r3,[r0],#4\n");\r
305 ot(" bgt unc_fill4\n");\r
306 ot(" bx lr\n");\r
307 ltorg();\r
308#else\r
590d780f 309 ot(";@ fix final jumptable entries\n");\r
310 ot(" ldr r12,=CycloneJumpTab\n");\r
311 ot(" add r12,r12,#0x10000*4\n");\r
312 ot(" ldr r0,[r12,#-3*4]\n");\r
313 ot(" str r0,[r12,#-2*4]\n");\r
314 ot(" str r0,[r12,#-1*4]\n");\r
d9d77995 315 ot(" bx lr\n");\r
316#endif\r
6003a768 317 ot("\n");\r
d9d77995 318\r
319 // --------------\r
320 ot("CycloneReset%s\n", ms?"":":");\r
321 ot(" stmfd sp!,{r7,lr}\n");\r
322 ot(" mov r7,r0\n");\r
323 ot(" mov r0,#0\n");\r
324 ot(" str r0,[r7,#0x58] ;@ state_flags\n");\r
325 ot(" str r0,[r7,#0x48] ;@ OSP\n");\r
326 ot(" mov r1,#0x27 ;@ Supervisor mode\n");\r
327 ot(" strb r1,[r7,#0x44] ;@ set SR high\n");\r
328 ot(" strb r0,[r7,#0x47] ;@ IRQ\n");\r
6003a768 329 MemHandler(0,2);\r
d9d77995 330 ot(" str r0,[r7,#0x3c] ;@ Stack pointer\n");\r
331 ot(" mov r0,#0\n");\r
332 ot(" str r0,[r7,#0x60] ;@ Membase\n");\r
333 ot(" mov r0,#4\n");\r
334 MemHandler(0,2);\r
335#ifdef MEMHANDLERS_DIRECT_PREFIX\r
336 ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);\r
337#else\r
6003a768 338 ot(" mov lr,pc\n");\r
339 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
d9d77995 340#endif\r
341 ot(" str r0,[r7,#0x40] ;@ PC + base\n");\r
342 ot(" ldmfd sp!,{r7,pc}\n");\r
343 ot("\n");\r
344\r
345 // --------------\r
346 // 68k: XNZVC, ARM: NZCV\r
347 ot("CycloneSetSr%s\n", ms?"":":");\r
348 ot(" mov r2,r1,lsr #8\n");\r
349// ot(" ldrb r3,[r0,#0x44] ;@ get SR high\n");\r
350// ot(" eor r3,r3,r2\n");\r
351// ot(" tst r3,#0x20\n");\r
352#if EMULATE_TRACE\r
353 ot(" and r2,r2,#0xa7 ;@ only defined bits\n");\r
354#else\r
355 ot(" and r2,r2,#0x27 ;@ only defined bits\n");\r
356#endif\r
357 ot(" strb r2,[r0,#0x44] ;@ set SR high\n");\r
358 ot(" mov r2,r1,lsl #25\n");\r
359 ot(" str r2,[r0,#0x4c] ;@ the X flag\n");\r
360 ot(" bic r2,r1,#0xf3\n");\r
361 ot(" tst r1,#1\n");\r
362 ot(" orrne r2,r2,#2\n");\r
363 ot(" tst r1,#2\n");\r
364 ot(" orrne r2,r2,#1\n");\r
365 ot(" strb r2,[r0,#0x46] ;@ flags\n");\r
366 ot(" bx lr\n");\r
367 ot("\n");\r
368\r
369 // --------------\r
370 ot("CycloneGetSr%s\n", ms?"":":");\r
371 ot(" ldrb r1,[r0,#0x46] ;@ flags\n");\r
372 ot(" bic r2,r1,#0xf3\n");\r
373 ot(" tst r1,#1\n");\r
374 ot(" orrne r2,r2,#2\n");\r
375 ot(" tst r1,#2\n");\r
376 ot(" orrne r2,r2,#1\n");\r
377 ot(" ldr r1,[r0,#0x4c] ;@ the X flag\n");\r
378 ot(" tst r1,#0x20000000\n");\r
379 ot(" orrne r2,r2,#0x10\n");\r
380 ot(" ldrb r1,[r0,#0x44] ;@ the SR high\n");\r
381 ot(" orr r0,r2,r1,lsl #8\n");\r
382 ot(" bx lr\n");\r
383 ot("\n");\r
384\r
385 // --------------\r
386 ot("CyclonePack%s\n", ms?"":":");\r
387 ot(" stmfd sp!,{r4,r5,lr}\n");\r
6003a768 388 ot(" mov r4,r0\n");\r
d9d77995 389 ot(" mov r5,r1\n");\r
390 ot(" mov r3,#16\n");\r
391 ot(";@ 0x00-0x3f: DA registers\n");\r
392 ot("c_pack_loop%s\n",ms?"":":");\r
393 ot(" ldr r1,[r0],#4\n");\r
394 ot(" subs r3,r3,#1\n");\r
395 ot(" str r1,[r5],#4\n");\r
396 ot(" bne c_pack_loop\n");\r
397 ot(";@ 0x40: PC\n");\r
398 ot(" ldr r0,[r4,#0x40] ;@ PC + Memory Base\n");\r
399 ot(" ldr r1,[r4,#0x60] ;@ Memory base\n");\r
400 ot(" sub r0,r0,r1\n");\r
401 ot(" str r0,[r5],#4\n");\r
402 ot(";@ 0x44: SR\n");\r
403 ot(" mov r0,r4\n");\r
404 ot(" bl CycloneGetSr\n");\r
405 ot(" strh r0,[r5],#2\n");\r
406 ot(";@ 0x46: IRQ level\n");\r
407 ot(" ldrb r0,[r4,#0x47]\n");\r
408 ot(" strb r0,[r5],#2\n");\r
409 ot(";@ 0x48: other SP\n");\r
410 ot(" ldr r0,[r4,#0x48]\n");\r
411 ot(" str r0,[r5],#4\n");\r
412 ot(";@ 0x4c: CPU state flags\n");\r
413 ot(" ldr r0,[r4,#0x58]\n");\r
414 ot(" str r0,[r5],#4\n");\r
415 ot(" ldmfd sp!,{r4,r5,pc}\n");\r
416 ot("\n");\r
417\r
418 // --------------\r
419 ot("CycloneUnpack%s\n", ms?"":":");\r
420 ot(" stmfd sp!,{r5,r7,lr}\n");\r
421 ot(" mov r7,r0\n");\r
422 ot(" movs r5,r1\n");\r
423 ot(" beq c_unpack_do_pc\n");\r
424 ot(" mov r3,#16\n");\r
425 ot(";@ 0x00-0x3f: DA registers\n");\r
426 ot("c_unpack_loop%s\n",ms?"":":");\r
427 ot(" ldr r1,[r5],#4\n");\r
428 ot(" subs r3,r3,#1\n");\r
429 ot(" str r1,[r0],#4\n");\r
430 ot(" bne c_unpack_loop\n");\r
431 ot(";@ 0x40: PC\n");\r
432 ot(" ldr r0,[r5],#4 ;@ PC\n");\r
433 ot(" str r0,[r7,#0x40] ;@ handle later\n");\r
434 ot(";@ 0x44: SR\n");\r
435 ot(" ldrh r1,[r5],#2\n");\r
436 ot(" mov r0,r7\n");\r
437 ot(" bl CycloneSetSr\n");\r
438 ot(";@ 0x46: IRQ level\n");\r
439 ot(" ldrb r0,[r5],#2\n");\r
440 ot(" strb r0,[r7,#0x47]\n");\r
441 ot(";@ 0x48: other SP\n");\r
442 ot(" ldr r0,[r5],#4\n");\r
443 ot(" str r0,[r7,#0x48]\n");\r
444 ot(";@ 0x4c: CPU state flags\n");\r
445 ot(" ldr r0,[r5],#4\n");\r
446 ot(" str r0,[r7,#0x58]\n");\r
447 ot("c_unpack_do_pc%s\n",ms?"":":");\r
448 ot(" ldr r0,[r7,#0x40] ;@ unbased PC\n");\r
449#if USE_CHECKPC_CALLBACK\r
450 ot(" mov r1,#0\n");\r
451 ot(" str r1,[r7,#0x60] ;@ Memory base\n");\r
452 #ifdef MEMHANDLERS_DIRECT_PREFIX\r
453 ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);\r
454 #else\r
455 ot(" mov lr,pc\n");\r
456 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
457 #endif\r
458#else\r
459 ot(" ldr r1,[r7,#0x60] ;@ Memory base\n");\r
460 ot(" add r0,r0,r1 ;@ r0 = Memory Base + New PC\n");\r
461#endif\r
462 ot(" str r0,[r7,#0x40] ;@ PC + Memory Base\n");\r
463 ot(" ldmfd sp!,{r5,r7,pc}\n");\r
464 ot("\n");\r
465\r
466 // --------------\r
467 ot("CycloneFlushIrq%s\n", ms?"":":");\r
468 ot(" ldr r1,[r0,#0x44] ;@ Get SR high T_S__III and irq level\n");\r
469 ot(" mov r2,r1,lsr #24 ;@ Get IRQ level\n"); // same as ldrb r0,[r7,#0x47]\r
470 ot(" cmp r2,#6 ;@ irq>6 ?\n");\r
471 ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");\r
472 ot(" cmple r2,r1 ;@ irq<=6: Is irq<=mask ?\n");\r
473 ot(" movle r0,#0\n");\r
474 ot(" bxle lr ;@ no ints\n");\r
475 ot("\n");\r
476 ot(" stmdb sp!,{r4,r5,r7,r8,r10,r11,lr}\n");\r
477 ot(" mov r7,r0\n");\r
478 ot(" mov r0,r2\n");\r
479 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Flags (NZCV)\n");\r
480 ot(" mov r5,#0\n");\r
481 ot(" ldr r4,[r7,#0x40] ;@ r4 = Current PC + Memory Base\n");\r
482 ot(" mov r10,r10,lsl #28 ;@ r10 = Flags 0xf0000000, cpsr format\n");\r
483 ot(" adr r2,CycloneFlushIrqEnd\n");\r
484 ot(" str r2,[r7,#0x98] ;@ set custom CycloneEnd\n");\r
485 ot(" b CycloneDoInterrupt\n");\r
486 ot("\n");\r
487 ot("CycloneFlushIrqEnd%s\n", ms?"":":");\r
488 ot(" rsb r0,r5,#0\n");\r
489 ot(" str r4,[r7,#0x40] ;@ Save Current PC + Memory Base\n");\r
490 ot(" strb r10,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
491 ot(" ldmia sp!,{r4,r5,r7,r8,r10,r11,lr}\n");\r
492 ot(" bx lr\n");\r
493 ot("\n");\r
494 ot("\n");\r
495\r
496 // --------------\r
497 ot("CycloneSetRealTAS%s\n", ms?"":":");\r
498#if (CYCLONE_FOR_GENESIS == 2)\r
499 ot(" ldr r12,=CycloneJumpTab\n");\r
500 ot(" tst r0,r0\n");\r
501 ot(" add r12,r12,#0x4a00*4\n");\r
502 ot(" add r12,r12,#0x00d0*4\n");\r
503 ot(" beq setrtas_off\n");\r
504 ChangeTAS(1);\r
505 ot(" bx lr\n");\r
506 ot("setrtas_off%s\n",ms?"":":");\r
507 ChangeTAS(0);\r
508 ot(" bx lr\n");\r
509 ltorg();\r
510#else\r
511 ot(" bx lr\n");\r
512#endif\r
513 ot("\n");\r
514\r
515 // --------------\r
516 ot(";@ DoInterrupt - r0=IRQ level\n");\r
517 ot("CycloneDoInterruptGoBack%s\n", ms?"":":");\r
518 ot(" sub r4,r4,#2\n");\r
519 ot("CycloneDoInterrupt%s\n", ms?"":":");\r
520 ot(" bic r8,r8,#0xff000000\n");\r
521 ot(" orr r8,r8,r0,lsl #29 ;@ abuse r8\n");\r
522\r
523 // Steps are from "M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL", p. 6-4\r
524 // but their order is based on http://pasti.fxatari.com/68kdocs/68kPrefetch.html\r
525 // 1. Make a temporary copy of the status register and set the status register for exception processing.\r
526 ot(" ldr r2,[r7,#0x58] ;@ state flags\n");\r
527 ot(" and r0,r0,#7\n");\r
528 ot(" orr r3,r0,#0x20 ;@ Supervisor mode + IRQ level\n");\r
529 ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");\r
530#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
531 ot(" orr r2,r2,#4 ;@ set activity bit: 'not processing instruction'\n");\r
532#endif\r
533 ot(" str r2,[r7,#0x58]\n");\r
534 ot(" ldrb r6,[r7,#0x44] ;@ Get old SR high, abuse r6\n");\r
535 ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");\r
6003a768 536 ot("\n");\r
d9d77995 537\r
538 // 3. Save the current processor context.\r
539 ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");\r
540 ot(" ldr r11,[r7,#0x3c] ;@ Get A7\n");\r
541 ot(" tst r6,#0x20\n");\r
542 ot(";@ get our SP:\n");\r
543 ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");\r
544 ot(" streq r11,[r7,#0x48]\n");\r
545 ot(" moveq r11,r2\n");\r
546 ot(";@ Push old PC onto stack\n");\r
547 ot(" sub r0,r11,#4 ;@ Predecremented A7\n");\r
548 ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");\r
549 MemHandler(1,2);\r
550 ot(";@ Push old SR:\n");\r
551 ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");\r
552 ot(" mov r1,r10,lsr #28 ;@ ____NZCV\n");\r
553 ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");\r
554 ot(" tst r2,#1 ;@ 1 if C!=V\n");\r
555 ot(" eorne r1,r1,#3 ;@ ____NZVC\n");\r
556 ot(" and r0,r0,#0x20000000\n");\r
557 ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");\r
558 ot(" orr r1,r1,r6,lsl #8 ;@ Include old SR high\n");\r
559 ot(" sub r0,r11,#6 ;@ Predecrement A7\n");\r
560 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
561 MemHandler(1,1,0,0); // already checked for address error by prev MemHandler\r
6003a768 562 ot("\n");\r
d9d77995 563\r
564 // 2. Obtain the exception vector.\r
565 ot(" mov r11,r8,lsr #29\n");\r
566 ot(" mov r0,r11\n");\r
567#if USE_INT_ACK_CALLBACK\r
568 ot(";@ call IrqCallback if it is defined\n");\r
569#if INT_ACK_NEEDS_STUFF\r
570 ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
571 ot(" mov r1,r10,lsr #28\n");\r
572 ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
573 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
574#endif\r
575 ot(" ldr r3,[r7,#0x8c] ;@ IrqCallback\n");\r
576 ot(" add lr,pc,#4*3\n");\r
577 ot(" tst r3,r3\n");\r
578 ot(" streqb r3,[r7,#0x47] ;@ just clear IRQ if there is no callback\n");\r
579 ot(" mvneq r0,#0 ;@ and simulate -1 return\n");\r
580 ot(" bxne r3\n");\r
581#if INT_ACK_CHANGES_CYCLES\r
582 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
583#endif\r
584 ot(";@ get IRQ vector address:\n");\r
585 ot(" cmn r0,#1 ;@ returned -1?\n");\r
586 ot(" addeq r0,r11,#0x18 ;@ use autovector then\n");\r
587 ot(" cmn r0,#2 ;@ returned -2?\n"); // should be safe as above add should never result in -2\r
588 ot(" moveq r0,#0x18 ;@ use spurious interrupt then\n");\r
589#else // !USE_INT_ACK_CALLBACK\r
6003a768 590 ot(";@ Clear irq:\n");\r
d9d77995 591 ot(" mov r2,#0\n");\r
592 ot(" strb r2,[r7,#0x47]\n");\r
593 ot(" add r0,r0,#0x18 ;@ use autovector\n");\r
594#endif\r
595 ot(" mov r0,r0,lsl #2 ;@ get vector address\n");\r
596 ot("\n");\r
597 ot(" ldr r11,[r7,#0x60] ;@ Get Memory base\n");\r
598 ot(";@ Read IRQ Vector:\n");\r
599 MemHandler(0,2,0,0);\r
600 ot(" tst r0,r0 ;@ uninitialized int vector?\n");\r
601 ot(" moveq r0,#0x3c\n");\r
602 #ifdef MEMHANDLERS_DIRECT_PREFIX\r
603 ot(" bleq %sread32 ;@ Call read32(r0) handler\n", MEMHANDLERS_DIRECT_PREFIX);\r
604 #else\r
605 ot(" moveq lr,pc\n");\r
606 ot(" ldreq pc,[r7,#0x70] ;@ Call read32(r0) handler\n");\r
607 #endif\r
608#if USE_CHECKPC_CALLBACK\r
609 ot(" add lr,pc,#4\n");\r
610 ot(" add r0,r0,r11 ;@ r0 = Memory Base + New PC\n");\r
611 #ifdef MEMHANDLERS_DIRECT_PREFIX\r
612 ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);\r
613 #else\r
614 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
615 #endif\r
616 #if EMULATE_ADDRESS_ERRORS_JUMP\r
617 ot(" mov r4,r0\n");\r
618 #else\r
619 ot(" bic r4,r0,#1\n");\r
620 #endif\r
621#else\r
622 ot(" add r4,r0,r11 ;@ r4 = Memory Base + New PC\n");\r
623 #if EMULATE_ADDRESS_ERRORS_JUMP\r
624 ot(" bic r4,r4,#1\n");\r
625 #endif\r
626#endif\r
6003a768 627 ot("\n");\r
628\r
d9d77995 629 // 4. Obtain a new context and resume instruction processing.\r
630 // note: the obtain part was already done in previous steps\r
631#if EMULATE_ADDRESS_ERRORS_JUMP\r
632 ot(" tst r4,#1\n");\r
633 ot(" bne ExceptionAddressError_r_prg_r4\n");\r
634#endif\r
635 ot(" ldr r6,[r7,#0x54]\n");\r
636 ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
637 ot(" subs r5,r5,#44 ;@ Subtract cycles\n");\r
c204973a 638 ot(" ldrgt pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
d9d77995 639 ot(" b CycloneEnd\n");\r
6003a768 640 ot("\n");\r
d9d77995 641\r
642 // --------------\r
643 // trashes all temp regs\r
644 ot("Exception%s\n", ms?"":":");\r
645 ot(" ;@ Cause an Exception - Vector number in r0\n");\r
6003a768 646 ot(" mov r11,lr ;@ Preserve ARM return address\n");\r
d9d77995 647 ot(" bic r8,r8,#0xff000000\n");\r
648 ot(" orr r8,r8,r0,lsl #24 ;@ abuse r8\n");\r
649\r
650 // 1. Make a temporary copy of the status register and set the status register for exception processing.\r
651 ot(" ldr r6,[r7,#0x44] ;@ Get old SR high, abuse r6\n");\r
652 ot(" ldr r2,[r7,#0x58] ;@ state flags\n");\r
653 ot(" and r3,r6,#0x27 ;@ clear trace and unused flags\n");\r
654 ot(" orr r3,r3,#0x20 ;@ set supervisor mode\n");\r
655 ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");\r
656 ot(" str r2,[r7,#0x58]\n");\r
657 ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");\r
658 ot("\n");\r
659\r
660 // 3. Save the current processor context.\r
661 ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");\r
662 ot(" tst r6,#0x20\n");\r
663 ot(";@ get our SP:\n");\r
664 ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");\r
665 ot(" streq r0,[r7,#0x48]\n");\r
666 ot(" moveq r0,r2\n");\r
667 ot(";@ Push old PC onto stack\n");\r
668 ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");\r
669 ot(" sub r0,r0,#4 ;@ Predecremented A7\n");\r
670 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
671 ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");\r
672 MemHandler(1,2);\r
673 ot(";@ Push old SR:\n");\r
674 ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");\r
675 ot(" mov r1,r10,lsr #28 ;@ ____NZCV\n");\r
676 ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");\r
677 ot(" tst r2,#1 ;@ 1 if C!=V\n");\r
678 ot(" eorne r1,r1,#3 ;@ ____NZVC\n");\r
679 ot(" and r0,r0,#0x20000000\n");\r
680 ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");\r
681 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
682 ot(" orr r1,r1,r6,lsl #8 ;@ Include SR high\n");\r
683 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
684 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
685 MemHandler(1,1,0,0);\r
686 ot("\n");\r
687\r
688 // 2. Obtain the exception vector\r
689 ot(";@ Read Exception Vector:\n");\r
690 ot(" mov r0,r8,lsr #24\n");\r
691 ot(" mov r0,r0,lsl #2\n");\r
692 MemHandler(0,2,0,0);\r
693 ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");\r
694#if USE_CHECKPC_CALLBACK\r
695 ot(" add lr,pc,#4\n");\r
696 ot(" add r0,r0,r3 ;@ r0 = Memory Base + New PC\n");\r
697 #ifdef MEMHANDLERS_DIRECT_PREFIX\r
698 ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);\r
699 #else\r
700 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
701 #endif\r
702 #if EMULATE_ADDRESS_ERRORS_JUMP\r
703 ot(" mov r4,r0\n");\r
704 #else\r
705 ot(" bic r4,r0,#1\n");\r
706 #endif\r
707#else\r
708 ot(" add r4,r0,r3 ;@ r4 = Memory Base + New PC\n");\r
709 #if EMULATE_ADDRESS_ERRORS_JUMP\r
710 ot(" bic r4,r4,#1\n");\r
711 #endif\r
712#endif\r
6003a768 713 ot("\n");\r
d9d77995 714\r
715 // 4. Resume execution.\r
716#if EMULATE_ADDRESS_ERRORS_JUMP\r
717 ot(" tst r4,#1\n");\r
718 ot(" bne ExceptionAddressError_r_prg_r4\n");\r
719#endif\r
720 ot(" ldr r6,[r7,#0x54]\n");\r
721 ot(" bx r11 ;@ Return\n");\r
722 ot("\n");\r
723\r
724 // --------------\r
725#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
726 // first some wrappers: I see no point inlining this code,\r
727 // as it will be executed in really rare cases.\r
728 AddressErrorWrapper('r', "data", 0x11);\r
729 AddressErrorWrapper('r', "prg", 0x12);\r
730 AddressErrorWrapper('w', "data", 0x01);\r
731 // there are no program writes\r
732 // cpu space is only for bus errors?\r
733 ot("ExceptionAddressError_r_prg_r4%s\n", ms?"":":");\r
734 ot(" ldr r1,[r7,#0x44]\n");\r
735 ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");\r
736 ot(" mov r6,#0x12\n");\r
737 ot(" sub r11,r4,r3\n");\r
738 ot(" tst r1,#0x20\n");\r
739 ot(" orrne r6,r6,#4\n");\r
740 ot("\n");\r
741\r
742 ot("ExceptionAddressError%s\n", ms?"":":");\r
743 ot(";@ r6 - info word (without instruction/not bit), r11 - faulting address\n");\r
744\r
745 // 1. Make a temporary copy of the status register and set the status register for exception processing.\r
746 ot(" ldrb r0,[r7,#0x44] ;@ Get old SR high\n");\r
747 ot(" ldr r2,[r7,#0x58] ;@ state flags\n");\r
748 ot(" and r3,r0,#0x27 ;@ clear trace and unused flags\n");\r
749 ot(" orr r3,r3,#0x20 ;@ set supervisor mode\n");\r
750 ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");\r
751 ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");\r
752 ot(" tst r2,#4\n");\r
753 ot(" orrne r6,r6,#8 ;@ complete info word\n");\r
754 ot(" orr r2,r2,#4 ;@ set activity bit: 'not processing instruction'\n");\r
755#if EMULATE_HALT\r
756 ot(" tst r2,#8\n");\r
757 ot(" orrne r2,r2,#0x10 ;@ HALT\n");\r
758 ot(" orr r2,r2,#8 ;@ processing address error\n");\r
759 ot(" str r2,[r7,#0x58]\n");\r
760 ot(" movne r5,#0\n");\r
761 ot(" bne CycloneEndNoBack ;@ bye bye\n");\r
762#else\r
763 ot(" str r2,[r7,#0x58]\n");\r
764#endif\r
765 ot(" and r10,r10,#0xf0000000\n");\r
766 ot(" orr r10,r10,r0,lsl #4 ;@ some preparations for SR push\n");\r
767 ot("\n");\r
768\r
769 // 3. Save the current processor context + additional information.\r
770 ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");\r
771 ot(" tst r10,#0x200\n");\r
772 ot(";@ get our SP:\n");\r
773 ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");\r
774 ot(" streq r0,[r7,#0x48]\n");\r
775 ot(" moveq r0,r2\n");\r
776 // PC\r
777 ot(";@ Push old PC onto stack\n");\r
778 ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");\r
779 ot(" sub r0,r0,#4 ;@ Predecremented A7\n");\r
780 ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");\r
781 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
782 MemHandler(1,2,0,EMULATE_HALT);\r
783 // SR\r
784 ot(";@ Push old SR:\n");\r
785 ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");\r
786 ot(" mov r1,r10,ror #28 ;@ ____NZCV\n");\r
787 ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");\r
788 ot(" tst r2,#1 ;@ 1 if C!=V\n");\r
789 ot(" eorne r1,r1,#3 ;@ ____NZVC\n");\r
790 ot(" and r0,r0,#0x20000000\n");\r
791 ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");\r
792 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
793 ot(" and r10,r10,#0xf0000000\n");\r
794 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
795 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
796 MemHandler(1,1,0,0);\r
797 // IR (instruction register)\r
798 ot(";@ Push IR:\n");\r
799 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
800 ot(" mov r1,r8\n");\r
801 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
802 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
803 MemHandler(1,1,0,0);\r
804 // access address\r
805 ot(";@ Push address:\n");\r
806 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
807 ot(" mov r1,r11\n");\r
808 ot(" sub r0,r0,#4 ;@ Predecrement A7\n");\r
809 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
810 MemHandler(1,2,0,0);\r
811 // information word\r
812 ot(";@ Push info word:\n");\r
813 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
814 ot(" mov r1,r6\n");\r
815 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
816 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
817 MemHandler(1,1,0,0);\r
818 ot("\n");\r
819\r
820 // 2. Obtain the exception vector\r
821 ot(";@ Read Exception Vector:\n");\r
822 ot(" mov r0,#0x0c\n");\r
823 MemHandler(0,2,0,0);\r
824 ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");\r
825#if USE_CHECKPC_CALLBACK\r
826 ot(" add lr,pc,#4\n");\r
827 ot(" add r0,r0,r3 ;@ r0 = Memory Base + New PC\n");\r
828 #ifdef MEMHANDLERS_DIRECT_PREFIX\r
829 ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);\r
830 #else\r
831 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
832 #endif\r
833 ot(" mov r4,r0\n");\r
834#else\r
835 ot(" add r4,r0,r3 ;@ r4 = Memory Base + New PC\n");\r
836#endif\r
837 ot("\n");\r
838\r
839#if EMULATE_ADDRESS_ERRORS_JUMP && EMULATE_HALT\r
840 ot(" tst r4,#1\n");\r
841 ot(" bne ExceptionAddressError_r_prg_r4\n");\r
842#else\r
843 ot(" bic r4,r4,#1\n");\r
844#endif\r
845\r
846 // 4. Resume execution.\r
847 ot(" ldr r6,[r7,#0x54]\n");\r
848 ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
849 ot(" subs r5,r5,#50 ;@ Subtract cycles\n");\r
c204973a 850 ot(" ldrgt pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
d9d77995 851 ot(" b CycloneEnd\n");\r
852 ot("\n");\r
853#endif\r
854\r
855 // --------------\r
856#if EMULATE_TRACE\r
857 // expects srh and irq level in r1, next opcode already fetched to r8\r
858 ot("CycloneDoTraceWithChecks%s\n", ms?"":":");\r
859 ot(" ldr r0,[r7,#0x58]\n");\r
860 ot(" cmp r5,#0\n");\r
861 ot(" orr r0,r0,#2 ;@ go to trace mode\n");\r
862 ot(" str r0,[r7,#0x58]\n");\r
c204973a 863 ot(" ble CycloneEnd\n"); // should take care of situation where we come here when already tracing\r
d9d77995 864 ot(";@ CheckInterrupt:\n");\r
865 ot(" movs r0,r1,lsr #24 ;@ Get IRQ level\n");\r
866 ot(" beq CycloneDoTrace\n");\r
867 ot(" cmp r0,#6 ;@ irq>6 ?\n");\r
868 ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");\r
869 ot(" cmple r0,r1 ;@ irq<=6: Is irq<=mask ?\n");\r
870 ot(" bgt CycloneDoInterruptGoBack\n");\r
871 ot("\n");\r
872\r
873 // expects next opcode to be already fetched to r8\r
874 ot("CycloneDoTrace%s\n", ms?"":":");\r
875 ot(" str r5,[r7,#0x9c] ;@ save cycles\n");\r
876 ot(" ldr r1,[r7,#0x98]\n");\r
877 ot(" mov r5,#0\n");\r
878 ot(" str r1,[r7,#0xa0]\n");\r
879 ot(" adr r0,TraceEnd\n");\r
880 ot(" str r0,[r7,#0x98] ;@ store TraceEnd as CycloneEnd hadler\n");\r
881 ot(" ldr pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
882 ot("\n");\r
883\r
884 ot("TraceEnd%s\n", ms?"":":");\r
885 ot(" ldr r2,[r7,#0x58]\n");\r
886 ot(" ldr r0,[r7,#0x9c] ;@ restore cycles\n");\r
887 ot(" ldr r1,[r7,#0xa0] ;@ old CycloneEnd handler\n");\r
888 ot(" mov r10,r10,lsl #28\n");\r
889 ot(" add r5,r0,r5\n");\r
890 ot(" str r1,[r7,#0x98]\n");\r
891 ot(";@ still tracing?\n"); // exception might have happend\r
892 ot(" tst r2,#2\n");\r
893 ot(" beq TraceDisabled\n");\r
894 ot(";@ trace exception\n");\r
895#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
896 ot(" ldr r1,[r7,#0x58]\n");\r
897 ot(" mov r0,#9\n");\r
898 ot(" orr r1,r1,#4 ;@ set activity bit: 'not processing instruction'\n");\r
899 ot(" str r1,[r7,#0x58]\n");\r
900#else\r
901 ot(" mov r0,#9\n");\r
902#endif\r
903 ot(" bl Exception\n");\r
904 ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
905 ot(" subs r5,r5,#34 ;@ Subtract cycles\n");\r
c204973a 906 ot(" ldrgt pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
d9d77995 907 ot(" b CycloneEnd\n");\r
908 ot("\n");\r
909 ot("TraceDisabled%s\n", ms?"":":");\r
910 ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
911 ot(" cmp r5,#0\n");\r
c204973a 912 ot(" ldrgt pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
d9d77995 913 ot(" b CycloneEnd\n");\r
914 ot("\n");\r
915#endif\r
6003a768 916}\r
917\r
918// ---------------------------------------------------------------------------\r
919// Call Read(r0), Write(r0,r1) or Fetch(r0)\r
d9d77995 920// Trashes r0-r3,r12,lr\r
921int MemHandler(int type,int size,int addrreg,int need_addrerr_check)\r
6003a768 922{\r
d9d77995 923 int func=0x68+type*0xc+(size<<2); // Find correct offset\r
924 char what[32];\r
6003a768 925\r
d9d77995 926#if MEMHANDLERS_NEED_FLAGS\r
927 ot(" mov r3,r10,lsr #28\n");\r
928 ot(" strb r3,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
929#endif\r
930 FlushPC();\r
6003a768 931\r
d9d77995 932#if (MEMHANDLERS_ADDR_MASK & 0xff000000)\r
933 ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0xff000000);\r
934 addrreg=0;\r
935#endif\r
936#if (MEMHANDLERS_ADDR_MASK & 0x00ff0000)\r
937 ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0x00ff0000);\r
938 addrreg=0;\r
939#endif\r
940#if (MEMHANDLERS_ADDR_MASK & 0x0000ff00)\r
941 ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0x0000ff00);\r
942 addrreg=0;\r
943#endif\r
944#if (MEMHANDLERS_ADDR_MASK & 0x000000ff)\r
945 ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0x000000ff);\r
946 addrreg=0;\r
947#endif\r
948\r
949#if EMULATE_ADDRESS_ERRORS_IO\r
950 if (size > 0 && need_addrerr_check)\r
951 {\r
952 ot(" add lr,pc,#4*%i\n", addrreg==0?2:3); // helps to prevent interlocks\r
953 if (addrreg != 0) ot(" mov r0,r%i\n", addrreg);\r
954 ot(" tst r0,#1 ;@ address error?\n");\r
955 switch (type) {\r
956 case 0: ot(" bne ExceptionAddressError_r_data\n"); break;\r
957 case 1: ot(" bne ExceptionAddressError_w_data\n"); break;\r
958 case 2: ot(" bne ExceptionAddressError_r_prg\n"); break;\r
959 }\r
960 }\r
961 else\r
962#endif\r
963\r
964 sprintf(what, "%s%d", type==0 ? "read" : (type==1 ? "write" : "fetch"), 8<<size);\r
965#ifdef MEMHANDLERS_DIRECT_PREFIX\r
966 if (addrreg != 0)\r
967 ot(" mov r0,r%i\n", addrreg);\r
968 ot(" bl %s%s ;@ Call ", MEMHANDLERS_DIRECT_PREFIX, what);\r
969 (void)func; // avoid warning\r
970#else\r
971 if (addrreg != 0)\r
972 {\r
973 ot(" add lr,pc,#4\n");\r
974 ot(" mov r0,r%i\n", addrreg);\r
975 }\r
976 else\r
977 ot(" mov lr,pc\n");\r
6003a768 978 ot(" ldr pc,[r7,#0x%x] ;@ Call ",func);\r
d9d77995 979#endif\r
6003a768 980\r
981 // Document what we are calling:\r
d9d77995 982 if (type==1) ot("%s(r0,r1)",what);\r
983 else ot("%s(r0)", what);\r
6003a768 984 ot(" handler\n");\r
985\r
d9d77995 986#if MEMHANDLERS_CHANGE_FLAGS\r
987 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");\r
988 ot(" mov r10,r10,lsl #28\n");\r
989#endif\r
990#if MEMHANDLERS_CHANGE_PC\r
991 ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
992#endif\r
993\r
6003a768 994 return 0;\r
995}\r
996\r
997static void PrintOpcodes()\r
998{\r
999 int op=0;\r
d9d77995 1000\r
6003a768 1001 printf("Creating Opcodes: [");\r
1002\r
1003 ot(";@ ---------------------------- Opcodes ---------------------------\n");\r
1004\r
1005 // Emit null opcode:\r
1006 ot("Op____%s ;@ Called if an opcode is not recognised\n", ms?"":":");\r
d9d77995 1007#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
1008 ot(" ldr r1,[r7,#0x58]\n");\r
1009 ot(" sub r4,r4,#2\n");\r
1010 ot(" orr r1,r1,#4 ;@ set activity bit: 'not processing instruction'\n");\r
1011 ot(" str r1,[r7,#0x58]\n");\r
1012#else\r
1013 ot(" sub r4,r4,#2\n");\r
1014#endif\r
1015#if USE_UNRECOGNIZED_CALLBACK\r
1016 ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
1017 ot(" mov r1,r10,lsr #28\n");\r
1018 ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
1019 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
1020 ot(" ldr r11,[r7,#0x94] ;@ UnrecognizedCallback\n");\r
1021 ot(" tst r11,r11\n");\r
1022 ot(" movne lr,pc\n");\r
1023 ot(" movne pc,r11 ;@ call UnrecognizedCallback if it is defined\n");\r
1024 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");\r
1025 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
1026 ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
1027 ot(" mov r10,r10,lsl #28\n");\r
1028 ot(" tst r0,r0\n");\r
1029 ot(" moveq r0,#4\n");\r
1030 ot(" bleq Exception\n");\r
1031#else\r
1032 ot(" mov r0,#4\n");\r
1033 ot(" bl Exception\n");\r
1034#endif\r
1035 ot("\n");\r
1036 Cycles=34;\r
1037 OpEnd();\r
1038\r
1039 // Unrecognised a-line and f-line opcodes throw an exception:\r
1040 ot("Op__al%s ;@ Unrecognised a-line opcode\n", ms?"":":");\r
1041 ot(" sub r4,r4,#2\n");\r
1042#if USE_AFLINE_CALLBACK\r
1043 ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
1044 ot(" mov r1,r10,lsr #28\n");\r
1045 ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
1046 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
1047 ot(" ldr r11,[r7,#0x94] ;@ UnrecognizedCallback\n");\r
1048 ot(" tst r11,r11\n");\r
1049 ot(" movne lr,pc\n");\r
1050 ot(" movne pc,r11 ;@ call UnrecognizedCallback if it is defined\n");\r
1051 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");\r
1052 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
1053 ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
1054 ot(" mov r10,r10,lsl #28\n");\r
1055 ot(" tst r0,r0\n");\r
1056 ot(" moveq r0,#0x0a\n");\r
1057 ot(" bleq Exception\n");\r
1058#else\r
1059 ot(" mov r0,#0x0a\n");\r
1060 ot(" bl Exception\n");\r
1061#endif\r
1062 ot("\n");\r
1063 Cycles=4;\r
1064 OpEnd();\r
1065\r
1066 ot("Op__fl%s ;@ Unrecognised f-line opcode\n", ms?"":":");\r
1067 ot(" sub r4,r4,#2\n");\r
1068#if USE_AFLINE_CALLBACK\r
1069 ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
1070 ot(" mov r1,r10,lsr #28\n");\r
1071 ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
1072 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
1073 ot(" ldr r11,[r7,#0x94] ;@ UnrecognizedCallback\n");\r
1074 ot(" tst r11,r11\n");\r
1075 ot(" movne lr,pc\n");\r
1076 ot(" movne pc,r11 ;@ call UnrecognizedCallback if it is defined\n");\r
1077 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");\r
1078 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
1079 ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
1080 ot(" mov r10,r10,lsl #28\n");\r
1081 ot(" tst r0,r0\n");\r
1082 ot(" moveq r0,#0x0b\n");\r
1083 ot(" bleq Exception\n");\r
1084#else\r
1085 ot(" mov r0,#0x0b\n");\r
1086 ot(" bl Exception\n");\r
1087#endif\r
1088 ot("\n");\r
1089 Cycles=4;\r
1090 OpEnd();\r
1091\r
6003a768 1092\r
d9d77995 1093 for (op=0;op<hot_opcode_count;op++)\r
1094 OpAny(hot_opcodes[op]);\r
6003a768 1095\r
1096 for (op=0;op<0x10000;op++)\r
1097 {\r
1098 if ((op&0xfff)==0) { printf("%x",op>>12); fflush(stdout); } // Update progress\r
1099\r
d9d77995 1100 if (!is_op_hot(op))\r
1101 OpAny(op);\r
6003a768 1102 }\r
1103\r
1104 ot("\n");\r
1105\r
1106 printf("]\n");\r
1107}\r
1108\r
d9d77995 1109// helper\r
1110static void ott(const char *str, int par, const char *nl, int nlp, int counter, int size)\r
1111{\r
1112 switch(size) {\r
1113 case 0: if((counter&7)==0) ot(ms?" dcb ":" .byte "); break;\r
1114 case 1: if((counter&7)==0) ot(ms?" dcw ":" .hword "); break;\r
1115 case 2: if((counter&7)==0) ot(ms?" dcd ":" .long "); break;\r
1116 }\r
1117 ot(str, par);\r
1118 if((counter&7)==7) ot(nl,nlp); else ot(",");\r
1119}\r
1120\r
6003a768 1121static void PrintJumpTable()\r
1122{\r
1123 int i=0,op=0,len=0;\r
1124\r
1125 ot(";@ -------------------------- Jump Table --------------------------\n");\r
6003a768 1126\r
d9d77995 1127 // space for decompressed table\r
1128 ot(ms?" area |.data|, data\n":" .data\n .align 4\n\n");\r
6003a768 1129\r
d9d77995 1130#if COMPRESS_JUMPTABLE\r
1131 int handlers=0,reps=0,*indexes,ip,u,out;\r
1132 // use some weird compression on the jump table\r
1133 indexes=(int *)malloc(0x10000*4);\r
1134 if(!indexes) { printf("ERROR: out of memory\n"); exit(1); }\r
1135 len=0x10000;\r
6003a768 1136\r
d9d77995 1137 ot("CycloneJumpTab%s\n", ms?"":":");\r
1138 if(ms) {\r
1139 for(i = 0; i < 0xa000/8; i++)\r
1140 ot(" dcd 0,0,0,0,0,0,0,0\n");\r
1141 } else\r
1142 ot(" .rept 0x%x\n .long 0,0,0,0,0,0,0,0\n .endr\n", 0xa000/8);\r
1143\r
1144 // hanlers live in "a-line" part of the table\r
1145 // first output nop,a-line,f-line handlers\r
1146 ot(ms?" dcd Op____,Op__al,Op__fl,":" .long Op____,Op__al,Op__fl,");\r
1147 handlers=3;\r
1148\r
1149 for(i=0;i<len;i++)\r
1150 {\r
1151 op=CyJump[i];\r
1152\r
1153 for(u=i-1; u>=0; u--) if(op == CyJump[u]) break; // already done with this op?\r
1154 if(u==-1 && op >= 0) {\r
1155 ott("Op%.4x",op," ;@ %.4x\n",i,handlers,2);\r
1156 indexes[op] = handlers;\r
1157 handlers++;\r
1158 }\r
1159 }\r
1160 if(handlers&7) {\r
1161 fseek(AsmFile, -1, SEEK_CUR); // remove last comma\r
1162 for(i = 8-(handlers&7); i > 0; i--)\r
1163 ot(",000000");\r
1164 ot("\n");\r
1165 }\r
1166 if(ms) {\r
1167 for(i = (0x4000-handlers)/8; i > 0; i--)\r
1168 ot(" dcd 0,0,0,0,0,0,0,0\n");\r
1169 } else {\r
1170 ot(ms?"":" .rept 0x%x\n .long 0,0,0,0,0,0,0,0\n .endr\n", (0x4000-handlers)/8);\r
1171 }\r
1172 printf("total distinct hanlers: %i\n",handlers);\r
1173 // output data\r
1174 for(i=0,ip=0; i < 0xf000; i++, ip++) {\r
1175 op=CyJump[i];\r
1176 if(op == -2) {\r
1177 // it must skip a-line area, because we keep our data there\r
1178 ott("0x%.4x", handlers<<4, "\n",0,ip++,1);\r
1179 ott("0x%.4x", 0x1000, "\n",0,ip,1);\r
1180 i+=0xfff;\r
1181 continue;\r
1182 }\r
1183 for(reps=1; i < 0xf000; i++, reps++) if(op != CyJump[i+1]) break;\r
1184 if(op>=0) out=indexes[op]<<4; else out=0; // unrecognised\r
1185 if(reps <= 0xe || reps==0x10) {\r
1186 if(reps!=0x10) out|=reps; else out|=0xf; // 0xf means 0x10 (0xf appeared to be unused anyway)\r
1187 ott("0x%.4x", out, "\n",0,ip,1);\r
1188 } else {\r
1189 ott("0x%.4x", out, "\n",0,ip++,1);\r
1190 ott("0x%.4x", reps,"\n",0,ip,1);\r
1191 }\r
1192 }\r
1193 if(ip&1) ott("0x%.4x", 0, "\n",0,ip++,1);\r
1194 if(ip&7) fseek(AsmFile, -1, SEEK_CUR); // remove last comma\r
1195 if(ip&7) {\r
1196 for(i = 8-(ip&7); i > 0; i--)\r
1197 ot(",0x0000");\r
1198 }\r
1199 ot("\n");\r
1200 if(ms) {\r
1201 for(i = (0x2000-ip/2)/8+1; i > 0; i--)\r
1202 ot(" dcd 0,0,0,0,0,0,0,0\n");\r
1203 } else {\r
1204 ot(" .rept 0x%x\n .long 0,0,0,0,0,0,0,0\n .endr\n", (0x2000-ip/2)/8+1);\r
1205 }\r
1206 ot("\n");\r
1207 free(indexes);\r
1208#else\r
1209 ot("CycloneJumpTab%s\n", ms?"":":");\r
1210 len=0xfffe; // Hmmm, armasm 2.50.8684 messes up with a 0x10000 long jump table\r
1211 // notaz: same thing with GNU as 2.9-psion-98r2 (reloc overflow)\r
1212 // this is due to COFF objects using only 2 bytes for reloc count\r
1213\r
1214 for (i=0;i<len;i++)\r
1215 {\r
1216 op=CyJump[i];\r
1217\r
1218 if(op>=0) ott("Op%.4x",op," ;@ %.4x\n",i-7,i,2);\r
1219 else if(op==-2) ott("Op__al",0, " ;@ %.4x\n",i-7,i,2);\r
1220 else if(op==-3) ott("Op__fl",0, " ;@ %.4x\n",i-7,i,2);\r
1221 else ott("Op____",0, " ;@ %.4x\n",i-7,i,2);\r
1222 }\r
1223 if(i&7) fseek(AsmFile, -1, SEEK_CUR); // remove last comma\r
1224\r
1225 ot("\n");\r
1226 ot(";@ notaz: we don't want to crash if we run into those 2 missing opcodes\n");\r
1227 ot(";@ so we leave this pattern to patch it later\n");\r
1228 ot("%s 0x78563412\n", ms?" dcd":" .long");\r
1229 ot("%s 0x56341290\n", ms?" dcd":" .long");\r
1230#endif\r
6003a768 1231}\r
1232\r
1233static int CycloneMake()\r
1234{\r
d9d77995 1235 int i;\r
1236 const char *name="Cyclone.s";\r
1237 const char *globl=ms?"export":".global";\r
1238\r
6003a768 1239 // Open the assembly file\r
1240 if (ms) name="Cyclone.asm";\r
1241 AsmFile=fopen(name,"wt"); if (AsmFile==NULL) return 1;\r
d9d77995 1242\r
6003a768 1243 printf("Making %s...\n",name);\r
1244\r
1245 ot("\n;@ Cyclone 68000 Emulator v%x.%.3x - Assembler Output\n\n",CycloneVer>>12,CycloneVer&0xfff);\r
1246\r
d9d77995 1247 ot(";@ Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)\n");\r
1248 ot(";@ Copyright (c) 2005-2011 Gražvydas \"notaz\" Ignotas (notasas (at) gmail.com)\n\n");\r
c41b9b97 1249\r
6003a768 1250 ot(";@ This code is licensed under the GNU General Public License version 2.0 and the MAME License.\n");\r
1251 ot(";@ You can choose the license that has the most advantages for you.\n\n");\r
1252 ot(";@ SVN repository can be found at http://code.google.com/p/cyclone68000/\n\n");\r
1253\r
1254 CyJump=(int *)malloc(0x40000); if (CyJump==NULL) return 1;\r
1255 memset(CyJump,0xff,0x40000); // Init to -1\r
d9d77995 1256 for(i=0xa000; i<0xb000; i++) CyJump[i] = -2; // a-line emulation\r
1257 for(i=0xf000; i<0x10000; i++) CyJump[i] = -3; // f-line emulation\r
6003a768 1258\r
d9d77995 1259 ot(ms?" area |.text|, code\n":" .text\n .align 4\n\n");\r
1260 ot(" %s CycloneInit\n",globl);\r
1261 ot(" %s CycloneReset\n",globl);\r
1262 ot(" %s CycloneRun\n",globl);\r
1263 ot(" %s CycloneSetSr\n",globl);\r
1264 ot(" %s CycloneGetSr\n",globl);\r
1265 ot(" %s CycloneFlushIrq\n",globl);\r
1266 ot(" %s CyclonePack\n",globl);\r
1267 ot(" %s CycloneUnpack\n",globl);\r
1268 ot(" %s CycloneVer\n",globl);\r
1269#if (CYCLONE_FOR_GENESIS == 2)\r
1270 ot(" %s CycloneSetRealTAS\n",globl);\r
1271 ot(" %s CycloneDoInterrupt\n",globl);\r
1272 ot(" %s CycloneDoTrace\n",globl);\r
1273 ot(" %s CycloneJumpTab\n",globl);\r
1274 ot(" %s Op____\n",globl);\r
c6237d9e 1275 ot(" %s Op6002\n",globl);\r
1276 ot(" %s Op6602\n",globl);\r
1277 ot(" %s Op6702\n",globl);\r
d9d77995 1278#endif\r
1279 ot("\n");\r
1280 ot(ms?"CycloneVer dcd 0x":"CycloneVer: .long 0x");\r
1281 ot("%.4x\n",CycloneVer);\r
6003a768 1282 ot("\n");\r
1283\r
1284 PrintFramework();\r
d9d77995 1285 arm_op_count = 0;\r
6003a768 1286 PrintOpcodes();\r
d9d77995 1287 printf("~%i ARM instructions used for opcode handlers\n", arm_op_count);\r
6003a768 1288 PrintJumpTable();\r
1289\r
1290 if (ms) ot(" END\n");\r
1291\r
d9d77995 1292 ot("\n\n;@ vim:filetype=armasm\n");\r
1293\r
6003a768 1294 fclose(AsmFile); AsmFile=NULL;\r
1295\r
d9d77995 1296#if 0\r
6003a768 1297 printf("Assembling...\n");\r
1298 // Assemble the file\r
1299 if (ms) system("armasm Cyclone.asm");\r
1300 else system("as -o Cyclone.o Cyclone.s");\r
1301 printf("Done!\n\n");\r
d9d77995 1302#endif\r
6003a768 1303\r
1304 free(CyJump);\r
1305 return 0;\r
1306}\r
1307\r
1308int main()\r
1309{\r
1310 printf("\n Cyclone 68000 Emulator v%x.%.3x - Core Creator\n\n",CycloneVer>>12,CycloneVer&0xfff);\r
1311\r
d9d77995 1312 // Make GAS or ARMASM version\r
1313 CycloneMake();\r
6003a768 1314 return 0;\r
1315}\r
d9d77995 1316\r
68000 emulator written in ARM 32-bit assembly