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dbra tracking and branch improvements
[cyclone68000.git] / OpBranch.cpp
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1\r
2// This file is part of the Cyclone 68000 Emulator\r
3\r
4// Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)\r
5// Copyright (c) 2005-2011 GraÅžvydas "notaz" Ignotas (notasas (at) gmail.com)\r
6\r
7// This code is licensed under the GNU General Public License version 2.0 and the MAME License.\r
8// You can choose the license that has the most advantages for you.\r
9\r
10// SVN repository can be found at http://code.google.com/p/cyclone68000/\r
11\r
12\r
13#include "app.h"\r
14\r
15// in/out address in r0, trashes all temp regs\r
16static void CheckPc(void)\r
17{\r
18#if USE_CHECKPC_CALLBACK\r
19 #ifdef MEMHANDLERS_DIRECT_PREFIX\r
20 ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);\r
21 #else\r
22 ot(";@ Check Memory Base+pc\n");\r
23 ot(" mov lr,pc\n");\r
24 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
25 ot("\n");\r
26 #endif\r
27#endif\r
28}\r
29\r
30// Push 32-bit value in r1 - trashes r0-r3,r12,lr\r
31void OpPush32()\r
32{\r
33 ot(";@ Push r1 onto stack\n");\r
34 ot(" ldr r0,[r7,#0x3c]\n");\r
35 ot(" sub r0,r0,#4 ;@ Predecrement A7\n");\r
36 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
37 MemHandler(1,2);\r
38 ot("\n");\r
39}\r
40\r
41// Push SR - trashes r0-r3,r12,lr\r
42void OpPushSr(int high)\r
43{\r
44 ot(";@ Push SR:\n");\r
45 OpFlagsToReg(high);\r
46 ot(" ldr r0,[r7,#0x3c]\n");\r
47 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
48 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
49 MemHandler(1,1);\r
50 ot("\n");\r
51}\r
52\r
53// Pop SR - trashes r0-r3\r
54static void PopSr(int high)\r
55{\r
56 ot(";@ Pop SR:\n");\r
57 ot(" ldr r0,[r7,#0x3c]\n");\r
58 ot(" add r1,r0,#2 ;@ Postincrement A7\n");\r
59 ot(" str r1,[r7,#0x3c] ;@ Save A7\n");\r
60 MemHandler(0,1);\r
61 ot("\n");\r
62 OpRegToFlags(high);\r
63}\r
64\r
65// Pop PC - trashes r0-r3\r
66static void PopPc()\r
67{\r
68 ot(";@ Pop PC:\n");\r
69 ot(" ldr r0,[r7,#0x3c]\n");\r
70 ot(" add r1,r0,#4 ;@ Postincrement A7\n");\r
71 ot(" str r1,[r7,#0x3c] ;@ Save A7\n");\r
72 MemHandler(0,2);\r
73 ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");\r
74 ot(" add r0,r0,r1 ;@ Memory Base+PC\n");\r
75 ot("\n");\r
76 CheckPc();\r
77#if EMULATE_ADDRESS_ERRORS_JUMP\r
78 ot(" mov r4,r0\n");\r
79#else\r
80 ot(" bic r4,r0,#1\n");\r
81#endif\r
82}\r
83\r
84int OpTrap(int op)\r
85{\r
86 int use=0;\r
87\r
88 use=op&~0xf;\r
89 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
90\r
91 OpStart(op,0x10);\r
92 ot(" and r0,r8,#0xf ;@ Get trap number\n");\r
93 ot(" orr r0,r0,#0x20 ;@ 32+n\n");\r
94 ot(" bl Exception\n");\r
95 ot("\n");\r
96\r
97 Cycles=38; OpEnd(0x10);\r
98\r
99 return 0;\r
100}\r
101\r
102// --------------------- Opcodes 0x4e50+ ---------------------\r
103int OpLink(int op)\r
104{\r
105 int use=0,reg;\r
106\r
107 use=op&~7;\r
108 reg=op&7;\r
109 if (reg==7) use=op;\r
110 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
111\r
112 OpStart(op,0x10);\r
113\r
114 if(reg!=7) {\r
115 ot(";@ Get An\n");\r
116 EaCalc(11, 7, 8, 2, 1);\r
117 EaRead(11, 1, 8, 2, 7, 1);\r
118 }\r
119\r
120 ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");\r
121 ot(" sub r0,r0,#4 ;@ A7-=4\n");\r
122 ot(" mov r8,r0 ;@ abuse r8\n");\r
123 if(reg==7) ot(" mov r1,r0\n");\r
124 ot("\n");\r
125 \r
126 ot(";@ Write An to Stack\n");\r
127 MemHandler(1,2);\r
128\r
129 ot(";@ Save to An\n");\r
130 if(reg!=7)\r
131 EaWrite(11,8, 8, 2, 7, 1);\r
132\r
133 ot(";@ Get offset:\n");\r
134 EaCalc(0,0,0x3c,1); // abused r8 is ok because of imm EA\r
135 EaRead(0,0,0x3c,1,0);\r
136\r
137 ot(" add r8,r8,r0 ;@ Add offset to A7\n");\r
138 ot(" str r8,[r7,#0x3c]\n");\r
139 ot("\n");\r
140\r
141 Cycles=16;\r
142 OpEnd(0x10);\r
143 return 0;\r
144}\r
145\r
146// --------------------- Opcodes 0x4e58+ ---------------------\r
147int OpUnlk(int op)\r
148{\r
149 int use=0;\r
150\r
151 use=op&~7;\r
152 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
153\r
154 OpStart(op,0x10);\r
155\r
156 ot(";@ Get An\n");\r
157 EaCalc(11, 0xf, 8, 2, 1);\r
158 EaRead(11, 0, 8, 2, 0xf, 1);\r
159\r
160 ot(" add r8,r0,#4 ;@ A7+=4, abuse r8\n");\r
161 ot("\n");\r
162 ot(";@ Pop An from stack:\n");\r
163 MemHandler(0,2);\r
164 ot("\n");\r
165 ot(" str r8,[r7,#0x3c] ;@ Save A7\n");\r
166 ot("\n");\r
167 ot(";@ An = value from stack:\n");\r
168 EaWrite(11, 0, 8, 2, 7, 1);\r
169\r
170 Cycles=12;\r
171 OpEnd(0x10);\r
172 return 0;\r
173}\r
174\r
175// --------------------- Opcodes 0x4e70+ ---------------------\r
176// 01001110 01110ttt\r
177int Op4E70(int op)\r
178{\r
179 int type=0;\r
180\r
181 type=op&7; // reset/nop/stop/rte/rtd/rts/trapv/rtr\r
182\r
183 switch (type)\r
184 {\r
185 case 1: // nop\r
186 OpStart(op);\r
187 Cycles=4;\r
188 OpEnd();\r
189 return 0;\r
190\r
191 case 3: // rte\r
192 OpStart(op,0x10,0,0,1); Cycles=20;\r
193 PopSr(1);\r
194 PopPc();\r
195 ot(" ldr r1,[r7,#0x44] ;@ reload SR high\n");\r
196 SuperChange(op,1);\r
197#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO || EMULATE_HALT\r
198 ot(" ldr r1,[r7,#0x58]\n");\r
199 ot(" bic r1,r1,#0x0c ;@ clear 'not processing instruction' and 'doing addr error' bits\n");\r
200 ot(" str r1,[r7,#0x58]\n");\r
201#endif\r
202#if EMULATE_ADDRESS_ERRORS_JUMP\r
203 ot(" tst r4,#1 ;@ address error?\n");\r
204 ot(" bne ExceptionAddressError_r_prg_r4\n");\r
205#endif\r
206 opend_check_interrupt = 1;\r
207 opend_check_trace = 1;\r
208 OpEnd(0x10,0);\r
209 return 0;\r
210\r
211 case 5: // rts\r
212 OpStart(op,0x10); Cycles=16;\r
213 PopPc();\r
214#if EMULATE_ADDRESS_ERRORS_JUMP\r
215 ot(" tst r4,#1 ;@ address error?\n");\r
216 ot(" bne ExceptionAddressError_r_prg_r4\n");\r
217#endif\r
218 OpEnd(0x10);\r
219 return 0;\r
220\r
221 case 6: // trapv\r
222 OpStart(op,0x10,0,1); Cycles=4;\r
223 ot(" tst r10,#0x10000000\n");\r
224 ot(" subne r5,r5,#%i\n",34);\r
225 ot(" movne r0,#7 ;@ TRAPV exception\n");\r
226 ot(" blne Exception\n");\r
227 opend_op_changes_cycles = 1;\r
228 OpEnd(0x10,0);\r
229 return 0;\r
230\r
231 case 7: // rtr\r
232 OpStart(op,0x10); Cycles=20;\r
233 PopSr(0);\r
234 PopPc();\r
235#if EMULATE_ADDRESS_ERRORS_JUMP\r
236 ot(" tst r4,#1 ;@ address error?\n");\r
237 ot(" bne ExceptionAddressError_r_prg_r4\n");\r
238#endif\r
239 OpEnd(0x10);\r
240 return 0;\r
241\r
242 default:\r
243 return 1;\r
244 }\r
245}\r
246\r
247// --------------------- Opcodes 0x4e80+ ---------------------\r
248// Emit a Jsr/Jmp opcode, 01001110 1meeeeee\r
249int OpJsr(int op)\r
250{\r
251 int use=0;\r
252 int sea=0;\r
253\r
254 sea=op&0x003f;\r
255\r
256 // See if we can do this opcode:\r
257 if (EaCanRead(sea,-1)==0) return 1;\r
258\r
259 use=OpBase(op,0);\r
260 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
261\r
262 OpStart(op,(op&0x40)?0:0x10);\r
263\r
264 ot(" ldr r11,[r7,#0x60] ;@ Get Memory base\n");\r
265 ot("\n");\r
266 EaCalc(12,0x003f,sea,0);\r
267\r
268 ot(";@ Jump - Get new PC from r12\n");\r
269 ot(" add r0,r12,r11 ;@ Memory Base + New PC\n");\r
270 ot("\n");\r
271 CheckPc();\r
272 if (!(op&0x40))\r
273 {\r
274 ot(" ldr r2,[r7,#0x3c]\n");\r
275 ot(" sub r1,r4,r11 ;@ r1 = Old PC\n");\r
276 }\r
277#if EMULATE_ADDRESS_ERRORS_JUMP\r
278 // jsr prefetches next instruction before pushing old PC,\r
279 // according to http://pasti.fxatari.com/68kdocs/68kPrefetch.html\r
280 ot(" mov r4,r0\n");\r
281 ot(" tst r4,#1 ;@ address error?\n");\r
282 ot(" bne ExceptionAddressError_r_prg_r4\n");\r
283#else\r
284 ot(" bic r4,r0,#1\n");\r
285#endif\r
286\r
287 if (!(op&0x40))\r
288 {\r
289 ot(";@ Push old PC onto stack\n");\r
290 ot(" sub r0,r2,#4 ;@ Predecrement A7\n");\r
291 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
292 MemHandler(1,2);\r
293 }\r
294\r
295 Cycles=(op&0x40) ? 4 : 12;\r
296 Cycles+=Ea_add_ns((op&0x40) ? g_jmp_cycle_table : g_jsr_cycle_table, sea);\r
297\r
298 OpEnd((op&0x40)?0:0x10);\r
299\r
300 return 0;\r
301}\r
302\r
303// --------------------- Opcodes 0x50c8+ ---------------------\r
304\r
305// ARM version of 68000 condition codes:\r
306static const char * const Cond[16]=\r
307{\r
308 "", "", "hi","ls","cc","cs","ne","eq",\r
309 "vc","vs","pl","mi","ge","lt","gt","le"\r
310};\r
311\r
312// Emit a Dbra opcode, 0101cccc 11001nnn vv\r
313int OpDbra(int op)\r
314{\r
315 int use=0;\r
316 int cc=0;\r
317\r
318 use=op&~7; // Use same handler\r
319 cc=(op>>8)&15;\r
320 \r
321 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
322 OpStart(op);\r
323\r
324 switch (cc)\r
325 {\r
326 case 0: // T\r
327 case 1: // F\r
328 break;\r
329 case 2: // hi\r
330 ot(" tst r10,#0x60000000 ;@ hi: !C && !Z\n");\r
331 ot(" beq DbraTrue\n\n");\r
332 break;\r
333 case 3: // ls\r
334 ot(" tst r10,#0x60000000 ;@ ls: C || Z\n");\r
335 ot(" bne DbraTrue\n\n");\r
336 break;\r
337 default:\r
338 ot(";@ Is the condition true?\n");\r
339 ot(" msr cpsr_flg,r10 ;@ ARM flags = 68000 flags\n");\r
340 ot(";@ If so, don't dbra\n");\r
341 ot(" b%s DbraTrue\n\n",Cond[cc]);\r
342 break;\r
343 }\r
344\r
345 if (cc!=0)\r
346 {\r
347 ot(";@ Decrement Dn.w\n");\r
348 ot(" and r1,r8,#0x0007\n");\r
349 ot(" mov r1,r1,lsl #2\n");\r
350 ot(" ldrsh r0,[r7,r1]\n");\r
351 ot(" strb r8,[r7,#0x45] ;@ not polling\n");\r
352 ot(" sub r0,r0,#1\n");\r
353 ot(" strh r0,[r7,r1]\n");\r
354 ot("\n");\r
355\r
356 ot(";@ Check if Dn.w is -1\n");\r
357 ot(" cmn r0,#1\n");\r
358\r
359#if (USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA) || EMULATE_ADDRESS_ERRORS_JUMP\r
360 ot(" beq DbraMin1\n");\r
361 ot("\n");\r
362\r
363 ot(";@ Get Branch offset:\n");\r
364 ot(" ldrsh r0,[r4]\n");\r
365 ot(" add r0,r4,r0 ;@ r0 = New PC\n");\r
366 CheckPc();\r
367#if EMULATE_ADDRESS_ERRORS_JUMP\r
368 ot(" mov r4,r0\n");\r
369 ot(" tst r4,#1 ;@ address error?\n");\r
370 ot(" bne ExceptionAddressError_r_prg_r4\n");\r
371#else\r
372 ot(" bic r4,r0,#1\n");\r
373#endif\r
374#else\r
375 ot("\n");\r
376 ot(";@ Get Branch offset:\n");\r
377 ot(" ldrnesh r0,[r4]\n");\r
378 ot(" addeq r4,r4,#2 ;@ Skip branch offset\n");\r
379 ot(" subeq r5,r5,#4 ;@ additional cycles\n");\r
380 ot(" addne r4,r4,r0 ;@ r4 = New PC\n");\r
381 ot(" bic r4,r4,#1\n"); // we do not emulate address errors\r
382 ot("\n");\r
383#endif\r
384 Cycles=12-2;\r
385 OpEnd();\r
386 }\r
387 \r
388 //if (cc==0||cc>=2)\r
389 if (op==0x50c8)\r
390 {\r
391 ot(";@ condition true:\n");\r
392 ot("DbraTrue%s\n", ms?"":":");\r
393 ot(" add r4,r4,#2 ;@ Skip branch offset\n");\r
394 ot("\n");\r
395 Cycles=12;\r
396 OpEnd();\r
397 }\r
398\r
399#if (USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA) || EMULATE_ADDRESS_ERRORS_JUMP\r
400 if (op==0x51c8)\r
401 {\r
402 ot(";@ Dn.w is -1:\n");\r
403 ot("DbraMin1%s\n", ms?"":":");\r
404 ot(" add r4,r4,#2 ;@ Skip branch offset\n");\r
405 ot("\n");\r
406 Cycles=12+2;\r
407 OpEnd();\r
408 }\r
409#endif\r
410\r
411 return 0;\r
412}\r
413\r
414// --------------------- Opcodes 0x6000+ ---------------------\r
415// Emit a Branch opcode 0110cccc nn (cccc=condition)\r
416int OpBranch(int op)\r
417{\r
418 int size=0,use=0,checkpc=0;\r
419 int offset=0;\r
420 int cc=0;\r
421 const char *asr_r11="";\r
422 int pc_reg=0;\r
423\r
424 offset=(char)(op&0xff);\r
425 cc=(op>>8)&15;\r
426\r
427 // Special offsets:\r
428 if (offset==0) size=1;\r
429 if (offset==-1) size=2;\r
430\r
431 if (size==2) size=0; // 000 model does not support long displacement\r
432 if (size) use=op; // 16-bit or 32-bit\r
433 else use=(op&0xff01)+2; // Use same opcode for all 8-bit branches\r
434\r
435 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
436 OpStart(op,size?0x10:0);\r
437 Cycles=10; // Assume branch taken\r
438\r
439 switch (cc)\r
440 {\r
441 case 0: // T\r
442 case 1: // F\r
443 break;\r
444 case 2: // hi\r
445 ot(" tst r10,#0x60000000 ;@ hi: !C && !Z\n");\r
446 ot(" bne BccDontBranch%i\n\n",8<<size);\r
447 break;\r
448 case 3: // ls\r
449 ot(" tst r10,#0x60000000 ;@ ls: C || Z\n");\r
450 ot(" beq BccDontBranch%i\n\n",8<<size);\r
451 break;\r
452 default:\r
453 ot(";@ Is the condition true?\n");\r
454 ot(" msr cpsr_flg,r10 ;@ ARM flags = 68000 flags\n");\r
455 ot(" b%s BccDontBranch%i\n\n",Cond[cc^1],8<<size);\r
456 break;\r
457 }\r
458\r
459 if (size) \r
460 {\r
461 if (size<2)\r
462 {\r
463 ot(" ldrsh r11,[r4] ;@ Fetch Branch offset\n");\r
464 }\r
465 else\r
466 {\r
467 ot(" ldrh r2,[r4] ;@ Fetch Branch offset\n");\r
468 ot(" ldrh r11,[r4,#2]\n");\r
469 ot(" orr r11,r11,r2,lsl #16\n");\r
470 }\r
471 }\r
472 else\r
473 {\r
474 ot(" mov r11,r8,asl #24 ;@ Shift 8-bit signed offset up...\n\n");\r
475 asr_r11=",asr #24";\r
476 }\r
477\r
478 ot(";@ Branch taken - Add on r0 to PC\n");\r
479\r
480 if (cc==1)\r
481 {\r
482 ot(";@ Bsr - remember old PC\n");\r
483 ot(" ldr r12,[r7,#0x60] ;@ Get Memory base\n");\r
484 ot(" ldr r2,[r7,#0x3c]\n");\r
485 ot(" sub r1,r4,r12 ;@ r1 = Old PC\n");\r
486 if (size) ot(" add r1,r1,#%d\n",1<<size);\r
487 ot("\n");\r
488 ot(";@ Push r1 onto stack\n");\r
489 ot(" sub r0,r2,#4 ;@ Predecrement A7\n");\r
490 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
491 MemHandler(1,2);\r
492 ot("\n");\r
493 Cycles=18; // always 18\r
494 }\r
495\r
496#if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_8\r
497 if (offset!=0 && offset!=-1) checkpc=1;\r
498#endif\r
499#if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_16\r
500 if (offset==0) checkpc=1;\r
501#endif\r
502#if USE_CHECKPC_CALLBACK\r
503 if (offset==-1) checkpc=1;\r
504#endif\r
505 if (checkpc)\r
506 {\r
507 ot(" add r0,r4,r11%s ;@ New PC\n",asr_r11);\r
508 CheckPc();\r
509 pc_reg=0;\r
510 }\r
511 else\r
512 {\r
513 ot(" add r4,r4,r11%s ;@ r4 = New PC\n",asr_r11);\r
514 pc_reg=4;\r
515 }\r
516\r
517 if ((op & 1) || size != 0)\r
518 {\r
519#if EMULATE_ADDRESS_ERRORS_JUMP\r
520 if (pc_reg!=4)\r
521 {\r
522 ot(" mov r4,r%d\n",pc_reg);\r
523 pc_reg=4;\r
524 }\r
525 if (size)\r
526 {\r
527 ot(" tst r4,#1 ;@ address error?\n");\r
528 ot(" bne ExceptionAddressError_r_prg_r4\n");\r
529 }\r
530 else\r
531 {\r
532 ot(" b ExceptionAddressError_r_prg_r4\n");\r
533 }\r
534#else\r
535 ot(" bic r4,r%d,#1\n",pc_reg);\r
536 pc_reg=4;\r
537#endif\r
538 }\r
539 if (pc_reg!=4)\r
540 ot(" mov r4,r%d\n",pc_reg);\r
541 ot("\n");\r
542\r
543 OpEnd(size?0x10:0);\r
544\r
545 // since all "DontBranch" code is same for every size, output only once\r
546 if (cc>=2&&(op&0xff01)==0x6700)\r
547 {\r
548 ot("BccDontBranch%i%s\n", 8<<size, ms?"":":");\r
549 if (size) ot(" add r4,r4,#%d\n",1<<size);\r
550 Cycles+=(size==1) ? 2 : -2; // Branch not taken\r
551 OpEnd(0);\r
552 }\r
553\r
554 return 0;\r
555}\r
556\r
68000 emulator written in ARM 32-bit assembly