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restructure the repository to be Cyclone only
[cyclone68000.git] / OpLogic.cpp
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1\r
2// This file is part of the Cyclone 68000 Emulator\r
3\r
4// Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)\r
5// Copyright (c) 2005-2011 GraÅžvydas "notaz" Ignotas (notasas (at) gmail.com)\r
6\r
7// This code is licensed under the GNU General Public License version 2.0 and the MAME License.\r
8// You can choose the license that has the most advantages for you.\r
9\r
10// SVN repository can be found at http://code.google.com/p/cyclone68000/\r
11\r
12\r
13#include "app.h"\r
14\r
15// --------------------- Opcodes 0x0100+ ---------------------\r
16// Emit a Btst (Register) opcode 0000nnn1 ttaaaaaa\r
17int OpBtstReg(int op)\r
18{\r
19 int use=0;\r
20 int type=0,sea=0,tea=0;\r
21 int size=0;\r
22\r
23 type=(op>>6)&3; // Btst/Bchg/Bclr/Bset\r
24 // Get source and target EA\r
25 sea=(op>>9)&7;\r
26 tea=op&0x003f;\r
27 if (tea<0x10) size=2; // For registers, 32-bits\r
28\r
29 if ((tea&0x38)==0x08) return 1; // movep\r
30\r
31 // See if we can do this opcode:\r
32 if (EaCanRead(tea,0)==0) return 1;\r
33 if (type>0)\r
34 {\r
35 if (EaCanWrite(tea)==0) return 1;\r
36 }\r
37\r
38 use=OpBase(op,size);\r
39 use&=~0x0e00; // Use same handler for all registers\r
40 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
41\r
42 OpStart(op,tea);\r
43\r
44 if(type==1||type==3) {\r
45 Cycles=8;\r
46 } else {\r
47 Cycles=type?8:4;\r
48 if(size>=2) Cycles+=2;\r
49 }\r
50\r
51 EaCalcReadNoSE(-1,11,sea,0,0x0e00);\r
52\r
53 EaCalcReadNoSE((type>0)?8:-1,0,tea,size,0x003f);\r
54\r
55 if (tea>=0x10)\r
56 ot(" and r11,r11,#7 ;@ mem - do mod 8\n"); // size always 0\r
57 else ot(" and r11,r11,#31 ;@ reg - do mod 32\n"); // size always 2\r
58 ot("\n");\r
59\r
60 ot(" mov r1,#1\n");\r
61 ot(" tst r0,r1,lsl r11 ;@ Do arithmetic\n");\r
62 ot(" bicne r10,r10,#0x40000000\n");\r
63 ot(" orreq r10,r10,#0x40000000 ;@ Get Z flag\n");\r
64 ot("\n");\r
65\r
66 if (type>0)\r
67 {\r
68 if (type==1) ot(" eor r1,r0,r1,lsl r11 ;@ Toggle bit\n");\r
69 if (type==2) ot(" bic r1,r0,r1,lsl r11 ;@ Clear bit\n");\r
70 if (type==3) ot(" orr r1,r0,r1,lsl r11 ;@ Set bit\n");\r
71 ot("\n");\r
72 EaWrite(8,1,tea,size,0x003f,0,0);\r
73 }\r
74 OpEnd(tea);\r
75\r
76 return 0;\r
77}\r
78\r
79// --------------------- Opcodes 0x0800+ ---------------------\r
80// Emit a Btst/Bchg/Bclr/Bset (Immediate) opcode 00001000 ttaaaaaa nn\r
81int OpBtstImm(int op)\r
82{\r
83 int type=0,sea=0,tea=0;\r
84 int use=0;\r
85 int size=0;\r
86\r
87 type=(op>>6)&3;\r
88 // Get source and target EA\r
89 sea= 0x003c;\r
90 tea=op&0x003f;\r
91 if (tea<0x10) size=2; // For registers, 32-bits\r
92\r
93 // See if we can do this opcode:\r
94 if (EaCanRead(tea,0)==0||EaAn(tea)||tea==0x3c) return 1;\r
95 if (type>0)\r
96 {\r
97 if (EaCanWrite(tea)==0) return 1;\r
98 }\r
99\r
100 use=OpBase(op,size);\r
101 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
102\r
103 OpStart(op,sea,tea);\r
104\r
105 ot("\n");\r
106 EaCalcReadNoSE(-1,0,sea,0,0);\r
107 ot(" mov r11,#1\n");\r
108 ot(" bic r10,r10,#0x40000000 ;@ Blank Z flag\n");\r
109 if (tea>=0x10)\r
110 ot(" and r0,r0,#7 ;@ mem - do mod 8\n"); // size always 0\r
111 else ot(" and r0,r0,#0x1F ;@ reg - do mod 32\n"); // size always 2\r
112 ot(" mov r11,r11,lsl r0 ;@ Make bit mask\n");\r
113 ot("\n");\r
114\r
115 if(type==1||type==3) {\r
116 Cycles=12;\r
117 } else {\r
118 Cycles=type?12:8;\r
119 if(size>=2) Cycles+=2;\r
120 }\r
121\r
122 EaCalcReadNoSE((type>0)?8:-1,0,tea,size,0x003f);\r
123 ot(" tst r0,r11 ;@ Do arithmetic\n");\r
124 ot(" orreq r10,r10,#0x40000000 ;@ Get Z flag\n");\r
125 ot("\n");\r
126\r
127 if (type>0)\r
128 {\r
129 if (type==1) ot(" eor r1,r0,r11 ;@ Toggle bit\n");\r
130 if (type==2) ot(" bic r1,r0,r11 ;@ Clear bit\n");\r
131 if (type==3) ot(" orr r1,r0,r11 ;@ Set bit\n");\r
132 ot("\n");\r
133 EaWrite(8, 1,tea,size,0x003f,0,0);\r
134#if CYCLONE_FOR_GENESIS && !MEMHANDLERS_CHANGE_CYCLES\r
135 // this is a bit hacky (device handlers might modify cycles)\r
136 if (tea==0x38||tea==0x39)\r
137 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
138#endif\r
139 }\r
140\r
141 OpEnd(sea,tea);\r
142\r
143 return 0;\r
144}\r
145\r
146// --------------------- Opcodes 0x4000+ ---------------------\r
147int OpNeg(int op)\r
148{\r
149 // 01000tt0 xxeeeeee (tt=negx/clr/neg/not, xx=size, eeeeee=EA)\r
150 int type=0,size=0,ea=0,use=0;\r
151\r
152 type=(op>>9)&3;\r
153 ea =op&0x003f;\r
154 size=(op>>6)&3; if (size>=3) return 1;\r
155\r
156 // See if we can do this opcode:\r
157 if (EaCanRead (ea,size)==0||EaAn(ea)) return 1;\r
158 if (EaCanWrite(ea )==0) return 1;\r
159\r
160 use=OpBase(op,size);\r
161 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
162\r
163 OpStart(op,ea); Cycles=size<2?4:6;\r
164 if(ea >= 0x10) Cycles*=2;\r
165\r
166 EaCalc (11,0x003f,ea,size,0,0);\r
167\r
168 if (type!=1) EaRead (11,0,ea,size,0x003f,0,0); // Don't need to read for 'clr' (or do we, for a dummy read?)\r
169 if (type==1) ot("\n");\r
170\r
171 if (type==0)\r
172 {\r
173 ot(";@ Negx:\n");\r
174 GetXBit(1);\r
175 if(size!=2) ot(" mov r0,r0,asl #%i\n",size?16:24);\r
176 ot(" rscs r1,r0,#0 ;@ do arithmetic\n");\r
177 ot(" orr r3,r10,#0xb0000000 ;@ for old Z\n");\r
178 OpGetFlags(1,1,0);\r
179 if(size!=2) {\r
180 ot(" movs r1,r1,asr #%i\n",size?16:24);\r
181 ot(" orreq r10,r10,#0x40000000 ;@ possily missed Z\n");\r
182 }\r
183 ot(" andeq r10,r10,r3 ;@ fix Z\n");\r
184 ot("\n");\r
185 }\r
186\r
187 if (type==1)\r
188 {\r
189 ot(";@ Clear:\n");\r
190 ot(" mov r1,#0\n");\r
191 ot(" mov r10,#0x40000000 ;@ NZCV=0100\n");\r
192 ot("\n");\r
193 }\r
194\r
195 if (type==2)\r
196 {\r
197 ot(";@ Neg:\n");\r
198 if(size!=2) ot(" mov r0,r0,asl #%i\n",size?16:24);\r
199 ot(" rsbs r1,r0,#0\n");\r
200 OpGetFlags(1,1);\r
201 if(size!=2) ot(" mov r1,r1,asr #%i\n",size?16:24);\r
202 ot("\n");\r
203 }\r
204\r
205 if (type==3)\r
206 {\r
207 ot(";@ Not:\n");\r
208 if(size!=2) {\r
209 ot(" mov r0,r0,asl #%i\n",size?16:24);\r
210 ot(" mvn r1,r0,asr #%i\n",size?16:24);\r
211 }\r
212 else\r
213 ot(" mvn r1,r0\n");\r
214 ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
215 OpGetFlags(0,0);\r
216 ot("\n");\r
217 }\r
218\r
219 if (type==1) eawrite_check_addrerr=1;\r
220 EaWrite(11, 1,ea,size,0x003f,0,0);\r
221\r
222 OpEnd(ea);\r
223\r
224 return 0;\r
225}\r
226\r
227// --------------------- Opcodes 0x4840+ ---------------------\r
228// Swap, 01001000 01000nnn swap Dn\r
229int OpSwap(int op)\r
230{\r
231 int ea=0,use=0;\r
232\r
233 ea=op&7;\r
234 use=op&~0x0007; // Use same opcode for all An\r
235\r
236 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
237\r
238 OpStart(op); Cycles=4;\r
239\r
240 EaCalc (11,0x0007,ea,2,1);\r
241 EaRead (11, 0,ea,2,0x0007,1);\r
242\r
243 ot(" mov r1,r0,ror #16\n");\r
244 ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
245 OpGetFlags(0,0);\r
246\r
247 EaWrite(11, 1,8,2,0x0007,1);\r
248\r
249 OpEnd();\r
250\r
251 return 0;\r
252}\r
253\r
254// --------------------- Opcodes 0x4a00+ ---------------------\r
255// Emit a Tst opcode, 01001010 xxeeeeee\r
256int OpTst(int op)\r
257{\r
258 int sea=0;\r
259 int size=0,use=0;\r
260\r
261 sea=op&0x003f;\r
262 size=(op>>6)&3; if (size>=3) return 1;\r
263\r
264 // See if we can do this opcode:\r
265 if (EaCanWrite(sea)==0||EaAn(sea)) return 1;\r
266\r
267 use=OpBase(op,size);\r
268 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
269\r
270 OpStart(op,sea); Cycles=4;\r
271\r
272 EaCalc ( 0,0x003f,sea,size,1);\r
273 EaRead ( 0, 0,sea,size,0x003f,1);\r
274\r
275 ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
276 ot(" mrs r10,cpsr ;@ r10=flags\n");\r
277 ot("\n");\r
278\r
279 OpEnd(sea);\r
280 return 0;\r
281}\r
282\r
283// --------------------- Opcodes 0x4880+ ---------------------\r
284// Emit an Ext opcode, 01001000 1x000nnn\r
285int OpExt(int op)\r
286{\r
287 int ea=0;\r
288 int size=0,use=0;\r
289 int shift=0;\r
290\r
291 ea=op&0x0007;\r
292 size=(op>>6)&1;\r
293 shift=32-(8<<size);\r
294\r
295 use=OpBase(op,size);\r
296 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
297\r
298 OpStart(op); Cycles=4;\r
299\r
300 EaCalc (11,0x0007,ea,size+1,0,0);\r
301 EaRead (11, 0,ea,size+1,0x0007,0,0);\r
302\r
303 ot(" mov r0,r0,asl #%d\n",shift);\r
304 ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
305 ot(" mrs r10,cpsr ;@ r10=flags\n");\r
306 ot(" mov r1,r0,asr #%d\n",shift);\r
307 ot("\n");\r
308\r
309 EaWrite(11, 1,ea,size+1,0x0007,0,0);\r
310\r
311 OpEnd();\r
312 return 0;\r
313}\r
314\r
315// --------------------- Opcodes 0x50c0+ ---------------------\r
316// Emit a Set cc opcode, 0101cccc 11eeeeee\r
317int OpSet(int op)\r
318{\r
319 int cc=0,ea=0;\r
320 int size=0,use=0,changed_cycles=0;\r
321 static const char * const cond[16]=\r
322 {\r
323 "al","", "hi","ls","cc","cs","ne","eq",\r
324 "vc","vs","pl","mi","ge","lt","gt","le"\r
325 };\r
326\r
327 cc=(op>>8)&15;\r
328 ea=op&0x003f;\r
329\r
330 if ((ea&0x38)==0x08) return 1; // dbra, not scc\r
331 \r
332 // See if we can do this opcode:\r
333 if (EaCanWrite(ea)==0) return 1;\r
334\r
335 use=OpBase(op,size);\r
336 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
337\r
338 changed_cycles=ea<8 && cc>=2;\r
339 OpStart(op,ea,0,changed_cycles); Cycles=8;\r
340 if (ea<8) Cycles=4;\r
341\r
342 if (cc)\r
343 ot(" mov r1,#0\n");\r
344\r
345 switch (cc)\r
346 {\r
347 case 0: // T\r
348 ot(" mvn r1,#0\n");\r
349 if (ea<8) Cycles+=2;\r
350 break;\r
351 case 1: // F\r
352 break;\r
353 case 2: // hi\r
354 ot(" tst r10,#0x60000000 ;@ hi: !C && !Z\n");\r
355 ot(" mvneq r1,r1\n");\r
356 if (ea<8) ot(" subeq r5,r5,#2 ;@ Extra cycles\n");\r
357 break;\r
358 case 3: // ls\r
359 ot(" tst r10,#0x60000000 ;@ ls: C || Z\n");\r
360 ot(" mvnne r1,r1\n");\r
361 if (ea<8) ot(" subne r5,r5,#2 ;@ Extra cycles\n");\r
362 break;\r
363 default:\r
364 ot(";@ Is the condition true?\n");\r
365 ot(" msr cpsr_flg,r10 ;@ ARM flags = 68000 flags\n");\r
366 ot(" mvn%s r1,r1\n",cond[cc]);\r
367 if (ea<8) ot(" sub%s r5,r5,#2 ;@ Extra cycles\n",cond[cc]);\r
368 break;\r
369 }\r
370\r
371 ot("\n");\r
372\r
373 eawrite_check_addrerr=1;\r
374 EaCalc (0,0x003f, ea,size,0,0);\r
375 EaWrite(0, 1, ea,size,0x003f,0,0);\r
376\r
377 opend_op_changes_cycles=changed_cycles;\r
378 OpEnd(ea,0);\r
379 return 0;\r
380}\r
381\r
382// Emit a Asr/Lsr/Roxr/Ror opcode\r
383static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)\r
384{\r
385 char pct[8]=""; // count\r
386 int shift=32-(8<<size);\r
387\r
388 if (count>=1) sprintf(pct,"#%d",count); // Fixed count\r
389\r
390 if (usereg)\r
391 {\r
392 ot(";@ Use Dn for count:\n");\r
393 ot(" and r2,r8,#0x0e00\n");\r
394 ot(" ldr r2,[r7,r2,lsr #7]\n");\r
395 ot(" and r2,r2,#63\n");\r
396 ot("\n");\r
397 strcpy(pct,"r2");\r
398 }\r
399 else if (count<0)\r
400 {\r
401 ot(" mov r2,r8,lsr #9 ;@ Get 'n'\n");\r
402 ot(" and r2,r2,#7\n\n"); strcpy(pct,"r2");\r
403 }\r
404\r
405 // Take 2*n cycles:\r
406 if (count<0) ot(" sub r5,r5,r2,asl #1 ;@ Take 2*n cycles\n\n");\r
407 else Cycles+=count<<1;\r
408\r
409 if (type<2)\r
410 {\r
411 // Asr/Lsr\r
412 if (dir==0 && size<2)\r
413 {\r
414 ot(";@ For shift right, use loworder bits for the operation:\n");\r
415 ot(" mov r0,r0,%s #%d\n",type?"lsr":"asr",32-(8<<size));\r
416 ot("\n");\r
417 }\r
418\r
419 if (type==0 && dir) ot(" adds r3,r0,#0 ;@ save old value for V flag calculation, also clear V\n");\r
420\r
421 ot(";@ Shift register:\n");\r
422 if (type==0) ot(" movs r0,r0,%s %s\n",dir?"asl":"asr",pct);\r
423 if (type==1) ot(" movs r0,r0,%s %s\n",dir?"lsl":"lsr",pct);\r
424\r
425 OpGetFlags(0,0);\r
426 if (usereg) { // store X only if count is not 0\r
427 ot(" cmp %s,#0 ;@ shifting by 0?\n",pct);\r
428 ot(" biceq r10,r10,#0x20000000 ;@ if so, clear carry\n");\r
429 ot(" strne r10,[r7,#0x4c] ;@ else Save X bit\n");\r
430 } else {\r
431 // count will never be 0 if we use immediate\r
432 ot(" str r10,[r7,#0x4c] ;@ Save X bit\n");\r
433 }\r
434 ot("\n");\r
435\r
436 if (dir==0 && size<2)\r
437 {\r
438 ot(";@ restore after right shift:\n");\r
439 ot(" movs r0,r0,lsl #%d\n",32-(8<<size));\r
440 if (type)\r
441 ot(" orrmi r10,r10,#0x80000000 ;@ Potentially missed N flag\n");\r
442 ot("\n");\r
443 }\r
444\r
445 if (type==0 && dir) {\r
446 ot(";@ calculate V flag (set if sign bit changes at anytime):\n");\r
447 ot(" mov r1,#0x80000000\n");\r
448 ot(" ands r3,r3,r1,asr %s\n", pct);\r
449 ot(" cmpne r3,r1,asr %s\n", pct);\r
450 ot(" eoreq r1,r0,r3\n"); // above check doesn't catch (-1)<<(32+), so we need this\r
451 ot(" tsteq r1,#0x80000000\n");\r
452 ot(" orrne r10,r10,#0x10000000\n");\r
453 ot("\n");\r
454 }\r
455 }\r
456\r
457 // --------------------------------------\r
458 if (type==2)\r
459 {\r
460 int wide=8<<size;\r
461\r
462 // Roxr\r
463 if(count == 1)\r
464 {\r
465 if(dir==0) {\r
466 if(size!=2) {\r
467 ot(" orr r0,r0,r0,lsr #%i\n", size?16:24);\r
468 ot(" bic r0,r0,#0x%x\n", 1<<(32-wide));\r
469 }\r
470 GetXBit(0);\r
471 ot(" movs r0,r0,rrx\n");\r
472 OpGetFlags(0,1);\r
473 } else {\r
474 ot(" ldr r3,[r7,#0x4c]\n");\r
475 ot(" movs r0,r0,lsl #1\n");\r
476 OpGetFlags(0,1);\r
477 ot(" tst r3,#0x20000000\n");\r
478 ot(" orrne r0,r0,#0x%x\n", 1<<(32-wide));\r
479 ot(" bicne r10,r10,#0x40000000 ;@ clear Z in case it got there\n");\r
480 }\r
481 ot(" bic r10,r10,#0x10000000 ;@ make suve V is clear\n");\r
482 return 0;\r
483 }\r
484\r
485 if (usereg)\r
486 {\r
487 if (size==2)\r
488 {\r
489 ot(" subs r2,r2,#33\n");\r
490 ot(" addmis r2,r2,#33 ;@ Now r2=0-%d\n",wide);\r
491 }\r
492 else\r
493 {\r
494 ot(";@ Reduce r2 until <0:\n");\r
495 ot("Reduce_%.4x%s\n",op,ms?"":":");\r
496 ot(" subs r2,r2,#%d\n",wide+1);\r
497 ot(" bpl Reduce_%.4x\n",op);\r
498 ot(" adds r2,r2,#%d ;@ Now r2=0-%d\n",wide+1,wide);\r
499 }\r
500 ot(" beq norotx_%.4x\n",op);\r
501 ot("\n");\r
502 }\r
503\r
504 if (usereg||count < 0)\r
505 {\r
506 if (dir) ot(" rsb r2,r2,#%d ;@ Reverse direction\n",wide+1);\r
507 }\r
508 else\r
509 {\r
510 if (dir) ot(" mov r2,#%d ;@ Reversed\n",wide+1-count);\r
511 else ot(" mov r2,#%d\n",count);\r
512 }\r
513\r
514 if (shift) ot(" mov r0,r0,lsr #%d ;@ Shift down\n",shift);\r
515\r
516 ot("\n");\r
517 ot(";@ First get X bit (middle):\n");\r
518 ot(" ldr r3,[r7,#0x4c]\n");\r
519 ot(" rsb r1,r2,#%d\n",wide);\r
520 ot(" and r3,r3,#0x20000000\n");\r
521 ot(" mov r3,r3,lsr #29\n");\r
522 ot(" mov r3,r3,lsl r1\n");\r
523\r
524 ot(";@ Rotate bits:\n");\r
525 ot(" orr r3,r3,r0,lsr r2 ;@ Orr right part\n");\r
526 ot(" rsbs r2,r2,#%d ;@ should also clear ARM V\n",wide+1);\r
527 ot(" orrs r0,r3,r0,lsl r2 ;@ Orr left part, set flags\n");\r
528 ot("\n");\r
529\r
530 if (shift) ot(" movs r0,r0,lsl #%d ;@ Shift up and get correct NC flags\n",shift);\r
531 OpGetFlags(0,!usereg);\r
532 if (usereg) { // store X only if count is not 0\r
533 ot(" str r10,[r7,#0x4c] ;@ if not 0, Save X bit\n");\r
534 ot(" b nozerox%.4x\n",op);\r
535 ot("norotx_%.4x%s\n",op,ms?"":":");\r
536 ot(" ldr r2,[r7,#0x4c]\n");\r
537 ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
538 OpGetFlags(0,0);\r
539 ot(" and r2,r2,#0x20000000\n");\r
540 ot(" orr r10,r10,r2 ;@ C = old_X\n");\r
541 ot("nozerox%.4x%s\n",op,ms?"":":");\r
542 }\r
543\r
544 ot("\n");\r
545 }\r
546\r
547 // --------------------------------------\r
548 if (type==3)\r
549 {\r
550 // Ror\r
551 if (size<2)\r
552 {\r
553 ot(";@ Mirror value in whole 32 bits:\n");\r
554 if (size<=0) ot(" orr r0,r0,r0,lsr #8\n");\r
555 if (size<=1) ot(" orr r0,r0,r0,lsr #16\n");\r
556 ot("\n");\r
557 }\r
558\r
559 ot(";@ Rotate register:\n");\r
560 if (!dir) ot(" adds r0,r0,#0 ;@ first clear V and C\n"); // ARM does not clear C if rot count is 0\r
561 if (count<0)\r
562 {\r
563 if (dir) ot(" rsb %s,%s,#32\n",pct,pct);\r
564 ot(" movs r0,r0,ror %s\n",pct);\r
565 }\r
566 else\r
567 {\r
568 int ror=count;\r
569 if (dir) ror=32-ror;\r
570 if (ror&31) ot(" movs r0,r0,ror #%d\n",ror);\r
571 }\r
572\r
573 OpGetFlags(0,0);\r
574 if (dir)\r
575 {\r
576 ot(" bic r10,r10,#0x30000000 ;@ clear CV\n");\r
577 ot(";@ Get carry bit from bit 0:\n");\r
578 if (usereg)\r
579 {\r
580 ot(" cmp %s,#32 ;@ rotating by 0?\n",pct);\r
581 ot(" tstne r0,#1 ;@ no, check bit 0\n");\r
582 }\r
583 else\r
584 ot(" tst r0,#1\n");\r
585 ot(" orrne r10,r10,#0x20000000\n");\r
586 }\r
587 ot("\n");\r
588\r
589 }\r
590 // --------------------------------------\r
591 \r
592 return 0;\r
593}\r
594\r
595// Emit a Asr/Lsr/Roxr/Ror opcode - 1110cccd xxuttnnn\r
596// (ccc=count, d=direction(r,l) xx=size extension, u=use reg for count, tt=type, nnn=register Dn)\r
597int OpAsr(int op)\r
598{\r
599 int ea=0,use=0;\r
600 int count=0,dir=0;\r
601 int size=0,usereg=0,type=0;\r
602\r
603 count =(op>>9)&7;\r
604 dir =(op>>8)&1;\r
605 size =(op>>6)&3;\r
606 if (size>=3) return 1; // use OpAsrEa()\r
607 usereg=(op>>5)&1;\r
608 type =(op>>3)&3;\r
609\r
610 if (usereg==0) count=((count-1)&7)+1; // because ccc=000 means 8\r
611\r
612 // Use the same opcode for target registers:\r
613 use=op&~0x0007;\r
614\r
615 // As long as count is not 8, use the same opcode for all shift counts:\r
616 if (usereg==0 && count!=8 && !(count==1&&type==2)) { use|=0x0e00; count=-1; }\r
617 if (usereg) { use&=~0x0e00; count=-1; } // Use same opcode for all Dn\r
618\r
619 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
620\r
621 OpStart(op,ea,0,count<0); Cycles=size<2?6:8;\r
622\r
623 EaCalc(11,0x0007, ea,size,1);\r
624 EaRead(11, 0, ea,size,0x0007,1);\r
625\r
626 EmitAsr(op,type,dir,count, size,usereg);\r
627\r
628 EaWrite(11, 0, ea,size,0x0007,1);\r
629\r
630 opend_op_changes_cycles = (count<0);\r
631 OpEnd(ea,0);\r
632\r
633 return 0;\r
634}\r
635\r
636// Asr/Lsr/Roxr/Ror etc EA - 11100ttd 11eeeeee \r
637int OpAsrEa(int op)\r
638{\r
639 int use=0,type=0,dir=0,ea=0,size=1;\r
640\r
641 type=(op>>9)&3;\r
642 dir =(op>>8)&1;\r
643 ea = op&0x3f;\r
644\r
645 if (ea<0x10) return 1;\r
646 // See if we can do this opcode:\r
647 if (EaCanRead(ea,0)==0) return 1;\r
648 if (EaCanWrite(ea)==0) return 1;\r
649\r
650 use=OpBase(op,size);\r
651 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
652\r
653 OpStart(op,ea); Cycles=6; // EmitAsr() will add 2\r
654\r
655 EaCalc (11,0x003f,ea,size,1);\r
656 EaRead (11, 0,ea,size,0x003f,1);\r
657\r
658 EmitAsr(op,type,dir,1,size,0);\r
659\r
660 EaWrite(11, 0,ea,size,0x003f,1);\r
661\r
662 OpEnd(ea);\r
663 return 0;\r
664}\r
665\r
666int OpTas(int op, int gen_special)\r
667{\r
668 int ea=0;\r
669 int use=0;\r
670\r
671 ea=op&0x003f;\r
672\r
673 // See if we can do this opcode:\r
674 if (EaCanWrite(ea)==0 || EaAn(ea)) return 1;\r
675\r
676 use=OpBase(op,0);\r
677 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
678\r
679 if (!gen_special) OpStart(op,ea);\r
680 else\r
681 ot("Op%.4x_%s\n", op, ms?"":":");\r
682\r
683 Cycles=4;\r
684 if(ea>=8) Cycles+=10;\r
685\r
686 EaCalc (11,0x003f,ea,0,1);\r
687 EaRead (11, 1,ea,0,0x003f,1);\r
688\r
689 ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
690 OpGetFlags(0,0);\r
691 ot("\n");\r
692\r
693#if CYCLONE_FOR_GENESIS\r
694 // the original Sega hardware ignores write-back phase (to memory only)\r
695 if (ea < 0x10 || gen_special) {\r
696#endif\r
697 ot(" orr r1,r1,#0x80000000 ;@ set bit7\n");\r
698\r
699 EaWrite(11, 1,ea,0,0x003f,1);\r
700#if CYCLONE_FOR_GENESIS\r
701 }\r
702#endif\r
703\r
704 OpEnd(ea);\r
705\r
706#if (CYCLONE_FOR_GENESIS == 2)\r
707 if (!gen_special && ea >= 0x10) {\r
708 OpTas(op, 1);\r
709 }\r
710#endif\r
711\r
712 return 0;\r
713}\r
714\r
68000 emulator written in ARM 32-bit assembly