2 // This file is part of the Cyclone 68000 Emulator
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4 // This code is licensed under the GNU General Public License version 2.0 and the MAME License.
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5 // You can choose the license that has the most advantages for you.
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7 // SVN repository can be found at http://code.google.com/p/cyclone68000/
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11 // ---------------------------------------------------------------------------
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12 // Gets the offset of a register for an ea, and puts it in 'r'
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13 // Shifted left by 'shift'
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14 // Doesn't trash anything
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15 static int EaCalcReg(int r,int ea,int mask,int forceor,int shift)
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17 int i=0,low=0,needor=0;
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20 for (i=mask|0x8000; (i&1)==0; i>>=1) low++; // Find out how high up the EA mask is
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21 mask&=0xf<<low; // This is the max we can do
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23 if (ea>=8) needor=1; // Need to OR to access A0-7
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25 if ((mask>>low)&8) if (ea&8) needor=0; // Ah - no we don't actually need to or, since the bit is high in r8
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27 if (forceor) needor=1; // Special case for 0x30-0x38 EAs ;)
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29 ot(" and r%d,r8,#0x%.4x\n",r,mask);
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31 // Find out amount to shift left:
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36 ot(" mov r%d,r%d,",r,r);
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37 if (lsl>0) ot("lsl #%d\n", lsl);
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38 else ot("lsr #%d\n",-lsl);
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41 if (needor) ot(" orr r%d,r%d,#0x%x ;@ A0-7\n",r,r,8<<shift);
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45 // EaCalc - ARM Register 'a' = Effective Address
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46 // Trashes r0,r2 and r3
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47 int EaCalc(int a,int mask,int ea,int size)
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52 DisaPc=2; DisaGetEa(text,ea,size); // Get text version of the effective address
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53 func=0x68+(size<<2); // Get correct read handler
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58 if (size>=2) lsl=0; // Saves one opcode
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60 ot(";@ EaCalc : Get register index into r%d:\n",a);
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62 EaCalcReg(a,ea,mask,0,lsl);
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66 ot(";@ EaCalc : Get '%s' into r%d:\n",text,a);
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67 // (An), (An)+, -(An):
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72 if ((ea&7)==7 && step<2) step=2; // move.b (a7)+ or -(a7) steps by 2 not 1
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74 EaCalcReg(2,ea,mask,0,2);
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75 ot(" ldr r%d,[r7,r2]\n",a);
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77 if ((ea&0x38)==0x18)
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79 ot(" add r3,r%d,#%d ;@ Post-increment An\n",a,step);
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80 ot(" str r3,[r7,r2]\n");
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83 if ((ea&0x38)==0x20)
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85 ot(" sub r%d,r%d,#%d ;@ Pre-decrement An\n",a,a,step);
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86 ot(" str r%d,[r7,r2]\n",a);
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89 if ((ea&0x38)==0x20) Cycles+=size<2 ? 6:10; // -(An) Extra cycles
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90 else Cycles+=size<2 ? 4:8; // (An),(An)+ Extra cycles
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94 if (ea<0x30) // ($nn,An)
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96 EaCalcReg(2,8,mask,0,2);
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97 ot(" ldr r2,[r7,r2]\n");
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98 ot(" ldrsh r0,[r4],#2 ;@ Fetch offset\n");
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99 ot(" add r%d,r0,r2 ;@ Add on offset\n",a);
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100 Cycles+=size<2 ? 8:12; // Extra cycles
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104 if (ea<0x38) // ($nn,An,Rn)
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106 ot(";@ Get extension word into r3:\n");
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107 ot(" ldrh r3,[r4],#2 ;@ ($Disp,PC,Rn)\n");
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108 ot(" mov r2,r3,lsr #10\n");
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109 ot(" tst r3,#0x0800 ;@ Is Rn Word or Long\n");
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110 ot(" and r2,r2,#0x3c ;@ r2=Index of Rn\n");
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111 ot(" mov r0,r3,asl #24 ;@ r0=Get 8-bit signed Disp\n");
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112 ot(" ldreqsh r2,[r7,r2] ;@ r2=Rn.w\n");
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113 ot(" ldrne r2,[r7,r2] ;@ r2=Rn.l\n");
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114 ot(" add r3,r2,r0,asr #24 ;@ r3=Disp+Rn\n");
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116 EaCalcReg(2,8,mask,1,2);
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117 ot(" ldr r2,[r7,r2]\n");
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118 ot(" add r%d,r2,r3 ;@ r%d=Disp+An+Rn\n",a,a);
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119 Cycles+=size<2 ? 10:14; // Extra cycles
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125 ot(" ldrsh r%d,[r4],#2 ;@ Fetch Absolute Short address\n",a);
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126 Cycles+=size<2 ? 8:12; // Extra cycles
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132 ot(" ldrh r2,[r4],#2 ;@ Fetch Absolute Long address\n");
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133 ot(" ldrh r0,[r4],#2\n");
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134 ot(" orr r%d,r0,r2,lsl #16\n",a);
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135 Cycles+=size<2 ? 12:16; // Extra cycles
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141 ot(" ldr r0,[r7,#0x60] ;@ Get Memory base\n");
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142 ot(" sub r0,r4,r0 ;@ Real PC\n");
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143 ot(" ldrsh r2,[r4],#2 ;@ Fetch extension\n");
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144 ot(" add r%d,r0,r2 ;@ ($nn,PC)\n",a);
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145 Cycles+=size<2 ? 8:12; // Extra cycles
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149 if (ea==0x3b) // ($nn,pc,Rn)
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151 ot(";@ Get extension word into r3:\n");
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152 ot(" ldrh r3,[r4]\n");
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153 ot(" mov r2,r3,lsr #10\n");
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154 ot(" tst r3,#0x0800 ;@ Is Rn Word or Long\n");
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155 ot(" and r2,r2,#0x3c ;@ r2=Index of Rn\n");
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156 ot(" mov r0,r3,asl #24 ;@ r0=Get 8-bit signed Disp\n");
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157 ot(" ldreqsh r2,[r7,r2] ;@ r2=Rn.w\n");
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158 ot(" ldrne r2,[r7,r2] ;@ r2=Rn.l\n");
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159 ot(" add r2,r2,r0,asr #24 ;@ r2=Disp+Rn\n");
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160 ot(" ldr r0,[r7,#0x60] ;@ Get Memory base\n");
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161 ot(" add r2,r2,r4 ;@ r2=Disp+Rn + Base+PC\n");
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162 ot(" add r4,r4,#2 ;@ Increase PC\n");
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163 ot(" sub r%d,r2,r0 ;@ r%d=Disp+PC+Rn\n",a,a);
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164 Cycles+=size<2 ? 10:14; // Extra cycles
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172 ot(" ldr%s r%d,[r4],#2 ;@ Fetch immediate value\n",Sarm[size&3],a);
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173 Cycles+=4; // Extra cycles
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177 ot(" ldrh r2,[r4],#2 ;@ Fetch immediate value\n");
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178 ot(" ldrh r0,[r4],#2\n");
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179 ot(" orr r%d,r0,r2,lsl #16\n",a);
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180 Cycles+=8; // Extra cycles
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187 // ---------------------------------------------------------------------------
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188 // Read effective address in (ARM Register 'a') to ARM register 'v'
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189 // 'a' and 'v' can be anything but 0 is generally best (for both)
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190 // If (ea<0x10) nothing is trashed, else r0-r3 is trashed
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191 // If 'top' is 1, the ARM register v shifted to the top, e.g. 0xc000 -> 0xc0000000
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192 // Otherwise the ARM register v is sign extended, e.g. 0xc000 -> 0xffffc000
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194 int EaRead(int a,int v,int ea,int size,int top)
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199 shift=32-(8<<size);
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201 DisaPc=2; DisaGetEa(text,ea,size); // Get text version of the effective address
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206 if (size>=2) lsl=0; // Having a lsl #2 here saves one opcode
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208 ot(";@ EaRead : Read register[r%d] into r%d:\n",a,v);
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210 if (lsl==0) ot(" ldr r%d,[r7,r%d,lsl #2]\n",v,a);
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211 else ot(" ldr%s r%d,[r7,r%d]\n",Sarm[size&3],v,a);
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213 if (top && shift) ot(" mov r%d,r%d,asl #%d\n",v,v,shift);
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215 ot("\n"); return 0;
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218 ot(";@ EaRead : Read '%s' (address in r%d) into r%d:\n",text,a,v);
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224 if (top) asl=shift;
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226 if (v!=a || asl) ot(" mov r%d,r%d,asl #%d\n",v,a,asl);
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227 ot("\n"); return 0;
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230 if (a!=0) ot(" mov r0,r%d\n",a);
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232 if (ea>=0x3a && ea<=0x3b) MemHandler(2,size); // Fetch
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233 else MemHandler(0,size); // Read
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235 if (v!=0 || shift) ot(" mov r%d,r0,asl #%d\n",v,shift);
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236 if (top==0 && shift) ot(" mov r%d,r%d,asr #%d\n",v,v,shift);
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238 ot("\n"); return 0;
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241 // Return 1 if we can read this ea
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242 int EaCanRead(int ea,int size)
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247 // These don't make sense?:
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248 if (ea<0x10) return 0; // Register
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249 if (ea==0x3c) return 0; // Immediate
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250 if (ea>=0x18 && ea<0x28) return 0; // Pre/Post inc/dec An
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253 if (ea<=0x3c) return 1;
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257 // ---------------------------------------------------------------------------
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258 // Write effective address (ARM Register 'a') with ARM register 'v'
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259 // Trashes r0-r3, 'a' can be 0 or 2+, 'v' can be 1 or higher
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260 // If a==0 and v==1 it's faster though.
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261 int EaWrite(int a,int v,int ea,int size,int top)
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266 if (top) shift=32-(8<<size);
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268 DisaPc=2; DisaGetEa(text,ea,size); // Get text version of the effective address
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273 if (size>=2) lsl=0; // Having a lsl #2 here saves one opcode
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275 ot(";@ EaWrite: r%d into register[r%d]:\n",v,a);
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276 if (shift) ot(" mov r%d,r%d,asr #%d\n",v,v,shift);
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278 if (lsl==0) ot(" str r%d,[r7,r%d,lsl #2]\n",v,a);
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279 else ot(" str%s r%d,[r7,r%d]\n",Narm[size&3],v,a);
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281 ot("\n"); return 0;
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284 ot(";@ EaWrite: Write r%d into '%s' (address in r%d):\n",v,text,a);
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286 if (ea==0x3c) { ot("Error! Write EA=0x%x\n\n",ea); return 1; }
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288 if (a!=0 && v!=0) ot(" mov r0,r%d\n",a);
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289 if (v!=1 || shift) ot(" mov r1,r%d,asr #%d\n",v,shift);
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290 if (a!=0 && v==0) ot(" mov r0,r%d\n",a);
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292 MemHandler(1,size); // Call write handler
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294 ot("\n"); return 0;
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297 // Return 1 if we can write this ea
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298 int EaCanWrite(int ea)
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300 if (ea<=0x3b) return 1;
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303 // ---------------------------------------------------------------------------
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