--- /dev/null
+\r
+// This file is part of the Cyclone 68000 Emulator\r
+\r
+// Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)\r
+// Copyright (c) 2005-2011 GraÅžvydas "notaz" Ignotas (notasas (at) gmail.com)\r
+\r
+// This code is licensed under the GNU General Public License version 2.0 and the MAME License.\r
+// You can choose the license that has the most advantages for you.\r
+\r
+// SVN repository can be found at http://code.google.com/p/cyclone68000/\r
+\r
+\r
+#include "app.h"\r
+\r
+// --------------------- Opcodes 0x0100+ ---------------------\r
+// Emit a Btst (Register) opcode 0000nnn1 ttaaaaaa\r
+int OpBtstReg(int op)\r
+{\r
+ int use=0;\r
+ int type=0,sea=0,tea=0;\r
+ int size=0;\r
+\r
+ type=(op>>6)&3; // Btst/Bchg/Bclr/Bset\r
+ // Get source and target EA\r
+ sea=(op>>9)&7;\r
+ tea=op&0x003f;\r
+ if (tea<0x10) size=2; // For registers, 32-bits\r
+\r
+ if ((tea&0x38)==0x08) return 1; // movep\r
+\r
+ // See if we can do this opcode:\r
+ if (EaCanRead(tea,0)==0) return 1;\r
+ if (type>0)\r
+ {\r
+ if (EaCanWrite(tea)==0) return 1;\r
+ }\r
+\r
+ use=OpBase(op,size);\r
+ use&=~0x0e00; // Use same handler for all registers\r
+ if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
+\r
+ OpStart(op,tea);\r
+\r
+ if(type==1||type==3) {\r
+ Cycles=8;\r
+ } else {\r
+ Cycles=type?8:4;\r
+ if(size>=2) Cycles+=2;\r
+ }\r
+\r
+ EaCalcReadNoSE(-1,11,sea,0,0x0e00);\r
+\r
+ EaCalcReadNoSE((type>0)?8:-1,0,tea,size,0x003f);\r
+\r
+ if (tea>=0x10)\r
+ ot(" and r11,r11,#7 ;@ mem - do mod 8\n"); // size always 0\r
+ else ot(" and r11,r11,#31 ;@ reg - do mod 32\n"); // size always 2\r
+ ot("\n");\r
+\r
+ ot(" mov r1,#1\n");\r
+ ot(" tst r0,r1,lsl r11 ;@ Do arithmetic\n");\r
+ ot(" bicne r10,r10,#0x40000000\n");\r
+ ot(" orreq r10,r10,#0x40000000 ;@ Get Z flag\n");\r
+ ot("\n");\r
+\r
+ if (type>0)\r
+ {\r
+ if (type==1) ot(" eor r1,r0,r1,lsl r11 ;@ Toggle bit\n");\r
+ if (type==2) ot(" bic r1,r0,r1,lsl r11 ;@ Clear bit\n");\r
+ if (type==3) ot(" orr r1,r0,r1,lsl r11 ;@ Set bit\n");\r
+ ot("\n");\r
+ EaWrite(8,1,tea,size,0x003f,0,0);\r
+ }\r
+ OpEnd(tea);\r
+\r
+ return 0;\r
+}\r
+\r
+// --------------------- Opcodes 0x0800+ ---------------------\r
+// Emit a Btst/Bchg/Bclr/Bset (Immediate) opcode 00001000 ttaaaaaa nn\r
+int OpBtstImm(int op)\r
+{\r
+ int type=0,sea=0,tea=0;\r
+ int use=0;\r
+ int size=0;\r
+\r
+ type=(op>>6)&3;\r
+ // Get source and target EA\r
+ sea= 0x003c;\r
+ tea=op&0x003f;\r
+ if (tea<0x10) size=2; // For registers, 32-bits\r
+\r
+ // See if we can do this opcode:\r
+ if (EaCanRead(tea,0)==0||EaAn(tea)||tea==0x3c) return 1;\r
+ if (type>0)\r
+ {\r
+ if (EaCanWrite(tea)==0) return 1;\r
+ }\r
+\r
+ use=OpBase(op,size);\r
+ if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
+\r
+ OpStart(op,sea,tea);\r
+\r
+ ot("\n");\r
+ EaCalcReadNoSE(-1,0,sea,0,0);\r
+ ot(" mov r11,#1\n");\r
+ ot(" bic r10,r10,#0x40000000 ;@ Blank Z flag\n");\r
+ if (tea>=0x10)\r
+ ot(" and r0,r0,#7 ;@ mem - do mod 8\n"); // size always 0\r
+ else ot(" and r0,r0,#0x1F ;@ reg - do mod 32\n"); // size always 2\r
+ ot(" mov r11,r11,lsl r0 ;@ Make bit mask\n");\r
+ ot("\n");\r
+\r
+ if(type==1||type==3) {\r
+ Cycles=12;\r
+ } else {\r
+ Cycles=type?12:8;\r
+ if(size>=2) Cycles+=2;\r
+ }\r
+\r
+ EaCalcReadNoSE((type>0)?8:-1,0,tea,size,0x003f);\r
+ ot(" tst r0,r11 ;@ Do arithmetic\n");\r
+ ot(" orreq r10,r10,#0x40000000 ;@ Get Z flag\n");\r
+ ot("\n");\r
+\r
+ if (type>0)\r
+ {\r
+ if (type==1) ot(" eor r1,r0,r11 ;@ Toggle bit\n");\r
+ if (type==2) ot(" bic r1,r0,r11 ;@ Clear bit\n");\r
+ if (type==3) ot(" orr r1,r0,r11 ;@ Set bit\n");\r
+ ot("\n");\r
+ EaWrite(8, 1,tea,size,0x003f,0,0);\r
+#if CYCLONE_FOR_GENESIS && !MEMHANDLERS_CHANGE_CYCLES\r
+ // this is a bit hacky (device handlers might modify cycles)\r
+ if (tea==0x38||tea==0x39)\r
+ ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
+#endif\r
+ }\r
+\r
+ OpEnd(sea,tea);\r
+\r
+ return 0;\r
+}\r
+\r
+// --------------------- Opcodes 0x4000+ ---------------------\r
+int OpNeg(int op)\r
+{\r
+ // 01000tt0 xxeeeeee (tt=negx/clr/neg/not, xx=size, eeeeee=EA)\r
+ int type=0,size=0,ea=0,use=0;\r
+\r
+ type=(op>>9)&3;\r
+ ea =op&0x003f;\r
+ size=(op>>6)&3; if (size>=3) return 1;\r
+\r
+ // See if we can do this opcode:\r
+ if (EaCanRead (ea,size)==0||EaAn(ea)) return 1;\r
+ if (EaCanWrite(ea )==0) return 1;\r
+\r
+ use=OpBase(op,size);\r
+ if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
+\r
+ OpStart(op,ea); Cycles=size<2?4:6;\r
+ if(ea >= 0x10) Cycles*=2;\r
+\r
+ EaCalc (11,0x003f,ea,size,0,0);\r
+\r
+ if (type!=1) EaRead (11,0,ea,size,0x003f,0,0); // Don't need to read for 'clr' (or do we, for a dummy read?)\r
+ if (type==1) ot("\n");\r
+\r
+ if (type==0)\r
+ {\r
+ ot(";@ Negx:\n");\r
+ GetXBit(1);\r
+ if(size!=2) ot(" mov r0,r0,asl #%i\n",size?16:24);\r
+ ot(" rscs r1,r0,#0 ;@ do arithmetic\n");\r
+ ot(" orr r3,r10,#0xb0000000 ;@ for old Z\n");\r
+ OpGetFlags(1,1,0);\r
+ if(size!=2) {\r
+ ot(" movs r1,r1,asr #%i\n",size?16:24);\r
+ ot(" orreq r10,r10,#0x40000000 ;@ possily missed Z\n");\r
+ }\r
+ ot(" andeq r10,r10,r3 ;@ fix Z\n");\r
+ ot("\n");\r
+ }\r
+\r
+ if (type==1)\r
+ {\r
+ ot(";@ Clear:\n");\r
+ ot(" mov r1,#0\n");\r
+ ot(" mov r10,#0x40000000 ;@ NZCV=0100\n");\r
+ ot("\n");\r
+ }\r
+\r
+ if (type==2)\r
+ {\r
+ ot(";@ Neg:\n");\r
+ if(size!=2) ot(" mov r0,r0,asl #%i\n",size?16:24);\r
+ ot(" rsbs r1,r0,#0\n");\r
+ OpGetFlags(1,1);\r
+ if(size!=2) ot(" mov r1,r1,asr #%i\n",size?16:24);\r
+ ot("\n");\r
+ }\r
+\r
+ if (type==3)\r
+ {\r
+ ot(";@ Not:\n");\r
+ if(size!=2) {\r
+ ot(" mov r0,r0,asl #%i\n",size?16:24);\r
+ ot(" mvn r1,r0,asr #%i\n",size?16:24);\r
+ }\r
+ else\r
+ ot(" mvn r1,r0\n");\r
+ ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
+ OpGetFlags(0,0);\r
+ ot("\n");\r
+ }\r
+\r
+ if (type==1) eawrite_check_addrerr=1;\r
+ EaWrite(11, 1,ea,size,0x003f,0,0);\r
+\r
+ OpEnd(ea);\r
+\r
+ return 0;\r
+}\r
+\r
+// --------------------- Opcodes 0x4840+ ---------------------\r
+// Swap, 01001000 01000nnn swap Dn\r
+int OpSwap(int op)\r
+{\r
+ int ea=0,use=0;\r
+\r
+ ea=op&7;\r
+ use=op&~0x0007; // Use same opcode for all An\r
+\r
+ if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
+\r
+ OpStart(op); Cycles=4;\r
+\r
+ EaCalc (11,0x0007,ea,2,1);\r
+ EaRead (11, 0,ea,2,0x0007,1);\r
+\r
+ ot(" mov r1,r0,ror #16\n");\r
+ ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
+ OpGetFlags(0,0);\r
+\r
+ EaWrite(11, 1,8,2,0x0007,1);\r
+\r
+ OpEnd();\r
+\r
+ return 0;\r
+}\r
+\r
+// --------------------- Opcodes 0x4a00+ ---------------------\r
+// Emit a Tst opcode, 01001010 xxeeeeee\r
+int OpTst(int op)\r
+{\r
+ int sea=0;\r
+ int size=0,use=0;\r
+\r
+ sea=op&0x003f;\r
+ size=(op>>6)&3; if (size>=3) return 1;\r
+\r
+ // See if we can do this opcode:\r
+ if (EaCanWrite(sea)==0||EaAn(sea)) return 1;\r
+\r
+ use=OpBase(op,size);\r
+ if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
+\r
+ OpStart(op,sea); Cycles=4;\r
+\r
+ EaCalc ( 0,0x003f,sea,size,1);\r
+ EaRead ( 0, 0,sea,size,0x003f,1);\r
+\r
+ ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
+ ot(" mrs r10,cpsr ;@ r10=flags\n");\r
+ ot("\n");\r
+\r
+ OpEnd(sea);\r
+ return 0;\r
+}\r
+\r
+// --------------------- Opcodes 0x4880+ ---------------------\r
+// Emit an Ext opcode, 01001000 1x000nnn\r
+int OpExt(int op)\r
+{\r
+ int ea=0;\r
+ int size=0,use=0;\r
+ int shift=0;\r
+\r
+ ea=op&0x0007;\r
+ size=(op>>6)&1;\r
+ shift=32-(8<<size);\r
+\r
+ use=OpBase(op,size);\r
+ if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
+\r
+ OpStart(op); Cycles=4;\r
+\r
+ EaCalc (11,0x0007,ea,size+1,0,0);\r
+ EaRead (11, 0,ea,size+1,0x0007,0,0);\r
+\r
+ ot(" mov r0,r0,asl #%d\n",shift);\r
+ ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
+ ot(" mrs r10,cpsr ;@ r10=flags\n");\r
+ ot(" mov r1,r0,asr #%d\n",shift);\r
+ ot("\n");\r
+\r
+ EaWrite(11, 1,ea,size+1,0x0007,0,0);\r
+\r
+ OpEnd();\r
+ return 0;\r
+}\r
+\r
+// --------------------- Opcodes 0x50c0+ ---------------------\r
+// Emit a Set cc opcode, 0101cccc 11eeeeee\r
+int OpSet(int op)\r
+{\r
+ int cc=0,ea=0;\r
+ int size=0,use=0,changed_cycles=0;\r
+ static const char * const cond[16]=\r
+ {\r
+ "al","", "hi","ls","cc","cs","ne","eq",\r
+ "vc","vs","pl","mi","ge","lt","gt","le"\r
+ };\r
+\r
+ cc=(op>>8)&15;\r
+ ea=op&0x003f;\r
+\r
+ if ((ea&0x38)==0x08) return 1; // dbra, not scc\r
+ \r
+ // See if we can do this opcode:\r
+ if (EaCanWrite(ea)==0) return 1;\r
+\r
+ use=OpBase(op,size);\r
+ if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
+\r
+ changed_cycles=ea<8 && cc>=2;\r
+ OpStart(op,ea,0,changed_cycles); Cycles=8;\r
+ if (ea<8) Cycles=4;\r
+\r
+ if (cc)\r
+ ot(" mov r1,#0\n");\r
+\r
+ switch (cc)\r
+ {\r
+ case 0: // T\r
+ ot(" mvn r1,#0\n");\r
+ if (ea<8) Cycles+=2;\r
+ break;\r
+ case 1: // F\r
+ break;\r
+ case 2: // hi\r
+ ot(" tst r10,#0x60000000 ;@ hi: !C && !Z\n");\r
+ ot(" mvneq r1,r1\n");\r
+ if (ea<8) ot(" subeq r5,r5,#2 ;@ Extra cycles\n");\r
+ break;\r
+ case 3: // ls\r
+ ot(" tst r10,#0x60000000 ;@ ls: C || Z\n");\r
+ ot(" mvnne r1,r1\n");\r
+ if (ea<8) ot(" subne r5,r5,#2 ;@ Extra cycles\n");\r
+ break;\r
+ default:\r
+ ot(";@ Is the condition true?\n");\r
+ ot(" msr cpsr_flg,r10 ;@ ARM flags = 68000 flags\n");\r
+ ot(" mvn%s r1,r1\n",cond[cc]);\r
+ if (ea<8) ot(" sub%s r5,r5,#2 ;@ Extra cycles\n",cond[cc]);\r
+ break;\r
+ }\r
+\r
+ ot("\n");\r
+\r
+ eawrite_check_addrerr=1;\r
+ EaCalc (0,0x003f, ea,size,0,0);\r
+ EaWrite(0, 1, ea,size,0x003f,0,0);\r
+\r
+ opend_op_changes_cycles=changed_cycles;\r
+ OpEnd(ea,0);\r
+ return 0;\r
+}\r
+\r
+// Emit a Asr/Lsr/Roxr/Ror opcode\r
+static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)\r
+{\r
+ char pct[8]=""; // count\r
+ int shift=32-(8<<size);\r
+\r
+ if (count>=1) sprintf(pct,"#%d",count); // Fixed count\r
+\r
+ if (usereg)\r
+ {\r
+ ot(";@ Use Dn for count:\n");\r
+ ot(" and r2,r8,#0x0e00\n");\r
+ ot(" ldr r2,[r7,r2,lsr #7]\n");\r
+ ot(" and r2,r2,#63\n");\r
+ ot("\n");\r
+ strcpy(pct,"r2");\r
+ }\r
+ else if (count<0)\r
+ {\r
+ ot(" mov r2,r8,lsr #9 ;@ Get 'n'\n");\r
+ ot(" and r2,r2,#7\n\n"); strcpy(pct,"r2");\r
+ }\r
+\r
+ // Take 2*n cycles:\r
+ if (count<0) ot(" sub r5,r5,r2,asl #1 ;@ Take 2*n cycles\n\n");\r
+ else Cycles+=count<<1;\r
+\r
+ if (type<2)\r
+ {\r
+ // Asr/Lsr\r
+ if (dir==0 && size<2)\r
+ {\r
+ ot(";@ For shift right, use loworder bits for the operation:\n");\r
+ ot(" mov r0,r0,%s #%d\n",type?"lsr":"asr",32-(8<<size));\r
+ ot("\n");\r
+ }\r
+\r
+ if (type==0 && dir) ot(" adds r3,r0,#0 ;@ save old value for V flag calculation, also clear V\n");\r
+\r
+ ot(";@ Shift register:\n");\r
+ if (type==0) ot(" movs r0,r0,%s %s\n",dir?"asl":"asr",pct);\r
+ if (type==1) ot(" movs r0,r0,%s %s\n",dir?"lsl":"lsr",pct);\r
+\r
+ OpGetFlags(0,0);\r
+ if (usereg) { // store X only if count is not 0\r
+ ot(" cmp %s,#0 ;@ shifting by 0?\n",pct);\r
+ ot(" biceq r10,r10,#0x20000000 ;@ if so, clear carry\n");\r
+ ot(" strne r10,[r7,#0x4c] ;@ else Save X bit\n");\r
+ } else {\r
+ // count will never be 0 if we use immediate\r
+ ot(" str r10,[r7,#0x4c] ;@ Save X bit\n");\r
+ }\r
+ ot("\n");\r
+\r
+ if (dir==0 && size<2)\r
+ {\r
+ ot(";@ restore after right shift:\n");\r
+ ot(" movs r0,r0,lsl #%d\n",32-(8<<size));\r
+ if (type)\r
+ ot(" orrmi r10,r10,#0x80000000 ;@ Potentially missed N flag\n");\r
+ ot("\n");\r
+ }\r
+\r
+ if (type==0 && dir) {\r
+ ot(";@ calculate V flag (set if sign bit changes at anytime):\n");\r
+ ot(" mov r1,#0x80000000\n");\r
+ ot(" ands r3,r3,r1,asr %s\n", pct);\r
+ ot(" cmpne r3,r1,asr %s\n", pct);\r
+ ot(" eoreq r1,r0,r3\n"); // above check doesn't catch (-1)<<(32+), so we need this\r
+ ot(" tsteq r1,#0x80000000\n");\r
+ ot(" orrne r10,r10,#0x10000000\n");\r
+ ot("\n");\r
+ }\r
+ }\r
+\r
+ // --------------------------------------\r
+ if (type==2)\r
+ {\r
+ int wide=8<<size;\r
+\r
+ // Roxr\r
+ if(count == 1)\r
+ {\r
+ if(dir==0) {\r
+ if(size!=2) {\r
+ ot(" orr r0,r0,r0,lsr #%i\n", size?16:24);\r
+ ot(" bic r0,r0,#0x%x\n", 1<<(32-wide));\r
+ }\r
+ GetXBit(0);\r
+ ot(" movs r0,r0,rrx\n");\r
+ OpGetFlags(0,1);\r
+ } else {\r
+ ot(" ldr r3,[r7,#0x4c]\n");\r
+ ot(" movs r0,r0,lsl #1\n");\r
+ OpGetFlags(0,1);\r
+ ot(" tst r3,#0x20000000\n");\r
+ ot(" orrne r0,r0,#0x%x\n", 1<<(32-wide));\r
+ ot(" bicne r10,r10,#0x40000000 ;@ clear Z in case it got there\n");\r
+ }\r
+ ot(" bic r10,r10,#0x10000000 ;@ make suve V is clear\n");\r
+ return 0;\r
+ }\r
+\r
+ if (usereg)\r
+ {\r
+ if (size==2)\r
+ {\r
+ ot(" subs r2,r2,#33\n");\r
+ ot(" addmis r2,r2,#33 ;@ Now r2=0-%d\n",wide);\r
+ }\r
+ else\r
+ {\r
+ ot(";@ Reduce r2 until <0:\n");\r
+ ot("Reduce_%.4x%s\n",op,ms?"":":");\r
+ ot(" subs r2,r2,#%d\n",wide+1);\r
+ ot(" bpl Reduce_%.4x\n",op);\r
+ ot(" adds r2,r2,#%d ;@ Now r2=0-%d\n",wide+1,wide);\r
+ }\r
+ ot(" beq norotx_%.4x\n",op);\r
+ ot("\n");\r
+ }\r
+\r
+ if (usereg||count < 0)\r
+ {\r
+ if (dir) ot(" rsb r2,r2,#%d ;@ Reverse direction\n",wide+1);\r
+ }\r
+ else\r
+ {\r
+ if (dir) ot(" mov r2,#%d ;@ Reversed\n",wide+1-count);\r
+ else ot(" mov r2,#%d\n",count);\r
+ }\r
+\r
+ if (shift) ot(" mov r0,r0,lsr #%d ;@ Shift down\n",shift);\r
+\r
+ ot("\n");\r
+ ot(";@ First get X bit (middle):\n");\r
+ ot(" ldr r3,[r7,#0x4c]\n");\r
+ ot(" rsb r1,r2,#%d\n",wide);\r
+ ot(" and r3,r3,#0x20000000\n");\r
+ ot(" mov r3,r3,lsr #29\n");\r
+ ot(" mov r3,r3,lsl r1\n");\r
+\r
+ ot(";@ Rotate bits:\n");\r
+ ot(" orr r3,r3,r0,lsr r2 ;@ Orr right part\n");\r
+ ot(" rsbs r2,r2,#%d ;@ should also clear ARM V\n",wide+1);\r
+ ot(" orrs r0,r3,r0,lsl r2 ;@ Orr left part, set flags\n");\r
+ ot("\n");\r
+\r
+ if (shift) ot(" movs r0,r0,lsl #%d ;@ Shift up and get correct NC flags\n",shift);\r
+ OpGetFlags(0,!usereg);\r
+ if (usereg) { // store X only if count is not 0\r
+ ot(" str r10,[r7,#0x4c] ;@ if not 0, Save X bit\n");\r
+ ot(" b nozerox%.4x\n",op);\r
+ ot("norotx_%.4x%s\n",op,ms?"":":");\r
+ ot(" ldr r2,[r7,#0x4c]\n");\r
+ ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
+ OpGetFlags(0,0);\r
+ ot(" and r2,r2,#0x20000000\n");\r
+ ot(" orr r10,r10,r2 ;@ C = old_X\n");\r
+ ot("nozerox%.4x%s\n",op,ms?"":":");\r
+ }\r
+\r
+ ot("\n");\r
+ }\r
+\r
+ // --------------------------------------\r
+ if (type==3)\r
+ {\r
+ // Ror\r
+ if (size<2)\r
+ {\r
+ ot(";@ Mirror value in whole 32 bits:\n");\r
+ if (size<=0) ot(" orr r0,r0,r0,lsr #8\n");\r
+ if (size<=1) ot(" orr r0,r0,r0,lsr #16\n");\r
+ ot("\n");\r
+ }\r
+\r
+ ot(";@ Rotate register:\n");\r
+ if (!dir) ot(" adds r0,r0,#0 ;@ first clear V and C\n"); // ARM does not clear C if rot count is 0\r
+ if (count<0)\r
+ {\r
+ if (dir) ot(" rsb %s,%s,#32\n",pct,pct);\r
+ ot(" movs r0,r0,ror %s\n",pct);\r
+ }\r
+ else\r
+ {\r
+ int ror=count;\r
+ if (dir) ror=32-ror;\r
+ if (ror&31) ot(" movs r0,r0,ror #%d\n",ror);\r
+ }\r
+\r
+ OpGetFlags(0,0);\r
+ if (dir)\r
+ {\r
+ ot(" bic r10,r10,#0x30000000 ;@ clear CV\n");\r
+ ot(";@ Get carry bit from bit 0:\n");\r
+ if (usereg)\r
+ {\r
+ ot(" cmp %s,#32 ;@ rotating by 0?\n",pct);\r
+ ot(" tstne r0,#1 ;@ no, check bit 0\n");\r
+ }\r
+ else\r
+ ot(" tst r0,#1\n");\r
+ ot(" orrne r10,r10,#0x20000000\n");\r
+ }\r
+ ot("\n");\r
+\r
+ }\r
+ // --------------------------------------\r
+ \r
+ return 0;\r
+}\r
+\r
+// Emit a Asr/Lsr/Roxr/Ror opcode - 1110cccd xxuttnnn\r
+// (ccc=count, d=direction(r,l) xx=size extension, u=use reg for count, tt=type, nnn=register Dn)\r
+int OpAsr(int op)\r
+{\r
+ int ea=0,use=0;\r
+ int count=0,dir=0;\r
+ int size=0,usereg=0,type=0;\r
+\r
+ count =(op>>9)&7;\r
+ dir =(op>>8)&1;\r
+ size =(op>>6)&3;\r
+ if (size>=3) return 1; // use OpAsrEa()\r
+ usereg=(op>>5)&1;\r
+ type =(op>>3)&3;\r
+\r
+ if (usereg==0) count=((count-1)&7)+1; // because ccc=000 means 8\r
+\r
+ // Use the same opcode for target registers:\r
+ use=op&~0x0007;\r
+\r
+ // As long as count is not 8, use the same opcode for all shift counts:\r
+ if (usereg==0 && count!=8 && !(count==1&&type==2)) { use|=0x0e00; count=-1; }\r
+ if (usereg) { use&=~0x0e00; count=-1; } // Use same opcode for all Dn\r
+\r
+ if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
+\r
+ OpStart(op,ea,0,count<0); Cycles=size<2?6:8;\r
+\r
+ EaCalc(11,0x0007, ea,size,1);\r
+ EaRead(11, 0, ea,size,0x0007,1);\r
+\r
+ EmitAsr(op,type,dir,count, size,usereg);\r
+\r
+ EaWrite(11, 0, ea,size,0x0007,1);\r
+\r
+ opend_op_changes_cycles = (count<0);\r
+ OpEnd(ea,0);\r
+\r
+ return 0;\r
+}\r
+\r
+// Asr/Lsr/Roxr/Ror etc EA - 11100ttd 11eeeeee \r
+int OpAsrEa(int op)\r
+{\r
+ int use=0,type=0,dir=0,ea=0,size=1;\r
+\r
+ type=(op>>9)&3;\r
+ dir =(op>>8)&1;\r
+ ea = op&0x3f;\r
+\r
+ if (ea<0x10) return 1;\r
+ // See if we can do this opcode:\r
+ if (EaCanRead(ea,0)==0) return 1;\r
+ if (EaCanWrite(ea)==0) return 1;\r
+\r
+ use=OpBase(op,size);\r
+ if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
+\r
+ OpStart(op,ea); Cycles=6; // EmitAsr() will add 2\r
+\r
+ EaCalc (11,0x003f,ea,size,1);\r
+ EaRead (11, 0,ea,size,0x003f,1);\r
+\r
+ EmitAsr(op,type,dir,1,size,0);\r
+\r
+ EaWrite(11, 0,ea,size,0x003f,1);\r
+\r
+ OpEnd(ea);\r
+ return 0;\r
+}\r
+\r
+int OpTas(int op, int gen_special)\r
+{\r
+ int ea=0;\r
+ int use=0;\r
+\r
+ ea=op&0x003f;\r
+\r
+ // See if we can do this opcode:\r
+ if (EaCanWrite(ea)==0 || EaAn(ea)) return 1;\r
+\r
+ use=OpBase(op,0);\r
+ if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
+\r
+ if (!gen_special) OpStart(op,ea);\r
+ else\r
+ ot("Op%.4x_%s\n", op, ms?"":":");\r
+\r
+ Cycles=4;\r
+ if(ea>=8) Cycles+=10;\r
+\r
+ EaCalc (11,0x003f,ea,0,1);\r
+ EaRead (11, 1,ea,0,0x003f,1);\r
+\r
+ ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
+ OpGetFlags(0,0);\r
+ ot("\n");\r
+\r
+#if CYCLONE_FOR_GENESIS\r
+ // the original Sega hardware ignores write-back phase (to memory only)\r
+ if (ea < 0x10 || gen_special) {\r
+#endif\r
+ ot(" orr r1,r1,#0x80000000 ;@ set bit7\n");\r
+\r
+ EaWrite(11, 1,ea,0,0x003f,1);\r
+#if CYCLONE_FOR_GENESIS\r
+ }\r
+#endif\r
+\r
+ OpEnd(ea);\r
+\r
+#if (CYCLONE_FOR_GENESIS == 2)\r
+ if (!gen_special && ea >= 0x10) {\r
+ OpTas(op, 1);\r
+ }\r
+#endif\r
+\r
+ return 0;\r
+}\r
+\r
notaz.gp2x.de / cyclone68000.git / blobdiff