\r
#include "app.h"\r
\r
+// trashes r0\r
+const char *TestCond(int m68k_cc, int invert)\r
+{\r
+ const char *cond="";\r
+ const char *icond="";\r
+\r
+ // ARM: NZCV\r
+ switch (m68k_cc)\r
+ {\r
+ case 0x00: // T\r
+ case 0x01: // F\r
+ break;\r
+ case 0x02: // hi\r
+ ot(" tst r10,#0x60000000 ;@ hi: !C && !Z\n");\r
+ cond="eq", icond="ne";\r
+ break;\r
+ case 0x03: // ls\r
+ ot(" tst r10,#0x60000000 ;@ ls: C || Z\n");\r
+ cond="ne", icond="eq";\r
+ break;\r
+ case 0x04: // cc\r
+ ot(" tst r10,#0x20000000 ;@ cc: !C\n");\r
+ cond="eq", icond="ne";\r
+ break;\r
+ case 0x05: // cs\r
+ ot(" tst r10,#0x20000000 ;@ cs: C\n");\r
+ cond="ne", icond="eq";\r
+ break;\r
+ case 0x06: // ne\r
+ ot(" tst r10,#0x40000000 ;@ ne: !Z\n");\r
+ cond="eq", icond="ne";\r
+ break;\r
+ case 0x07: // eq\r
+ ot(" tst r10,#0x40000000 ;@ eq: Z\n");\r
+ cond="ne", icond="eq";\r
+ break;\r
+ case 0x08: // vc\r
+ ot(" tst r10,#0x10000000 ;@ vc: !V\n");\r
+ cond="eq", icond="ne";\r
+ break;\r
+ case 0x09: // vs\r
+ ot(" tst r10,#0x10000000 ;@ vs: V\n");\r
+ cond="ne", icond="eq";\r
+ break;\r
+ case 0x0a: // pl\r
+ ot(" tst r10,r10 ;@ pl: !N\n");\r
+ cond="pl", icond="mi";\r
+ break;\r
+ case 0x0b: // mi\r
+ ot(" tst r10,r10 ;@ mi: N\n");\r
+ cond="mi", icond="pl";\r
+ break;\r
+ case 0x0c: // ge\r
+ ot(" teq r10,r10,lsl #3 ;@ ge: N == V\n");\r
+ cond="pl", icond="mi";\r
+ break;\r
+ case 0x0d: // lt\r
+ ot(" teq r10,r10,lsl #3 ;@ lt: N != V\n");\r
+ cond="mi", icond="pl";\r
+ break;\r
+ case 0x0e: // gt\r
+ ot(" eor r0,r10,r10,lsl #3 ;@ gt: !Z && N == V\n");\r
+ ot(" orrs r0,r10,lsl #1\n");\r
+ cond="pl", icond="mi";\r
+ break;\r
+ case 0x0f: // le\r
+ ot(" eor r0,r10,r10,lsl #3 ;@ le: Z || N != V\n");\r
+ ot(" orrs r0,r10,lsl #1\n");\r
+ cond="mi", icond="pl";\r
+ break;\r
+ default:\r
+ printf("invalid m68k_cc: %x\n", m68k_cc);\r
+ exit(1);\r
+ break;\r
+ }\r
+ return invert?icond:cond;\r
+}\r
+\r
// --------------------- Opcodes 0x0100+ ---------------------\r
// Emit a Btst (Register) opcode 0000nnn1 ttaaaaaa\r
int OpBtstReg(int op)\r
ot(";@ Not:\n");\r
if(size!=2) {\r
ot(" mov r0,r0,asl #%i\n",size?16:24);\r
- ot(" mvn r1,r0,asr #%i\n",size?16:24);\r
+ ot(" mvns r1,r0,asr #%i\n",size?16:24);\r
}\r
else\r
- ot(" mvn r1,r0\n");\r
- ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
- OpGetFlags(0,0);\r
+ ot(" mvns r1,r0\n");\r
+ OpGetFlagsNZ(1);\r
ot("\n");\r
}\r
\r
EaCalc (11,0x0007,ea,2,1);\r
EaRead (11, 0,ea,2,0x0007,1);\r
\r
- ot(" mov r1,r0,ror #16\n");\r
- ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
- OpGetFlags(0,0);\r
+ ot(" movs r1,r0,ror #16\n");\r
+ OpGetFlagsNZ(1);\r
\r
EaWrite(11, 1,8,2,0x0007,1);\r
\r
\r
OpStart(op,sea); Cycles=4;\r
\r
- EaCalc ( 0,0x003f,sea,size,1);\r
- EaRead ( 0, 0,sea,size,0x003f,1);\r
+ EaCalc (0,0x003f,sea,size,1);\r
+ EaRead (0, 0,sea,size,0x003f,1,0,1);\r
\r
- ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
- ot(" mrs r10,cpsr ;@ r10=flags\n");\r
+ OpGetFlagsNZ(0);\r
ot("\n");\r
\r
OpEnd(sea);\r
EaCalc (11,0x0007,ea,size+1,0,0);\r
EaRead (11, 0,ea,size+1,0x0007,0,0);\r
\r
- ot(" mov r0,r0,asl #%d\n",shift);\r
- ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
- ot(" mrs r10,cpsr ;@ r10=flags\n");\r
+ ot(" movs r0,r0,asl #%d\n",shift);\r
+ OpGetFlagsNZ(0);\r
ot(" mov r1,r0,asr #%d\n",shift);\r
ot("\n");\r
\r
{\r
int cc=0,ea=0;\r
int size=0,use=0,changed_cycles=0;\r
- static const char * const cond[16]=\r
- {\r
- "al","", "hi","ls","cc","cs","ne","eq",\r
- "vc","vs","pl","mi","ge","lt","gt","le"\r
- };\r
+ const char *cond;\r
\r
cc=(op>>8)&15;\r
ea=op&0x003f;\r
OpStart(op,ea,0,changed_cycles); Cycles=8;\r
if (ea<8) Cycles=4;\r
\r
- if (cc)\r
- ot(" mov r1,#0\n");\r
-\r
switch (cc)\r
{\r
- case 0: // T\r
+ case 0x00: // T\r
ot(" mvn r1,#0\n");\r
if (ea<8) Cycles+=2;\r
break;\r
- case 1: // F\r
- break;\r
- case 2: // hi\r
- ot(" tst r10,#0x60000000 ;@ hi: !C && !Z\n");\r
- ot(" mvneq r1,r1\n");\r
- if (ea<8) ot(" subeq r5,r5,#2 ;@ Extra cycles\n");\r
- break;\r
- case 3: // ls\r
- ot(" tst r10,#0x60000000 ;@ ls: C || Z\n");\r
- ot(" mvnne r1,r1\n");\r
- if (ea<8) ot(" subne r5,r5,#2 ;@ Extra cycles\n");\r
+ case 0x01: // F\r
+ ot(" mov r1,#0\n");\r
break;\r
default:\r
- ot(";@ Is the condition true?\n");\r
- ot(" msr cpsr_flg,r10 ;@ ARM flags = 68000 flags\n");\r
- ot(" mvn%s r1,r1\n",cond[cc]);\r
- if (ea<8) ot(" sub%s r5,r5,#2 ;@ Extra cycles\n",cond[cc]);\r
+ ot(" mov r1,#0\n");\r
+ cond=TestCond(cc);\r
+ ot(" mvn%s r1,#0\n",cond);\r
+ if (ea<8) ot(" sub%s r5,r5,#2 ;@ Extra cycles\n",cond);\r
break;\r
}\r
\r
ot(" b nozerox%.4x\n",op);\r
ot("norotx_%.4x%s\n",op,ms?"":":");\r
ot(" ldr r2,[r7,#0x4c]\n");\r
- ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
- OpGetFlags(0,0);\r
+ ot(" adds r0,r0,#0 ;@ Define flags\n");\r
+ OpGetFlagsNZ(0);\r
ot(" and r2,r2,#0x20000000\n");\r
ot(" orr r10,r10,r2 ;@ C = old_X\n");\r
ot("nozerox%.4x%s\n",op,ms?"":":");\r
if(ea>=8) Cycles+=10;\r
\r
EaCalc (11,0x003f,ea,0,1);\r
- EaRead (11, 1,ea,0,0x003f,1);\r
+ EaRead (11, 1,ea,0,0x003f,1,0,1);\r
\r
- ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
- OpGetFlags(0,0);\r
+ OpGetFlagsNZ(1);\r
ot("\n");\r
\r
#if CYCLONE_FOR_GENESIS\r