Compile-tested under Linux, VisualStudio project might be not up-to-date.
\r
// Cyclone 68000 Emulator - Header File\r
\r
-// Copyright (c) 2011 FinalDave (emudave (at) gmail.com)\r
+// Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)\r
+// Copyright (c) 2005-2011 Gražvydas "notaz" Ignotas (notasas (at) gmail.com)\r
\r
// This code is licensed under the GNU General Public License version 2.0 and the MAME License.\r
// You can choose the license that has the most advantages for you.\r
\r
// SVN repository can be found at http://code.google.com/p/cyclone68000/\r
\r
+\r
+#ifndef __CYCLONE_H__\r
+#define __CYCLONE_H__\r
+\r
#ifdef __cplusplus\r
extern "C" {\r
#endif\r
\r
struct Cyclone\r
{\r
- unsigned int d[8]; // [r7,#0x00]\r
- unsigned int a[8]; // [r7,#0x20]\r
- unsigned int pc; // [r7,#0x40] Memory Base+PC\r
- unsigned char srh; // [r7,#0x44] Status Register high (T_S__III)\r
- unsigned char xc; // [r7,#0x45] Extend flag (____??X?)\r
- unsigned char flags; // [r7,#0x46] Flags (ARM order: ____NZCV)\r
- unsigned char irq; // [r7,#0x47] IRQ level\r
- unsigned int osp; // [r7,#0x48] Other Stack Pointer (USP/SSP)\r
- unsigned int vector; // [r7,#0x50] IRQ vector (temporary)\r
- int pad1[3];\r
- int cycles; // [r7,#0x5c]\r
- int membase; // [r7,#0x60] Memory Base (ARM address minus 68000 address)\r
- unsigned int (*checkpc)(unsigned int pc); // [r7,#0x64] - Called to recalc Memory Base+pc\r
- unsigned char (*read8 )(unsigned int a); // [r7,#0x68]\r
- unsigned short (*read16 )(unsigned int a); // [r7,#0x6c]\r
- unsigned int (*read32 )(unsigned int a); // [r7,#0x70]\r
+ unsigned int d[8]; // [r7,#0x00]\r
+ unsigned int a[8]; // [r7,#0x20]\r
+ unsigned int pc; // [r7,#0x40] Memory Base (.membase) + 68k PC\r
+ unsigned char srh; // [r7,#0x44] Status Register high (T_S__III)\r
+ unsigned char unused; // [r7,#0x45] Unused\r
+ unsigned char flags; // [r7,#0x46] Flags (ARM order: ____NZCV) [68k order is XNZVC]\r
+ unsigned char irq; // [r7,#0x47] IRQ level\r
+ unsigned int osp; // [r7,#0x48] Other Stack Pointer (USP/SSP)\r
+ unsigned int xc; // [r7,#0x4c] Extend flag (bit29: ??X? _)\r
+ unsigned int prev_pc; // [r7,#0x50] Set to start address of currently executed opcode + 2 (if enabled in config.h)\r
+ unsigned int jumptab; // [r7,#0x54] Jump table pointer\r
+ int state_flags; // [r7,#0x58] bit: 0: stopped state, 1: trace state, 2: activity bit, 3: addr error, 4: fatal halt\r
+ int cycles; // [r7,#0x5c] Number of cycles to execute - 1. Updates to cycles left after CycloneRun()\r
+ int membase; // [r7,#0x60] Memory Base (ARM address minus 68000 address)\r
+ unsigned int (*checkpc)(unsigned int pc); // [r7,#0x64] called to recalc Memory Base+pc\r
+ unsigned int (*read8 )(unsigned int a); // [r7,#0x68]\r
+ unsigned int (*read16 )(unsigned int a); // [r7,#0x6c]\r
+ unsigned int (*read32 )(unsigned int a); // [r7,#0x70]\r
void (*write8 )(unsigned int a,unsigned char d); // [r7,#0x74]\r
void (*write16)(unsigned int a,unsigned short d); // [r7,#0x78]\r
void (*write32)(unsigned int a,unsigned int d); // [r7,#0x7c]\r
- unsigned char (*fetch8 )(unsigned int a); // [r7,#0x80]\r
- unsigned short (*fetch16)(unsigned int a); // [r7,#0x84]\r
- unsigned int (*fetch32)(unsigned int a); // [r7,#0x88]\r
+ unsigned int (*fetch8 )(unsigned int a); // [r7,#0x80]\r
+ unsigned int (*fetch16)(unsigned int a); // [r7,#0x84]\r
+ unsigned int (*fetch32)(unsigned int a); // [r7,#0x88]\r
+ int (*IrqCallback)(int int_level); // [r7,#0x8c] optional irq callback function, see config.h\r
+ void (*ResetCallback)(void); // [r7,#0x90] if enabled in config.h, calls this whenever RESET opcode is encountered.\r
+ int (*UnrecognizedCallback)(void); // [r7,#0x94] if enabled in config.h, calls this whenever unrecognized opcode is encountered.\r
+ unsigned int internal[6]; // [r7,#0x98] reserved for internal use, do not change.\r
};\r
\r
+// Initialize. Used only if Cyclone was compiled with compressed jumptable, see config.h\r
+void CycloneInit(void);\r
+\r
+// Reset\r
+void CycloneReset(struct Cyclone *pcy);\r
+\r
+// Run cyclone. Cycles should be specified in context (pcy->cycles)\r
void CycloneRun(struct Cyclone *pcy);\r
\r
+// Utility functions to get and set SR\r
+void CycloneSetSr(struct Cyclone *pcy, unsigned int sr);\r
+unsigned int CycloneGetSr(const struct Cyclone *pcy);\r
+\r
+// Generates irq exception if needed (if pcy->irq > mask).\r
+// Returns cycles used for exception if it was generated, 0 otherwise.\r
+int CycloneFlushIrq(struct Cyclone *pcy);\r
+\r
+// Functions for saving and restoring state.\r
+// CycloneUnpack() uses checkpc(), so it must be initialized.\r
+// save_buffer must point to buffer of 128 (0x80) bytes of size.\r
+void CyclonePack(const struct Cyclone *pcy, void *save_buffer);\r
+void CycloneUnpack(struct Cyclone *pcy, const void *save_buffer);\r
+\r
+// genesis: if 1, switch to normal TAS handlers\r
+void CycloneSetRealTAS(int use_real);\r
+\r
+\r
+// These values are special return values for IrqCallback.\r
+\r
+// Causes an interrupt autovector (0x18 + interrupt level) to be taken.\r
+// This happens in a real 68K if VPA or AVEC is asserted during an interrupt\r
+// acknowledge cycle instead of DTACK (the most common situation).\r
+#define CYCLONE_INT_ACK_AUTOVECTOR -1\r
+\r
+// Causes the spurious interrupt vector (0x18) to be taken\r
+// This happens in a real 68K if BERR is asserted during the interrupt\r
+// acknowledge cycle (i.e. no devices responded to the acknowledge).\r
+#define CYCLONE_INT_ACK_SPURIOUS -2\r
+\r
+\r
#ifdef __cplusplus\r
} // End of extern "C"\r
#endif\r
+\r
+#endif // __CYCLONE_H__\r
+\r
\r
___________________________________________________________________________\r
\r
+ Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)\r
+ Copyright (c) 2005-2011 Gražvydas "notaz" Ignotas (notasas (at) gmail.com)\r
\r
-This code is licensed under the GNU General Public License version 2.0 and the MAME License.\r
-You can choose the license that has the most advantages for you.\r
+ This code is licensed under the GNU General Public License version 2.0 and the MAME License.\r
+ You can choose the license that has the most advantages for you.\r
+\r
+ Homepage: http://code.google.com/p/cyclone68000/\r
\r
___________________________________________________________________________\r
\r
\r
-What is it?\r
------------\r
+About\r
+-----\r
\r
Cyclone 68000 is an emulator for the 68000 microprocessor, written in ARM 32-bit assembly.\r
It is aimed at chips such as ARM7 and ARM9 cores, StrongARM and XScale, to interpret 68000\r
-code as fast as possible.\r
-\r
-Flags are mapped onto ARM flags whenever possible, which speeds up the processing of opcode.\r
-\r
-Developers:\r
------------\r
-\r
-Dave / FinalDave: emudave(atsymbol)gmail.com\r
-\r
-\r
-What's New\r
-----------\r
-v0.069\r
- + Added SBCD and the flags for ABCD/SBCD. Score and time now works in games such as\r
- Rolling Thunder 2, Ghouls 'N Ghosts\r
- + Fixed a problem with addx and subx with 8-bit and 16-bit values.\r
- Ghouls 'N' Ghosts now works!\r
-\r
-v0.068\r
- + Added ABCD opcode (Streets of Rage works now!)\r
-\r
-v0.067\r
- + Added dbCC (After Burner)\r
- + Added asr EA (Sonic 1 Boss/Labyrinth Zone)\r
- + Added andi/ori/eori ccr (Altered Beast)\r
- + Added trap (After Burner)\r
- + Added special case for move.b (a7)+ and -(a7), stepping by 2\r
- After Burner is playable! Eternal Champions shows more\r
- + Fixed lsr.b/w zero flag (Ghostbusters)\r
- Rolling Thunder 2 now works!\r
- + Fixed N flag for .b and .w arithmetic. Golden Axe works!\r
-\r
-v0.066\r
- + Fixed a stupid typo for exg (orr r10,r10, not orr r10,r8), which caused alignment\r
- crashes on Strider\r
-\r
-v0.065\r
- + Fixed a problem with immediate values - they weren't being shifted up correctly for some\r
- opcodes. Spiderman works, After Burner shows a bit of graphics.\r
- + Fixed a problem with EA:"110nnn" extension word. 32-bit offsets were being decoded as 8-bit\r
- offsets by mistake. Castlevania Bloodlines seems fine now.\r
- + Added exg opcode\r
- + Fixed asr opcode (Sonic jumping left is fixed)\r
- + Fixed a problem with the carry bit in rol.b (Marble Madness)\r
-\r
-v0.064\r
- + Added rtr\r
- + Fixed addq/subq.l (all An opcodes are 32-bit) (Road Rash)\r
- + Fixed various little timings\r
-\r
-v0.063\r
- + Added link/unlk opcodes\r
- + Fixed various little timings\r
- + Fixed a problem with dbCC opcode being emitted at set opcodes\r
- + Improved long register access, the EA fetch now does ldr r0,[r7,r0,lsl #2] whenever\r
- possible, saving 1 or 2 cycles on many opcodes, which should give a nice speed up.\r
- + May have fixed N flag on ext opcode?\r
- + Added dasm for link opcode.\r
+code as fast as possible. It can emulate all 68000 instructions quite accurately, instruction\r
+timing was synchronized with MAME's Musashi. Most 68k features are emulated (trace mode,\r
+address errors), but prefetch is not emulated.\r
\r
-v0.062\r
- * I was a bit too keen with the Arithmetic opcodes! Some of them should have been abcd,\r
- exg and addx. Removed the incorrect opcodes, pending re-adding them as abcd, exg and addx.\r
- + Changed unknown opcodes to act as nops.\r
- Not very technical, but fun - a few more games show more graphics ;)\r
\r
-v0.060\r
- + Fixed divu (EA intro)\r
- + Added sf (set false) opcode - SOR2\r
- * Todo: pea/link/unlk opcodes\r
+How to Compile\r
+--------------\r
\r
-v0.059: Added remainder to divide opcodes.\r
+Like Starscream and A68K, Cyclone uses a 'Core Creator' program which calculates and outputs\r
+all possible 68000 Opcodes and a jump table into file called Cyclone.s or Cyclone.asm.\r
+Only Cyclone.h and the mentioned .s or .asm file will be needed for your project, other files\r
+are here to produce or test it.\r
\r
+First unzip "Cyclone.zip" into a "Cyclone" directory. The next thing to do is to edit config.h\r
+file to tune Cyclone for your project. There are lots of options in config.h, but all of them\r
+are documented and have defaults. You should set a define value to 1 to enable option, and\r
+to 0 to disable.\r
\r
-ARM Register Usage\r
-------------------\r
+After you are done with config.h, save it and compile Cyclone. If you are using Linux, Cygwin,\r
+mingw or similar, you can simply cd to Cyclone/proj and type "make". If you are under Windows\r
+and have Visual Studio installed, you can import cyclone.dsp in the proj/ directory and compile\r
+it from there (this will produce cyclone.exe which you will have to run to get .s or .asm).\r
+You can also use Microsoft command line compile tools by entering Cyclone/proj directory and\r
+typing "nmake -f Makefile.win". Note that this step is done only to produce .s or .asm, and it\r
+is done using native tools on your PC (not using cross-compiler or similar).\r
\r
-See source code for up to date of register usage, however a summary is here:\r
+The .s file is meant to be compiled with GNU assembler, and .asm with ARMASM.EXE\r
+(the Microsoft ARM assembler). Once you have the file, you can add it to your\r
+Makefile/project/whatever.\r
\r
- r0-3: Temporary registers\r
- r4 : Current PC + Memory Base (i.e. pointer to next opcode)\r
- r5 : Cycles remaining\r
- r6 : Pointer to Opcode Jump table\r
- r7 : Pointer to Cpu Context\r
- r8 : Current Opcode\r
- r9 : Flags (NZCV) in highest four bits\r
- (r10 : Temporary source value or Memory Base)\r
- (r11 : Temporary register)\r
\r
+Adding to your project\r
+----------------------\r
\r
-How to Compile\r
---------------\r
-\r
-Like Starscream and A68K, Cyclone uses a 'Core Creator' program which calculates and outputs\r
-all possible 68000 Opcodes and a jump table into files called Cyclone.s and .asm\r
-It then assembles these files into Cyclone.o and .obj\r
-\r
-Cyclone.o is the GCC assembled version and Cyclone.obj is the Microsoft assembled version.\r
+Compiling the .s or .asm (from previous step) for your target platform may require custom\r
+build rules in your Makefile/project.\r
\r
-First unzip "Cyclone.zip" into a "Cyclone" directory.\r
-If you are compiling for Windows CE, find ARMASM.EXE (the Microsoft ARM assembler) and\r
-put it in the directory as well or put it on your path.\r
+If you use some gcc-based toolchain, you will need to add Cyclone.o to an object list in\r
+the Makefile. GNU make will use "as" to build Cyclone.o from Cyclone.s by default, so\r
+you may need to define correct cross-assembler by setting AS variable like this:\r
\r
-Open up Cyclone.dsw in Visual Studio 6.0, compile and run the project.\r
-Cyclone.obj and Cyclone.o will be created.\r
+AS = arm-linux-as\r
\r
-Compiling without Visual C++\r
-----------------------------\r
-If you aren't using Visual C++, it still shouldn't be too hard to compile, just get a C compiler,\r
-compile all the CPPs and C file, link them into an EXE, and run the exe.\r
+This might be different in your case, basically it should be same prefix as for gcc.\r
+You may also need to specify floating point type in your assembler flags for Cyclone.o\r
+to link properly. This is done like this:\r
\r
- e.g. gcc Main.cpp OpAny.cpp OpArith.cpp OpBranch.cpp OpLogic.cpp OpMove.cpp Disa.c\r
- Main.exe\r
+ASFLAGS = -mfloat-abi=soft\r
\r
+Note that Cyclone does not use floating points, this is just to make the linker happy.\r
\r
-Adding to your project\r
-----------------------\r
\r
-To add Cyclone to you project, add Cyclone.o or obj, and include Cyclone.h\r
-There is one structure: 'struct Cyclone', and one function: CycloneRun\r
+If you are using Visual Studio, you may need to add "custom build step", which creates\r
+Cyclone.obj from Cyclone.asm (asmasm.exe Cyclone.asm). Alternatively you can create\r
+Cyclone.obj by using armasm once and then just add it to you project.\r
\r
Don't worry if this seem very minimal - its all you need to run as many 68000s as you want.\r
It works with both C and C++.\r
\r
+\r
Byteswapped Memory\r
------------------\r
\r
\r
Any memory which the 68000 can access directly must be have every two bytes swapped around.\r
This is to speed up 16-bit memory accesses, because the 68000 has Big-Endian memory\r
-and ARM has Little-Endian memory.\r
+and ARM has Little-Endian memory (in most cases).\r
\r
Now you may think you only technically have to byteswap ROM, not RAM, because\r
16-bit RAM reads go through a memory handler and you could just return (mem[a]<<8) | mem[a+1].\r
return *(unsigned short *)(mem+a)\r
\r
\r
-Declaring a Memory handlers\r
----------------------------\r
+Declaring Memory handlers\r
+-------------------------\r
\r
Before you can reset or execute 68000 opcodes you must first set up a set of memory handlers.\r
There are 7 functions you have to set up per CPU, like this:\r
\r
The other 5 read/write functions are similar. I'll describe the CheckPc function later on.\r
\r
+\r
Declaring a CPU Context\r
-----------------------\r
\r
-To declare a CPU simple declare a struct Cyclone in your code. For example to declare\r
-two 68000s:\r
+To declare a CPU simple declare a struct Cyclone in your code (don't forget to include Cyclone.h).\r
+For example to declare two 68000s:\r
\r
struct Cyclone MyCpu;\r
struct Cyclone MyCpu2;\r
\r
-It's probably a good idea to initialise the memory to zero:\r
+It's probably a good idea to initialize the memory to zero:\r
\r
memset(&MyCpu, 0,sizeof(MyCpu));\r
memset(&MyCpu2,0,sizeof(MyCpu2));\r
If this is the case, you can set up different functions for fetch reads.\r
Generally though you don't need to. )\r
\r
-Now you are nearly ready to reset the 68000, except you need one more function: checkpc().\r
+Now you are nearly ready to reset the 68000, except a few more functions,\r
+one of them is: checkpc().\r
+\r
\r
The checkpc() function\r
----------------------\r
Cyclone's program counter would be 0x3000206.\r
\r
The difference between an ARM address and a 68000 address is also stored in a variable called\r
-'membase'. In the above example it's 0x3000000. To retrieve the real PC, Cyclone just\r
+'membase'. In the above example it's 0x3000000. To retrieve the real 68k PC, Cyclone just\r
subtracts 'membase'.\r
\r
When a long jump happens, Cyclone calls checkpc(). If the PC is in a different bank,\r
Notice that the membase is always ARM address minus 68000 address.\r
\r
The above example doesn't consider mirrored ram, but for an example of what to do see\r
-PicoDrive (in Memory.cpp).\r
+PicoDrive (in Memory.c).\r
+\r
+The exact cases when checkpc() is called can be configured in config.h.\r
+\r
+\r
+Initialization\r
+--------------\r
+\r
+Add a call to CycloneInit(). This is really only needed to be called once at startup\r
+if you enabled COMPRESS_JUMPTABLE in config.h, but you can add this in any case,\r
+it won't hurt.\r
\r
\r
Almost there - Reset the 68000!\r
-------------------------------\r
\r
-Next we need to Reset the 68000 to get the initial Program Counter and Stack Pointer. This\r
-is obtained from addresses 000000 and 000004.\r
+Cyclone doesn't provide a reset function, so next we need to Reset the 68000 to get\r
+the initial Program Counter and Stack Pointer. This is obtained from addresses\r
+000000 and 000004.\r
\r
Here is code which resets the 68000 (using your memory handlers):\r
\r
+ MyCpu.state_flags=0; // Go to default state (not stopped, halted, etc.)\r
MyCpu.srh=0x27; // Set supervisor mode\r
MyCpu.a[7]=MyCpu.read32(0); // Get Stack Pointer\r
- MyCpu.membase=0;\r
+ MyCpu.membase=0; // Will be set by checkpc()\r
MyCpu.pc=MyCpu.checkpc(MyCpu.read32(4)); // Get Program Counter\r
\r
And that's ready to go.\r
MyCpu.cycles=1000; CycloneRun(&MyCpu);\r
\r
For each opcode, the number of cycles it took is subtracted and the function returns when\r
-it reaches 0.\r
+it reaches negative number. The result is stored back to MyCpu.cycles.\r
\r
e.g.\r
// Execute one instruction on the 68000:\r
Note that the interrupt is not actually processed until the next call to CycloneRun,\r
and the interrupt may not be taken until the 68000 interrupt mask is changed to allow it.\r
\r
-( The IRQ isn't checked on exiting from a memory handler: I don't think this will cause\r
- me any trouble because I've never needed to trigger an interrupt from a memory handler,\r
- but if someone needs to, let me know...)\r
+If you need to force interrupt processing, you can use CycloneFlushIrq() function.\r
+It is the same as doing\r
\r
-Accessing Cycle Counter\r
------------------------\r
+MyCpu.cycles=0; CycloneRun(&MyCpu);\r
+\r
+but is better optimized and doesn't update .cycles (returns them instead).\r
+This function can't be used from memory handlers and has no effect if interrupt is masked.\r
\r
-The cycle counter in the Cyclone structure is not, by default, updated before\r
-calling a memory handler, only at the end of an execution.\r
+The IRQ isn't checked on exiting from a memory handler. If you need to cause interrupt\r
+check immediately, you should change cycle counter to 0 to cause a return from CycloneRun(),\r
+and then call CycloneRun() again or just call CycloneFlushIrq(). Note that you need to\r
+enable MEMHANDLERS_CHANGE_CYCLES in config.h for this to work.\r
\r
-If you do need to read the cycle counter inside memory handlers, there is a\r
-bitfield called 'Debug' in Cyclone/Main.cpp.\r
-You can try setting Debug to 1 and then making the Cyclone library.\r
-This will add extra instructions so Cyclone writes register r5 back into the structure.\r
+If you need to do something during the interrupt acknowledge (the moment when interrupt\r
+is taken), you can set USE_INT_ACK_CALLBACK in config.h and specify IrqCallback function.\r
+This function should update the IRQ level (.irq variable in context) and return the\r
+interrupt vector number. But for most cases it should return special constant\r
+CYCLONE_INT_ACK_AUTOVECTOR so that Cyclone uses autovectors, which is what most real\r
+systems were doing. Another less commonly used option is to return CYCLONE_INT_ACK_SPURIOUS\r
+for spurious interrupt.\r
\r
-If you need to *modify* cycles in a memory handler, set Debug to 3, this will read back\r
-the cycle counter as well.\r
\r
Accessing Program Counter and registers\r
---------------------------------------\r
\r
-You can read Cyclone's registers directly from the structure at any time (as far as I know).\r
+You can read most Cyclone's registers directly from the structure at any time.\r
+However, the PC value, CCR and cycle counter are cached in ARM registers and can't\r
+be accessed from memory handlers by default. They are written back and can be\r
+accessed after execution.\r
+\r
+But if you need to access the mentioned registers during execution, you can set\r
+MEMHANDLERS_NEED_* and MEMHANDLERS_CHANGE_* options in config.h\r
\r
The Program Counter, should you need to read or write it, is stored with membase\r
added on. So use this formula to calculate the real 68000 program counter:\r
\r
pc = MyCpu.pc - MyCpu.membase;\r
\r
-The program counter is stored in r4 during execution, and isn't written back to the\r
-structure until the end of execution, which means you can't read normally real it from\r
-a memory handler.\r
-However you can try setting Debug to 4 and then making the Cyclone library, this will\r
-write back r4 to the structure.\r
-\r
-You can't access the flags from a handler either. I can't imagine why anyone would particularly\r
-need to do this, but if you do e-mail me and I'll add another bit to 'Debug' ;)\r
+For performance reasons Cyclone keeps the status register split into .srh\r
+(status register "high" supervisor byte), .xc for the X flag, and .flags for remaining\r
+CCR flags (in ARM order). To easily read/write the status register as normal 68k\r
+16bit SR register, use CycloneGetSr() and CycloneSetSr() utility functions.\r
\r
\r
Emulating more than one CPU\r
MyCpu2.cycles=1000; CycloneRun(&MyCpu2);\r
\r
\r
+Quick API reference\r
+-------------------\r
+\r
+void CycloneInit(void);\r
+ Initializes Cyclone. Must be called if the jumptable is compressed,\r
+ doesn't matter otherwise.\r
+\r
+void CycloneRun(struct Cyclone *pcy);\r
+ Runs cyclone for pcy->cycles. Writes amount of cycles left back to\r
+ pcy->cycles (always negative).\r
+\r
+unsigned int CycloneGetSr(const struct Cyclone *pcy);\r
+ Reads status register in internal form from pcy, converts to standard 68k SR and returns it.\r
+\r
+void CycloneSetSr(struct Cyclone *pcy, unsigned int sr);\r
+ Takes standard 68k status register (sr), and updates Cyclone context with it.\r
+ \r
+int CycloneFlushIrq(struct Cyclone *pcy);\r
+ If .irq is greater than IRQ mask in SR, or it is equal to 7 (NMI), processes interrupt\r
+ exception and returns number of cycles used. Otherwise, does nothing and returns 0.\r
+\r
+void CyclonePack(const struct Cyclone *pcy, void *save_buffer);\r
+ Writes Cyclone state to save_buffer. This allows to avoid all the trouble figuring what\r
+ actually needs to be saved from the Cyclone structure, as saving whole struct Cyclone\r
+ to a file will also save various pointers, which may become invalid after your program\r
+ is restarted, so simply reloading the structure will cause a crash. save_buffer size\r
+ should be 128 bytes (now it is really using less, but this allows future expansion).\r
+\r
+void CycloneUnpack(struct Cyclone *pcy, const void *save_buffer);\r
+ Reloads Cyclone state from save_buffer, which was previously saved by CyclonePack().\r
+ This function uses checkpc() callback to rebase the PC, so .checkpc must be initialized\r
+ before calling it.\r
+\r
+Callbacks:\r
+\r
+.checkpc\r
+unsigned int (*checkpc)(unsigned int pc);\r
+ This function is called when PC changes are performed in 68k code or because of exceptions.\r
+ It is passed ARM pointer and should return ARM pointer casted to int. It must also update\r
+ .membase if needed. See "The checkpc() function" section above.\r
+\r
+unsigned int (*read8 )(unsigned int a);\r
+unsigned int (*read16 )(unsigned int a);\r
+unsigned int (*read32 )(unsigned int a);\r
+ These are the read memory handler callbacks. They are called when 68k code reads from memory.\r
+ The parameter is a 68k address in data space, return value is a data value read. Data value\r
+ doesn't have to be masked to 8 or 16 bits for read8 or read16, Cyclone will do that itself\r
+ if needed.\r
+\r
+unsigned int (*fetch8 )(unsigned int a);\r
+unsigned int (*fetch16)(unsigned int a);\r
+unsigned int (*fetch32)(unsigned int a);\r
+ Same as above, but these are reads from program space (PC relative reads mostly).\r
+ \r
+void (*write8 )(unsigned int a,unsigned char d);\r
+void (*write16)(unsigned int a,unsigned short d);\r
+void (*write32)(unsigned int a,unsigned int d);\r
+ These are called when 68k code writes to data space. d is the data value.\r
+\r
+int (*IrqCallback)(int int_level);\r
+ This function is called when Cyclone acknowledges an interrupt. The parameter is the IRQ\r
+ level being acknowledged, and return value is exception vector to use, or one of these special\r
+ values: CYCLONE_INT_ACK_AUTOVECTOR or CYCLONE_INT_ACK_SPURIOUS. Can be disabled in config.h.\r
+ See "Interrupts" section for more information.\r
+\r
+void (*ResetCallback)(void);\r
+ Cyclone will call this function if it encounters RESET 68k instruction.\r
+ Can be disabled in config.h.\r
+\r
+int (*UnrecognizedCallback)(void);\r
+ Cyclone will call this function if it encounters illegal instructions (including A-line and\r
+ F-line ones). Can be tuned / disabled in config.h.\r
+\r
+\r
+Function codes\r
+--------------\r
+\r
+Cyclone doesn't pass function codes to it's memory handlers, but they can be calculated:\r
+FC2: just use supervisor state bit from status register (eg. (MyCpu.srh & 0x20) >> 5)\r
+FC1: if we are in fetch* function, then 1, else 0.\r
+FC0: if we are in read* or write*, then 1, else 0.\r
+CPU state (all FC bits set) is active in IrqCallback function.\r
+\r
+\r
+References\r
+----------\r
+\r
+These documents were used while writing Cyclone and should be useful for those who want to\r
+understand deeper how the 68000 works.\r
+\r
+MOTOROLA M68000 FAMILY Programmer's Reference Manual\r
+common name: 68kPM.pdf\r
+\r
+M68000 8-/16-/32-Bit Microprocessors User's Manual\r
+common name: MC68000UM.pdf\r
+\r
+68000 Undocumented Behavior Notes by Bart Trzynadlowski\r
+http://www.trzy.org/files/68knotes.txt\r
+\r
+Instruction prefetch on the Motorola 68000 processor by Jorge Cwik\r
+http://pasti.fxatari.com/68kdocs/68kPrefetch.html\r
+\r
+\r
+ARM Register Usage\r
+------------------\r
+\r
+See source code for up to date of register usage, however a summary is here:\r
+\r
+ r0-3: Temporary registers\r
+ r4 : Current PC + Memory Base (i.e. pointer to next opcode)\r
+ r5 : Cycles remaining\r
+ r6 : Pointer to Opcode Jump table\r
+ r7 : Pointer to Cpu Context\r
+ r8 : Current Opcode\r
+ r10 : Flags (NZCV) in highest four bits\r
+ (r11 : Temporary register)\r
+\r
+Flags are mapped onto ARM flags whenever possible, which speeds up the processing of opcode.\r
+r9 is not used intentionally, because AAPCS defines it as "platform register", so it's\r
+reserved in some systems.\r
+\r
+\r
Thanks to...\r
------------\r
\r
* All the previous code-generating assembler cpu core guys!\r
Who are iirc... Neill Corlett, Neil Bradley, Mike Coates, Darren Olafson\r
- and Bart Trzynadlowski\r
+ Karl Stenerud and Bart Trzynadlowski\r
\r
* Charles Macdonald, for researching just about every console ever\r
* MameDev+FBA, for keeping on going and going and going\r
+\r
+\r
+What's New\r
+----------\r
+v0.0099\r
+ * Cyclone no longer uses r9, because AAPCS defines it as "platform register",\r
+ so it's reserved in some systems.\r
+ * Made SPLIT_MOVEL_PD to affect MOVEM too.\r
+\r
+v0.0088\r
+ - Reduced amount of code in opcode handlers by ~23% by doing the following:\r
+ - Removed duplicate opcode handlers\r
+ - Optimized code to use less ARM instructions\r
+ - Merged some duplicate handler endings\r
+ + Cyclone now does better job avoiding pipeline interlocks.\r
+ + Replaced incorrect handler of DBT with proper one.\r
+ + Changed "MOVEA (An)+ An" behavior.\r
+ + Fixed flag behavior of ROXR, ASL, LSR and NBCD in certain situations.\r
+ Hopefully got them right now.\r
+ + Cyclone no longer sets most significant bits while pushing PC to stack.\r
+ Amiga Kickstart depends on this.\r
+ + Added optional trace mode emulation.\r
+ + Added optional address error emulation.\r
+ + Additional functionality added for MAME and other ports (see config.h).\r
+ + Added return value for IrqCallback to make it suitable for emulating devices which\r
+ pass the vector number during interrupt acknowledge cycle. For usual autovector\r
+ processing this function must return CYCLONE_INT_ACK_AUTOVECTOR, so those who are\r
+ upgrading must add "return CYCLONE_INT_ACK_AUTOVECTOR;" to their IrqCallback functions.\r
+ * Updated documentation.\r
+\r
+v0.0086\r
+ + Cyclone now can be customized to better suit your project, see config.h .\r
+ + Added an option to compress the jumptable at compile-time. Must call CycloneInit()\r
+ at runtime to decompress it if enabled (see config.h).\r
+ + Added missing CHK opcode handler (used by SeaQuest DSV).\r
+ + Added missing TAS opcode handler (Gargoyles,Bubba N Stix,...). As in real genesis,\r
+ memory write-back phase is ignored (but can be enabled in config.h if needed).\r
+ + Added missing NBCD and TRAPV opcode handlers.\r
+ + Added missing addressing mode for CMP/EOR.\r
+ + Added some minor optimizations.\r
+ - Removed 216 handlers for 2927 opcodes which were generated for invalid addressing modes.\r
+ + Fixed flags for ASL, NEG, NEGX, DIVU, ADDX, SUBX, ROXR.\r
+ + Bugs fixed in MOVEP, LINK, ADDQ, DIVS handlers.\r
+ * Undocumented flags for CHK, ABCD, SBCD and NBCD are now emulated the same way as in Musashi.\r
+ + Added Uninitialized Interrupt emulation.\r
+ + Altered timing for about half of opcodes to match Musashi's.\r
+\r
+v0.0082\r
+ + Change cyclone to clear cycles before returning when halted\r
+ + Added Irq call back function. This allows emulators to be notified\r
+ when cyclone has taken an interrupt allowing them to set internal flags\r
+ which can help fix timing problems.\r
+\r
+v0.0081\r
+ + .asm version was broken and did not compile with armasm. Fixed.\r
+ + Finished implementing Stop opcode. Now it really stops the processor.\r
+\r
+v0.0080\r
+ + Added real cmpm opcode, it was using eor handler before this.\r
+ Fixes Dune and Sensible Soccer.\r
+\r
+v0.0078\r
+ note: these bugs were actually found Reesy, I reimplemented these by\r
+ using his changelog as a guide.\r
+ + Fixed a problem with divu which was using long divisor instead of word.\r
+ Fixes gear switching in Top Gear 2.\r
+ + Fixed btst opcode, The bit to test should shifted a max of 31 or 7\r
+ depending on if a register or memory location is being tested.\r
+ + Fixed abcd,sbcd. They did bad decimal correction on invalid BCD numbers\r
+ Score counters in Streets of Rage level end work now.\r
+ + Changed flag handling of abcd,sbcd,addx,subx,asl,lsl,...\r
+ Some ops did not have flag handling at all.\r
+ Some ops must not change Z flag when result is zero, but they did.\r
+ Shift ops must not change X if shift count is zero, but they did.\r
+ There are probably still some flag problems left.\r
+ + Patially implemented Stop and Reset opcodes - Fixes Thunderforce IV\r
+\r
+v0.0075\r
+ + Added missing displacement addressing mode for movem (Fantastic Dizzy)\r
+ + Added OSP <-> A7 swapping code in opcodes, which change privilege mode\r
+ + Implemented privilege violation, line emulator and divide by zero exceptions\r
+ + Added negx opcode (Shining Force works!)\r
+ + Added overflow detection for divs/divu\r
+\r
+v0.0072\r
+ note: I could only get v0.0069 cyclone, so I had to implement these myself using Dave's\r
+ changelog as a guide.\r
+ + Fixed a problem with divs - remainder should be negative when divident is negative\r
+ + Added movep opcode (Sonic 3 works)\r
+ + Fixed a problem with DBcc incorrectly decrementing if the condition is true (Shadow of the Beast)\r
+\r
+v0.0069\r
+ + Added SBCD and the flags for ABCD/SBCD. Score and time now works in games such as\r
+ Rolling Thunder 2, Ghouls 'N Ghosts\r
+ + Fixed a problem with addx and subx with 8-bit and 16-bit values.\r
+ Ghouls 'N' Ghosts now works!\r
+\r
+v0.0068\r
+ + Added ABCD opcode (Streets of Rage works now!)\r
+\r
+v0.0067\r
+ + Added dbCC (After Burner)\r
+ + Added asr EA (Sonic 1 Boss/Labyrinth Zone)\r
+ + Added andi/ori/eori ccr (Altered Beast)\r
+ + Added trap (After Burner)\r
+ + Added special case for move.b (a7)+ and -(a7), stepping by 2\r
+ After Burner is playable! Eternal Champions shows more\r
+ + Fixed lsr.b/w zero flag (Ghostbusters)\r
+ Rolling Thunder 2 now works!\r
+ + Fixed N flag for .b and .w arithmetic. Golden Axe works!\r
+\r
+v0.0066\r
+ + Fixed a stupid typo for exg (orr r10,r10, not orr r10,r8), which caused alignment\r
+ crashes on Strider\r
+\r
+v0.0065\r
+ + Fixed a problem with immediate values - they weren't being shifted up correctly for some\r
+ opcodes. Spiderman works, After Burner shows a bit of graphics.\r
+ + Fixed a problem with EA:"110nnn" extension word. 32-bit offsets were being decoded as 8-bit\r
+ offsets by mistake. Castlevania Bloodlines seems fine now.\r
+ + Added exg opcode\r
+ + Fixed asr opcode (Sonic jumping left is fixed)\r
+ + Fixed a problem with the carry bit in rol.b (Marble Madness)\r
+\r
+v0.0064\r
+ + Added rtr\r
+ + Fixed addq/subq.l (all An opcodes are 32-bit) (Road Rash)\r
+ + Fixed various little timings\r
+\r
+v0.0063\r
+ + Added link/unlk opcodes\r
+ + Fixed various little timings\r
+ + Fixed a problem with dbCC opcode being emitted at set opcodes\r
+ + Improved long register access, the EA fetch now does ldr r0,[r7,r0,lsl #2] whenever\r
+ possible, saving 1 or 2 cycles on many opcodes, which should give a nice speed up.\r
+ + May have fixed N flag on ext opcode?\r
+ + Added dasm for link opcode.\r
+\r
+v0.0062\r
+ * I was a bit too keen with the Arithmetic opcodes! Some of them should have been abcd,\r
+ exg and addx. Removed the incorrect opcodes, pending re-adding them as abcd, exg and addx.\r
+ + Changed unknown opcodes to act as nops.\r
+ Not very technical, but fun - a few more games show more graphics ;)\r
+\r
+v0.0060\r
+ + Fixed divu (EA intro)\r
+ + Added sf (set false) opcode - SOR2\r
+ * Todo: pea/link/unlk opcodes\r
+\r
+v0.0059: Added remainder to divide opcodes.\r
+\r
+\r
\r
// This file is part of the Cyclone 68000 Emulator\r
\r
-// Copyright (c) 2011 FinalDave (emudave (at) gmail.com)\r
+// Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)\r
+// Copyright (c) 2005-2011 Gražvydas "notaz" Ignotas (notasas (at) gmail.com)\r
\r
// This code is licensed under the GNU General Public License version 2.0 and the MAME License.\r
// You can choose the license that has the most advantages for you.\r
\r
// SVN repository can be found at http://code.google.com/p/cyclone68000/\r
\r
+\r
#include "app.h"\r
\r
+int earead_check_addrerr = 1, eawrite_check_addrerr = 0;\r
+\r
+// some ops use non-standard cycle counts for EAs, so are listed here.\r
+// all constants borrowed from the MUSASHI core by Karl Stenerud.\r
+\r
+/* Extra cycles for JMP instruction (000, 010) */\r
+int g_jmp_cycle_table[8] =\r
+{\r
+ 4, /* EA_MODE_AI */\r
+ 6, /* EA_MODE_DI */\r
+ 10, /* EA_MODE_IX */\r
+ 6, /* EA_MODE_AW */\r
+ 8, /* EA_MODE_AL */\r
+ 6, /* EA_MODE_PCDI */\r
+ 10, /* EA_MODE_PCIX */\r
+ 0, /* EA_MODE_I */\r
+};\r
+\r
+/* Extra cycles for JSR instruction (000, 010) */\r
+int g_jsr_cycle_table[8] =\r
+{\r
+ 4, /* EA_MODE_AI */\r
+ 6, /* EA_MODE_DI */\r
+ 10, /* EA_MODE_IX */\r
+ 6, /* EA_MODE_AW */\r
+ 8, /* EA_MODE_AL */\r
+ 6, /* EA_MODE_PCDI */\r
+ 10, /* EA_MODE_PCIX */\r
+ 0, /* EA_MODE_I */\r
+};\r
+\r
+/* Extra cycles for LEA instruction (000, 010) */\r
+int g_lea_cycle_table[8] =\r
+{\r
+ 4, /* EA_MODE_AI */\r
+ 8, /* EA_MODE_DI */\r
+ 12, /* EA_MODE_IX */\r
+ 8, /* EA_MODE_AW */\r
+ 12, /* EA_MODE_AL */\r
+ 8, /* EA_MODE_PCDI */\r
+ 12, /* EA_MODE_PCIX */\r
+ 0, /* EA_MODE_I */\r
+};\r
+\r
+/* Extra cycles for PEA instruction (000, 010) */\r
+int g_pea_cycle_table[8] =\r
+{\r
+ 6, /* EA_MODE_AI */\r
+ 10, /* EA_MODE_DI */\r
+ 14, /* EA_MODE_IX */\r
+ 10, /* EA_MODE_AW */\r
+ 14, /* EA_MODE_AL */\r
+ 10, /* EA_MODE_PCDI */\r
+ 14, /* EA_MODE_PCIX */\r
+ 0, /* EA_MODE_I */\r
+};\r
+\r
+/* Extra cycles for MOVEM instruction (000, 010) */\r
+int g_movem_cycle_table[8] =\r
+{\r
+ 0, /* EA_MODE_AI */\r
+ 4, /* EA_MODE_DI */\r
+ 6, /* EA_MODE_IX */\r
+ 4, /* EA_MODE_AW */\r
+ 8, /* EA_MODE_AL */\r
+ 0, /* EA_MODE_PCDI */\r
+ 0, /* EA_MODE_PCIX */\r
+ 0, /* EA_MODE_I */\r
+};\r
+\r
+// add nonstandard EA\r
+int Ea_add_ns(int *tab, int ea)\r
+{\r
+ if(ea<0x10) return 0;\r
+ if((ea&0x38)==0x10) return tab[0]; // (An) (ai)\r
+ if(ea<0x28) return 0;\r
+ if(ea<0x30) return tab[1]; // ($nn,An) (di)\r
+ if(ea<0x38) return tab[2]; // ($nn,An,Rn) (ix)\r
+ if(ea==0x38) return tab[3]; // (aw)\r
+ if(ea==0x39) return tab[4]; // (al)\r
+ if(ea==0x3a) return tab[5]; // ($nn,PC) (pcdi)\r
+ if(ea==0x3b) return tab[6]; // ($nn,pc,Rn) (pcix)\r
+ if(ea==0x3c) return tab[7]; // #$nnnn (i)\r
+ return 0;\r
+}\r
+\r
+\r
// ---------------------------------------------------------------------------\r
// Gets the offset of a register for an ea, and puts it in 'r'\r
// Shifted left by 'shift'\r
// Doesn't trash anything\r
-static int EaCalcReg(int r,int ea,int mask,int forceor,int shift)\r
+static int EaCalcReg(int r,int ea,int mask,int forceor,int shift,int noshift=0)\r
{\r
int i=0,low=0,needor=0;\r
int lsl=0;\r
for (i=mask|0x8000; (i&1)==0; i>>=1) low++; // Find out how high up the EA mask is\r
mask&=0xf<<low; // This is the max we can do\r
\r
- if (ea>=8) needor=1; // Need to OR to access A0-7\r
-\r
- if ((mask>>low)&8) if (ea&8) needor=0; // Ah - no we don't actually need to or, since the bit is high in r8\r
-\r
- if (forceor) needor=1; // Special case for 0x30-0x38 EAs ;)\r
+ if (ea>=8)\r
+ {\r
+ needor=1; // Need to OR to access A0-7\r
+ if ((g_op>>low)&8) { needor=0; mask|=8<<low; } // Ah - no we don't actually need to or, since the bit is high in r8\r
+ if (forceor) needor=1; // Special case for 0x30-0x38 EAs ;)\r
+ }\r
\r
ot(" and r%d,r8,#0x%.4x\n",r,mask);\r
+ if (needor) ot(" orr r%d,r%d,#0x%x ;@ A0-7\n",r,r,8<<low);\r
\r
// Find out amount to shift left:\r
lsl=shift-low;\r
\r
- if (lsl)\r
+ if (lsl&&!noshift)\r
{\r
ot(" mov r%d,r%d,",r,r);\r
if (lsl>0) ot("lsl #%d\n", lsl);\r
else ot("lsr #%d\n",-lsl);\r
}\r
\r
- if (needor) ot(" orr r%d,r%d,#0x%x ;@ A0-7\n",r,r,8<<shift);\r
return 0;\r
}\r
\r
// EaCalc - ARM Register 'a' = Effective Address\r
-// Trashes r0,r2 and r3\r
-int EaCalc(int a,int mask,int ea,int size)\r
+// If ea>=0x10, trashes r0,r2 and r3, else nothing\r
+// size values 0, 1, 2 ~ byte, word, long\r
+// mask shows usable bits in r8\r
+int EaCalc(int a,int mask,int ea,int size,int top,int sign_extend)\r
{\r
char text[32]="";\r
int func=0;\r
\r
if (ea<0x10)\r
{\r
- int lsl=2;\r
- if (size>=2) lsl=0; // Saves one opcode\r
+ int noshift=0;\r
+ if (size>=2||(size==0&&(top||!sign_extend))) noshift=1; // Saves one opcode\r
\r
ot(";@ EaCalc : Get register index into r%d:\n",a);\r
\r
- EaCalcReg(a,ea,mask,0,lsl);\r
+ EaCalcReg(a,ea,mask,0,2,noshift);\r
return 0;\r
}\r
- \r
+\r
ot(";@ EaCalc : Get '%s' into r%d:\n",text,a);\r
- // (An), (An)+, -(An):\r
+ // (An), (An)+, -(An)\r
if (ea<0x28)\r
{\r
- int step=1<<size;\r
+ int step=1<<size, strr=a;\r
+ int low=0,lsl=0,i;\r
\r
if ((ea&7)==7 && step<2) step=2; // move.b (a7)+ or -(a7) steps by 2 not 1\r
\r
- EaCalcReg(2,ea,mask,0,2);\r
- ot(" ldr r%d,[r7,r2]\n",a);\r
+ if (ea==0x1f||ea==0x27) // A7 handlers are always separate\r
+ {\r
+ ot(" ldr r%d,[r7,#0x3c] ;@ A7\n",a);\r
+ }\r
+ else\r
+ {\r
+ EaCalcReg(2,ea,mask,0,0,1);\r
+ if(mask)\r
+ for (i=mask|0x8000; (i&1)==0; i>>=1) low++; // Find out how high up the EA mask is\r
+ lsl=2-low; // Having a lsl #x here saves one opcode\r
+ if (lsl>=0) ot(" ldr r%d,[r7,r2,lsl #%i]\n",a,lsl);\r
+ else if (lsl<0) ot(" ldr r%d,[r7,r2,lsr #%i]\n",a,-lsl);\r
+ }\r
\r
- if ((ea&0x38)==0x18)\r
+ if ((ea&0x38)==0x18) // (An)+\r
{\r
ot(" add r3,r%d,#%d ;@ Post-increment An\n",a,step);\r
- ot(" str r3,[r7,r2]\n");\r
+ strr=3;\r
}\r
\r
- if ((ea&0x38)==0x20)\r
- {\r
+ if ((ea&0x38)==0x20) // -(An)\r
ot(" sub r%d,r%d,#%d ;@ Pre-decrement An\n",a,a,step);\r
- ot(" str r%d,[r7,r2]\n",a);\r
+\r
+ if ((ea&0x38)==0x18||(ea&0x38)==0x20)\r
+ {\r
+ if (ea==0x1f||ea==0x27)\r
+ {\r
+ ot(" str r%d,[r7,#0x3c] ;@ A7\n",strr);\r
+ }\r
+ else\r
+ {\r
+ if (lsl>=0) ot(" str r%d,[r7,r2,lsl #%i]\n",strr,lsl);\r
+ else if (lsl<0) ot(" str r%d,[r7,r2,lsr #%i]\n",strr,-lsl);\r
+ }\r
}\r
\r
if ((ea&0x38)==0x20) Cycles+=size<2 ? 6:10; // -(An) Extra cycles\r
return 0;\r
}\r
\r
- if (ea<0x30) // ($nn,An)\r
+ if (ea<0x30) // ($nn,An) (di)\r
{\r
- EaCalcReg(2,8,mask,0,2);\r
- ot(" ldr r2,[r7,r2]\n");\r
- ot(" ldrsh r0,[r4],#2 ;@ Fetch offset\n");\r
+ ot(" ldrsh r0,[r4],#2 ;@ Fetch offset\n"); pc_dirty=1;\r
+ EaCalcReg(2,8,mask,0,0);\r
+ ot(" ldr r2,[r7,r2,lsl #2]\n");\r
ot(" add r%d,r0,r2 ;@ Add on offset\n",a);\r
Cycles+=size<2 ? 8:12; // Extra cycles\r
return 0;\r
}\r
\r
- if (ea<0x38) // ($nn,An,Rn)\r
+ if (ea<0x38) // ($nn,An,Rn) (ix)\r
{\r
ot(";@ Get extension word into r3:\n");\r
- ot(" ldrh r3,[r4],#2 ;@ ($Disp,PC,Rn)\n");\r
+ ot(" ldrh r3,[r4],#2 ;@ ($Disp,PC,Rn)\n"); pc_dirty=1;\r
ot(" mov r2,r3,lsr #10\n");\r
ot(" tst r3,#0x0800 ;@ Is Rn Word or Long\n");\r
ot(" and r2,r2,#0x3c ;@ r2=Index of Rn\n");\r
- ot(" mov r0,r3,asl #24 ;@ r0=Get 8-bit signed Disp\n");\r
ot(" ldreqsh r2,[r7,r2] ;@ r2=Rn.w\n");\r
ot(" ldrne r2,[r7,r2] ;@ r2=Rn.l\n");\r
+ ot(" mov r0,r3,asl #24 ;@ r0=Get 8-bit signed Disp\n");\r
ot(" add r3,r2,r0,asr #24 ;@ r3=Disp+Rn\n");\r
\r
- EaCalcReg(2,8,mask,1,2);\r
- ot(" ldr r2,[r7,r2]\n");\r
+ EaCalcReg(2,8,mask,1,0);\r
+ ot(" ldr r2,[r7,r2,lsl #2]\n");\r
ot(" add r%d,r2,r3 ;@ r%d=Disp+An+Rn\n",a,a);\r
Cycles+=size<2 ? 10:14; // Extra cycles\r
return 0;\r
}\r
\r
- if (ea==0x38)\r
+ if (ea==0x38) // (aw)\r
{\r
- ot(" ldrsh r%d,[r4],#2 ;@ Fetch Absolute Short address\n",a);\r
+ ot(" ldrsh r%d,[r4],#2 ;@ Fetch Absolute Short address\n",a); pc_dirty=1;\r
Cycles+=size<2 ? 8:12; // Extra cycles\r
return 0;\r
}\r
\r
- if (ea==0x39)\r
+ if (ea==0x39) // (al)\r
{\r
ot(" ldrh r2,[r4],#2 ;@ Fetch Absolute Long address\n");\r
- ot(" ldrh r0,[r4],#2\n");\r
+ ot(" ldrh r0,[r4],#2\n"); pc_dirty=1;\r
ot(" orr r%d,r0,r2,lsl #16\n",a);\r
Cycles+=size<2 ? 12:16; // Extra cycles\r
return 0;\r
}\r
\r
- if (ea==0x3a)\r
+ if (ea==0x3a) // ($nn,PC) (pcdi)\r
{\r
ot(" ldr r0,[r7,#0x60] ;@ Get Memory base\n");\r
ot(" sub r0,r4,r0 ;@ Real PC\n");\r
- ot(" ldrsh r2,[r4],#2 ;@ Fetch extension\n");\r
- ot(" add r%d,r0,r2 ;@ ($nn,PC)\n",a);\r
+ ot(" ldrsh r2,[r4],#2 ;@ Fetch extension\n"); pc_dirty=1;\r
+ ot(" mov r0,r0,lsl #8\n");\r
+ ot(" add r%d,r2,r0,asr #8 ;@ ($nn,PC)\n",a);\r
Cycles+=size<2 ? 8:12; // Extra cycles\r
return 0;\r
}\r
\r
- if (ea==0x3b) // ($nn,pc,Rn)\r
+ if (ea==0x3b) // ($nn,pc,Rn) (pcix)\r
{\r
- ot(";@ Get extension word into r3:\n");\r
- ot(" ldrh r3,[r4]\n");\r
+ ot(" ldr r0,[r7,#0x60] ;@ Get Memory base\n");\r
+ ot(" ldrh r3,[r4] ;@ Get extension word\n");\r
+ ot(" sub r0,r4,r0 ;@ r0=PC\n");\r
+ ot(" add r4,r4,#2\n"); pc_dirty=1;\r
+ ot(" mov r0,r0,asl #8 ;@ use only 24bits of PC\n");\r
ot(" mov r2,r3,lsr #10\n");\r
ot(" tst r3,#0x0800 ;@ Is Rn Word or Long\n");\r
ot(" and r2,r2,#0x3c ;@ r2=Index of Rn\n");\r
- ot(" mov r0,r3,asl #24 ;@ r0=Get 8-bit signed Disp\n");\r
ot(" ldreqsh r2,[r7,r2] ;@ r2=Rn.w\n");\r
ot(" ldrne r2,[r7,r2] ;@ r2=Rn.l\n");\r
- ot(" add r2,r2,r0,asr #24 ;@ r2=Disp+Rn\n");\r
- ot(" ldr r0,[r7,#0x60] ;@ Get Memory base\n");\r
- ot(" add r2,r2,r4 ;@ r2=Disp+Rn + Base+PC\n");\r
- ot(" add r4,r4,#2 ;@ Increase PC\n");\r
- ot(" sub r%d,r2,r0 ;@ r%d=Disp+PC+Rn\n",a,a);\r
+ ot(" mov r3,r3,asl #24 ;@ r3=Get 8-bit signed Disp\n");\r
+ ot(" add r2,r2,r3,asr #24 ;@ r2=Disp+Rn\n");\r
+ ot(" add r%d,r2,r0,asr #8 ;@ r%d=Disp+PC+Rn\n",a,a);\r
Cycles+=size<2 ? 10:14; // Extra cycles\r
return 0;\r
}\r
\r
- if (ea==0x3c)\r
+ if (ea==0x3c) // #$nnnn (i)\r
{\r
if (size<2)\r
{\r
- ot(" ldr%s r%d,[r4],#2 ;@ Fetch immediate value\n",Sarm[size&3],a);\r
+ ot(" ldr%s r%d,[r4],#2 ;@ Fetch immediate value\n",Sarm[size&3],a); pc_dirty=1;\r
Cycles+=4; // Extra cycles\r
return 0;\r
}\r
\r
ot(" ldrh r2,[r4],#2 ;@ Fetch immediate value\n");\r
- ot(" ldrh r0,[r4],#2\n");\r
- ot(" orr r%d,r0,r2,lsl #16\n",a);\r
+ ot(" ldrh r3,[r4],#2\n"); pc_dirty=1;\r
+ ot(" orr r%d,r3,r2,lsl #16\n",a);\r
Cycles+=8; // Extra cycles\r
return 0;\r
}\r
// Read effective address in (ARM Register 'a') to ARM register 'v'\r
// 'a' and 'v' can be anything but 0 is generally best (for both)\r
// If (ea<0x10) nothing is trashed, else r0-r3 is trashed\r
-// If 'top' is 1, the ARM register v shifted to the top, e.g. 0xc000 -> 0xc0000000\r
-// Otherwise the ARM register v is sign extended, e.g. 0xc000 -> 0xffffc000\r
+// If 'top' is given, the ARM register v shifted to the top, e.g. 0xc000 -> 0xc0000000\r
+// If top is 0 and sign_extend is not, then ARM register v is sign extended,\r
+// e.g. 0xc000 -> 0xffffc000 (else it may or may not be sign extended)\r
\r
-int EaRead(int a,int v,int ea,int size,int top)\r
+int EaRead(int a,int v,int ea,int size,int mask,int top,int sign_extend)\r
{\r
char text[32]="";\r
int shift=0;\r
- \r
+\r
shift=32-(8<<size);\r
\r
DisaPc=2; DisaGetEa(text,ea,size); // Get text version of the effective address\r
\r
if (ea<0x10)\r
{\r
- int lsl=2;\r
- if (size>=2) lsl=0; // Having a lsl #2 here saves one opcode\r
+ int lsl=0,low=0,nsarm=size&3,i;\r
+ if (size>=2||(size==0&&(top||!sign_extend))) {\r
+ if(mask)\r
+ for (i=mask|0x8000; (i&1)==0; i>>=1) low++; // Find out how high up the EA mask is\r
+ lsl=2-low; // Having a lsl #2 here saves one opcode\r
+ }\r
+\r
+ if (top||!sign_extend) nsarm=3;\r
\r
ot(";@ EaRead : Read register[r%d] into r%d:\n",a,v);\r
\r
- if (lsl==0) ot(" ldr r%d,[r7,r%d,lsl #2]\n",v,a);\r
- else ot(" ldr%s r%d,[r7,r%d]\n",Sarm[size&3],v,a);\r
+ if (lsl>0) ot(" ldr%s r%d,[r7,r%d,lsl #%i]\n",Narm[nsarm],v,a,lsl);\r
+ else if (lsl<0) ot(" ldr%s r%d,[r7,r%d,lsr #%i]\n",Narm[nsarm],v,a,-lsl);\r
+ else ot(" ldr%s r%d,[r7,r%d]\n",Sarm[nsarm],v,a);\r
\r
- if (top && shift) ot(" mov r%d,r%d,asl #%d\n",v,v,shift);\r
+ if (top&&shift) ot(" mov r%d,r%d,asl #%d\n",v,v,shift);\r
\r
ot("\n"); return 0;\r
}\r
\r
if (top) asl=shift;\r
\r
- if (v!=a || asl) ot(" mov r%d,r%d,asl #%d\n",v,a,asl);\r
+ if (asl) ot(" mov r%d,r%d,asl #%d\n",v,a,asl);\r
+ else if (v!=a) ot(" mov r%d,r%d\n",v,a);\r
ot("\n"); return 0;\r
}\r
\r
- if (a!=0) ot(" mov r0,r%d\n",a);\r
+ if (ea>=0x3a && ea<=0x3b) MemHandler(2,size,a,earead_check_addrerr); // Fetch\r
+ else MemHandler(0,size,a,earead_check_addrerr); // Read\r
\r
- if (ea>=0x3a && ea<=0x3b) MemHandler(2,size); // Fetch\r
- else MemHandler(0,size); // Read\r
+ // defaults to 1, as most things begins with a read\r
+ earead_check_addrerr=1;\r
\r
- if (v!=0 || shift) ot(" mov r%d,r0,asl #%d\n",v,shift);\r
- if (top==0 && shift) ot(" mov r%d,r%d,asr #%d\n",v,v,shift);\r
+ if (sign_extend)\r
+ {\r
+ int d_reg=0;\r
+ if (shift) {\r
+ ot(" mov r%d,r%d,asl #%d\n",v,d_reg,shift);\r
+ d_reg=v;\r
+ }\r
+ if (!top && shift) {\r
+ ot(" mov r%d,r%d,asr #%d\n",v,d_reg,shift);\r
+ d_reg=v;\r
+ }\r
+ if (d_reg != v)\r
+ ot(" mov r%d,r%d\n",v,d_reg);\r
+ }\r
+ else\r
+ {\r
+ if (top && shift)\r
+ ot(" mov r%d,r0,asl #%d\n",v,shift);\r
+ else if (v!=0)\r
+ ot(" mov r%d,r0\n",v);\r
+ }\r
\r
ot("\n"); return 0;\r
}\r
\r
+// calculate EA and read\r
+// if (ea < 0x10) nothing is trashed\r
+// if (ea == 0x3c) r2 and r3 are trashed\r
+// else r0-r3 are trashed\r
+// size values 0, 1, 2 ~ byte, word, long\r
+// r_ea is reg to store ea in (-1 means ea is not needed), r is dst reg\r
+// if sign_extend is 0, non-32bit values will have MS bits undefined\r
+int EaCalcRead(int r_ea,int r,int ea,int size,int mask,int sign_extend)\r
+{\r
+ if (ea<0x10)\r
+ {\r
+ if (r_ea==-1)\r
+ {\r
+ r_ea=r;\r
+ if (!sign_extend) size=2;\r
+ }\r
+ }\r
+ else if (ea==0x3c) // #imm\r
+ {\r
+ r_ea=r;\r
+ }\r
+ else\r
+ {\r
+ if (r_ea==-1) r_ea=0;\r
+ }\r
+\r
+ EaCalc (r_ea,mask,ea,size,0,sign_extend);\r
+ EaRead (r_ea, r,ea,size,mask,0,sign_extend);\r
+\r
+ return 0;\r
+}\r
+\r
+int EaCalcReadNoSE(int r_ea,int r,int ea,int size,int mask)\r
+{\r
+ return EaCalcRead(r_ea,r,ea,size,mask,0);\r
+}\r
+\r
// Return 1 if we can read this ea\r
int EaCanRead(int ea,int size)\r
{\r
{\r
// LEA:\r
// These don't make sense?:\r
- if (ea<0x10) return 0; // Register\r
+ if (ea< 0x10) return 0; // Register\r
if (ea==0x3c) return 0; // Immediate\r
if (ea>=0x18 && ea<0x28) return 0; // Pre/Post inc/dec An\r
}\r
\r
// ---------------------------------------------------------------------------\r
// Write effective address (ARM Register 'a') with ARM register 'v'\r
-// Trashes r0-r3, 'a' can be 0 or 2+, 'v' can be 1 or higher\r
+// Trashes r0-r3,r12,lr; 'a' can be 0 or 2+, 'v' can be 1 or higher\r
// If a==0 and v==1 it's faster though.\r
-int EaWrite(int a,int v,int ea,int size,int top)\r
+int EaWrite(int a,int v,int ea,int size,int mask,int top,int sign_extend_ea)\r
{\r
char text[32]="";\r
int shift=0;\r
\r
+ if(a == 1) { printf("Error! EaWrite a==1 !\n"); return 1; }\r
+\r
if (top) shift=32-(8<<size);\r
\r
DisaPc=2; DisaGetEa(text,ea,size); // Get text version of the effective address\r
\r
if (ea<0x10)\r
{\r
- int lsl=2;\r
- if (size>=2) lsl=0; // Having a lsl #2 here saves one opcode\r
+ int lsl=0,low=0,i;\r
+ if (size>=2||(size==0&&(top||!sign_extend_ea))) {\r
+ if(mask)\r
+ for (i=mask|0x8000; (i&1)==0; i>>=1) low++; // Find out how high up the EA mask is\r
+ lsl=2-low; // Having a lsl #x here saves one opcode\r
+ }\r
\r
ot(";@ EaWrite: r%d into register[r%d]:\n",v,a);\r
- if (shift) ot(" mov r%d,r%d,asr #%d\n",v,v,shift);\r
+ if (shift) ot(" mov r%d,r%d,asr #%d\n",v,v,shift);\r
\r
- if (lsl==0) ot(" str r%d,[r7,r%d,lsl #2]\n",v,a);\r
- else ot(" str%s r%d,[r7,r%d]\n",Narm[size&3],v,a);\r
+ if (lsl>0) ot(" str%s r%d,[r7,r%d,lsl #%i]\n",Narm[size&3],v,a,lsl);\r
+ else if (lsl<0) ot(" str%s r%d,[r7,r%d,lsr #%i]\n",Narm[size&3],v,a,-lsl);\r
+ else ot(" str%s r%d,[r7,r%d]\n",Narm[size&3],v,a);\r
\r
ot("\n"); return 0;\r
}\r
\r
if (ea==0x3c) { ot("Error! Write EA=0x%x\n\n",ea); return 1; }\r
\r
- if (a!=0 && v!=0) ot(" mov r0,r%d\n",a);\r
- if (v!=1 || shift) ot(" mov r1,r%d,asr #%d\n",v,shift);\r
- if (a!=0 && v==0) ot(" mov r0,r%d\n",a);\r
+ if (shift) ot(" mov r1,r%d,asr #%d\n",v,shift);\r
+ else if (v!=1) ot(" mov r1,r%d\n",v);\r
\r
- MemHandler(1,size); // Call write handler\r
+ MemHandler(1,size,a,eawrite_check_addrerr); // Call write handler\r
+\r
+ // not check by default, because most cases are rmw and\r
+ // address was already checked before reading\r
+ eawrite_check_addrerr = 0;\r
\r
ot("\n"); return 0;\r
}\r
// Return 1 if we can write this ea\r
int EaCanWrite(int ea)\r
{\r
- if (ea<=0x3b) return 1;\r
+ if (ea<=0x39) return 1; // 3b?\r
return 0;\r
}\r
// ---------------------------------------------------------------------------\r
+\r
+// Return 1 if EA is An reg\r
+int EaAn(int ea)\r
+{\r
+ if((ea&0x38)==8) return 1;\r
+ return 0;\r
+}\r
+\r
\r
// This file is part of the Cyclone 68000 Emulator\r
\r
-// Copyright (c) 2011 FinalDave (emudave (at) gmail.com)\r
+// Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)\r
+// Copyright (c) 2005-2011 Gražvydas "notaz" Ignotas (notasas (at) gmail.com)\r
\r
// This code is licensed under the GNU General Public License version 2.0 and the MAME License.\r
// You can choose the license that has the most advantages for you.\r
\r
// SVN repository can be found at http://code.google.com/p/cyclone68000/\r
\r
+\r
#include "app.h"\r
\r
static FILE *AsmFile=NULL;\r
\r
-static int CycloneVer=0x0069; // Version number of library\r
+static int CycloneVer=0x0099; // Version number of library\r
int *CyJump=NULL; // Jump table\r
-int ms=0; // If non-zero, output in Microsoft ARMASM format\r
-char *Narm[4]={ "b", "h","",""}; // Normal ARM Extensions for operand sizes 0,1,2\r
-char *Sarm[4]={"sb","sh","",""}; // Sign-extend ARM Extensions for operand sizes 0,1,2\r
-int Cycles=0; // Current cycles for opcode\r
-int Amatch=1; // If one, try to match A68K timing\r
-int Accu=-1; // Accuracy\r
-int Debug=0; // Debug info\r
+int ms=USE_MS_SYNTAX; // If non-zero, output in Microsoft ARMASM format\r
+const char * const Narm[4]={ "b", "h","",""}; // Normal ARM Extensions for operand sizes 0,1,2\r
+const char * const Sarm[4]={"sb","sh","",""}; // Sign-extend ARM Extensions for operand sizes 0,1,2\r
+int Cycles; // Current cycles for opcode\r
+int pc_dirty; // something changed PC during processing\r
+int arm_op_count;\r
+\r
+// opcodes often used by games\r
+static const unsigned short hot_opcodes[] = {\r
+ 0x6701, // beq $3\r
+ 0x6601, // bne $3\r
+ 0x51c8, // dbra Dn, $2\r
+ 0x4a38, // tst.b $0.w\r
+ 0xd040, // add.w Dn, Dn\r
+ 0x4a79, // tst.w $0.l\r
+ 0x0240, // andi.w #$0, D0\r
+ 0x2038, // move.l $0.w, D0\r
+ 0xb0b8, // cmp.l $0.w, D0\r
+ 0x6001, // bra $3\r
+ 0x30c0, // move.w D0, (A0)+\r
+ 0x3028, // move.w ($0,A0), D0\r
+ 0x0c40, // cmpi.w #$0, D0\r
+ 0x0c79, // cmpi.w #$0, $0.l\r
+ 0x4e75, // rts\r
+ 0x4e71, // nop\r
+ 0x3000, // move.w D0, D0\r
+ 0x0839, // btst #$0, $0.l\r
+ 0x7000, // moveq #$0, D0\r
+ 0x3040, // movea.w D0, A0\r
+ 0x0838, // btst #$0, $0.w\r
+ 0x4a39, // tst.b $0.l\r
+ 0x33d8, // move.w (A0)+, $0.l\r
+ 0x6700, // beq $2\r
+ 0xb038, // cmp.b $0.w, D0\r
+ 0x3039, // move.w $0.l, D0\r
+ 0x4840, // swap D0\r
+ 0x6101, // bsr $3\r
+ 0x6100, // bsr $2\r
+ 0x5e40, // addq.w #7, D0\r
+ 0x1039, // move.b $0.l, D0\r
+ 0x20c0, // move.l D0, (A0)+\r
+ 0x1018, // move.b (A0)+, D0\r
+ 0x30d0, // move.w (A0), (A0)+\r
+ 0x3080, // move.w D0, (A0)\r
+ 0x3018, // move.w (A0)+, D0\r
+ 0xc040, // and.w D0, D0\r
+ 0x3180, // move.w D0, (A0,D0.w)\r
+ 0x1198, // move.b (A0)+, (A0,D0.w)\r
+ 0x6501, // bcs $3\r
+ 0x6500, // bcs $2\r
+ 0x6401, // bcc $3\r
+ 0x6a01, // bpl $3\r
+ 0x41f0, // lea (A0,D0.w), A0\r
+ 0x4a28, // tst.b ($0,A0)\r
+ 0x0828, // btst #$0, ($0,A0)\r
+ 0x0640, // addi.w #$0, D0\r
+ 0x10c0, // move.b D0, (A0)+\r
+ 0x10d8, // move.b (A0)+, (A0)+\r
+};\r
+#define hot_opcode_count (int)(sizeof(hot_opcodes) / sizeof(hot_opcodes[0]))\r
+\r
+static int is_op_hot(int op)\r
+{\r
+ int i;\r
+ for (i = 0; i < hot_opcode_count; i++)\r
+ if (op == hot_opcodes[i])\r
+ return 1;\r
+ return 0;\r
+}\r
\r
void ot(const char *format, ...)\r
{\r
va_list valist;\r
+ int i, len;\r
+\r
+ // notaz: stop me from leaving newlines in the middle of format string\r
+ // and generating bad code\r
+ for(i=0, len=strlen(format); i < len && format[i] != '\n'; i++);\r
+ if(i < len-1 && format[len-1] != '\n') printf("\nWARNING: possible improper newline placement:\n%s\n", format);\r
+\r
+ if (format[0] == ' ' && format[1] == ' ' && format[2] != ' ' && format[2] != '.')\r
+ arm_op_count++;\r
+\r
va_start(valist,format);\r
if (AsmFile) vfprintf(AsmFile,format,valist);\r
va_end(valist);\r
else ot(" .ltorg\n");\r
}\r
\r
-static void PrintException()\r
+#if (CYCLONE_FOR_GENESIS == 2)\r
+// r12=ptr to tas in table, trashes r0,r1\r
+static void ChangeTAS(int norm)\r
{\r
- ot(" ;@ Cause an Exception - Vector in [r7,#0x50]\n");\r
- ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
- ot(" sub r1,r4,r10 ;@ r1 = Old PC\n");\r
- OpPush32();\r
- OpPushSr(1);\r
- ot(" ldr r0,[r7,#0x50] ;@ Get Vector\n");\r
- ot(";@ Read IRQ Vector:\n");\r
- MemHandler(0,2);\r
- ot(" add r0,r0,r10 ;@ r0 = Memory Base + New PC\n");\r
- ot(" mov lr,pc\n");\r
- ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
- ot(" mov r4,r0\n");\r
- ot("\n");\r
-\r
- // todo - make Interrupt code use this function as well\r
+ ot(" ldr r0,=Op4ad0%s\n",norm?"_":"");\r
+ ot(" mov r1,#8\n");\r
+ ot("setrtas_loop%i0%s ;@ 4ad0-4ad7\n",norm,ms?"":":");\r
+ ot(" subs r1,r1,#1\n");\r
+ ot(" str r0,[r12],#4\n");\r
+ ot(" bne setrtas_loop%i0\n",norm);\r
+ ot(" ldr r0,=Op4ad8%s\n",norm?"_":"");\r
+ ot(" mov r1,#7\n");\r
+ ot("setrtas_loop%i1%s ;@ 4ad8-4ade\n",norm,ms?"":":");\r
+ ot(" subs r1,r1,#1\n");\r
+ ot(" str r0,[r12],#4\n");\r
+ ot(" bne setrtas_loop%i1\n",norm);\r
+ ot(" ldr r0,=Op4adf%s\n",norm?"_":"");\r
+ ot(" str r0,[r12],#4\n");\r
+ ot(" ldr r0,=Op4ae0%s\n",norm?"_":"");\r
+ ot(" mov r1,#7\n");\r
+ ot("setrtas_loop%i2%s ;@ 4ae0-4ae6\n",norm,ms?"":":");\r
+ ot(" subs r1,r1,#1\n");\r
+ ot(" str r0,[r12],#4\n");\r
+ ot(" bne setrtas_loop%i2\n",norm);\r
+ ot(" ldr r0,=Op4ae7%s\n",norm?"_":"");\r
+ ot(" str r0,[r12],#4\n");\r
+ ot(" ldr r0,=Op4ae8%s\n",norm?"_":"");\r
+ ot(" mov r1,#8\n");\r
+ ot("setrtas_loop%i3%s ;@ 4ae8-4aef\n",norm,ms?"":":");\r
+ ot(" subs r1,r1,#1\n");\r
+ ot(" str r0,[r12],#4\n");\r
+ ot(" bne setrtas_loop%i3\n",norm);\r
+ ot(" ldr r0,=Op4af0%s\n",norm?"_":"");\r
+ ot(" mov r1,#8\n");\r
+ ot("setrtas_loop%i4%s ;@ 4af0-4af7\n",norm,ms?"":":");\r
+ ot(" subs r1,r1,#1\n");\r
+ ot(" str r0,[r12],#4\n");\r
+ ot(" bne setrtas_loop%i4\n",norm);\r
+ ot(" ldr r0,=Op4af8%s\n",norm?"_":"");\r
+ ot(" str r0,[r12],#4\n");\r
+ ot(" ldr r0,=Op4af9%s\n",norm?"_":"");\r
+ ot(" str r0,[r12],#4\n");\r
}\r
+#endif\r
\r
-// Trashes r0\r
-void CheckInterrupt()\r
+#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
+static void AddressErrorWrapper(char rw, const char *dataprg, int iw)\r
{\r
- ot(";@ CheckInterrupt:\n");\r
- ot(" ldrb r0,[r7,#0x47] ;@ Get IRQ level\n");\r
- ot(" tst r0,r0\n");\r
- ot(" blne DoInterrupt\n");\r
+ ot("ExceptionAddressError_%c_%s%s\n", rw, dataprg, ms?"":":");\r
+ ot(" ldr r1,[r7,#0x44]\n");\r
+ ot(" mov r6,#0x%02x\n", iw);\r
+ ot(" mov r11,r0\n");\r
+ ot(" tst r1,#0x20\n");\r
+ ot(" orrne r6,r6,#4\n");\r
+ ot(" b ExceptionAddressError\n");\r
ot("\n");\r
}\r
+#endif\r
+\r
+void FlushPC(void)\r
+{\r
+#if MEMHANDLERS_NEED_PC\r
+ if (pc_dirty)\r
+ ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
+#endif\r
+ pc_dirty = 0;\r
+}\r
\r
static void PrintFramework()\r
{\r
+ int state_flags_to_check = 1; // stopped\r
+#if EMULATE_TRACE\r
+ state_flags_to_check |= 2; // tracing\r
+#endif\r
+#if EMULATE_HALT\r
+ state_flags_to_check |= 0x10; // halted\r
+#endif\r
+\r
ot(";@ --------------------------- Framework --------------------------\n");\r
if (ms) ot("CycloneRun\n");\r
else ot("CycloneRun:\n");\r
\r
- ot(" stmdb sp!,{r4-r11,lr}\n");\r
+ ot(" stmdb sp!,{r4-r8,r10,r11,lr}\n");\r
\r
ot(" mov r7,r0 ;@ r7 = Pointer to Cpu Context\n");\r
ot(" ;@ r0-3 = Temporary registers\n");\r
- ot(" ldrb r9,[r7,#0x46] ;@ r9 = Flags (NZCV)\n");\r
- ot(" ldr r6,=JumpTab ;@ r6 = Opcode Jump table\n");\r
+ ot(" ldrb r10,[r7,#0x46] ;@ r10 = Flags (NZCV)\n");\r
+ ot(" ldr r6,=CycloneJumpTab ;@ r6 = Opcode Jump table\n");\r
ot(" ldr r5,[r7,#0x5c] ;@ r5 = Cycles\n");\r
ot(" ldr r4,[r7,#0x40] ;@ r4 = Current PC + Memory Base\n");\r
ot(" ;@ r8 = Current Opcode\n");\r
- ot(" mov r9,r9,lsl #28 ;@ r9 = Flags 0xf0000000, cpsr format\n");\r
- ot(" ;@ r10 = Source value / Memory Base\n");\r
+ ot(" ldr r1,[r7,#0x44] ;@ Get SR high T_S__III and irq level\n");\r
+ ot(" mov r10,r10,lsl #28;@ r10 = Flags 0xf0000000, cpsr format\n");\r
+ ot(" ;@ r11 = Source value / Memory Base\n");\r
+ ot(" str r6,[r7,#0x54] ;@ make a copy to avoid literal pools\n");\r
+ ot("\n");\r
+#if (CYCLONE_FOR_GENESIS == 2) || EMULATE_TRACE\r
+ ot(" mov r2,#0\n");\r
+ ot(" str r2,[r7,#0x98] ;@ clear custom CycloneEnd\n");\r
+#endif\r
+ ot(";@ CheckInterrupt:\n");\r
+ ot(" movs r0,r1,lsr #24 ;@ Get IRQ level\n"); // same as ldrb r0,[r7,#0x47]\r
+ ot(" beq NoInts0\n");\r
+ ot(" cmp r0,#6 ;@ irq>6 ?\n");\r
+ ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");\r
+ ot(" cmple r0,r1 ;@ irq<=6: Is irq<=mask ?\n");\r
+ ot(" bgt CycloneDoInterrupt\n");\r
+ ot("NoInts0%s\n", ms?"":":");\r
+ ot("\n");\r
+ ot(";@ Check if our processor is in special state\n");\r
+ ot(";@ and jump to opcode handler if not\n");\r
+ ot(" ldr r0,[r7,#0x58] ;@ state_flags\n");\r
+ ot(" ldrh r8,[r4],#2 ;@ Fetch first opcode\n");\r
+ ot(" tst r0,#0x%02x ;@ special state?\n", state_flags_to_check);\r
+ ot(" ldreq pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
+ ot("\n");\r
+ ot("CycloneSpecial%s\n", ms?"":":");\r
+#if EMULATE_TRACE\r
+ ot(" tst r0,#2 ;@ tracing?\n");\r
+ ot(" bne CycloneDoTrace\n");\r
+#endif\r
+ ot(";@ stopped or halted\n");\r
+ ot(" mov r5,#0\n");\r
+ ot(" str r5,[r7,#0x5C] ;@ eat all cycles\n");\r
+ ot(" ldmia sp!,{r4-r8,r10,r11,pc} ;@ we are stopped, do nothing!\n");\r
ot("\n");\r
- CheckInterrupt();\r
- ot(";@ Check if interrupt used up all the cycles:\n");\r
- ot(" subs r5,r5,#0\n");\r
- ot(" blt CycloneEndNoBack\n");\r
-\r
- OpFirst();\r
- ltorg();\r
ot("\n");\r
\r
ot(";@ We come back here after execution\n");\r
ot("CycloneEnd%s\n", ms?"":":");\r
ot(" sub r4,r4,#2\n");\r
ot("CycloneEndNoBack%s\n", ms?"":":");\r
- ot(" mov r9,r9,lsr #28\n");\r
+#if (CYCLONE_FOR_GENESIS == 2) || EMULATE_TRACE\r
+ ot(" ldr r1,[r7,#0x98]\n");\r
+ ot(" mov r10,r10,lsr #28\n");\r
+ ot(" tst r1,r1\n");\r
+ ot(" bxne r1 ;@ jump to alternative CycloneEnd\n");\r
+#else\r
+ ot(" mov r10,r10,lsr #28\n");\r
+#endif\r
ot(" str r4,[r7,#0x40] ;@ Save Current PC + Memory Base\n");\r
ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
- ot(" strb r9,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
- ot(" ldmia sp!,{r4-r11,pc}\n");\r
+ ot(" strb r10,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
+ ot(" ldmia sp!,{r4-r8,r10,r11,pc}\n");\r
+ ltorg();\r
ot("\n");\r
-\r
- ot(";@ DoInterrupt - r0=IRQ number\n");\r
- ot("DoInterrupt%s\n", ms?"":":");\r
ot("\n");\r
- ot(" ldrb r1,[r7,#0x44] ;@ Get SR high: T_S__III\n");\r
- ot(" and r1,r1,#7 ;@ Get interrupt mask\n");\r
- ot(" cmp r0,#6 ;@ irq>6 ?\n");\r
- ot(" cmple r0,r1 ;@ irq<=6: Is irq<=mask ?\n");\r
- ot(" movle pc,lr ;@ irq<=6 and mask, not allowed\n");\r
+\r
+ ot("CycloneInit%s\n", ms?"":":");\r
+#if COMPRESS_JUMPTABLE\r
+ ot(";@ decompress jump table\n");\r
+ ot(" ldr r12,=CycloneJumpTab\n");\r
+ ot(" add r0,r12,#0xe000*4 ;@ ctrl code pointer\n");\r
+ ot(" ldr r1,[r0,#-4]\n");\r
+ ot(" tst r1,r1\n");\r
+ ot(" movne pc,lr ;@ already uncompressed\n");\r
+ ot(" add r3,r12,#0xa000*4 ;@ handler table pointer, r12=dest\n");\r
+ ot("unc_loop%s\n", ms?"":":");\r
+ ot(" ldrh r1,[r0],#2\n");\r
+ ot(" and r2,r1,#0xf\n");\r
+ ot(" bic r1,r1,#0xf\n");\r
+ ot(" ldr r1,[r3,r1,lsr #2] ;@ r1=handler\n");\r
+ ot(" cmp r2,#0xf\n");\r
+ ot(" addeq r2,r2,#1 ;@ 0xf is really 0x10\n");\r
+ ot(" tst r2,r2\n");\r
+ ot(" ldreqh r2,[r0],#2 ;@ counter is in next word\n");\r
+ ot(" tst r2,r2\n");\r
+ ot(" beq unc_finish ;@ done decompressing\n");\r
+ ot(" tst r1,r1\n");\r
+ ot(" addeq r12,r12,r2,lsl #2 ;@ 0 handler means we should skip those bytes\n");\r
+ ot(" beq unc_loop\n");\r
+ ot("unc_loop_in%s\n", ms?"":":");\r
+ ot(" subs r2,r2,#1\n");\r
+ ot(" str r1,[r12],#4\n");\r
+ ot(" bgt unc_loop_in\n");\r
+ ot(" b unc_loop\n");\r
+ ot("unc_finish%s\n", ms?"":":");\r
+ ot(" ldr r12,=CycloneJumpTab\n");\r
+ ot(" ;@ set a-line and f-line handlers\n");\r
+ ot(" add r0,r12,#0xa000*4\n");\r
+ ot(" ldr r1,[r0,#4] ;@ a-line handler\n");\r
+ ot(" ldr r3,[r0,#8] ;@ f-line handler\n");\r
+ ot(" mov r2,#0x1000\n");\r
+ ot("unc_fill3%s\n", ms?"":":");\r
+ ot(" subs r2,r2,#1\n");\r
+ ot(" str r1,[r0],#4\n");\r
+ ot(" bgt unc_fill3\n");\r
+ ot(" add r0,r12,#0xf000*4\n");\r
+ ot(" mov r2,#0x1000\n");\r
+ ot("unc_fill4%s\n", ms?"":":");\r
+ ot(" subs r2,r2,#1\n");\r
+ ot(" str r3,[r0],#4\n");\r
+ ot(" bgt unc_fill4\n");\r
+ ot(" bx lr\n");\r
+ ltorg();\r
+#else\r
+ ot(";@ do nothing\n");\r
+ ot(" bx lr\n");\r
+#endif\r
ot("\n");\r
- ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
- ot(" mov r11,lr ;@ Preserve ARM return address\n");\r
- ot(" sub r1,r4,r10 ;@ r1 = Old PC\n");\r
- OpPush32();\r
- OpPushSr(1);\r
- ot(";@ Get IRQ Vector address:\n");\r
- ot(" ldrb r1,[r7,#0x47] ;@ IRQ\n");\r
- ot(" mov r0,r1,asl #2\n");\r
- ot(" add r0,r0,#0x60\n");\r
- ot(";@ Read IRQ Vector:\n");\r
+\r
+ // --------------\r
+ ot("CycloneReset%s\n", ms?"":":");\r
+ ot(" stmfd sp!,{r7,lr}\n");\r
+ ot(" mov r7,r0\n");\r
+ ot(" mov r0,#0\n");\r
+ ot(" str r0,[r7,#0x58] ;@ state_flags\n");\r
+ ot(" str r0,[r7,#0x48] ;@ OSP\n");\r
+ ot(" mov r1,#0x27 ;@ Supervisor mode\n");\r
+ ot(" strb r1,[r7,#0x44] ;@ set SR high\n");\r
+ ot(" strb r0,[r7,#0x47] ;@ IRQ\n");\r
MemHandler(0,2);\r
- ot(" add r0,r0,r10 ;@ r0 = Memory Base + New PC\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Stack pointer\n");\r
+ ot(" mov r0,#0\n");\r
+ ot(" str r0,[r7,#0x60] ;@ Membase\n");\r
+ ot(" mov r0,#4\n");\r
+ MemHandler(0,2);\r
+#ifdef MEMHANDLERS_DIRECT_PREFIX\r
+ ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);\r
+#else\r
ot(" mov lr,pc\n");\r
ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
+#endif\r
+ ot(" str r0,[r7,#0x40] ;@ PC + base\n");\r
+ ot(" ldmfd sp!,{r7,pc}\n");\r
+ ot("\n");\r
+\r
+ // --------------\r
+ // 68k: XNZVC, ARM: NZCV\r
+ ot("CycloneSetSr%s\n", ms?"":":");\r
+ ot(" mov r2,r1,lsr #8\n");\r
+// ot(" ldrb r3,[r0,#0x44] ;@ get SR high\n");\r
+// ot(" eor r3,r3,r2\n");\r
+// ot(" tst r3,#0x20\n");\r
+#if EMULATE_TRACE\r
+ ot(" and r2,r2,#0xa7 ;@ only defined bits\n");\r
+#else\r
+ ot(" and r2,r2,#0x27 ;@ only defined bits\n");\r
+#endif\r
+ ot(" strb r2,[r0,#0x44] ;@ set SR high\n");\r
+ ot(" mov r2,r1,lsl #25\n");\r
+ ot(" str r2,[r0,#0x4c] ;@ the X flag\n");\r
+ ot(" bic r2,r1,#0xf3\n");\r
+ ot(" tst r1,#1\n");\r
+ ot(" orrne r2,r2,#2\n");\r
+ ot(" tst r1,#2\n");\r
+ ot(" orrne r2,r2,#1\n");\r
+ ot(" strb r2,[r0,#0x46] ;@ flags\n");\r
+ ot(" bx lr\n");\r
+ ot("\n");\r
+\r
+ // --------------\r
+ ot("CycloneGetSr%s\n", ms?"":":");\r
+ ot(" ldrb r1,[r0,#0x46] ;@ flags\n");\r
+ ot(" bic r2,r1,#0xf3\n");\r
+ ot(" tst r1,#1\n");\r
+ ot(" orrne r2,r2,#2\n");\r
+ ot(" tst r1,#2\n");\r
+ ot(" orrne r2,r2,#1\n");\r
+ ot(" ldr r1,[r0,#0x4c] ;@ the X flag\n");\r
+ ot(" tst r1,#0x20000000\n");\r
+ ot(" orrne r2,r2,#0x10\n");\r
+ ot(" ldrb r1,[r0,#0x44] ;@ the SR high\n");\r
+ ot(" orr r0,r2,r1,lsl #8\n");\r
+ ot(" bx lr\n");\r
+ ot("\n");\r
+\r
+ // --------------\r
+ ot("CyclonePack%s\n", ms?"":":");\r
+ ot(" stmfd sp!,{r4,r5,lr}\n");\r
ot(" mov r4,r0\n");\r
+ ot(" mov r5,r1\n");\r
+ ot(" mov r3,#16\n");\r
+ ot(";@ 0x00-0x3f: DA registers\n");\r
+ ot("c_pack_loop%s\n",ms?"":":");\r
+ ot(" ldr r1,[r0],#4\n");\r
+ ot(" subs r3,r3,#1\n");\r
+ ot(" str r1,[r5],#4\n");\r
+ ot(" bne c_pack_loop\n");\r
+ ot(";@ 0x40: PC\n");\r
+ ot(" ldr r0,[r4,#0x40] ;@ PC + Memory Base\n");\r
+ ot(" ldr r1,[r4,#0x60] ;@ Memory base\n");\r
+ ot(" sub r0,r0,r1\n");\r
+ ot(" str r0,[r5],#4\n");\r
+ ot(";@ 0x44: SR\n");\r
+ ot(" mov r0,r4\n");\r
+ ot(" bl CycloneGetSr\n");\r
+ ot(" strh r0,[r5],#2\n");\r
+ ot(";@ 0x46: IRQ level\n");\r
+ ot(" ldrb r0,[r4,#0x47]\n");\r
+ ot(" strb r0,[r5],#2\n");\r
+ ot(";@ 0x48: other SP\n");\r
+ ot(" ldr r0,[r4,#0x48]\n");\r
+ ot(" str r0,[r5],#4\n");\r
+ ot(";@ 0x4c: CPU state flags\n");\r
+ ot(" ldr r0,[r4,#0x58]\n");\r
+ ot(" str r0,[r5],#4\n");\r
+ ot(" ldmfd sp!,{r4,r5,pc}\n");\r
+ ot("\n");\r
+\r
+ // --------------\r
+ ot("CycloneUnpack%s\n", ms?"":":");\r
+ ot(" stmfd sp!,{r5,r7,lr}\n");\r
+ ot(" mov r7,r0\n");\r
+ ot(" movs r5,r1\n");\r
+ ot(" beq c_unpack_do_pc\n");\r
+ ot(" mov r3,#16\n");\r
+ ot(";@ 0x00-0x3f: DA registers\n");\r
+ ot("c_unpack_loop%s\n",ms?"":":");\r
+ ot(" ldr r1,[r5],#4\n");\r
+ ot(" subs r3,r3,#1\n");\r
+ ot(" str r1,[r0],#4\n");\r
+ ot(" bne c_unpack_loop\n");\r
+ ot(";@ 0x40: PC\n");\r
+ ot(" ldr r0,[r5],#4 ;@ PC\n");\r
+ ot(" str r0,[r7,#0x40] ;@ handle later\n");\r
+ ot(";@ 0x44: SR\n");\r
+ ot(" ldrh r1,[r5],#2\n");\r
+ ot(" mov r0,r7\n");\r
+ ot(" bl CycloneSetSr\n");\r
+ ot(";@ 0x46: IRQ level\n");\r
+ ot(" ldrb r0,[r5],#2\n");\r
+ ot(" strb r0,[r7,#0x47]\n");\r
+ ot(";@ 0x48: other SP\n");\r
+ ot(" ldr r0,[r5],#4\n");\r
+ ot(" str r0,[r7,#0x48]\n");\r
+ ot(";@ 0x4c: CPU state flags\n");\r
+ ot(" ldr r0,[r5],#4\n");\r
+ ot(" str r0,[r7,#0x58]\n");\r
+ ot("c_unpack_do_pc%s\n",ms?"":":");\r
+ ot(" ldr r0,[r7,#0x40] ;@ unbased PC\n");\r
+#if USE_CHECKPC_CALLBACK\r
+ ot(" mov r1,#0\n");\r
+ ot(" str r1,[r7,#0x60] ;@ Memory base\n");\r
+ #ifdef MEMHANDLERS_DIRECT_PREFIX\r
+ ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);\r
+ #else\r
+ ot(" mov lr,pc\n");\r
+ ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
+ #endif\r
+#else\r
+ ot(" ldr r1,[r7,#0x60] ;@ Memory base\n");\r
+ ot(" add r0,r0,r1 ;@ r0 = Memory Base + New PC\n");\r
+#endif\r
+ ot(" str r0,[r7,#0x40] ;@ PC + Memory Base\n");\r
+ ot(" ldmfd sp!,{r5,r7,pc}\n");\r
+ ot("\n");\r
+\r
+ // --------------\r
+ ot("CycloneFlushIrq%s\n", ms?"":":");\r
+ ot(" ldr r1,[r0,#0x44] ;@ Get SR high T_S__III and irq level\n");\r
+ ot(" mov r2,r1,lsr #24 ;@ Get IRQ level\n"); // same as ldrb r0,[r7,#0x47]\r
+ ot(" cmp r2,#6 ;@ irq>6 ?\n");\r
+ ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");\r
+ ot(" cmple r2,r1 ;@ irq<=6: Is irq<=mask ?\n");\r
+ ot(" movle r0,#0\n");\r
+ ot(" bxle lr ;@ no ints\n");\r
+ ot("\n");\r
+ ot(" stmdb sp!,{r4,r5,r7,r8,r10,r11,lr}\n");\r
+ ot(" mov r7,r0\n");\r
+ ot(" mov r0,r2\n");\r
+ ot(" ldrb r10,[r7,#0x46] ;@ r10 = Flags (NZCV)\n");\r
+ ot(" mov r5,#0\n");\r
+ ot(" ldr r4,[r7,#0x40] ;@ r4 = Current PC + Memory Base\n");\r
+ ot(" mov r10,r10,lsl #28 ;@ r10 = Flags 0xf0000000, cpsr format\n");\r
+ ot(" adr r2,CycloneFlushIrqEnd\n");\r
+ ot(" str r2,[r7,#0x98] ;@ set custom CycloneEnd\n");\r
+ ot(" b CycloneDoInterrupt\n");\r
+ ot("\n");\r
+ ot("CycloneFlushIrqEnd%s\n", ms?"":":");\r
+ ot(" rsb r0,r5,#0\n");\r
+ ot(" str r4,[r7,#0x40] ;@ Save Current PC + Memory Base\n");\r
+ ot(" strb r10,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
+ ot(" ldmia sp!,{r4,r5,r7,r8,r10,r11,lr}\n");\r
+ ot(" bx lr\n");\r
+ ot("\n");\r
+ ot("\n");\r
+\r
+ // --------------\r
+ ot("CycloneSetRealTAS%s\n", ms?"":":");\r
+#if (CYCLONE_FOR_GENESIS == 2)\r
+ ot(" ldr r12,=CycloneJumpTab\n");\r
+ ot(" tst r0,r0\n");\r
+ ot(" add r12,r12,#0x4a00*4\n");\r
+ ot(" add r12,r12,#0x00d0*4\n");\r
+ ot(" beq setrtas_off\n");\r
+ ChangeTAS(1);\r
+ ot(" bx lr\n");\r
+ ot("setrtas_off%s\n",ms?"":":");\r
+ ChangeTAS(0);\r
+ ot(" bx lr\n");\r
+ ltorg();\r
+#else\r
+ ot(" bx lr\n");\r
+#endif\r
+ ot("\n");\r
+\r
+ // --------------\r
+ ot(";@ DoInterrupt - r0=IRQ level\n");\r
+ ot("CycloneDoInterruptGoBack%s\n", ms?"":":");\r
+ ot(" sub r4,r4,#2\n");\r
+ ot("CycloneDoInterrupt%s\n", ms?"":":");\r
+ ot(" bic r8,r8,#0xff000000\n");\r
+ ot(" orr r8,r8,r0,lsl #29 ;@ abuse r8\n");\r
+\r
+ // Steps are from "M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL", p. 6-4\r
+ // but their order is based on http://pasti.fxatari.com/68kdocs/68kPrefetch.html\r
+ // 1. Make a temporary copy of the status register and set the status register for exception processing.\r
+ ot(" ldr r2,[r7,#0x58] ;@ state flags\n");\r
+ ot(" and r0,r0,#7\n");\r
+ ot(" orr r3,r0,#0x20 ;@ Supervisor mode + IRQ level\n");\r
+ ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");\r
+#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
+ ot(" orr r2,r2,#4 ;@ set activity bit: 'not processing instruction'\n");\r
+#endif\r
+ ot(" str r2,[r7,#0x58]\n");\r
+ ot(" ldrb r6,[r7,#0x44] ;@ Get old SR high, abuse r6\n");\r
+ ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");\r
ot("\n");\r
- ot(";@ todo - swap OSP and A7 if not in Supervisor mode\n");\r
- ot(" ldrb r0,[r7,#0x47] ;@ IRQ\n");\r
- ot(" orr r0,r0,#0x20 ;@ Supervisor mode + IRQ number\n");\r
- ot(" strb r0,[r7,#0x44] ;@ Put SR high\n");\r
+\r
+ // 3. Save the current processor context.\r
+ ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");\r
+ ot(" ldr r11,[r7,#0x3c] ;@ Get A7\n");\r
+ ot(" tst r6,#0x20\n");\r
+ ot(";@ get our SP:\n");\r
+ ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");\r
+ ot(" streq r11,[r7,#0x48]\n");\r
+ ot(" moveq r11,r2\n");\r
+ ot(";@ Push old PC onto stack\n");\r
+ ot(" sub r0,r11,#4 ;@ Predecremented A7\n");\r
+ ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");\r
+ MemHandler(1,2);\r
+ ot(";@ Push old SR:\n");\r
+ ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");\r
+ ot(" mov r1,r10,lsr #28 ;@ ____NZCV\n");\r
+ ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");\r
+ ot(" tst r2,#1 ;@ 1 if C!=V\n");\r
+ ot(" eorne r1,r1,#3 ;@ ____NZVC\n");\r
+ ot(" and r0,r0,#0x20000000\n");\r
+ ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");\r
+ ot(" orr r1,r1,r6,lsl #8 ;@ Include old SR high\n");\r
+ ot(" sub r0,r11,#6 ;@ Predecrement A7\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ MemHandler(1,1,0,0); // already checked for address error by prev MemHandler\r
ot("\n");\r
+\r
+ // 2. Obtain the exception vector.\r
+ ot(" mov r11,r8,lsr #29\n");\r
+ ot(" mov r0,r11\n");\r
+#if USE_INT_ACK_CALLBACK\r
+ ot(";@ call IrqCallback if it is defined\n");\r
+#if INT_ACK_NEEDS_STUFF\r
+ ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
+ ot(" mov r1,r10,lsr #28\n");\r
+ ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
+ ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
+#endif\r
+ ot(" ldr r3,[r7,#0x8c] ;@ IrqCallback\n");\r
+ ot(" add lr,pc,#4*3\n");\r
+ ot(" tst r3,r3\n");\r
+ ot(" streqb r3,[r7,#0x47] ;@ just clear IRQ if there is no callback\n");\r
+ ot(" mvneq r0,#0 ;@ and simulate -1 return\n");\r
+ ot(" bxne r3\n");\r
+#if INT_ACK_CHANGES_CYCLES\r
+ ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
+#endif\r
+ ot(";@ get IRQ vector address:\n");\r
+ ot(" cmn r0,#1 ;@ returned -1?\n");\r
+ ot(" addeq r0,r11,#0x18 ;@ use autovector then\n");\r
+ ot(" cmn r0,#2 ;@ returned -2?\n"); // should be safe as above add should never result in -2\r
+ ot(" moveq r0,#0x18 ;@ use spurious interrupt then\n");\r
+#else // !USE_INT_ACK_CALLBACK\r
ot(";@ Clear irq:\n");\r
- ot(" mov r0,#0\n");\r
- ot(" strb r0,[r7,#0x47]\n");\r
- ot(" subs r5,r5,#%d ;@ Subtract cycles\n",46);\r
- ot(" mov pc,r11 ;@ Return\n");\r
+ ot(" mov r2,#0\n");\r
+ ot(" strb r2,[r7,#0x47]\n");\r
+ ot(" add r0,r0,#0x18 ;@ use autovector\n");\r
+#endif\r
+ ot(" mov r0,r0,lsl #2 ;@ get vector address\n");\r
+ ot("\n");\r
+ ot(" ldr r11,[r7,#0x60] ;@ Get Memory base\n");\r
+ ot(";@ Read IRQ Vector:\n");\r
+ MemHandler(0,2,0,0);\r
+ ot(" tst r0,r0 ;@ uninitialized int vector?\n");\r
+ ot(" moveq r0,#0x3c\n");\r
+ #ifdef MEMHANDLERS_DIRECT_PREFIX\r
+ ot(" bleq %sread32 ;@ Call read32(r0) handler\n", MEMHANDLERS_DIRECT_PREFIX);\r
+ #else\r
+ ot(" moveq lr,pc\n");\r
+ ot(" ldreq pc,[r7,#0x70] ;@ Call read32(r0) handler\n");\r
+ #endif\r
+#if USE_CHECKPC_CALLBACK\r
+ ot(" add lr,pc,#4\n");\r
+ ot(" add r0,r0,r11 ;@ r0 = Memory Base + New PC\n");\r
+ #ifdef MEMHANDLERS_DIRECT_PREFIX\r
+ ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);\r
+ #else\r
+ ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
+ #endif\r
+ #if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" mov r4,r0\n");\r
+ #else\r
+ ot(" bic r4,r0,#1\n");\r
+ #endif\r
+#else\r
+ ot(" add r4,r0,r11 ;@ r4 = Memory Base + New PC\n");\r
+ #if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" bic r4,r4,#1\n");\r
+ #endif\r
+#endif\r
ot("\n");\r
\r
- ot("Exception%s\n", ms?"":":");\r
+ // 4. Obtain a new context and resume instruction processing.\r
+ // note: the obtain part was already done in previous steps\r
+#if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" tst r4,#1\n");\r
+ ot(" bne ExceptionAddressError_r_prg_r4\n");\r
+#endif\r
+ ot(" ldr r6,[r7,#0x54]\n");\r
+ ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
+ ot(" subs r5,r5,#44 ;@ Subtract cycles\n");\r
+ ot(" ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
+ ot(" b CycloneEnd\n");\r
ot("\n");\r
+\r
+ // --------------\r
+ // trashes all temp regs\r
+ ot("Exception%s\n", ms?"":":");\r
+ ot(" ;@ Cause an Exception - Vector number in r0\n");\r
ot(" mov r11,lr ;@ Preserve ARM return address\n");\r
- PrintException();\r
- ot(" mov pc,r11 ;@ Return\n");\r
+ ot(" bic r8,r8,#0xff000000\n");\r
+ ot(" orr r8,r8,r0,lsl #24 ;@ abuse r8\n");\r
+\r
+ // 1. Make a temporary copy of the status register and set the status register for exception processing.\r
+ ot(" ldr r6,[r7,#0x44] ;@ Get old SR high, abuse r6\n");\r
+ ot(" ldr r2,[r7,#0x58] ;@ state flags\n");\r
+ ot(" and r3,r6,#0x27 ;@ clear trace and unused flags\n");\r
+ ot(" orr r3,r3,#0x20 ;@ set supervisor mode\n");\r
+ ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");\r
+ ot(" str r2,[r7,#0x58]\n");\r
+ ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");\r
+ ot("\n");\r
+\r
+ // 3. Save the current processor context.\r
+ ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");\r
+ ot(" tst r6,#0x20\n");\r
+ ot(";@ get our SP:\n");\r
+ ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");\r
+ ot(" streq r0,[r7,#0x48]\n");\r
+ ot(" moveq r0,r2\n");\r
+ ot(";@ Push old PC onto stack\n");\r
+ ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");\r
+ ot(" sub r0,r0,#4 ;@ Predecremented A7\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");\r
+ MemHandler(1,2);\r
+ ot(";@ Push old SR:\n");\r
+ ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");\r
+ ot(" mov r1,r10,lsr #28 ;@ ____NZCV\n");\r
+ ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");\r
+ ot(" tst r2,#1 ;@ 1 if C!=V\n");\r
+ ot(" eorne r1,r1,#3 ;@ ____NZVC\n");\r
+ ot(" and r0,r0,#0x20000000\n");\r
+ ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");\r
+ ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
+ ot(" orr r1,r1,r6,lsl #8 ;@ Include SR high\n");\r
+ ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ MemHandler(1,1,0,0);\r
+ ot("\n");\r
+\r
+ // 2. Obtain the exception vector\r
+ ot(";@ Read Exception Vector:\n");\r
+ ot(" mov r0,r8,lsr #24\n");\r
+ ot(" mov r0,r0,lsl #2\n");\r
+ MemHandler(0,2,0,0);\r
+ ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");\r
+#if USE_CHECKPC_CALLBACK\r
+ ot(" add lr,pc,#4\n");\r
+ ot(" add r0,r0,r3 ;@ r0 = Memory Base + New PC\n");\r
+ #ifdef MEMHANDLERS_DIRECT_PREFIX\r
+ ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);\r
+ #else\r
+ ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
+ #endif\r
+ #if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" mov r4,r0\n");\r
+ #else\r
+ ot(" bic r4,r0,#1\n");\r
+ #endif\r
+#else\r
+ ot(" add r4,r0,r3 ;@ r4 = Memory Base + New PC\n");\r
+ #if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" bic r4,r4,#1\n");\r
+ #endif\r
+#endif\r
ot("\n");\r
+\r
+ // 4. Resume execution.\r
+#if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" tst r4,#1\n");\r
+ ot(" bne ExceptionAddressError_r_prg_r4\n");\r
+#endif\r
+ ot(" ldr r6,[r7,#0x54]\n");\r
+ ot(" bx r11 ;@ Return\n");\r
+ ot("\n");\r
+\r
+ // --------------\r
+#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
+ // first some wrappers: I see no point inlining this code,\r
+ // as it will be executed in really rare cases.\r
+ AddressErrorWrapper('r', "data", 0x11);\r
+ AddressErrorWrapper('r', "prg", 0x12);\r
+ AddressErrorWrapper('w', "data", 0x01);\r
+ // there are no program writes\r
+ // cpu space is only for bus errors?\r
+ ot("ExceptionAddressError_r_prg_r4%s\n", ms?"":":");\r
+ ot(" ldr r1,[r7,#0x44]\n");\r
+ ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");\r
+ ot(" mov r6,#0x12\n");\r
+ ot(" sub r11,r4,r3\n");\r
+ ot(" tst r1,#0x20\n");\r
+ ot(" orrne r6,r6,#4\n");\r
+ ot("\n");\r
+\r
+ ot("ExceptionAddressError%s\n", ms?"":":");\r
+ ot(";@ r6 - info word (without instruction/not bit), r11 - faulting address\n");\r
+\r
+ // 1. Make a temporary copy of the status register and set the status register for exception processing.\r
+ ot(" ldrb r0,[r7,#0x44] ;@ Get old SR high\n");\r
+ ot(" ldr r2,[r7,#0x58] ;@ state flags\n");\r
+ ot(" and r3,r0,#0x27 ;@ clear trace and unused flags\n");\r
+ ot(" orr r3,r3,#0x20 ;@ set supervisor mode\n");\r
+ ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");\r
+ ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");\r
+ ot(" tst r2,#4\n");\r
+ ot(" orrne r6,r6,#8 ;@ complete info word\n");\r
+ ot(" orr r2,r2,#4 ;@ set activity bit: 'not processing instruction'\n");\r
+#if EMULATE_HALT\r
+ ot(" tst r2,#8\n");\r
+ ot(" orrne r2,r2,#0x10 ;@ HALT\n");\r
+ ot(" orr r2,r2,#8 ;@ processing address error\n");\r
+ ot(" str r2,[r7,#0x58]\n");\r
+ ot(" movne r5,#0\n");\r
+ ot(" bne CycloneEndNoBack ;@ bye bye\n");\r
+#else\r
+ ot(" str r2,[r7,#0x58]\n");\r
+#endif\r
+ ot(" and r10,r10,#0xf0000000\n");\r
+ ot(" orr r10,r10,r0,lsl #4 ;@ some preparations for SR push\n");\r
+ ot("\n");\r
+\r
+ // 3. Save the current processor context + additional information.\r
+ ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");\r
+ ot(" tst r10,#0x200\n");\r
+ ot(";@ get our SP:\n");\r
+ ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");\r
+ ot(" streq r0,[r7,#0x48]\n");\r
+ ot(" moveq r0,r2\n");\r
+ // PC\r
+ ot(";@ Push old PC onto stack\n");\r
+ ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");\r
+ ot(" sub r0,r0,#4 ;@ Predecremented A7\n");\r
+ ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ MemHandler(1,2,0,EMULATE_HALT);\r
+ // SR\r
+ ot(";@ Push old SR:\n");\r
+ ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");\r
+ ot(" mov r1,r10,ror #28 ;@ ____NZCV\n");\r
+ ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");\r
+ ot(" tst r2,#1 ;@ 1 if C!=V\n");\r
+ ot(" eorne r1,r1,#3 ;@ ____NZVC\n");\r
+ ot(" and r0,r0,#0x20000000\n");\r
+ ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");\r
+ ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
+ ot(" and r10,r10,#0xf0000000\n");\r
+ ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ MemHandler(1,1,0,0);\r
+ // IR (instruction register)\r
+ ot(";@ Push IR:\n");\r
+ ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
+ ot(" mov r1,r8\n");\r
+ ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ MemHandler(1,1,0,0);\r
+ // access address\r
+ ot(";@ Push address:\n");\r
+ ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
+ ot(" mov r1,r11\n");\r
+ ot(" sub r0,r0,#4 ;@ Predecrement A7\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ MemHandler(1,2,0,0);\r
+ // information word\r
+ ot(";@ Push info word:\n");\r
+ ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
+ ot(" mov r1,r6\n");\r
+ ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ MemHandler(1,1,0,0);\r
+ ot("\n");\r
+\r
+ // 2. Obtain the exception vector\r
+ ot(";@ Read Exception Vector:\n");\r
+ ot(" mov r0,#0x0c\n");\r
+ MemHandler(0,2,0,0);\r
+ ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");\r
+#if USE_CHECKPC_CALLBACK\r
+ ot(" add lr,pc,#4\n");\r
+ ot(" add r0,r0,r3 ;@ r0 = Memory Base + New PC\n");\r
+ #ifdef MEMHANDLERS_DIRECT_PREFIX\r
+ ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);\r
+ #else\r
+ ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
+ #endif\r
+ ot(" mov r4,r0\n");\r
+#else\r
+ ot(" add r4,r0,r3 ;@ r4 = Memory Base + New PC\n");\r
+#endif\r
+ ot("\n");\r
+\r
+#if EMULATE_ADDRESS_ERRORS_JUMP && EMULATE_HALT\r
+ ot(" tst r4,#1\n");\r
+ ot(" bne ExceptionAddressError_r_prg_r4\n");\r
+#else\r
+ ot(" bic r4,r4,#1\n");\r
+#endif\r
+\r
+ // 4. Resume execution.\r
+ ot(" ldr r6,[r7,#0x54]\n");\r
+ ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
+ ot(" subs r5,r5,#50 ;@ Subtract cycles\n");\r
+ ot(" ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
+ ot(" b CycloneEnd\n");\r
+ ot("\n");\r
+#endif\r
+\r
+ // --------------\r
+#if EMULATE_TRACE\r
+ // expects srh and irq level in r1, next opcode already fetched to r8\r
+ ot("CycloneDoTraceWithChecks%s\n", ms?"":":");\r
+ ot(" ldr r0,[r7,#0x58]\n");\r
+ ot(" cmp r5,#0\n");\r
+ ot(" orr r0,r0,#2 ;@ go to trace mode\n");\r
+ ot(" str r0,[r7,#0x58]\n");\r
+ ot(" blt CycloneEnd\n"); // should take care of situation where we come here when already tracing\r
+ ot(";@ CheckInterrupt:\n");\r
+ ot(" movs r0,r1,lsr #24 ;@ Get IRQ level\n");\r
+ ot(" beq CycloneDoTrace\n");\r
+ ot(" cmp r0,#6 ;@ irq>6 ?\n");\r
+ ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");\r
+ ot(" cmple r0,r1 ;@ irq<=6: Is irq<=mask ?\n");\r
+ ot(" bgt CycloneDoInterruptGoBack\n");\r
+ ot("\n");\r
+\r
+ // expects next opcode to be already fetched to r8\r
+ ot("CycloneDoTrace%s\n", ms?"":":");\r
+ ot(" str r5,[r7,#0x9c] ;@ save cycles\n");\r
+ ot(" ldr r1,[r7,#0x98]\n");\r
+ ot(" mov r5,#0\n");\r
+ ot(" str r1,[r7,#0xa0]\n");\r
+ ot(" adr r0,TraceEnd\n");\r
+ ot(" str r0,[r7,#0x98] ;@ store TraceEnd as CycloneEnd hadler\n");\r
+ ot(" ldr pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
+ ot("\n");\r
+\r
+ ot("TraceEnd%s\n", ms?"":":");\r
+ ot(" ldr r2,[r7,#0x58]\n");\r
+ ot(" ldr r0,[r7,#0x9c] ;@ restore cycles\n");\r
+ ot(" ldr r1,[r7,#0xa0] ;@ old CycloneEnd handler\n");\r
+ ot(" mov r10,r10,lsl #28\n");\r
+ ot(" add r5,r0,r5\n");\r
+ ot(" str r1,[r7,#0x98]\n");\r
+ ot(";@ still tracing?\n"); // exception might have happend\r
+ ot(" tst r2,#2\n");\r
+ ot(" beq TraceDisabled\n");\r
+ ot(";@ trace exception\n");\r
+#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
+ ot(" ldr r1,[r7,#0x58]\n");\r
+ ot(" mov r0,#9\n");\r
+ ot(" orr r1,r1,#4 ;@ set activity bit: 'not processing instruction'\n");\r
+ ot(" str r1,[r7,#0x58]\n");\r
+#else\r
+ ot(" mov r0,#9\n");\r
+#endif\r
+ ot(" bl Exception\n");\r
+ ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
+ ot(" subs r5,r5,#34 ;@ Subtract cycles\n");\r
+ ot(" ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
+ ot(" b CycloneEnd\n");\r
+ ot("\n");\r
+ ot("TraceDisabled%s\n", ms?"":":");\r
+ ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
+ ot(" cmp r5,#0\n");\r
+ ot(" ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
+ ot(" b CycloneEnd\n");\r
+ ot("\n");\r
+#endif\r
}\r
\r
// ---------------------------------------------------------------------------\r
// Call Read(r0), Write(r0,r1) or Fetch(r0)\r
-// Trashes r0-r3\r
-int MemHandler(int type,int size)\r
+// Trashes r0-r3,r12,lr\r
+int MemHandler(int type,int size,int addrreg,int need_addrerr_check)\r
{\r
- int func=0;\r
- func=0x68+type*0xc+(size<<2); // Find correct offset\r
+ int func=0x68+type*0xc+(size<<2); // Find correct offset\r
+ char what[32];\r
\r
- if (Debug&4) ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
- if (Debug&3) ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
+#if MEMHANDLERS_NEED_FLAGS\r
+ ot(" mov r3,r10,lsr #28\n");\r
+ ot(" strb r3,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
+#endif\r
+ FlushPC();\r
\r
- ot(" mov lr,pc\n");\r
+#if (MEMHANDLERS_ADDR_MASK & 0xff000000)\r
+ ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0xff000000);\r
+ addrreg=0;\r
+#endif\r
+#if (MEMHANDLERS_ADDR_MASK & 0x00ff0000)\r
+ ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0x00ff0000);\r
+ addrreg=0;\r
+#endif\r
+#if (MEMHANDLERS_ADDR_MASK & 0x0000ff00)\r
+ ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0x0000ff00);\r
+ addrreg=0;\r
+#endif\r
+#if (MEMHANDLERS_ADDR_MASK & 0x000000ff)\r
+ ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0x000000ff);\r
+ addrreg=0;\r
+#endif\r
+\r
+#if EMULATE_ADDRESS_ERRORS_IO\r
+ if (size > 0 && need_addrerr_check)\r
+ {\r
+ ot(" add lr,pc,#4*%i\n", addrreg==0?2:3); // helps to prevent interlocks\r
+ if (addrreg != 0) ot(" mov r0,r%i\n", addrreg);\r
+ ot(" tst r0,#1 ;@ address error?\n");\r
+ switch (type) {\r
+ case 0: ot(" bne ExceptionAddressError_r_data\n"); break;\r
+ case 1: ot(" bne ExceptionAddressError_w_data\n"); break;\r
+ case 2: ot(" bne ExceptionAddressError_r_prg\n"); break;\r
+ }\r
+ }\r
+ else\r
+#endif\r
+\r
+ sprintf(what, "%s%d", type==0 ? "read" : (type==1 ? "write" : "fetch"), 8<<size);\r
+#ifdef MEMHANDLERS_DIRECT_PREFIX\r
+ if (addrreg != 0)\r
+ ot(" mov r0,r%i\n", addrreg);\r
+ ot(" bl %s%s ;@ Call ", MEMHANDLERS_DIRECT_PREFIX, what);\r
+ (void)func; // avoid warning\r
+#else\r
+ if (addrreg != 0)\r
+ {\r
+ ot(" add lr,pc,#4\n");\r
+ ot(" mov r0,r%i\n", addrreg);\r
+ }\r
+ else\r
+ ot(" mov lr,pc\n");\r
ot(" ldr pc,[r7,#0x%x] ;@ Call ",func);\r
+#endif\r
\r
// Document what we are calling:\r
- if (type==0) ot("read");\r
- if (type==1) ot("write");\r
- if (type==2) ot("fetch");\r
-\r
- if (type==1) ot("%d(r0,r1)",8<<size);\r
- else ot("%d(r0)", 8<<size);\r
+ if (type==1) ot("%s(r0,r1)",what);\r
+ else ot("%s(r0)", what);\r
ot(" handler\n");\r
\r
- if (Debug&2) ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
+#if MEMHANDLERS_CHANGE_FLAGS\r
+ ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");\r
+ ot(" mov r10,r10,lsl #28\n");\r
+#endif\r
+#if MEMHANDLERS_CHANGE_PC\r
+ ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
+#endif\r
+\r
return 0;\r
}\r
\r
static void PrintOpcodes()\r
{\r
int op=0;\r
- \r
+\r
printf("Creating Opcodes: [");\r
\r
ot(";@ ---------------------------- Opcodes ---------------------------\n");\r
\r
// Emit null opcode:\r
ot("Op____%s ;@ Called if an opcode is not recognised\n", ms?"":":");\r
- OpStart(-1); Cycles=4; OpEnd(); //test\r
+#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
+ ot(" ldr r1,[r7,#0x58]\n");\r
+ ot(" sub r4,r4,#2\n");\r
+ ot(" orr r1,r1,#4 ;@ set activity bit: 'not processing instruction'\n");\r
+ ot(" str r1,[r7,#0x58]\n");\r
+#else\r
+ ot(" sub r4,r4,#2\n");\r
+#endif\r
+#if USE_UNRECOGNIZED_CALLBACK\r
+ ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
+ ot(" mov r1,r10,lsr #28\n");\r
+ ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
+ ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
+ ot(" ldr r11,[r7,#0x94] ;@ UnrecognizedCallback\n");\r
+ ot(" tst r11,r11\n");\r
+ ot(" movne lr,pc\n");\r
+ ot(" movne pc,r11 ;@ call UnrecognizedCallback if it is defined\n");\r
+ ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");\r
+ ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
+ ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
+ ot(" mov r10,r10,lsl #28\n");\r
+ ot(" tst r0,r0\n");\r
+ ot(" moveq r0,#4\n");\r
+ ot(" bleq Exception\n");\r
+#else\r
+ ot(" mov r0,#4\n");\r
+ ot(" bl Exception\n");\r
+#endif\r
+ ot("\n");\r
+ Cycles=34;\r
+ OpEnd();\r
+\r
+ // Unrecognised a-line and f-line opcodes throw an exception:\r
+ ot("Op__al%s ;@ Unrecognised a-line opcode\n", ms?"":":");\r
+ ot(" sub r4,r4,#2\n");\r
+#if USE_AFLINE_CALLBACK\r
+ ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
+ ot(" mov r1,r10,lsr #28\n");\r
+ ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
+ ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
+ ot(" ldr r11,[r7,#0x94] ;@ UnrecognizedCallback\n");\r
+ ot(" tst r11,r11\n");\r
+ ot(" movne lr,pc\n");\r
+ ot(" movne pc,r11 ;@ call UnrecognizedCallback if it is defined\n");\r
+ ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");\r
+ ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
+ ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
+ ot(" mov r10,r10,lsl #28\n");\r
+ ot(" tst r0,r0\n");\r
+ ot(" moveq r0,#0x0a\n");\r
+ ot(" bleq Exception\n");\r
+#else\r
+ ot(" mov r0,#0x0a\n");\r
+ ot(" bl Exception\n");\r
+#endif\r
+ ot("\n");\r
+ Cycles=4;\r
+ OpEnd();\r
+\r
+ ot("Op__fl%s ;@ Unrecognised f-line opcode\n", ms?"":":");\r
+ ot(" sub r4,r4,#2\n");\r
+#if USE_AFLINE_CALLBACK\r
+ ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
+ ot(" mov r1,r10,lsr #28\n");\r
+ ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
+ ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
+ ot(" ldr r11,[r7,#0x94] ;@ UnrecognizedCallback\n");\r
+ ot(" tst r11,r11\n");\r
+ ot(" movne lr,pc\n");\r
+ ot(" movne pc,r11 ;@ call UnrecognizedCallback if it is defined\n");\r
+ ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");\r
+ ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
+ ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
+ ot(" mov r10,r10,lsl #28\n");\r
+ ot(" tst r0,r0\n");\r
+ ot(" moveq r0,#0x0b\n");\r
+ ot(" bleq Exception\n");\r
+#else\r
+ ot(" mov r0,#0x0b\n");\r
+ ot(" bl Exception\n");\r
+#endif\r
+ ot("\n");\r
+ Cycles=4;\r
+ OpEnd();\r
+\r
\r
- ot(" b CycloneEnd\n\n");\r
+ for (op=0;op<hot_opcode_count;op++)\r
+ OpAny(hot_opcodes[op]);\r
\r
for (op=0;op<0x10000;op++)\r
{\r
if ((op&0xfff)==0) { printf("%x",op>>12); fflush(stdout); } // Update progress\r
\r
- OpAny(op);\r
+ if (!is_op_hot(op))\r
+ OpAny(op);\r
}\r
\r
ot("\n");\r
printf("]\n");\r
}\r
\r
+// helper\r
+static void ott(const char *str, int par, const char *nl, int nlp, int counter, int size)\r
+{\r
+ switch(size) {\r
+ case 0: if((counter&7)==0) ot(ms?" dcb ":" .byte "); break;\r
+ case 1: if((counter&7)==0) ot(ms?" dcw ":" .hword "); break;\r
+ case 2: if((counter&7)==0) ot(ms?" dcd ":" .long "); break;\r
+ }\r
+ ot(str, par);\r
+ if((counter&7)==7) ot(nl,nlp); else ot(",");\r
+}\r
+\r
static void PrintJumpTable()\r
{\r
int i=0,op=0,len=0;\r
\r
ot(";@ -------------------------- Jump Table --------------------------\n");\r
- ot("JumpTab%s\n", ms?"":":");\r
\r
- len=0xfffe; // Hmmm, armasm 2.50.8684 messes up with a 0x10000 long jump table\r
- for (i=0;i<len;i++)\r
- {\r
- op=CyJump[i];\r
+ // space for decompressed table\r
+ ot(ms?" area |.data|, data\n":" .data\n .align 4\n\n");\r
\r
- if ((i&7)==0) ot(ms?" dcd ":" .long ");\r
- if (op<0) ot("Op____"); else ot("Op%.4x",op);\r
- \r
- if ((i&7)==7) ot(" ;@ %.4x\n",i-7);\r
- else if (i+1<len) ot(",");\r
- }\r
+#if COMPRESS_JUMPTABLE\r
+ int handlers=0,reps=0,*indexes,ip,u,out;\r
+ // use some weird compression on the jump table\r
+ indexes=(int *)malloc(0x10000*4);\r
+ if(!indexes) { printf("ERROR: out of memory\n"); exit(1); }\r
+ len=0x10000;\r
\r
- ot("\n");\r
+ ot("CycloneJumpTab%s\n", ms?"":":");\r
+ if(ms) {\r
+ for(i = 0; i < 0xa000/8; i++)\r
+ ot(" dcd 0,0,0,0,0,0,0,0\n");\r
+ } else\r
+ ot(" .rept 0x%x\n .long 0,0,0,0,0,0,0,0\n .endr\n", 0xa000/8);\r
+\r
+ // hanlers live in "a-line" part of the table\r
+ // first output nop,a-line,f-line handlers\r
+ ot(ms?" dcd Op____,Op__al,Op__fl,":" .long Op____,Op__al,Op__fl,");\r
+ handlers=3;\r
+\r
+ for(i=0;i<len;i++)\r
+ {\r
+ op=CyJump[i];\r
+\r
+ for(u=i-1; u>=0; u--) if(op == CyJump[u]) break; // already done with this op?\r
+ if(u==-1 && op >= 0) {\r
+ ott("Op%.4x",op," ;@ %.4x\n",i,handlers,2);\r
+ indexes[op] = handlers;\r
+ handlers++;\r
+ }\r
+ }\r
+ if(handlers&7) {\r
+ fseek(AsmFile, -1, SEEK_CUR); // remove last comma\r
+ for(i = 8-(handlers&7); i > 0; i--)\r
+ ot(",000000");\r
+ ot("\n");\r
+ }\r
+ if(ms) {\r
+ for(i = (0x4000-handlers)/8; i > 0; i--)\r
+ ot(" dcd 0,0,0,0,0,0,0,0\n");\r
+ } else {\r
+ ot(ms?"":" .rept 0x%x\n .long 0,0,0,0,0,0,0,0\n .endr\n", (0x4000-handlers)/8);\r
+ }\r
+ printf("total distinct hanlers: %i\n",handlers);\r
+ // output data\r
+ for(i=0,ip=0; i < 0xf000; i++, ip++) {\r
+ op=CyJump[i];\r
+ if(op == -2) {\r
+ // it must skip a-line area, because we keep our data there\r
+ ott("0x%.4x", handlers<<4, "\n",0,ip++,1);\r
+ ott("0x%.4x", 0x1000, "\n",0,ip,1);\r
+ i+=0xfff;\r
+ continue;\r
+ }\r
+ for(reps=1; i < 0xf000; i++, reps++) if(op != CyJump[i+1]) break;\r
+ if(op>=0) out=indexes[op]<<4; else out=0; // unrecognised\r
+ if(reps <= 0xe || reps==0x10) {\r
+ if(reps!=0x10) out|=reps; else out|=0xf; // 0xf means 0x10 (0xf appeared to be unused anyway)\r
+ ott("0x%.4x", out, "\n",0,ip,1);\r
+ } else {\r
+ ott("0x%.4x", out, "\n",0,ip++,1);\r
+ ott("0x%.4x", reps,"\n",0,ip,1);\r
+ }\r
+ }\r
+ if(ip&1) ott("0x%.4x", 0, "\n",0,ip++,1);\r
+ if(ip&7) fseek(AsmFile, -1, SEEK_CUR); // remove last comma\r
+ if(ip&7) {\r
+ for(i = 8-(ip&7); i > 0; i--)\r
+ ot(",0x0000");\r
+ }\r
+ ot("\n");\r
+ if(ms) {\r
+ for(i = (0x2000-ip/2)/8+1; i > 0; i--)\r
+ ot(" dcd 0,0,0,0,0,0,0,0\n");\r
+ } else {\r
+ ot(" .rept 0x%x\n .long 0,0,0,0,0,0,0,0\n .endr\n", (0x2000-ip/2)/8+1);\r
+ }\r
+ ot("\n");\r
+ free(indexes);\r
+#else\r
+ ot("CycloneJumpTab%s\n", ms?"":":");\r
+ len=0xfffe; // Hmmm, armasm 2.50.8684 messes up with a 0x10000 long jump table\r
+ // notaz: same thing with GNU as 2.9-psion-98r2 (reloc overflow)\r
+ // this is due to COFF objects using only 2 bytes for reloc count\r
+\r
+ for (i=0;i<len;i++)\r
+ {\r
+ op=CyJump[i];\r
+\r
+ if(op>=0) ott("Op%.4x",op," ;@ %.4x\n",i-7,i,2);\r
+ else if(op==-2) ott("Op__al",0, " ;@ %.4x\n",i-7,i,2);\r
+ else if(op==-3) ott("Op__fl",0, " ;@ %.4x\n",i-7,i,2);\r
+ else ott("Op____",0, " ;@ %.4x\n",i-7,i,2);\r
+ }\r
+ if(i&7) fseek(AsmFile, -1, SEEK_CUR); // remove last comma\r
+\r
+ ot("\n");\r
+ ot(";@ notaz: we don't want to crash if we run into those 2 missing opcodes\n");\r
+ ot(";@ so we leave this pattern to patch it later\n");\r
+ ot("%s 0x78563412\n", ms?" dcd":" .long");\r
+ ot("%s 0x56341290\n", ms?" dcd":" .long");\r
+#endif\r
}\r
\r
static int CycloneMake()\r
{\r
- char *name="Cyclone.s";\r
- \r
+ int i;\r
+ const char *name="Cyclone.s";\r
+ const char *globl=ms?"export":".global";\r
+\r
// Open the assembly file\r
if (ms) name="Cyclone.asm";\r
AsmFile=fopen(name,"wt"); if (AsmFile==NULL) return 1;\r
- \r
+\r
printf("Making %s...\n",name);\r
\r
ot("\n;@ Cyclone 68000 Emulator v%x.%.3x - Assembler Output\n\n",CycloneVer>>12,CycloneVer&0xfff);\r
\r
- ot(";@ Copyright (c) 2011 FinalDave (emudave (at) gmail.com)\n\n");\r
+ ot(";@ Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)\n");\r
+ ot(";@ Copyright (c) 2005-2011 Gražvydas \"notaz\" Ignotas (notasas (at) gmail.com)\n\n");\r
\r
ot(";@ This code is licensed under the GNU General Public License version 2.0 and the MAME License.\n");\r
ot(";@ You can choose the license that has the most advantages for you.\n\n");\r
\r
CyJump=(int *)malloc(0x40000); if (CyJump==NULL) return 1;\r
memset(CyJump,0xff,0x40000); // Init to -1\r
+ for(i=0xa000; i<0xb000; i++) CyJump[i] = -2; // a-line emulation\r
+ for(i=0xf000; i<0x10000; i++) CyJump[i] = -3; // f-line emulation\r
\r
- if (ms)\r
- {\r
- ot(" area |.text|, code\n");\r
- ot(" export CycloneRun\n");\r
- ot(" export CycloneVer\n");\r
- ot("\n");\r
- ot("CycloneVer dcd 0x%.4x\n",CycloneVer);\r
- }\r
- else\r
- {\r
- ot(" .global CycloneRun\n");\r
- ot(" .global CycloneVer\n");\r
- ot("CycloneVer: .long 0x%.4x\n",CycloneVer);\r
- }\r
+ ot(ms?" area |.text|, code\n":" .text\n .align 4\n\n");\r
+ ot(" %s CycloneInit\n",globl);\r
+ ot(" %s CycloneReset\n",globl);\r
+ ot(" %s CycloneRun\n",globl);\r
+ ot(" %s CycloneSetSr\n",globl);\r
+ ot(" %s CycloneGetSr\n",globl);\r
+ ot(" %s CycloneFlushIrq\n",globl);\r
+ ot(" %s CyclonePack\n",globl);\r
+ ot(" %s CycloneUnpack\n",globl);\r
+ ot(" %s CycloneVer\n",globl);\r
+#if (CYCLONE_FOR_GENESIS == 2)\r
+ ot(" %s CycloneSetRealTAS\n",globl);\r
+ ot(" %s CycloneDoInterrupt\n",globl);\r
+ ot(" %s CycloneDoTrace\n",globl);\r
+ ot(" %s CycloneJumpTab\n",globl);\r
+ ot(" %s Op____\n",globl);\r
+ ot(" %s Op6001\n",globl);\r
+ ot(" %s Op6601\n",globl);\r
+ ot(" %s Op6701\n",globl);\r
+#endif\r
+ ot("\n");\r
+ ot(ms?"CycloneVer dcd 0x":"CycloneVer: .long 0x");\r
+ ot("%.4x\n",CycloneVer);\r
ot("\n");\r
\r
PrintFramework();\r
+ arm_op_count = 0;\r
PrintOpcodes();\r
+ printf("~%i ARM instructions used for opcode handlers\n", arm_op_count);\r
PrintJumpTable();\r
\r
if (ms) ot(" END\n");\r
\r
+ ot("\n\n;@ vim:filetype=armasm\n");\r
+\r
fclose(AsmFile); AsmFile=NULL;\r
\r
+#if 0\r
printf("Assembling...\n");\r
// Assemble the file\r
if (ms) system("armasm Cyclone.asm");\r
else system("as -o Cyclone.o Cyclone.s");\r
printf("Done!\n\n");\r
+#endif\r
\r
free(CyJump);\r
return 0;\r
{\r
printf("\n Cyclone 68000 Emulator v%x.%.3x - Core Creator\n\n",CycloneVer>>12,CycloneVer&0xfff);\r
\r
- // Make GAS and ARMASM versions\r
- for (ms=0;ms<2;ms++) CycloneMake();\r
+ // Make GAS or ARMASM version\r
+ CycloneMake();\r
return 0;\r
}\r
+\r
CFLAGS += -Wall -ggdb
+CXXFLAGS += $(CFLAGS)
OBJS = Main.o Ea.o OpAny.o OpArith.o OpBranch.o OpLogic.o OpMove.o Disa/Disa.o
-all: cyclone.s
+all: Cyclone.s
-cyclone.s: cyclone_gen
+Cyclone.s: cyclone_gen
./$<
cyclone_gen: $(OBJS)
$(CXX) -o $@ $^ $(LDFLAGS)
clean:
- $(RM) $(OBJS) cyclone_gen cyclone.s
+ $(RM) $(OBJS) cyclone_gen Cyclone.s
\r
// This file is part of the Cyclone 68000 Emulator\r
\r
-// Copyright (c) 2011 FinalDave (emudave (at) gmail.com)\r
+// Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)\r
+// Copyright (c) 2005-2011 Gražvydas "notaz" Ignotas (notasas (at) gmail.com)\r
\r
// This code is licensed under the GNU General Public License version 2.0 and the MAME License.\r
// You can choose the license that has the most advantages for you.\r
\r
// SVN repository can be found at http://code.google.com/p/cyclone68000/\r
\r
+\r
#include "app.h"\r
\r
+int opend_op_changes_cycles, opend_check_interrupt, opend_check_trace;\r
+\r
static unsigned char OpData[16]={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};\r
\r
-static unsigned short CPU_CALL OpRead16(unsigned int a)\r
+static unsigned short OpRead16(unsigned int a)\r
{\r
return (unsigned short)( (OpData[a&15]<<8) | OpData[(a+1)&15] );\r
}\r
void OpUse(int op,int use)\r
{\r
char text[64]="";\r
- \r
- if (op>=0)\r
- CyJump[op]=use;\r
+ CyJump[op]=use;\r
\r
if (op!=use) return;\r
\r
ot(";@ ---------- [%.4x] %s uses Op%.4x ----------\n",op,text,use);\r
}\r
\r
-void OpFirst()\r
+void OpStart(int op, int sea, int tea, int op_changes_cycles, int supervisor_check)\r
{\r
- ot(" ldrh r8,[r4],#2 ;@ Fetch first opcode\n");\r
- ot(" ldr pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
-}\r
+ int last_op_count=arm_op_count;\r
\r
-void OpStart(int op)\r
-{\r
Cycles=0;\r
OpUse(op,op); // This opcode obviously uses this handler\r
ot("Op%.4x%s\n", op, ms?"":":");\r
+\r
+ if (supervisor_check)\r
+ {\r
+ // checks for supervisor bit, if not set, jumps to SuperEnd()\r
+ // also sets r11 to SR high value, SuperChange() uses this\r
+ ot(" ldr r11,[r7,#0x44] ;@ Get SR high\n");\r
+ }\r
+ if ((sea >= 0x10 && sea != 0x3c) || (tea >= 0x10 && tea != 0x3c))\r
+ {\r
+#if MEMHANDLERS_NEED_PREV_PC\r
+ ot(" str r4,[r7,#0x50] ;@ Save prev PC + 2\n");\r
+#endif\r
+#if MEMHANDLERS_NEED_CYCLES\r
+ ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
+#endif\r
+ }\r
+ if (supervisor_check)\r
+ {\r
+ ot(" tst r11,#0x20 ;@ Check we are in supervisor mode\n");\r
+ ot(" beq WrongPrivilegeMode ;@ No\n");\r
+ }\r
+ if ((sea >= 0x10 && sea != 0x3c) || (tea >= 0x10 && tea != 0x3c)) {\r
+#if MEMHANDLERS_CHANGE_CYCLES\r
+ if (op_changes_cycles)\r
+ ot(" mov r5,#0\n");\r
+#endif\r
+ }\r
+ if (last_op_count!=arm_op_count)\r
+ ot("\n");\r
+ pc_dirty = 1;\r
+ opend_op_changes_cycles = opend_check_interrupt = opend_check_trace = 0;\r
}\r
\r
-void OpEnd()\r
+void OpEnd(int sea, int tea)\r
{\r
- ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
+ int did_fetch=0;\r
+ opend_check_trace = opend_check_trace && EMULATE_TRACE;\r
+#if MEMHANDLERS_CHANGE_CYCLES\r
+ if ((sea >= 0x10 && sea != 0x3c) || (tea >= 0x10 && tea != 0x3c))\r
+ {\r
+ if (opend_op_changes_cycles)\r
+ {\r
+ ot(" ldr r0,[r7,#0x5c] ;@ Load Cycles\n");\r
+ ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
+ ot(" add r5,r0,r5\n");\r
+ did_fetch=1;\r
+ }\r
+ else\r
+ {\r
+ ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
+ }\r
+ }\r
+#endif\r
+ if (!did_fetch)\r
+ ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
+ if (opend_check_trace)\r
+ ot(" ldr r1,[r7,#0x44]\n");\r
ot(" subs r5,r5,#%d ;@ Subtract cycles\n",Cycles);\r
- ot(" ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
- ot(" b CycloneEnd\n");\r
- ltorg();\r
+ if (opend_check_trace)\r
+ {\r
+ ot(";@ CheckTrace:\n");\r
+ ot(" tst r1,#0x80\n");\r
+ ot(" bne CycloneDoTraceWithChecks\n");\r
+ ot(" cmp r5,#0\n");\r
+ }\r
+ if (opend_check_interrupt)\r
+ {\r
+ ot(" blt CycloneEnd\n");\r
+ ot(";@ CheckInterrupt:\n");\r
+ if (!opend_check_trace)\r
+ ot(" ldr r1,[r7,#0x44]\n");\r
+ ot(" movs r0,r1,lsr #24 ;@ Get IRQ level\n"); // same as ldrb r0,[r7,#0x47]\r
+ ot(" ldreq pc,[r6,r8,asl #2] ;@ Jump to next opcode handler\n");\r
+ ot(" cmp r0,#6 ;@ irq>6 ?\n");\r
+ ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");\r
+ ot(" cmple r0,r1 ;@ irq<=6: Is irq<=mask ?\n");\r
+ ot(" ldrle pc,[r6,r8,asl #2] ;@ Jump to next opcode handler\n");\r
+ ot(" b CycloneDoInterruptGoBack\n");\r
+ }\r
+ else\r
+ {\r
+ ot(" ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
+ ot(" b CycloneEnd\n");\r
+ }\r
ot("\n");\r
}\r
\r
-int OpBase(int op)\r
+int OpBase(int op,int size,int sepa)\r
{\r
int ea=op&0x3f; // Get Effective Address\r
- if (ea<0x10) return op&~0xf; // Use 1 handler for d0-d7 and a0-a7\r
- if (ea>=0x18 && ea<0x28 && (ea&7)==7) return op; // Specific handler for (a7)+ and -(a7)\r
+ if (ea<0x10) return sepa?(op&~0x7):(op&~0xf); // Use 1 handler for d0-d7 and a0-a7\r
+ if (size==0&&(ea==0x1f || ea==0x27)) return op; // Specific handler for (a7)+ and -(a7)\r
if (ea<0x38) return op&~7; // Use 1 handler for (a0)-(a7), etc...\r
return op;\r
}\r
\r
// Get flags, trashes r2\r
-int OpGetFlags(int subtract,int xbit)\r
+int OpGetFlags(int subtract,int xbit,int specialz)\r
{\r
- ot(" mrs r9,cpsr ;@ r9=flags\n");\r
+ if (specialz) ot(" orr r2,r10,#0xb0000000 ;@ for old Z\n");\r
+\r
+ ot(" mrs r10,cpsr ;@ r10=flags\n");\r
\r
- if (subtract) ot(" eor r9,r9,#0x20000000 ;@ Invert carry\n");\r
+ if (specialz) ot(" andeq r10,r10,r2 ;@ fix Z\n");\r
\r
- if (Accu&1) if (xbit)\r
+ if (subtract) ot(" eor r10,r10,#0x20000000 ;@ Invert carry\n");\r
+\r
+ if (xbit)\r
{\r
- ot(" mov r2,r9,lsr #28\n");\r
- ot(" strb r2,[r7,#0x45] ;@ Save X bit\n");\r
+ ot(" str r10,[r7,#0x4c] ;@ Save X bit\n");\r
}\r
return 0;\r
}\r
\r
// -----------------------------------------------------------------\r
\r
+int g_op;\r
+\r
void OpAny(int op)\r
{\r
memset(OpData,0x33,sizeof(OpData));\r
OpData[0]=(unsigned char)(op>>8);\r
OpData[1]=(unsigned char)op;\r
-\r
- if ((op&0xf100)==0x0000) OpArith(op);\r
- if ((op&0xc000)==0x0000) OpMove(op);\r
- if ((op&0xf5bf)==0x003c) OpArithSr(op); // Ori/Andi/Eori $nnnn,sr\r
- if ((op&0xf100)==0x0100) OpBtstReg(op);\r
- if ((op&0xff00)==0x0800) OpBtstImm(op);\r
- if ((op&0xf900)==0x4000) OpNeg(op);\r
- if ((op&0xf1c0)==0x41c0) OpLea(op);\r
- if ((op&0xf9c0)==0x40c0) OpMoveSr(op);\r
- if ((op&0xfff8)==0x4840) OpSwap(op);\r
- if ((op&0xffc0)==0x4840) OpPea(op);\r
- if ((op&0xffb8)==0x4880) OpExt(op);\r
- if ((op&0xfb80)==0x4880) OpMovem(op);\r
- if ((op&0xff00)==0x4a00) OpTst(op);\r
- if ((op&0xfff0)==0x4e40) OpTrap(op);\r
- if ((op&0xfff8)==0x4e50) OpLink(op);\r
- if ((op&0xfff8)==0x4e58) OpUnlk(op);\r
- if ((op&0xfff0)==0x4e60) OpMoveUsp(op);\r
- if ((op&0xfff8)==0x4e70) Op4E70(op); // Reset/Rts etc\r
- if ((op&0xff80)==0x4e80) OpJsr(op);\r
- if ((op&0xf000)==0x5000) OpAddq(op);\r
- if ((op&0xf0c0)==0x50c0) OpSet(op);\r
- if ((op&0xf0f8)==0x50c8) OpDbra(op);\r
- if ((op&0xf000)==0x6000) OpBranch(op);\r
- if ((op&0xf100)==0x7000) OpMoveq(op);\r
- if ((op&0xa000)==0x8000) OpArithReg(op); // Or/Sub/And/Add\r
- if ((op&0xb1f0)==0x8100) OpAbcd(op);\r
- if ((op&0xb0c0)==0x80c0) OpMul(op);\r
- if ((op&0x90c0)==0x90c0) OpAritha(op);\r
- if ((op&0xb138)==0x9100) OpAddx(op);\r
- if ((op&0xf000)==0xb000) OpCmpEor(op);\r
- if ((op&0xf130)==0xc100) OpExg(op);\r
- if ((op&0xf000)==0xe000) OpAsr(op); // Asr/l/Ror/l etc\r
- if ((op&0xf8c0)==0xe0c0) OpAsrEa(op);\r
-\r
+ g_op=op;\r
+\r
+ if ((op&0xf100)==0x0000) OpArith(op); // +\r
+ if ((op&0xc000)==0x0000) OpMove(op); // +\r
+ if ((op&0xf5bf)==0x003c) OpArithSr(op); // + Ori/Andi/Eori $nnnn,sr\r
+ if ((op&0xf100)==0x0100) OpBtstReg(op); // +\r
+ if ((op&0xf138)==0x0108) OpMovep(op); // +\r
+ if ((op&0xff00)==0x0800) OpBtstImm(op); // +\r
+ if ((op&0xf900)==0x4000) OpNeg(op); // +\r
+ if ((op&0xf140)==0x4100) OpChk(op); // +\r
+ if ((op&0xf1c0)==0x41c0) OpLea(op); // +\r
+ if ((op&0xf9c0)==0x40c0) OpMoveSr(op); // +\r
+ if ((op&0xffc0)==0x4800) OpNbcd(op); // +\r
+ if ((op&0xfff8)==0x4840) OpSwap(op); // +\r
+ if ((op&0xffc0)==0x4840) OpPea(op); // +\r
+ if ((op&0xffb8)==0x4880) OpExt(op); // +\r
+ if ((op&0xfb80)==0x4880) OpMovem(op); // +\r
+ if ((op&0xff00)==0x4a00) OpTst(op); // +\r
+ if ((op&0xffc0)==0x4ac0) OpTas(op); // +\r
+ if ((op&0xfff0)==0x4e40) OpTrap(op); // +\r
+ if ((op&0xfff8)==0x4e50) OpLink(op); // +\r
+ if ((op&0xfff8)==0x4e58) OpUnlk(op); // +\r
+ if ((op&0xfff0)==0x4e60) OpMoveUsp(op); // +\r
+ if ((op&0xfff8)==0x4e70) Op4E70(op); // + Reset/Rts etc\r
+ if ((op&0xfffd)==0x4e70) OpStopReset(op);// +\r
+ if ((op&0xff80)==0x4e80) OpJsr(op); // +\r
+ if ((op&0xf000)==0x5000) OpAddq(op); // +\r
+ if ((op&0xf0c0)==0x50c0) OpSet(op); // +\r
+ if ((op&0xf0f8)==0x50c8) OpDbra(op); // +\r
+ if ((op&0xf000)==0x6000) OpBranch(op); // +\r
+ if ((op&0xf100)==0x7000) OpMoveq(op); // +\r
+ if ((op&0xa000)==0x8000) OpArithReg(op); // + Or/Sub/And/Add\r
+ if ((op&0xb1f0)==0x8100) OpAbcd(op); // +\r
+ if ((op&0xb0c0)==0x80c0) OpMul(op); // +\r
+ if ((op&0x90c0)==0x90c0) OpAritha(op); // +\r
+ if ((op&0xb130)==0x9100) OpAddx(op); // +\r
+ if ((op&0xf000)==0xb000) OpCmpEor(op); // +\r
+ if ((op&0xf138)==0xb108) OpCmpm(op); // +\r
+ if ((op&0xf130)==0xc100) OpExg(op); // +\r
+ if ((op&0xf000)==0xe000) OpAsr(op); // + Asr/l/Ror/l etc\r
+ if ((op&0xf8c0)==0xe0c0) OpAsrEa(op); // +\r
+\r
+ if (op==0xffff)\r
+ {\r
+ SuperEnd();\r
+ }\r
}\r
+\r
\r
// This file is part of the Cyclone 68000 Emulator\r
\r
-// Copyright (c) 2011 FinalDave (emudave (at) gmail.com)\r
+// Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)\r
+// Copyright (c) 2005-2011 Gražvydas "notaz" Ignotas (notasas (at) gmail.com)\r
\r
// This code is licensed under the GNU General Public License version 2.0 and the MAME License.\r
// You can choose the license that has the most advantages for you.\r
\r
// SVN repository can be found at http://code.google.com/p/cyclone68000/\r
\r
+\r
#include "app.h"\r
\r
// --------------------- Opcodes 0x0000+ ---------------------\r
-// Emit an Ori/And/Sub/Add/Eor/Cmp Immediate opcode, 0000ttt0 00aaaaaa\r
+// Emit an Ori/And/Sub/Add/Eor/Cmp Immediate opcode, 0000ttt0 ssaaaaaa\r
int OpArith(int op)\r
{\r
int type=0,size=0;\r
int sea=0,tea=0;\r
int use=0;\r
+ const char *shiftstr="";\r
\r
// Get source and target EA\r
type=(op>>9)&7; if (type==4 || type>=7) return 1;\r
\r
// See if we can do this opcode:\r
if (EaCanRead(tea,size)==0) return 1;\r
- if (type!=6 && EaCanWrite(tea)==0) return 1;\r
+ if (EaCanWrite(tea)==0 || EaAn(tea)) return 1;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op); Cycles=4;\r
+ OpStart(op, sea, tea); Cycles=4;\r
\r
- EaCalc(10,0x0000, sea,size);\r
- EaRead(10, 10, sea,size,1);\r
+ // imm must be read first\r
+ EaCalcReadNoSE(-1,10,sea,size,0);\r
+ EaCalcReadNoSE((type!=6)?11:-1,0,tea,size,0x003f);\r
\r
- EaCalc(11,0x003f, tea,size);\r
- EaRead(11, 0, tea,size,1);\r
+ if (size<2) shiftstr=(char *)(size?",asl #16":",asl #24");\r
+ if (size<2) ot(" mov r10,r10,asl #%i\n",size?16:24);\r
\r
ot(";@ Do arithmetic:\n");\r
\r
- if (type==0) ot(" orr r1,r0,r10\n");\r
- if (type==1) ot(" and r1,r0,r10\n");\r
- if (type==2) ot(" subs r1,r0,r10 ;@ Defines NZCV\n");\r
- if (type==3) ot(" adds r1,r0,r10 ;@ Defines NZCV\n");\r
- if (type==5) ot(" eor r1,r0,r10\n");\r
- if (type==6) ot(" cmp r0,r10 ;@ Defines NZCV\n");\r
+ if (type==0) ot(" orr r1,r10,r0%s\n",shiftstr);\r
+ if (type==1) ot(" and r1,r10,r0%s\n",shiftstr);\r
+ if (type==2||type==6)\r
+ ot(" rsbs r1,r10,r0%s ;@ Defines NZCV\n",shiftstr);\r
+ if (type==3) ot(" adds r1,r10,r0%s ;@ Defines NZCV\n",shiftstr);\r
+ if (type==5) ot(" eor r1,r10,r0%s\n",shiftstr);\r
\r
if (type<2 || type==5) ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n"); // 0,1,5\r
\r
\r
if (type!=6)\r
{\r
- EaWrite(11, 1, tea,size,1);\r
+ EaWrite(11, 1, tea,size,0x003f,1);\r
}\r
\r
// Correct cycles:\r
else\r
{\r
if (size>=2) Cycles+=4;\r
- if (tea>=0x10) Cycles+=4;\r
- if (Amatch && type==1 && size>=2 && tea<0x10) Cycles-=2;\r
+ if (tea>=8) Cycles+=4;\r
+ if (type==1 && size>=2 && tea<8) Cycles-=2;\r
}\r
\r
- OpEnd();\r
+ OpEnd(sea,tea);\r
\r
return 0;\r
}\r
\r
// See if we can do this opcode:\r
if (EaCanRead (ea,size)==0) return 1;\r
- if (EaCanWrite(ea )==0) return 1;\r
+ if (EaCanWrite(ea) ==0) return 1;\r
+ if (size == 0 && EaAn(ea) ) return 1;\r
\r
- use=op; if (ea<0x38) use&=~7;\r
- if ((ea&0x38)==0x08) { size=2; use&=~0xc0; } // Every addq #n,An is 32-bit\r
+ use=OpBase(op,size,1);\r
\r
if (num!=8) use|=0x0e00; // If num is not 8, use same handler\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op);\r
+ OpStart(op,ea);\r
Cycles=ea<8?4:8;\r
- if (size>=2 && ea!=8) Cycles+=4;\r
+ if(type==0&&size==1) Cycles=ea<0x10?4:8;\r
+ if(size>=2) Cycles=ea<0x10?8:12;\r
+\r
+ if (size>0 && (ea&0x38)==0x08) size=2; // addq.w #n,An is also 32-bit\r
\r
- EaCalc(10,0x003f, ea,size);\r
- EaRead(10, 0, ea,size,1);\r
+ EaCalcReadNoSE(11,0,ea,size,0x003f);\r
\r
shift=32-(8<<size);\r
\r
{\r
int lsr=9-shift;\r
\r
- if (lsr>=0) ot(" mov r2,r8,lsr #%d ;@ Get quick value\n", lsr);\r
- else ot(" mov r2,r8,lsl #%d ;@ Get quick value\n",-lsr);\r
+ ot(" and r2,r8,#0x0e00 ;@ Get quick value\n");\r
+\r
+ if (lsr>=0) sprintf(count,"r2,lsr #%d", lsr);\r
+ else sprintf(count,"r2,lsl #%d", -lsr);\r
\r
- ot(" and r2,r2,#0x%.4x\n",7<<shift);\r
ot("\n");\r
- strcpy(count,"r2");\r
+ }\r
+ else\r
+ {\r
+ sprintf(count,"#0x%.4x",8<<shift);\r
}\r
\r
- if (num==8) sprintf(count,"#0x%.4x",8<<shift);\r
+ if (size<2) ot(" mov r0,r0,asl #%d\n\n",size?16:24);\r
\r
if (type==0) ot(" adds r1,r0,%s\n",count);\r
if (type==1) ot(" subs r1,r0,%s\n",count);\r
if ((ea&0x38)!=0x08) OpGetFlags(type,1);\r
ot("\n");\r
\r
- EaWrite(10, 1, ea,size,1);\r
+ EaWrite(11, 1, ea,size,0x003f,1);\r
\r
- OpEnd();\r
+ OpEnd(ea);\r
\r
return 0;\r
}\r
{\r
int use=0;\r
int type=0,size=0,dir=0,rea=0,ea=0;\r
+ const char *asl="";\r
+ const char *strop=0;\r
\r
type=(op>>12)&5;\r
rea =(op>> 9)&7;\r
- dir =(op>> 8)&1;\r
+ dir =(op>> 8)&1; // er,re\r
size=(op>> 6)&3; if (size>=3) return 1;\r
ea = op&0x3f;\r
\r
if (dir && ea<0x10) return 1; // addx/subx opcode\r
\r
// See if we can do this opcode:\r
- if (dir==0 && EaCanWrite(rea)==0) return 1;\r
- if (dir && EaCanWrite( ea)==0) return 1;\r
+ if (dir==0 && EaCanRead (ea,size)==0) return 1;\r
+ if (dir && EaCanWrite(ea)==0) return 1;\r
+ if ((size==0||!(type&1))&&EaAn(ea)) return 1;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
use&=~0x0e00; // Use same opcode for Dn\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op); Cycles=4;\r
+ OpStart(op,ea); Cycles=4;\r
\r
- ot(";@ Get r10=EA r11=EA value\n");\r
- EaCalc(10,0x003f, ea,size);\r
- EaRead(10, 11, ea,size,1);\r
- ot(";@ Get r0=Register r1=Register value\n");\r
- EaCalc( 0,0x0e00,rea,size);\r
- EaRead( 0, 1,rea,size,1);\r
+ EaCalcReadNoSE(dir?11:-1,0,ea,size,0x003f);\r
+\r
+ EaCalcReadNoSE(dir?-1:11,1,rea,size,0x0e00);\r
\r
ot(";@ Do arithmetic:\n");\r
- if (type==0) ot(" orr ");\r
- if (type==1) ot(" subs ");\r
- if (type==4) ot(" and ");\r
- if (type==5) ot(" adds ");\r
- if (dir) ot("r1,r11,r1\n");\r
- else ot("r1,r1,r11\n");\r
+ if (type==0) strop = "orr";\r
+ if (type==1) strop = (char *) (dir ? "subs" : "rsbs");\r
+ if (type==4) strop = "and";\r
+ if (type==5) strop = "adds";\r
+\r
+ if (size==0) asl=",asl #24";\r
+ if (size==1) asl=",asl #16";\r
+\r
+ if (size<2) ot(" mov r0,r0%s\n",asl);\r
+ ot(" %s r1,r0,r1%s\n",strop,asl);\r
\r
if ((type&1)==0) ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
\r
ot("\n");\r
\r
ot(";@ Save result:\n");\r
- if (dir) EaWrite(10, 1, ea,size,1);\r
- else EaWrite( 0, 1,rea,size,1);\r
-\r
- if (size==1 && ea>=0x10) Cycles+=4;\r
- if (size>=2) { if (ea<0x10) Cycles+=4; else Cycles+=2; }\r
+ if (size<2) ot(" mov r1,r1,asr #%d\n",size?16:24);\r
+ if (dir) EaWrite(11, 1, ea,size,0x003f,0,0);\r
+ else EaWrite(11, 1,rea,size,0x0e00,0,0);\r
+\r
+ if(rea==ea) {\r
+ if(ea<8) Cycles=(size>=2)?8:4; else Cycles+=(size>=2)?26:14;\r
+ } else if(dir) {\r
+ Cycles+=4;\r
+ if(size>=2) Cycles+=4;\r
+ } else {\r
+ if(size>=2) {\r
+ Cycles+=2;\r
+ if(ea<0x10||ea==0x3c) Cycles+=2;\r
+ }\r
+ }\r
\r
- OpEnd();\r
+ OpEnd(ea);\r
\r
return 0;\r
}\r
ea = op&0x3f;\r
\r
// See if we can do this opcode:\r
- if (EaCanRead(ea,1)==0) return 1;\r
+ if (EaCanRead(ea,1)==0||EaAn(ea)) return 1;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,1);\r
use&=~0x0e00; // Use same for all registers\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op); Cycles=type?70:133;\r
+ OpStart(op,ea);\r
+ if(type) Cycles=54;\r
+ else Cycles=sign?158:140;\r
\r
- EaCalc(10,0x003f, ea, 1);\r
- EaRead(10, 10, ea, 1);\r
+ EaCalcReadNoSE(-1,0,ea,1,0x003f);\r
\r
- EaCalc (0,0x0e00,rea, 2);\r
- EaRead (0, 2,rea, 2);\r
+ EaCalc(11,0x0e00,rea, 2);\r
+ EaRead(11, 2,rea, 2,0x0e00);\r
\r
- if (type==0)\r
+ ot(" movs r1,r0,asl #16\n");\r
+\r
+ if (type==0) // div\r
{\r
- ot(" cmp r10,#0\n");\r
- ot(" moveq r10,#1 ;@ Divide by zero\n");\r
+ // the manual says C is always cleared, but neither Musashi nor FAME do that\r
+ //ot(" bic r10,r10,#0x20000000 ;@ always clear C\n");\r
+ ot(" beq divzero%.4x ;@ division by zero\n",op);\r
ot("\n");\r
\r
if (sign)\r
{\r
- ot(" mov r11,#0 ;@ r11 = 1 if the result is negative\n");\r
- ot(" eorlt r11,r11,#1\n");\r
- ot(" rsblt r10,r10,#0 ;@ Make r10 positive\n");\r
+ ot(" mov r12,#0 ;@ r12 = 1 or 2 if the result is negative\n");\r
+ ot(" tst r2,r2\n");\r
+ ot(" orrmi r12,r12,#2\n");\r
+ ot(" rsbmi r2,r2,#0 ;@ Make r2 positive\n");\r
ot("\n");\r
- ot(" cmp r2,#0\n");\r
- ot(" eorlt r11,r11,#1\n");\r
- ot(" rsblt r2,r2,#0 ;@ Make r2 positive\n");\r
+ ot(" movs r0,r1,asr #16\n");\r
+ ot(" orrmi r12,r12,#1\n");\r
+ ot(" rsbmi r0,r0,#0 ;@ Make r0 positive\n");\r
ot("\n");\r
+ ot(";@ detect the nasty 0x80000000 / -1 situation\n");\r
+ ot(" mov r3,r2,asr #31\n");\r
+ ot(" eors r3,r3,r1,asr #16\n");\r
+ ot(" beq wrendofop%.4x\n",op);\r
+ }\r
+ else\r
+ {\r
+ ot(" mov r0,r1,lsr #16 ;@ use only 16 bits of divisor\n");\r
}\r
\r
- ot(";@ Divide r2 by r10\n");\r
+ ot("\n");\r
+ ot(";@ Divide r2 by r0\n");\r
ot(" mov r3,#0\n");\r
- ot(" mov r1,r10\n");\r
+ ot(" mov r1,r0\n");\r
ot("\n");\r
ot(";@ Shift up divisor till it's just less than numerator\n");\r
ot("Shift%.4x%s\n",op,ms?"":":");\r
ot(" cmp r2,r1\n");\r
ot(" adc r3,r3,r3 ;@ Double r3 and add 1 if carry set\n");\r
ot(" subcs r2,r2,r1\n");\r
- ot(" teq r1,r10\n");\r
+ ot(" teq r1,r0\n");\r
ot(" movne r1,r1,lsr #1\n");\r
ot(" bne Divide%.4x\n",op);\r
ot("\n");\r
+ ot(";@r3==quotient,r2==remainder\n");\r
\r
if (sign)\r
{\r
- ot(" tst r11,r11\n");\r
- ot(" rsbne r3,r3,#0 ;@ Negate if result is negative\n");\r
- }\r
+ // sign correction\r
+ ot(" and r1,r12,#1\n");\r
+ ot(" teq r1,r12,lsr #1\n");\r
+ ot(" rsbne r3,r3,#0 ;@ negate if quotient is negative\n");\r
+ ot(" tst r12,#2\n");\r
+ ot(" rsbne r2,r2,#0 ;@ negate the remainder if divident was negative\n");\r
+ ot("\n");\r
\r
- ot(" mov r11,r2 ;@ Remainder\n");\r
+ // signed overflow check\r
+ ot(" mov r1,r3,asl #16\n");\r
+ ot(" cmp r3,r1,asr #16 ;@ signed overflow?\n");\r
+ ot(" orrne r10,r10,#0x10000000 ;@ set overflow flag\n");\r
+ ot(" bne endofop%.4x ;@ overflow!\n",op);\r
+ ot("\n");\r
+ ot("wrendofop%.4x%s\n",op,ms?"":":");\r
+ }\r
+ else\r
+ {\r
+ // overflow check\r
+ ot(" movs r1,r3,lsr #16 ;@ check for overflow condition\n");\r
+ ot(" orrne r10,r10,#0x10000000 ;@ set overflow flag\n");\r
+ ot(" bne endofop%.4x ;@ overflow!\n",op);\r
+ ot("\n");\r
+ }\r
\r
- ot(" adds r1,r3,#0 ;@ Defines NZ, clears CV\n");\r
+ ot(" mov r1,r3,lsl #16 ;@ Clip to 16-bits\n");\r
+ ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
OpGetFlags(0,0);\r
\r
- ot(" mov r1,r1,lsl #16 ;@ Clip to 16-bits\n");\r
ot(" mov r1,r1,lsr #16\n");\r
- ot(" orr r1,r1,r11,lsl #16 ;@ Insert remainder\n");\r
+ ot(" orr r1,r1,r2,lsl #16 ;@ Insert remainder\n");\r
}\r
\r
if (type==1)\r
{\r
- char *shift="asr";\r
-\r
ot(";@ Get 16-bit signs right:\n");\r
- if (sign==0) { ot(" mov r10,r10,lsl #16\n"); shift="lsr"; }\r
+ ot(" mov r0,r1,%s #16\n",sign?"asr":"lsr");\r
ot(" mov r2,r2,lsl #16\n");\r
-\r
- if (sign==0) ot(" mov r10,r10,lsr #16\n");\r
- ot(" mov r2,r2,%s #16\n",shift);\r
+ ot(" mov r2,r2,%s #16\n",sign?"asr":"lsr");\r
ot("\n");\r
\r
- ot(" mul r1,r2,r10\n");\r
+ ot(" mul r1,r2,r0\n");\r
ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
OpGetFlags(0,0);\r
-\r
- if (Amatch && ea==0x3c) Cycles-=4;\r
}\r
ot("\n");\r
\r
- EaWrite(0, 1,rea, 2);\r
+ EaWrite(11, 1,rea, 2,0x0e00,1);\r
\r
+ if (type==0) ot("endofop%.4x%s\n",op,ms?"":":");\r
+ OpEnd(ea);\r
\r
- OpEnd();\r
+ if (type==0) // div\r
+ {\r
+ ot("divzero%.4x%s\n",op,ms?"":":");\r
+ ot(" mov r0,#5 ;@ Divide by zero\n");\r
+ ot(" bl Exception\n");\r
+ Cycles+=38;\r
+ OpEnd(ea);\r
+ ot("\n");\r
+ }\r
\r
return 0;\r
}\r
\r
// Get X Bit into carry - trashes r2\r
-static int GetXBit(int subtract)\r
+int GetXBit(int subtract)\r
{\r
ot(";@ Get X bit:\n");\r
- ot(" ldrb r2,[r7,#0x45]\n");\r
- if (subtract) ot(" mvn r2,r2,lsl #28 ;@ Invert it\n");\r
- else ot(" mov r2,r2,lsl #28\n");\r
+ ot(" ldr r2,[r7,#0x4c]\n");\r
+ if (subtract) ot(" mvn r2,r2 ;@ Invert it\n");\r
ot(" msr cpsr_flg,r2 ;@ Get into Carry\n");\r
ot("\n");\r
return 0;\r
int OpAbcd(int op)\r
{\r
int use=0;\r
- int type=0,sea=0,addr=0,dea=0;\r
+ int type=0,sea=0,mem=0,dea=0;\r
\r
- type=(op>>14)&1;\r
+ type=(op>>14)&1; // sbcd/abcd\r
dea =(op>> 9)&7;\r
- addr=(op>> 3)&1;\r
+ mem =(op>> 3)&1;\r
sea = op &7;\r
\r
- if (addr) { sea|=0x20; dea|=0x20; }\r
+ if (mem) { sea|=0x20; dea|=0x20; }\r
\r
- use=op&~0x0e07; // Use same opcode for all registers\r
+ use=op&~0x0e07; // Use same opcode for all registers..\r
+ if (sea==0x27) use|=0x0007; // ___x.b -(a7)\r
+ if (dea==0x27) use|=0x0e00; // ___x.b -(a7)\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op); Cycles=6;\r
+ OpStart(op,sea,dea); Cycles=6;\r
\r
- EaCalc( 0,0x0007, sea,0);\r
- EaRead( 0, 10, sea,0,1);\r
- EaCalc(11,0x0e00, dea,0);\r
- EaRead(11, 1, dea,0,1);\r
+ if (mem)\r
+ {\r
+ ot(";@ Get src/dest EA vals\n");\r
+ EaCalc (0,0x000f, sea,0,1);\r
+ EaRead (0, 6, sea,0,0x000f,1);\r
+ EaCalcReadNoSE(11,0,dea,0,0x0e00);\r
+ }\r
+ else\r
+ {\r
+ ot(";@ Get src/dest reg vals\n");\r
+ EaCalcReadNoSE(-1,6,sea,0,0x0007);\r
+ EaCalcReadNoSE(11,0,dea,0,0x0e00);\r
+ ot(" mov r6,r6,asl #24\n");\r
+ }\r
+ ot(" mov r1,r0,asl #24\n\n");\r
\r
- ot(" ldrb r2,[r7,#0x45] ;@ Get X bit\n");\r
- ot(" tst r2,#2\n");\r
- ot(" addne r10,r10,#0x01000000 ;@ Add carry bit\n");\r
+ ot(" bic r10,r10,#0xb1000000 ;@ clear all flags except old Z\n");\r
\r
if (type)\r
{\r
- ot(";@ Add units into r2:\n");\r
- ot(" and r2,r1, #0x0f000000\n");\r
- ot(" and r0,r10,#0x0f000000\n");\r
- ot(" add r2,r2,r0\n");\r
- ot(" cmp r2,#0x0a000000\n");\r
- ot(" addpl r1,r1,#0x06000000 ;@ Decimal adjust units\n");\r
- ot(" add r1,r1,r10 ;@ Add BCD\n");\r
- ot(" mov r0,r1,lsr #24\n");\r
- ot(" cmp r0,#0xa0\n");\r
- ot(" addpl r1,r1,#0x60000000 ;@ Decimal adjust tens\n");\r
- OpGetFlags(0,1);\r
+ ot(" ldr r0,[r7,#0x4c] ;@ Get X bit\n");\r
+ ot(" mov r3,#0x00f00000\n");\r
+ ot(" and r2,r3,r1,lsr #4\n");\r
+ ot(" tst r0,#0x20000000\n");\r
+ ot(" and r0,r3,r6,lsr #4\n");\r
+ ot(" add r0,r0,r2\n");\r
+ ot(" addne r0,r0,#0x00100000\n");\r
+// ot(" tst r0,#0x00800000\n");\r
+// ot(" orreq r10,r10,#0x01000000 ;@ Undefined V behavior\n");\r
+ ot(" cmp r0,#0x00900000\n");\r
+ ot(" addhi r0,r0,#0x00600000 ;@ Decimal adjust units\n");\r
+\r
+ ot(" mov r2,r1,lsr #28\n");\r
+ ot(" add r0,r0,r2,lsl #24\n");\r
+ ot(" mov r2,r6,lsr #28\n");\r
+ ot(" add r0,r0,r2,lsl #24\n");\r
+ ot(" cmp r0,#0x09900000\n");\r
+ ot(" orrhi r10,r10,#0x20000000 ;@ C\n");\r
+ ot(" subhi r0,r0,#0x0a000000\n");\r
+// ot(" and r3,r10,r0,lsr #3 ;@ Undefined V behavior part II\n");\r
+// ot(" orr r10,r10,r3,lsl #4 ;@ V\n");\r
+ ot(" movs r0,r0,lsl #4\n");\r
+ ot(" orrmi r10,r10,#0x90000000 ;@ Undefined N+V behavior\n"); // this is what Musashi really does\r
+ ot(" bicne r10,r10,#0x40000000 ;@ Z flag\n");\r
}\r
else\r
{\r
- ot(";@ Sub units into r2:\n");\r
- ot(" and r2,r1, #0x0f000000\n");\r
- ot(" and r0,r10,#0x0f000000\n");\r
- ot(" subs r2,r2,r0\n");\r
- ot(" submi r1,r1,#0x06000000 ;@ Decimal adjust units\n");\r
- ot(" subs r1,r1,r10 ;@ Subtract BCD\n");\r
- ot(" submis r1,r1,#0x60000000 ;@ Decimal adjust tens\n");\r
- OpGetFlags(1,1);\r
+ ot(" ldr r0,[r7,#0x4c] ;@ Get X bit\n");\r
+ ot(" mov r3,#0x00f00000\n");\r
+ ot(" and r2,r3,r6,lsr #4\n");\r
+ ot(" tst r0,#0x20000000\n");\r
+ ot(" and r0,r3,r1,lsr #4\n");\r
+ ot(" sub r0,r0,r2\n");\r
+ ot(" subne r0,r0,#0x00100000\n");\r
+// ot(" tst r0,#0x00800000\n");\r
+// ot(" orreq r10,r10,#0x01000000 ;@ Undefined V behavior\n");\r
+ ot(" cmp r0,#0x00900000\n");\r
+ ot(" subhi r0,r0,#0x00600000 ;@ Decimal adjust units\n");\r
+\r
+ ot(" mov r2,r1,lsr #28\n");\r
+ ot(" add r0,r0,r2,lsl #24\n");\r
+ ot(" mov r2,r6,lsr #28\n");\r
+ ot(" sub r0,r0,r2,lsl #24\n");\r
+ ot(" cmp r0,#0x09900000\n");\r
+ ot(" orrhi r10,r10,#0xa0000000 ;@ N and C\n");\r
+ ot(" addhi r0,r0,#0x0a000000\n");\r
+// ot(" and r3,r10,r0,lsr #3 ;@ Undefined V behavior part II\n");\r
+// ot(" orr r10,r10,r3,lsl #4 ;@ V\n");\r
+ ot(" movs r0,r0,lsl #4\n");\r
+// ot(" orrmi r10,r10,#0x80000000 ;@ Undefined N behavior\n");\r
+ ot(" bicne r10,r10,#0x40000000 ;@ Z flag\n");\r
}\r
+\r
+ ot(" str r10,[r7,#0x4c] ;@ Save X bit\n");\r
+ ot("\n");\r
+\r
+ EaWrite(11, 0, dea,0,0x0e00,1);\r
+\r
+ ot(" ldr r6,[r7,#0x54]\n");\r
+ OpEnd(sea,dea);\r
+\r
+ return 0;\r
+}\r
+\r
+// 01001000 00eeeeee - nbcd <ea>\r
+int OpNbcd(int op)\r
+{\r
+ int use=0;\r
+ int ea=0;\r
+ \r
+ ea=op&0x3f;\r
+\r
+ if(EaCanWrite(ea)==0||EaAn(ea)) return 1;\r
+\r
+ use=OpBase(op,0);\r
+ if(op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
+\r
+ OpStart(op,ea); Cycles=6;\r
+ if(ea >= 8) Cycles+=2;\r
+\r
+ EaCalcReadNoSE(6,0,ea,0,0x003f);\r
+\r
+ // this is rewrite of Musashi's code\r
+ ot(" ldr r2,[r7,#0x4c]\n");\r
+ ot(" bic r10,r10,#0xb0000000 ;@ clear all flags, except Z\n");\r
+ ot(" mov r0,r0,asl #24\n");\r
+ ot(" and r2,r2,#0x20000000\n");\r
+ ot(" add r2,r0,r2,lsr #5 ;@ add X\n");\r
+ ot(" rsb r11,r2,#0x9a000000 ;@ do arithmetic\n");\r
+\r
+ ot(" cmp r11,#0x9a000000\n");\r
+ ot(" beq finish%.4x\n",op);\r
ot("\n");\r
\r
- EaWrite(11, 1, dea,0,1);\r
+ ot(" mvn r3,r11,lsr #31 ;@ Undefined V behavior\n",op);\r
+ ot(" and r2,r11,#0x0f000000\n");\r
+ ot(" cmp r2,#0x0a000000\n");\r
+ ot(" andeq r11,r11,#0xf0000000\n");\r
+ ot(" addeq r11,r11,#0x10000000\n");\r
+ ot(" and r3,r3,r11,lsr #31 ;@ Undefined V behavior part II\n",op);\r
+ ot(" movs r1,r11,asr #24\n");\r
+ ot(" bicne r10,r10,#0x40000000 ;@ Z\n");\r
+ ot(" orr r10,r10,r3,lsl #28 ;@ save V\n",op);\r
+ ot(" orr r10,r10,#0x20000000 ;@ C\n");\r
+ ot("\n");\r
+\r
+ EaWrite(6, 1, ea,0,0x3f,0,0);\r
+\r
+ ot("finish%.4x%s\n",op,ms?"":":");\r
+ ot(" tst r11,r11\n");\r
+ ot(" orrmi r10,r10,#0x80000000 ;@ N\n");\r
+ ot(" str r10,[r7,#0x4c] ;@ Save X\n");\r
+ ot("\n");\r
\r
- OpEnd();\r
+ ot(" ldr r6,[r7,#0x54]\n");\r
+ OpEnd(ea);\r
\r
return 0;\r
}\r
{\r
int use=0;\r
int type=0,size=0,sea=0,dea=0;\r
+ const char *asr="";\r
\r
// Suba/Cmpa/Adda/(invalid):\r
type=(op>>13)&3; if (type>=3) return 1;\r
// See if we can do this opcode:\r
if (EaCanRead(sea,size)==0) return 1;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
use&=~0x0e00; // Use same opcode for An\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op); Cycles=4;\r
- EaCalc ( 0,0x003f, sea,size);\r
- EaRead ( 0, 10, sea,size);\r
+ OpStart(op,sea); Cycles=(size==2)?6:8;\r
+ if(size==2&&(sea<0x10||sea==0x3c)) Cycles+=2;\r
+ if(type==1) Cycles=6;\r
+\r
+ // EA calculation order defines how situations like suba.w (A0)+, A0 get handled.\r
+ // different emus act differently in this situation, I couldn't fugure which is right behaviour.\r
+ //if (type == 1)\r
+ {\r
+ EaCalcReadNoSE(-1,0,sea,size,0x003f);\r
+ EaCalcReadNoSE(type!=1?11:-1,1,dea,2,0x0e00);\r
+ }\r
+#if 0\r
+ else\r
+ {\r
+ EaCalcReadNoSE(type!=1?11:-1,1,dea,2,0x0e00);\r
+ EaCalcReadNoSE(-1,0,sea,size,0x003f);\r
+ }\r
+#endif\r
\r
- EaCalc ( 0,0x0e00, dea,2);\r
- EaRead ( 0, 1, dea,2);\r
+ if (size<2) ot(" mov r0,r0,asl #%d\n\n",size?16:24);\r
+ if (size<2) asr=(char *)(size?",asr #16":",asr #24");\r
\r
- if (type==0) ot(" sub r1,r1,r10\n");\r
- if (type==1) ot(" cmp r1,r10 ;@ Defines NZCV\n");\r
+ if (type==0) ot(" sub r1,r1,r0%s\n",asr);\r
+ if (type==1) ot(" cmp r1,r0%s ;@ Defines NZCV\n",asr);\r
if (type==1) OpGetFlags(1,0); // Get Cmp flags\r
- if (type==2) ot(" add r1,r1,r10\n");\r
+ if (type==2) ot(" add r1,r1,r0%s\n",asr);\r
ot("\n");\r
- \r
- EaWrite( 0, 1, dea,2);\r
\r
- if (Amatch && sea==0x3c) Cycles-=size<2?4:8; // Correct?\r
- if (size>=2) { if (sea<0x10) Cycles+=4; else Cycles+=2; }\r
+ if (type!=1) EaWrite(11, 1, dea,2,0x0e00);\r
\r
- OpEnd();\r
+ OpEnd(sea);\r
\r
return 0;\r
}\r
\r
// --------------------- Opcodes 0x9100+ ---------------------\r
-// Emit a Subx/Addx opcode, 1t01ddd1 zz000sss addx.z Ds,Dd\r
+// Emit a Subx/Addx opcode, 1t01ddd1 zz00rsss addx.z Ds,Dd\r
int OpAddx(int op)\r
{\r
int use=0;\r
- int type=0,size=0,dea=0,sea=0;\r
+ int type=0,size=0,dea=0,sea=0,mem=0;\r
+ const char *asl="";\r
\r
- type=(op>>12)&5;\r
+ type=(op>>14)&1;\r
dea =(op>> 9)&7;\r
size=(op>> 6)&3; if (size>=3) return 1;\r
- sea = op&0x3f;\r
+ sea = op&7;\r
+ mem =(op>> 3)&1;\r
\r
// See if we can do this opcode:\r
if (EaCanRead(sea,size)==0) return 1;\r
if (EaCanWrite(dea)==0) return 1;\r
\r
- use=OpBase(op);\r
- use&=~0x0e00; // Use same opcode for Dn\r
+ if (mem) { sea+=0x20; dea+=0x20; }\r
+\r
+ use=op&~0x0e07; // Use same opcode for Dn\r
+ if (size==0&&sea==0x27) use|=0x0007; // ___x.b -(a7)\r
+ if (size==0&&dea==0x27) use|=0x0e00; // ___x.b -(a7)\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op); Cycles=8;\r
+ OpStart(op,sea,dea); Cycles=4;\r
+ if(size>=2) Cycles+=4;\r
+ if(sea>=0x10) Cycles+=2;\r
\r
- ot(";@ Get r10=EA r11=EA value\n");\r
- EaCalc( 0,0x003f,sea,size);\r
- EaRead( 0, 11,sea,size,1);\r
- ot(";@ Get r0=Register r1=Register value\n");\r
- EaCalc( 0,0x0e00,dea,size);\r
- EaRead( 0, 1,dea,size,1);\r
+ if (mem)\r
+ {\r
+ ot(";@ Get src/dest EA vals\n");\r
+ EaCalc (0,0x000f, sea,size,1);\r
+ EaRead (0, 6, sea,size,0x000f,1);\r
+ EaCalcReadNoSE(11,0,dea,size,0x0e00);\r
+ }\r
+ else\r
+ {\r
+ ot(";@ Get src/dest reg vals\n");\r
+ EaCalcReadNoSE(-1,6,sea,size,0x0007);\r
+ EaCalcReadNoSE(11,0,dea,size,0x0e00);\r
+ if (size<2) ot(" mov r6,r6,asl #%d\n\n",size?16:24);\r
+ }\r
+\r
+ if (size<2) asl=(char *)(size?",asl #16":",asl #24");\r
\r
ot(";@ Do arithmetic:\n");\r
- GetXBit(type==1);\r
+ GetXBit(type==0);\r
\r
- if (type==5 && size<2)\r
+ if (type==1 && size<2)\r
{\r
ot(";@ Make sure the carry bit will tip the balance:\n");\r
- if (size==0) ot(" ldr r2,=0x00ffffff\n");\r
- else ot(" ldr r2,=0x0000ffff\n");\r
- ot(" orr r11,r11,r2\n");\r
+ ot(" mvn r2,#0\n");\r
+ ot(" orr r6,r6,r2,lsr #%i\n",(size==0)?8:16);\r
ot("\n");\r
}\r
\r
- if (type==1) ot(" sbcs r1,r1,r11\n");\r
- if (type==5) ot(" adcs r1,r1,r11\n");\r
- OpGetFlags(type==1,1); // subtract\r
+ if (type==0) ot(" rscs r1,r6,r0%s\n",asl);\r
+ if (type==1) ot(" adcs r1,r6,r0%s\n",asl);\r
+ ot(" orr r3,r10,#0xb0000000 ;@ for old Z\n");\r
+ OpGetFlags(type==0,1,0); // subtract\r
+ if (size<2) {\r
+ ot(" movs r2,r1,lsr #%i\n", size?16:24);\r
+ ot(" orreq r10,r10,#0x40000000 ;@ add potentially missed Z\n");\r
+ }\r
+ ot(" andeq r10,r10,r3 ;@ fix Z\n");\r
ot("\n");\r
\r
ot(";@ Save result:\n");\r
- EaWrite( 0, 1, dea,size,1);\r
+ EaWrite(11, 1, dea,size,0x0e00,1);\r
\r
- OpEnd();\r
+ ot(" ldr r6,[r7,#0x54]\n");\r
+ OpEnd(sea,dea);\r
\r
return 0;\r
}\r
{\r
int rea=0,eor=0;\r
int size=0,ea=0,use=0;\r
+ const char *asl="";\r
\r
// Get EA and register EA\r
rea=(op>>9)&7;\r
size=(op>>6)&3; if (size>=3) return 1;\r
ea=op&0x3f;\r
\r
+ if (eor && (ea>>3) == 1) return 1; // not a valid mode for eor\r
+\r
// See if we can do this opcode:\r
if (EaCanRead(ea,size)==0) return 1;\r
if (eor && EaCanWrite(ea)==0) return 1;\r
+ if (EaAn(ea)&&(eor||size==0)) return 1;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
use&=~0x0e00; // Use 1 handler for register d0-7\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op); Cycles=eor?8:4;\r
+ OpStart(op,ea); Cycles=4;\r
+ if(eor) {\r
+ if(ea>8) Cycles+=4;\r
+ if(size>=2) Cycles+=4;\r
+ } else {\r
+ if(size>=2) Cycles+=2;\r
+ }\r
\r
- ot(";@ Get EA into r10 and value into r0:\n");\r
- EaCalc (10,0x003f, ea,size);\r
- EaRead (10, 0, ea,size,1);\r
+ ot(";@ Get EA into r11 and value into r0:\n");\r
+ EaCalcReadNoSE(eor?11:-1,0,ea,size,0x003f);\r
\r
ot(";@ Get register operand into r1:\n");\r
- EaCalc (1 ,0x0e00, rea,size);\r
- EaRead (1, 1, rea,size,1);\r
+ EaCalcReadNoSE(-1,1,rea,size,0x0e00);\r
+\r
+ if (size<2) ot(" mov r0,r0,asl #%d\n\n",size?16:24);\r
+ if (size<2) asl=(char *)(size?",asl #16":",asl #24");\r
\r
ot(";@ Do arithmetic:\n");\r
- if (eor==0) ot(" cmp r1,r0\n");\r
+ if (eor==0) ot(" rsbs r1,r0,r1%s\n",asl);\r
if (eor)\r
{\r
- ot(" eor r1,r0,r1\n");\r
+ ot(" eor r1,r0,r1%s\n",asl);\r
ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
}\r
\r
OpGetFlags(eor==0,0); // Cmp like subtract\r
ot("\n");\r
\r
- if (size>=2) Cycles+=4; // Correct?\r
- if (ea==0x3c) Cycles-=4;\r
+ if (eor) EaWrite(11, 1,ea,size,0x003f,1);\r
+\r
+ OpEnd(ea);\r
+ return 0;\r
+}\r
+\r
+// Emit a Cmpm opcode, 1011ddd1 xx001sss (rrr=Adst, xx=size extension, sss=Asrc)\r
+int OpCmpm(int op)\r
+{\r
+ int size=0,sea=0,dea=0,use=0;\r
+ const char *asl="";\r
+\r
+ // get size, get EAs\r
+ size=(op>>6)&3; if (size>=3) return 1;\r
+ sea=(op&7)|0x18;\r
+ dea=(op>>9)&0x3f;\r
+\r
+ use=op&~0x0e07; // Use 1 handler for all registers..\r
+ if (size==0&&sea==0x1f) use|=0x0007; // ..except (a7)+\r
+ if (size==0&&dea==0x1f) use|=0x0e00;\r
+ if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
+\r
+ OpStart(op,sea); Cycles=4;\r
+\r
+ ot(";@ Get src operand into r11:\n");\r
+ EaCalc (0,0x0007, sea,size,1);\r
+ EaRead (0, 11, sea,size,0x0007,1);\r
+\r
+ ot(";@ Get dst operand into r0:\n");\r
+ EaCalcReadNoSE(-1,0,dea,size,0x0e00);\r
+\r
+ if (size<2) asl=(char *)(size?",asl #16":",asl #24");\r
+\r
+ ot(" rsbs r0,r11,r0%s\n",asl);\r
+ OpGetFlags(1,0); // Cmp like subtract\r
+ ot("\n");\r
+\r
+ OpEnd(sea);\r
+ return 0;\r
+}\r
+\r
+\r
+// Emit a Chk opcode, 0100ddd1 x0eeeeee (rrr=Dn, x=size extension, eeeeee=ea)\r
+int OpChk(int op)\r
+{\r
+ int rea=0;\r
+ int size=0,ea=0,use=0;\r
+\r
+ // Get EA and register EA\r
+ rea=(op>>9)&7;\r
+ if((op>>7)&1)\r
+ size=1; // word operation\r
+ else size=2; // long\r
+ ea=op&0x3f;\r
+\r
+ if (EaAn(ea)) return 1; // not a valid mode\r
+ if (size!=1) return 1; // 000 variant only supports word\r
+\r
+ // See if we can do this opcode:\r
+ if (EaCanRead(ea,size)==0) return 1;\r
+\r
+ use=OpBase(op,size);\r
+ use&=~0x0e00; // Use 1 handler for register d0-7\r
+ if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
+\r
+ OpStart(op,ea); Cycles=10;\r
+\r
+ ot(";@ Get value into r0:\n");\r
+ EaCalcReadNoSE(-1,0,ea,size,0x003f);\r
+\r
+ ot(";@ Get register operand into r1:\n");\r
+ EaCalcReadNoSE(-1,1,rea,size,0x0e00);\r
+\r
+ if (size<2) ot(" mov r0,r0,asl #%d\n",size?16:24);\r
+ if (size<2) ot(" mov r1,r1,asl #%d\n\n",size?16:24);\r
+\r
+ ot(";@ get flags, including undocumented ones\n");\r
+ ot(" and r3,r10,#0x80000000\n");\r
+ ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
+ OpGetFlags(0,0);\r
+\r
+ ot(";@ is reg negative?\n");\r
+ ot(" bmi chktrap%.4x\n",op);\r
+\r
+ ot(";@ Do arithmetic:\n");\r
+ ot(" bic r10,r10,#0x80000000 ;@ N\n");\r
+ ot(" cmp r1,r0\n");\r
+ ot(" bgt chktrap%.4x\n",op);\r
+\r
+ ot(";@ old N remains\n");\r
+ ot(" orr r10,r10,r3\n");\r
+ OpEnd(ea);\r
\r
- if (eor) EaWrite(10, 1,ea,size,1);\r
+ ot("chktrap%.4x%s ;@ CHK exception:\n",op,ms?"":":");\r
+ ot(" mov r0,#6\n");\r
+ ot(" bl Exception\n");\r
+ Cycles+=40;\r
+ OpEnd(ea);\r
\r
- OpEnd();\r
return 0;\r
}\r
\r
\r
// This file is part of the Cyclone 68000 Emulator\r
\r
-// Copyright (c) 2011 FinalDave (emudave (at) gmail.com)\r
+// Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)\r
+// Copyright (c) 2005-2011 Gražvydas "notaz" Ignotas (notasas (at) gmail.com)\r
\r
// This code is licensed under the GNU General Public License version 2.0 and the MAME License.\r
// You can choose the license that has the most advantages for you.\r
\r
// SVN repository can be found at http://code.google.com/p/cyclone68000/\r
\r
+\r
#include "app.h"\r
\r
-static void CheckPc()\r
+// in/out address in r0, trashes all temp regs\r
+static void CheckPc(void)\r
{\r
- ot(";@ Check Memory Base+pc (r4)\n");\r
- ot(" add lr,pc,#4\n");\r
- ot(" mov r0,r4\n");\r
+#if USE_CHECKPC_CALLBACK\r
+ #ifdef MEMHANDLERS_DIRECT_PREFIX\r
+ ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);\r
+ #else\r
+ ot(";@ Check Memory Base+pc\n");\r
+ ot(" mov lr,pc\n");\r
ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
- ot(" mov r4,r0\n");\r
ot("\n");\r
+ #endif\r
+#endif\r
}\r
\r
-// Push 32-bit value in r1 - trashes r0-r3\r
+// Push 32-bit value in r1 - trashes r0-r3,r12,lr\r
void OpPush32()\r
{\r
ot(";@ Push r1 onto stack\n");\r
ot("\n");\r
}\r
\r
-// Push SR - trashes r0-r3\r
+// Push SR - trashes r0-r3,r12,lr\r
void OpPushSr(int high)\r
{\r
ot(";@ Push SR:\n");\r
OpRegToFlags(high);\r
}\r
\r
-// Pop PC - assumes r10=Memory Base - trashes r0-r3\r
+// Pop PC - trashes r0-r3\r
static void PopPc()\r
{\r
ot(";@ Pop PC:\n");\r
ot(" add r1,r0,#4 ;@ Postincrement A7\n");\r
ot(" str r1,[r7,#0x3c] ;@ Save A7\n");\r
MemHandler(0,2);\r
- ot(" add r4,r0,r10 ;@ r4=Memory Base+PC\n");\r
+ ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");\r
+ ot(" add r0,r0,r1 ;@ Memory Base+PC\n");\r
ot("\n");\r
CheckPc();\r
+#if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" mov r4,r0\n");\r
+#else\r
+ ot(" bic r4,r0,#1\n");\r
+#endif\r
}\r
\r
int OpTrap(int op)\r
use=op&~0xf;\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(use);\r
+ OpStart(op,0x10);\r
ot(" and r0,r8,#0xf ;@ Get trap number\n");\r
- ot(" orr r0,r0,#0x20\n");\r
- ot(" mov r0,r0,asl #2\n");\r
- ot(" str r0,[r7,#0x50] ;@ Save Exception Vector\n");\r
+ ot(" orr r0,r0,#0x20 ;@ 32+n\n");\r
ot(" bl Exception\n");\r
ot("\n");\r
\r
- Cycles=38; OpEnd();\r
+ Cycles=38; OpEnd(0x10);\r
\r
return 0;\r
}\r
// --------------------- Opcodes 0x4e50+ ---------------------\r
int OpLink(int op)\r
{\r
- int use=0;\r
+ int use=0,reg;\r
\r
use=op&~7;\r
+ reg=op&7;\r
+ if (reg==7) use=op;\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(use);\r
+ OpStart(op,0x10);\r
\r
- ot(";@ Get An\n");\r
- EaCalc(10, 7, 8, 2);\r
- EaRead(10, 1, 8, 2, 1);\r
+ if(reg!=7) {\r
+ ot(";@ Get An\n");\r
+ EaCalc(11, 7, 8, 2, 1);\r
+ EaRead(11, 1, 8, 2, 7, 1);\r
+ }\r
\r
ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");\r
ot(" sub r0,r0,#4 ;@ A7-=4\n");\r
- ot(" mov r11,r0\n");\r
+ ot(" mov r8,r0 ;@ abuse r8\n");\r
+ if(reg==7) ot(" mov r1,r0\n");\r
ot("\n");\r
\r
ot(";@ Write An to Stack\n");\r
MemHandler(1,2);\r
\r
ot(";@ Save to An\n");\r
- EaWrite(10,11, 8, 2, 1);\r
+ if(reg!=7)\r
+ EaWrite(11,8, 8, 2, 7, 1);\r
\r
ot(";@ Get offset:\n");\r
- EaCalc(0,0,0x3c,1);\r
- EaRead(0,0,0x3c,1);\r
+ EaCalc(0,0,0x3c,1); // abused r8 is ok because of imm EA\r
+ EaRead(0,0,0x3c,1,0);\r
\r
- ot(" add r11,r11,r0 ;@ Add offset to A7\n");\r
- ot(" str r11,[r7,#0x3c]\n");\r
+ ot(" add r8,r8,r0 ;@ Add offset to A7\n");\r
+ ot(" str r8,[r7,#0x3c]\n");\r
ot("\n");\r
\r
Cycles=16;\r
- OpEnd();\r
+ OpEnd(0x10);\r
return 0;\r
}\r
\r
use=op&~7;\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(use);\r
+ OpStart(op,0x10);\r
\r
ot(";@ Get An\n");\r
- EaCalc(10, 7, 8, 2);\r
- EaRead(10, 0, 8, 2, 1);\r
+ EaCalc(11, 0xf, 8, 2, 1);\r
+ EaRead(11, 0, 8, 2, 0xf, 1);\r
\r
- ot(" add r11,r0,#4 ;@ A7+=4\n");\r
+ ot(" add r8,r0,#4 ;@ A7+=4, abuse r8\n");\r
ot("\n");\r
ot(";@ Pop An from stack:\n");\r
MemHandler(0,2);\r
ot("\n");\r
- ot(" str r11,[r7,#0x3c] ;@ Save A7\n");\r
+ ot(" str r8,[r7,#0x3c] ;@ Save A7\n");\r
ot("\n");\r
ot(";@ An = value from stack:\n");\r
- EaWrite(10, 0, 8, 2, 1);\r
- \r
+ EaWrite(11, 0, 8, 2, 7, 1);\r
+\r
Cycles=12;\r
- OpEnd();\r
+ OpEnd(0x10);\r
return 0;\r
}\r
\r
// --------------------- Opcodes 0x4e70+ ---------------------\r
+// 01001110 01110ttt\r
int Op4E70(int op)\r
{\r
int type=0;\r
\r
- type=op&7;\r
- // 01001110 01110ttt, reset/nop/stop/rte/rtd/rts/trapv/rtr\r
- if (type==1) { OpStart(op); Cycles=4; OpEnd(); return 0; } // nop\r
+ type=op&7; // reset/nop/stop/rte/rtd/rts/trapv/rtr\r
\r
- if (type==3 || type==7) // rte/rtr\r
+ switch (type)\r
{\r
- OpStart(op); Cycles=20;\r
- PopSr(type==3);\r
- ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
- PopPc();\r
- if (type==3) CheckInterrupt();\r
+ case 1: // nop\r
+ OpStart(op);\r
+ Cycles=4;\r
OpEnd();\r
return 0;\r
- }\r
\r
- if (type==5) // rts\r
- {\r
- OpStart(op); Cycles=16;\r
- ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
+ case 3: // rte\r
+ OpStart(op,0x10,0,0,1); Cycles=20;\r
+ PopSr(1);\r
PopPc();\r
- OpEnd();\r
+ ot(" ldr r1,[r7,#0x44] ;@ reload SR high\n");\r
+ SuperChange(op,1);\r
+#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO || EMULATE_HALT\r
+ ot(" ldr r1,[r7,#0x58]\n");\r
+ ot(" bic r1,r1,#0x0c ;@ clear 'not processing instruction' and 'doing addr error' bits\n");\r
+ ot(" str r1,[r7,#0x58]\n");\r
+#endif\r
+#if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" tst r4,#1 ;@ address error?\n");\r
+ ot(" bne ExceptionAddressError_r_prg_r4\n");\r
+#endif\r
+ opend_check_interrupt = 1;\r
+ opend_check_trace = 1;\r
+ OpEnd(0x10,0);\r
+ return 0;\r
+\r
+ case 5: // rts\r
+ OpStart(op,0x10); Cycles=16;\r
+ PopPc();\r
+#if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" tst r4,#1 ;@ address error?\n");\r
+ ot(" bne ExceptionAddressError_r_prg_r4\n");\r
+#endif\r
+ OpEnd(0x10);\r
+ return 0;\r
+\r
+ case 6: // trapv\r
+ OpStart(op,0x10,0,1); Cycles=4;\r
+ ot(" tst r10,#0x10000000\n");\r
+ ot(" subne r5,r5,#%i\n",34);\r
+ ot(" movne r0,#7 ;@ TRAPV exception\n");\r
+ ot(" blne Exception\n");\r
+ opend_op_changes_cycles = 1;\r
+ OpEnd(0x10,0);\r
return 0;\r
- }\r
\r
- return 1;\r
+ case 7: // rtr\r
+ OpStart(op,0x10); Cycles=20;\r
+ PopSr(0);\r
+ PopPc();\r
+#if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" tst r4,#1 ;@ address error?\n");\r
+ ot(" bne ExceptionAddressError_r_prg_r4\n");\r
+#endif\r
+ OpEnd(0x10);\r
+ return 0;\r
+\r
+ default:\r
+ return 1;\r
+ }\r
}\r
\r
// --------------------- Opcodes 0x4e80+ ---------------------\r
-// Emit a Jsr/Jmp opcode, 01001110 1mEEEeee\r
+// Emit a Jsr/Jmp opcode, 01001110 1meeeeee\r
int OpJsr(int op)\r
{\r
int use=0;\r
// See if we can do this opcode:\r
if (EaCanRead(sea,-1)==0) return 1;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,0);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op); Cycles=14; // Correct?\r
+ OpStart(op,(op&0x40)?0:0x10);\r
\r
- ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
+ ot(" ldr r11,[r7,#0x60] ;@ Get Memory base\n");\r
ot("\n");\r
- EaCalc(0,0x003f,sea,0);\r
+ EaCalc(12,0x003f,sea,0);\r
\r
- ot(";@ Jump - Get new PC from r0\n");\r
- if (op&0x40)\r
+ ot(";@ Jump - Get new PC from r12\n");\r
+ ot(" add r0,r12,r11 ;@ Memory Base + New PC\n");\r
+ ot("\n");\r
+ CheckPc();\r
+ if (!(op&0x40))\r
{\r
- // Jmp - Get new PC from r0\r
- ot(" add r4,r0,r10 ;@ r4 = Memory Base + New PC\n");\r
- ot("\n");\r
+ ot(" ldr r2,[r7,#0x3c]\n");\r
+ ot(" sub r1,r4,r11 ;@ r1 = Old PC\n");\r
}\r
- else\r
- {\r
- ot(";@ Jsr - Push old PC first\n");\r
- ot(" sub r1,r4,r10 ;@ r1 = Old PC\n");\r
- ot(" add r4,r0,r10 ;@ r4 = Memory Base + New PC\n");\r
- ot("\n");\r
- OpPush32();\r
+#if EMULATE_ADDRESS_ERRORS_JUMP\r
+ // jsr prefetches next instruction before pushing old PC,\r
+ // according to http://pasti.fxatari.com/68kdocs/68kPrefetch.html\r
+ ot(" mov r4,r0\n");\r
+ ot(" tst r4,#1 ;@ address error?\n");\r
+ ot(" bne ExceptionAddressError_r_prg_r4\n");\r
+#else\r
+ ot(" bic r4,r0,#1\n");\r
+#endif\r
\r
- Cycles+=8;\r
+ if (!(op&0x40))\r
+ {\r
+ ot(";@ Push old PC onto stack\n");\r
+ ot(" sub r0,r2,#4 ;@ Predecrement A7\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ MemHandler(1,2);\r
}\r
\r
- if (Amatch && sea==0x10) Cycles-=2; // (An) Correct?\r
-\r
- CheckPc();\r
+ Cycles=(op&0x40) ? 4 : 12;\r
+ Cycles+=Ea_add_ns((op&0x40) ? g_jmp_cycle_table : g_jsr_cycle_table, sea);\r
\r
- OpEnd();\r
+ OpEnd((op&0x40)?0:0x10);\r
\r
return 0;\r
}\r
// --------------------- Opcodes 0x50c8+ ---------------------\r
\r
// ARM version of 68000 condition codes:\r
-static char *Cond[16]=\r
+static const char * const Cond[16]=\r
{\r
"", "", "hi","ls","cc","cs","ne","eq",\r
"vc","vs","pl","mi","ge","lt","gt","le"\r
cc=(op>>8)&15;\r
\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
- OpStart(op); Cycles=10;\r
-\r
- ot(";@ Decrement Dn.w\n");\r
- ot(" and r1,r8,#0x0007\n");\r
- ot(" mov r1,r1,lsl #2\n");\r
- ot(" ldrsh r0,[r7,r1]\n");\r
- ot(" sub r0,r0,#1\n");\r
- ot(" strh r0,[r7,r1]\n");\r
- ot("\n");\r
+ OpStart(op);\r
\r
- if (cc>=2)\r
+ switch (cc)\r
{\r
- ot(";@ Is the condition true?\n");\r
- if ((cc&~1)==2) ot(" eor r9,r9,#0x20000000 ;@ Invert carry for hi/ls\n");\r
- ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");\r
- if ((cc&~1)==2) ot(" eor r9,r9,#0x20000000\n");\r
- ot(";@ If so, don't dbra\n");\r
- ot(" b%s DbraEnd%.4x\n",Cond[cc],op);\r
- ot("\n");\r
+ case 0: // T\r
+ case 1: // F\r
+ break;\r
+ case 2: // hi\r
+ ot(" tst r10,#0x60000000 ;@ hi: !C && !Z\n");\r
+ ot(" beq DbraTrue\n\n");\r
+ break;\r
+ case 3: // ls\r
+ ot(" tst r10,#0x60000000 ;@ ls: C || Z\n");\r
+ ot(" bne DbraTrue\n\n");\r
+ break;\r
+ default:\r
+ ot(";@ Is the condition true?\n");\r
+ ot(" msr cpsr_flg,r10 ;@ ARM flags = 68000 flags\n");\r
+ ot(";@ If so, don't dbra\n");\r
+ ot(" b%s DbraTrue\n\n",Cond[cc]);\r
+ break;\r
}\r
\r
- ot(";@ Check if Dn.w is -1\n");\r
- ot(" cmps r0,#-1\n");\r
- ot(" beq DbraEnd%.4x\n",op);\r
- ot("\n");\r
+ if (cc!=0)\r
+ {\r
+ ot(";@ Decrement Dn.w\n");\r
+ ot(" and r1,r8,#0x0007\n");\r
+ ot(" mov r1,r1,lsl #2\n");\r
+ ot(" ldrsh r0,[r7,r1]\n");\r
+ ot(" sub r0,r0,#1\n");\r
+ ot(" strh r0,[r7,r1]\n");\r
+ ot("\n");\r
\r
- ot(";@ Get Branch offset:\n");\r
- ot(" ldrsh r0,[r4]\n");\r
- ot(" add r4,r4,r0 ;@ r4 = New PC\n");\r
- ot("\n");\r
- OpEnd();\r
+ ot(";@ Check if Dn.w is -1\n");\r
+ ot(" cmn r0,#1\n");\r
+\r
+#if (USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA) || EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" beq DbraMin1\n");\r
+ ot("\n");\r
+\r
+ ot(";@ Get Branch offset:\n");\r
+ ot(" ldrsh r0,[r4]\n");\r
+ ot(" add r0,r4,r0 ;@ r0 = New PC\n");\r
+ CheckPc();\r
+#if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" mov r4,r0\n");\r
+ ot(" tst r4,#1 ;@ address error?\n");\r
+ ot(" bne ExceptionAddressError_r_prg_r4\n");\r
+#else\r
+ ot(" bic r4,r0,#1\n");\r
+#endif\r
+#else\r
+ ot("\n");\r
+ ot(";@ Get Branch offset:\n");\r
+ ot(" ldrnesh r0,[r4]\n");\r
+ ot(" addeq r4,r4,#2 ;@ Skip branch offset\n");\r
+ ot(" subeq r5,r5,#4 ;@ additional cycles\n");\r
+ ot(" addne r4,r4,r0 ;@ r4 = New PC\n");\r
+ ot(" bic r4,r4,#1\n"); // we do not emulate address errors\r
+ ot("\n");\r
+#endif\r
+ Cycles=12-2;\r
+ OpEnd();\r
+ }\r
\r
- ot("DbraEnd%.4x%s\n", op, ms?"":":");\r
- Cycles+=2;\r
- ot(" add r4,r4,#2 ;@ Skip branch offset\n");\r
- ot("\n");\r
- OpEnd();\r
+ //if (cc==0||cc>=2)\r
+ if (op==0x50c8)\r
+ {\r
+ ot(";@ condition true:\n");\r
+ ot("DbraTrue%s\n", ms?"":":");\r
+ ot(" add r4,r4,#2 ;@ Skip branch offset\n");\r
+ ot("\n");\r
+ Cycles=12;\r
+ OpEnd();\r
+ }\r
+\r
+#if (USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA) || EMULATE_ADDRESS_ERRORS_JUMP\r
+ if (op==0x51c8)\r
+ {\r
+ ot(";@ Dn.w is -1:\n");\r
+ ot("DbraMin1%s\n", ms?"":":");\r
+ ot(" add r4,r4,#2 ;@ Skip branch offset\n");\r
+ ot("\n");\r
+ Cycles=12+2;\r
+ OpEnd();\r
+ }\r
+#endif\r
\r
return 0;\r
}\r
// Emit a Branch opcode 0110cccc nn (cccc=condition)\r
int OpBranch(int op)\r
{\r
- int size=0,use=0;\r
+ int size=0,use=0,checkpc=0;\r
int offset=0;\r
int cc=0;\r
+ const char *asr_r11="";\r
\r
offset=(char)(op&0xff);\r
cc=(op>>8)&15;\r
if (offset==0) size=1;\r
if (offset==-1) size=2;\r
\r
+ if (size==2) size=0; // 000 model does not support long displacement\r
if (size) use=op; // 16-bit or 32-bit\r
else use=(op&0xff00)+1; // Use same opcode for all 8-bit branches\r
\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
- OpStart(op); Cycles=10; // Assume branch taken\r
+ OpStart(op,size?0x10:0);\r
+ Cycles=10; // Assume branch taken\r
\r
- ot(";@ Get Branch offset:\n");\r
- if (size)\r
+ switch (cc)\r
{\r
- EaCalc(0,0,0x3c,size);\r
- EaRead(0,0,0x3c,size);\r
- if (Amatch && size==1) Cycles-=4;\r
+ case 0: // T\r
+ case 1: // F\r
+ break;\r
+ case 2: // hi\r
+ ot(" tst r10,#0x60000000 ;@ hi: !C && !Z\n");\r
+ ot(" bne BccDontBranch%i\n\n",8<<size);\r
+ break;\r
+ case 3: // ls\r
+ ot(" tst r10,#0x60000000 ;@ ls: C || Z\n");\r
+ ot(" beq BccDontBranch%i\n\n",8<<size);\r
+ break;\r
+ default:\r
+ ot(";@ Is the condition true?\n");\r
+ ot(" msr cpsr_flg,r10 ;@ ARM flags = 68000 flags\n");\r
+ ot(" b%s BccDontBranch%i\n\n",Cond[cc^1],8<<size);\r
+ break;\r
}\r
\r
- if (size==0) ot(" mov r0,r8,asl #24 ;@ Shift 8-bit signed offset up...\n\n");\r
-\r
- if (cc>=2)\r
+ if (size) \r
{\r
- ot(";@ Is the condition true?\n");\r
- if ((cc&~1)==2) ot(" eor r9,r9,#0x20000000 ;@ Invert carry for hi/ls\n");\r
- ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");\r
- if ((cc&~1)==2) ot(" eor r9,r9,#0x20000000\n");\r
-\r
- if (size==0) ot(" mov r0,r0,asr #24 ;@ ...shift down\n\n");\r
-\r
- ot(" b%s DontBranch%.4x\n",Cond[cc^1],op);\r
-\r
- ot("\n");\r
+ if (size<2)\r
+ {\r
+ ot(" ldrsh r11,[r4] ;@ Fetch Branch offset\n");\r
+ }\r
+ else\r
+ {\r
+ ot(" ldrh r2,[r4] ;@ Fetch Branch offset\n");\r
+ ot(" ldrh r11,[r4,#2]\n");\r
+ ot(" orr r11,r11,r2,lsl #16\n");\r
+ }\r
}\r
else\r
{\r
- if (size==0) ot(" mov r0,r0,asr #24 ;@ ...shift down\n\n");\r
+ ot(" mov r11,r8,asl #24 ;@ Shift 8-bit signed offset up...\n\n");\r
+ asr_r11=",asr #24";\r
}\r
\r
ot(";@ Branch taken - Add on r0 to PC\n");\r
if (cc==1)\r
{\r
ot(";@ Bsr - remember old PC\n");\r
- ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
- ot(" sub r1,r4,r10 ;@ r1 = Old PC\n");\r
+ ot(" ldr r12,[r7,#0x60] ;@ Get Memory base\n");\r
+ ot(" ldr r2,[r7,#0x3c]\n");\r
+ ot(" sub r1,r4,r12 ;@ r1 = Old PC\n");\r
+ if (size) ot(" add r1,r1,#%d\n",1<<size);\r
ot("\n");\r
- if (size) ot(" sub r4,r4,#%d ;@ (Branch is relative to Opcode+2)\n",1<<size);\r
- ot(" add r4,r4,r0 ;@ r4 = New PC\n");\r
- ot("\n");\r
- OpPush32();\r
- Cycles+=8;\r
- }\r
- else\r
- {\r
- if (size) ot(" sub r4,r4,#%d ;@ (Branch is relative to Opcode+2)\n",1<<size);\r
- ot(" add r4,r4,r0 ;@ r4 = New PC\n");\r
+ ot(";@ Push r1 onto stack\n");\r
+ ot(" sub r0,r2,#4 ;@ Predecrement A7\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ MemHandler(1,2);\r
ot("\n");\r
+ Cycles=18; // always 18\r
}\r
\r
- if (offset==0 || offset==-1)\r
- {\r
- ot(";@ Branch is quite far, so may be a good idea to check Memory Base+pc\n");\r
- CheckPc();\r
- }\r
+ ot(" add r0,r4,r11%s ;@ r4 = New PC\n",asr_r11);\r
+\r
+#if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_8\r
+ if (offset!=0 && offset!=-1) checkpc=1;\r
+#endif\r
+#if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_16\r
+ if (offset==0) checkpc=1;\r
+#endif\r
+#if USE_CHECKPC_CALLBACK\r
+ if (offset==-1) checkpc=1;\r
+#endif\r
+ if (checkpc) CheckPc();\r
+#if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" mov r4,r0\n");\r
+ ot(" tst r4,#1 ;@ address error?\n");\r
+ ot(" bne ExceptionAddressError_r_prg_r4\n");\r
+#else\r
+ ot(" bic r4,r0,#1\n");\r
+#endif\r
+ ot("\n");\r
\r
- OpEnd();\r
+ OpEnd(size?0x10:0);\r
\r
- if (cc>=2)\r
+ // since all "DontBranch" code is same for every size, output only once\r
+ if (cc>=2&&(op&0xff00)==0x6700)\r
{\r
- ot("DontBranch%.4x%s\n", op, ms?"":":");\r
- Cycles-=2; // Branch not taken\r
- OpEnd();\r
+ ot("BccDontBranch%i%s\n", 8<<size, ms?"":":");\r
+ if (size) ot(" add r4,r4,#%d\n",1<<size);\r
+ Cycles+=(size==1) ? 2 : -2; // Branch not taken\r
+ OpEnd(0);\r
}\r
\r
return 0;\r
\r
// This file is part of the Cyclone 68000 Emulator\r
\r
-// Copyright (c) 2011 FinalDave (emudave (at) gmail.com)\r
+// Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)\r
+// Copyright (c) 2005-2011 Gražvydas "notaz" Ignotas (notasas (at) gmail.com)\r
\r
// This code is licensed under the GNU General Public License version 2.0 and the MAME License.\r
// You can choose the license that has the most advantages for you.\r
\r
// SVN repository can be found at http://code.google.com/p/cyclone68000/\r
\r
+\r
#include "app.h"\r
\r
// --------------------- Opcodes 0x0100+ ---------------------\r
-// Emit a Btst (Register) opcode 0000nnn1 00aaaaaa\r
+// Emit a Btst (Register) opcode 0000nnn1 ttaaaaaa\r
int OpBtstReg(int op)\r
{\r
int use=0;\r
int type=0,sea=0,tea=0;\r
int size=0;\r
\r
- type=(op>>6)&3;\r
+ type=(op>>6)&3; // Btst/Bchg/Bclr/Bset\r
// Get source and target EA\r
sea=(op>>9)&7;\r
tea=op&0x003f;\r
if (EaCanWrite(tea)==0) return 1;\r
}\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
use&=~0x0e00; // Use same handler for all registers\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op); Cycles=4;\r
- if (tea<0x10) Cycles+=2;\r
- if (type>0) Cycles+=4;\r
+ OpStart(op,tea);\r
\r
- ot(" mov r10,#1\n");\r
+ if(type==1||type==3) {\r
+ Cycles=8;\r
+ } else {\r
+ Cycles=type?8:4;\r
+ if(size>=2) Cycles+=2;\r
+ }\r
\r
- EaCalc (0,0x0e00,sea,0);\r
- EaRead (0, 0,sea,0);\r
- ot(" bic r9,r9,#0x40000000 ;@ Blank Z flag\n");\r
- ot(" mov r10,r10,lsl r0 ;@ Make bit mask\n");\r
+ EaCalcReadNoSE(-1,11,sea,0,0x0e00);\r
+\r
+ EaCalcReadNoSE((type>0)?8:-1,0,tea,size,0x003f);\r
+\r
+ if (tea>=0x10)\r
+ ot(" and r11,r11,#7 ;@ mem - do mod 8\n"); // size always 0\r
+ else ot(" and r11,r11,#31 ;@ reg - do mod 32\n"); // size always 2\r
ot("\n");\r
\r
- EaCalc(11,0x003f,tea,size);\r
- EaRead(11, 0,tea,size);\r
- ot(" tst r0,r10 ;@ Do arithmetic\n");\r
- ot(" orreq r9,r9,#0x40000000 ;@ Get Z flag\n");\r
+ ot(" mov r1,#1\n");\r
+ ot(" tst r0,r1,lsl r11 ;@ Do arithmetic\n");\r
+ ot(" bicne r10,r10,#0x40000000\n");\r
+ ot(" orreq r10,r10,#0x40000000 ;@ Get Z flag\n");\r
ot("\n");\r
\r
if (type>0)\r
{\r
- if (type==1) ot(" eor r1,r0,r10 ;@ Toggle bit\n");\r
- if (type==2) ot(" bic r1,r0,r10 ;@ Clear bit\n");\r
- if (type==3) ot(" orr r1,r0,r10 ;@ Set bit\n");\r
+ if (type==1) ot(" eor r1,r0,r1,lsl r11 ;@ Toggle bit\n");\r
+ if (type==2) ot(" bic r1,r0,r1,lsl r11 ;@ Clear bit\n");\r
+ if (type==3) ot(" orr r1,r0,r1,lsl r11 ;@ Set bit\n");\r
ot("\n");\r
- EaWrite(11, 1,tea,size);\r
+ EaWrite(8,1,tea,size,0x003f,0,0);\r
}\r
- OpEnd();\r
+ OpEnd(tea);\r
\r
return 0;\r
}\r
if (tea<0x10) size=2; // For registers, 32-bits\r
\r
// See if we can do this opcode:\r
- if (EaCanRead(tea,0)==0) return 1;\r
+ if (EaCanRead(tea,0)==0||EaAn(tea)||tea==0x3c) return 1;\r
if (type>0)\r
{\r
if (EaCanWrite(tea)==0) return 1;\r
}\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op); Cycles=4;\r
- if (type<3 && tea<0x10) Cycles+=2;\r
- if (type>0) Cycles+=4;\r
+ OpStart(op,sea,tea);\r
\r
- ot(" mov r10,#1\n");\r
ot("\n");\r
- EaCalc ( 0,0x0000,sea,0);\r
- EaRead ( 0, 0,sea,0);\r
- ot(" bic r9,r9,#0x40000000 ;@ Blank Z flag\n");\r
- ot(" mov r10,r10,lsl r0 ;@ Make bit mask\n");\r
+ EaCalcReadNoSE(-1,0,sea,0,0);\r
+ ot(" mov r11,#1\n");\r
+ ot(" bic r10,r10,#0x40000000 ;@ Blank Z flag\n");\r
+ if (tea>=0x10)\r
+ ot(" and r0,r0,#7 ;@ mem - do mod 8\n"); // size always 0\r
+ else ot(" and r0,r0,#0x1F ;@ reg - do mod 32\n"); // size always 2\r
+ ot(" mov r11,r11,lsl r0 ;@ Make bit mask\n");\r
ot("\n");\r
\r
- EaCalc (11,0x003f,tea,size);\r
- EaRead (11, 0,tea,size);\r
- ot(" tst r0,r10 ;@ Do arithmetic\n");\r
- ot(" orreq r9,r9,#0x40000000 ;@ Get Z flag\n");\r
+ if(type==1||type==3) {\r
+ Cycles=12;\r
+ } else {\r
+ Cycles=type?12:8;\r
+ if(size>=2) Cycles+=2;\r
+ }\r
+\r
+ EaCalcReadNoSE((type>0)?8:-1,0,tea,size,0x003f);\r
+ ot(" tst r0,r11 ;@ Do arithmetic\n");\r
+ ot(" orreq r10,r10,#0x40000000 ;@ Get Z flag\n");\r
ot("\n");\r
\r
if (type>0)\r
{\r
- if (type==1) ot(" eor r1,r0,r10 ;@ Toggle bit\n");\r
- if (type==2) ot(" bic r1,r0,r10 ;@ Clear bit\n");\r
- if (type==3) ot(" orr r1,r0,r10 ;@ Set bit\n");\r
+ if (type==1) ot(" eor r1,r0,r11 ;@ Toggle bit\n");\r
+ if (type==2) ot(" bic r1,r0,r11 ;@ Clear bit\n");\r
+ if (type==3) ot(" orr r1,r0,r11 ;@ Set bit\n");\r
ot("\n");\r
- EaWrite(11, 1,tea,size);\r
+ EaWrite(8, 1,tea,size,0x003f,0,0);\r
+#if CYCLONE_FOR_GENESIS && !MEMHANDLERS_CHANGE_CYCLES\r
+ // this is a bit hacky (device handlers might modify cycles)\r
+ if (tea==0x38||tea==0x39)\r
+ ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
+#endif\r
}\r
\r
- OpEnd();\r
+ OpEnd(sea,tea);\r
\r
return 0;\r
}\r
ea =op&0x003f;\r
size=(op>>6)&3; if (size>=3) return 1;\r
\r
- switch (type)\r
- {\r
- case 1: case 2: case 3: break;\r
- default: return 1; // todo\r
- }\r
-\r
// See if we can do this opcode:\r
- if (EaCanRead (ea,size)==0) return 1;\r
+ if (EaCanRead (ea,size)==0||EaAn(ea)) return 1;\r
if (EaCanWrite(ea )==0) return 1;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op); Cycles=size<2?4:6;\r
+ OpStart(op,ea); Cycles=size<2?4:6;\r
+ if(ea >= 0x10) Cycles*=2;\r
\r
- EaCalc (10,0x003f,ea,size);\r
+ EaCalc (11,0x003f,ea,size,0,0);\r
\r
- if (type!=1) EaRead (10,0,ea,size); // Don't need to read for 'clr'\r
+ if (type!=1) EaRead (11,0,ea,size,0x003f,0,0); // Don't need to read for 'clr' (or do we, for a dummy read?)\r
if (type==1) ot("\n");\r
\r
+ if (type==0)\r
+ {\r
+ ot(";@ Negx:\n");\r
+ GetXBit(1);\r
+ if(size!=2) ot(" mov r0,r0,asl #%i\n",size?16:24);\r
+ ot(" rscs r1,r0,#0 ;@ do arithmetic\n");\r
+ ot(" orr r3,r10,#0xb0000000 ;@ for old Z\n");\r
+ OpGetFlags(1,1,0);\r
+ if(size!=2) {\r
+ ot(" movs r1,r1,asr #%i\n",size?16:24);\r
+ ot(" orreq r10,r10,#0x40000000 ;@ possily missed Z\n");\r
+ }\r
+ ot(" andeq r10,r10,r3 ;@ fix Z\n");\r
+ ot("\n");\r
+ }\r
+\r
if (type==1)\r
{\r
ot(";@ Clear:\n");\r
ot(" mov r1,#0\n");\r
- ot(" mov r9,#0x40000000 ;@ NZCV=0100\n");\r
+ ot(" mov r10,#0x40000000 ;@ NZCV=0100\n");\r
ot("\n");\r
}\r
\r
if (type==2)\r
{\r
ot(";@ Neg:\n");\r
+ if(size!=2) ot(" mov r0,r0,asl #%i\n",size?16:24);\r
ot(" rsbs r1,r0,#0\n");\r
OpGetFlags(1,1);\r
+ if(size!=2) ot(" mov r1,r1,asr #%i\n",size?16:24);\r
ot("\n");\r
}\r
\r
if (type==3)\r
{\r
ot(";@ Not:\n");\r
- ot(" mvn r1,r0\n");\r
+ if(size!=2) {\r
+ ot(" mov r0,r0,asl #%i\n",size?16:24);\r
+ ot(" mvn r1,r0,asr #%i\n",size?16:24);\r
+ }\r
+ else\r
+ ot(" mvn r1,r0\n");\r
ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
OpGetFlags(0,0);\r
ot("\n");\r
}\r
\r
- EaWrite(10, 1,ea,size);\r
+ if (type==1) eawrite_check_addrerr=1;\r
+ EaWrite(11, 1,ea,size,0x003f,0,0);\r
\r
- OpEnd();\r
+ OpEnd(ea);\r
\r
return 0;\r
}\r
\r
OpStart(op); Cycles=4;\r
\r
- EaCalc (10,0x0007,ea,2);\r
- EaRead (10, 0,ea,2);\r
+ EaCalc (11,0x0007,ea,2,1);\r
+ EaRead (11, 0,ea,2,0x0007,1);\r
\r
ot(" mov r1,r0,ror #16\n");\r
ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
OpGetFlags(0,0);\r
\r
- EaWrite(10, 1,8,2);\r
+ EaWrite(11, 1,8,2,0x0007,1);\r
\r
OpEnd();\r
\r
size=(op>>6)&3; if (size>=3) return 1;\r
\r
// See if we can do this opcode:\r
- if (EaCanWrite(sea)==0) return 1;\r
+ if (EaCanWrite(sea)==0||EaAn(sea)) return 1;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op); Cycles=4;\r
+ OpStart(op,sea); Cycles=4;\r
\r
- EaCalc ( 0,0x003f,sea,size);\r
- EaRead ( 0, 0,sea,size);\r
+ EaCalc ( 0,0x003f,sea,size,1);\r
+ EaRead ( 0, 0,sea,size,0x003f,1);\r
\r
ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
- ot(" mrs r9,cpsr ;@ r9=flags\n");\r
+ ot(" mrs r10,cpsr ;@ r10=flags\n");\r
ot("\n");\r
\r
- OpEnd();\r
+ OpEnd(sea);\r
return 0;\r
}\r
\r
size=(op>>6)&1;\r
shift=32-(8<<size);\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
OpStart(op); Cycles=4;\r
\r
- EaCalc (10,0x0007,ea,size+1);\r
- EaRead (10, 0,ea,size+1);\r
+ EaCalc (11,0x0007,ea,size+1,0,0);\r
+ EaRead (11, 0,ea,size+1,0x0007,0,0);\r
\r
ot(" mov r0,r0,asl #%d\n",shift);\r
ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
- ot(" mrs r9,cpsr ;@ r9=flags\n");\r
+ ot(" mrs r10,cpsr ;@ r10=flags\n");\r
ot(" mov r1,r0,asr #%d\n",shift);\r
ot("\n");\r
\r
- EaWrite(10, 1,ea,size+1);\r
+ EaWrite(11, 1,ea,size+1,0x0007,0,0);\r
\r
OpEnd();\r
return 0;\r
int OpSet(int op)\r
{\r
int cc=0,ea=0;\r
- int size=0,use=0;\r
- char *cond[16]=\r
+ int size=0,use=0,changed_cycles=0;\r
+ static const char * const cond[16]=\r
{\r
"al","", "hi","ls","cc","cs","ne","eq",\r
"vc","vs","pl","mi","ge","lt","gt","le"\r
// See if we can do this opcode:\r
if (EaCanWrite(ea)==0) return 1;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op); Cycles=8;\r
-\r
- if (ea<0x10) Cycles=4;\r
+ changed_cycles=ea<8 && cc>=2;\r
+ OpStart(op,ea,0,changed_cycles); Cycles=8;\r
+ if (ea<8) Cycles=4;\r
\r
- ot(" mov r1,#0\n");\r
+ if (cc)\r
+ ot(" mov r1,#0\n");\r
\r
- if (cc!=1)\r
+ switch (cc)\r
{\r
- ot(";@ Is the condition true?\n");\r
- if ((cc&~1)==2) ot(" eor r9,r9,#0x20000000 ;@ Invert carry for hi/ls\n");\r
- ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");\r
- if ((cc&~1)==2) ot(" eor r9,r9,#0x20000000 ;@ Invert carry for hi/ls\n");\r
- ot(" mvn%s r1,r1\n",cond[cc]);\r
+ case 0: // T\r
+ ot(" mvn r1,#0\n");\r
+ if (ea<8) Cycles+=2;\r
+ break;\r
+ case 1: // F\r
+ break;\r
+ case 2: // hi\r
+ ot(" tst r10,#0x60000000 ;@ hi: !C && !Z\n");\r
+ ot(" mvneq r1,r1\n");\r
+ if (ea<8) ot(" subeq r5,r5,#2 ;@ Extra cycles\n");\r
+ break;\r
+ case 3: // ls\r
+ ot(" tst r10,#0x60000000 ;@ ls: C || Z\n");\r
+ ot(" mvnne r1,r1\n");\r
+ if (ea<8) ot(" subne r5,r5,#2 ;@ Extra cycles\n");\r
+ break;\r
+ default:\r
+ ot(";@ Is the condition true?\n");\r
+ ot(" msr cpsr_flg,r10 ;@ ARM flags = 68000 flags\n");\r
+ ot(" mvn%s r1,r1\n",cond[cc]);\r
+ if (ea<8) ot(" sub%s r5,r5,#2 ;@ Extra cycles\n",cond[cc]);\r
+ break;\r
}\r
\r
- if (ea<0x10) ot(" sub%s r5,r5,#2 ;@ Extra cycles\n",cond[cc]);\r
ot("\n");\r
\r
- EaCalc (0,0x003f, ea,size);\r
- EaWrite(0, 1, ea,size);\r
+ eawrite_check_addrerr=1;\r
+ EaCalc (0,0x003f, ea,size,0,0);\r
+ EaWrite(0, 1, ea,size,0x003f,0,0);\r
\r
- OpEnd();\r
+ opend_op_changes_cycles=changed_cycles;\r
+ OpEnd(ea,0);\r
return 0;\r
}\r
\r
// Emit a Asr/Lsr/Roxr/Ror opcode\r
static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)\r
{\r
- char pct[8]="";\r
+ char pct[8]=""; // count\r
int shift=32-(8<<size);\r
\r
if (count>=1) sprintf(pct,"#%d",count); // Fixed count\r
\r
- if (count<0)\r
- {\r
- ot(" mov r2,r8,lsr #9 ;@ Get 'n'\n");\r
- ot(" and r2,r2,#7\n\n"); strcpy(pct,"r2");\r
- }\r
-\r
if (usereg)\r
{\r
ot(";@ Use Dn for count:\n");\r
- ot(" ldr r2,[r7,r2,lsl #2]\n");\r
+ ot(" and r2,r8,#0x0e00\n");\r
+ ot(" ldr r2,[r7,r2,lsr #7]\n");\r
ot(" and r2,r2,#63\n");\r
ot("\n");\r
+ strcpy(pct,"r2");\r
+ }\r
+ else if (count<0)\r
+ {\r
+ ot(" mov r2,r8,lsr #9 ;@ Get 'n'\n");\r
+ ot(" and r2,r2,#7\n\n"); strcpy(pct,"r2");\r
}\r
\r
// Take 2*n cycles:\r
// Asr/Lsr\r
if (dir==0 && size<2)\r
{\r
- ot(";@ For shift right, also copy to lowest bits (to get carry bit):\n");\r
- ot(" orr r0,r0,r0,lsr #%d\n",32-(8<<size));\r
+ ot(";@ For shift right, use loworder bits for the operation:\n");\r
+ ot(" mov r0,r0,%s #%d\n",type?"lsr":"asr",32-(8<<size));\r
ot("\n");\r
}\r
\r
+ if (type==0 && dir) ot(" adds r3,r0,#0 ;@ save old value for V flag calculation, also clear V\n");\r
+\r
ot(";@ Shift register:\n");\r
if (type==0) ot(" movs r0,r0,%s %s\n",dir?"asl":"asr",pct);\r
if (type==1) ot(" movs r0,r0,%s %s\n",dir?"lsl":"lsr",pct);\r
- OpGetFlags(0,1);\r
+\r
+ OpGetFlags(0,0);\r
+ if (usereg) { // store X only if count is not 0\r
+ ot(" cmp %s,#0 ;@ shifting by 0?\n",pct);\r
+ ot(" biceq r10,r10,#0x20000000 ;@ if so, clear carry\n");\r
+ ot(" strne r10,[r7,#0x4c] ;@ else Save X bit\n");\r
+ } else {\r
+ // count will never be 0 if we use immediate\r
+ ot(" str r10,[r7,#0x4c] ;@ Save X bit\n");\r
+ }\r
ot("\n");\r
\r
- if (size<2)\r
+ if (dir==0 && size<2)\r
{\r
- ot(";@ Check if result is zero:\n");\r
- ot(" movs r2,r0,lsr #%d\n",shift);\r
- ot(" orreq r9,r9,#0x40000000\n");\r
+ ot(";@ restore after right shift:\n");\r
+ ot(" movs r0,r0,lsl #%d\n",32-(8<<size));\r
+ if (type)\r
+ ot(" orrmi r10,r10,#0x80000000 ;@ Potentially missed N flag\n");\r
+ ot("\n");\r
+ }\r
+\r
+ if (type==0 && dir) {\r
+ ot(";@ calculate V flag (set if sign bit changes at anytime):\n");\r
+ ot(" mov r1,#0x80000000\n");\r
+ ot(" ands r3,r3,r1,asr %s\n", pct);\r
+ ot(" cmpne r3,r1,asr %s\n", pct);\r
+ ot(" eoreq r1,r0,r3\n"); // above check doesn't catch (-1)<<(32+), so we need this\r
+ ot(" tsteq r1,#0x80000000\n");\r
+ ot(" orrne r10,r10,#0x10000000\n");\r
ot("\n");\r
}\r
}\r
// --------------------------------------\r
if (type==2)\r
{\r
- // Roxr\r
int wide=8<<size;\r
\r
- if (shift) ot(" mov r0,r0,lsr #%d ;@ Shift down\n",shift);\r
-\r
- ot(";@ Rotate register through X:\n");\r
- if (strcmp("r2",pct)!=0) { ot(" mov r2,%s\n",pct); strcpy(pct,"r2"); } // Get into register\r
+ // Roxr\r
+ if(count == 1)\r
+ {\r
+ if(dir==0) {\r
+ if(size!=2) {\r
+ ot(" orr r0,r0,r0,lsr #%i\n", size?16:24);\r
+ ot(" bic r0,r0,#0x%x\n", 1<<(32-wide));\r
+ }\r
+ GetXBit(0);\r
+ ot(" movs r0,r0,rrx\n");\r
+ OpGetFlags(0,1);\r
+ } else {\r
+ ot(" ldr r3,[r7,#0x4c]\n");\r
+ ot(" movs r0,r0,lsl #1\n");\r
+ OpGetFlags(0,1);\r
+ ot(" tst r3,#0x20000000\n");\r
+ ot(" orrne r0,r0,#0x%x\n", 1<<(32-wide));\r
+ ot(" bicne r10,r10,#0x40000000 ;@ clear Z in case it got there\n");\r
+ }\r
+ ot(" bic r10,r10,#0x10000000 ;@ make suve V is clear\n");\r
+ return 0;\r
+ }\r
\r
- if (count!=8)\r
+ if (usereg)\r
{\r
- ot(";@ Reduce r2 until <0:\n");\r
- ot("Reduce_%.4x%s\n",op,ms?"":":");\r
- ot(" subs r2,r2,#%d\n",wide+1);\r
- ot(" bpl Reduce_%.4x\n",op);\r
- ot(" add r2,r2,#%d ;@ Now r2=0-%d\n",wide+1,wide);\r
+ if (size==2)\r
+ {\r
+ ot(" subs r2,r2,#33\n");\r
+ ot(" addmis r2,r2,#33 ;@ Now r2=0-%d\n",wide);\r
+ }\r
+ else\r
+ {\r
+ ot(";@ Reduce r2 until <0:\n");\r
+ ot("Reduce_%.4x%s\n",op,ms?"":":");\r
+ ot(" subs r2,r2,#%d\n",wide+1);\r
+ ot(" bpl Reduce_%.4x\n",op);\r
+ ot(" adds r2,r2,#%d ;@ Now r2=0-%d\n",wide+1,wide);\r
+ }\r
+ ot(" beq norotx_%.4x\n",op);\r
ot("\n");\r
}\r
\r
- if (dir) ot(" rsb r2,r2,#%d ;@ Reverse direction\n",wide+1);\r
+ if (usereg||count < 0)\r
+ {\r
+ if (dir) ot(" rsb r2,r2,#%d ;@ Reverse direction\n",wide+1);\r
+ }\r
+ else\r
+ {\r
+ if (dir) ot(" mov r2,#%d ;@ Reversed\n",wide+1-count);\r
+ else ot(" mov r2,#%d\n",count);\r
+ }\r
+\r
+ if (shift) ot(" mov r0,r0,lsr #%d ;@ Shift down\n",shift);\r
+\r
+ ot("\n");\r
+ ot(";@ First get X bit (middle):\n");\r
+ ot(" ldr r3,[r7,#0x4c]\n");\r
+ ot(" rsb r1,r2,#%d\n",wide);\r
+ ot(" and r3,r3,#0x20000000\n");\r
+ ot(" mov r3,r3,lsr #29\n");\r
+ ot(" mov r3,r3,lsl r1\n");\r
\r
ot(";@ Rotate bits:\n");\r
- ot(" mov r3,r0,lsr r2 ;@ Get right part\n");\r
- ot(" rsb r2,r2,#%d\n",wide+1);\r
- ot(" movs r0,r0,lsl r2 ;@ Get left part\n");\r
- ot(" orr r0,r3,r0 ;@ r0=Rotated value\n");\r
-\r
- ot(";@ Insert X bit into r2-1:\n");\r
- ot(" ldrb r3,[r7,#0x45]\n");\r
- ot(" sub r2,r2,#1\n");\r
- ot(" and r3,r3,#2\n");\r
- ot(" mov r3,r3,lsr #1\n");\r
- ot(" orr r0,r0,r3,lsl r2\n");\r
+ ot(" orr r3,r3,r0,lsr r2 ;@ Orr right part\n");\r
+ ot(" rsbs r2,r2,#%d ;@ should also clear ARM V\n",wide+1);\r
+ ot(" orrs r0,r3,r0,lsl r2 ;@ Orr left part, set flags\n");\r
ot("\n");\r
\r
if (shift) ot(" movs r0,r0,lsl #%d ;@ Shift up and get correct NC flags\n",shift);\r
- OpGetFlags(0,1);\r
+ OpGetFlags(0,!usereg);\r
+ if (usereg) { // store X only if count is not 0\r
+ ot(" str r10,[r7,#0x4c] ;@ if not 0, Save X bit\n");\r
+ ot(" b nozerox%.4x\n",op);\r
+ ot("norotx_%.4x%s\n",op,ms?"":":");\r
+ ot(" ldr r2,[r7,#0x4c]\n");\r
+ ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
+ OpGetFlags(0,0);\r
+ ot(" and r2,r2,#0x20000000\n");\r
+ ot(" orr r10,r10,r2 ;@ C = old_X\n");\r
+ ot("nozerox%.4x%s\n",op,ms?"":":");\r
+ }\r
+\r
ot("\n");\r
}\r
\r
}\r
\r
ot(";@ Rotate register:\n");\r
+ if (!dir) ot(" adds r0,r0,#0 ;@ first clear V and C\n"); // ARM does not clear C if rot count is 0\r
if (count<0)\r
{\r
- if (dir) ot(" rsb r2,%s,#32\n",pct);\r
+ if (dir) ot(" rsb %s,%s,#32\n",pct,pct);\r
ot(" movs r0,r0,ror %s\n",pct);\r
}\r
else\r
if (ror&31) ot(" movs r0,r0,ror #%d\n",ror);\r
}\r
\r
+ OpGetFlags(0,0);\r
if (dir)\r
{\r
+ ot(" bic r10,r10,#0x30000000 ;@ clear CV\n");\r
ot(";@ Get carry bit from bit 0:\n");\r
- ot(" mov r9,#0\n");\r
- ot(" ands r2,r0,#1\n");\r
- ot(" orrne r9,r9,#0x20000000\n");\r
- }\r
- else\r
- {\r
- OpGetFlags(0,0);\r
+ if (usereg)\r
+ {\r
+ ot(" cmp %s,#32 ;@ rotating by 0?\n",pct);\r
+ ot(" tstne r0,#1 ;@ no, check bit 0\n");\r
+ }\r
+ else\r
+ ot(" tst r0,#1\n");\r
+ ot(" orrne r10,r10,#0x20000000\n");\r
}\r
ot("\n");\r
\r
}\r
\r
// Emit a Asr/Lsr/Roxr/Ror opcode - 1110cccd xxuttnnn\r
-// (ccc=count, d=direction xx=size extension, u=use reg for count, tt=type, nnn=register Dn)\r
+// (ccc=count, d=direction(r,l) xx=size extension, u=use reg for count, tt=type, nnn=register Dn)\r
int OpAsr(int op)\r
{\r
int ea=0,use=0;\r
int count=0,dir=0;\r
int size=0,usereg=0,type=0;\r
\r
- ea=0;\r
count =(op>>9)&7;\r
dir =(op>>8)&1;\r
size =(op>>6)&3;\r
- if (size>=3) return 1; // todo Asr EA\r
+ if (size>=3) return 1; // use OpAsrEa()\r
usereg=(op>>5)&1;\r
type =(op>>3)&3;\r
\r
// Use the same opcode for target registers:\r
use=op&~0x0007;\r
\r
- // As long as count is not 8, use the same opcode for all shift counts::\r
- if (usereg==0 && count!=8) { use|=0x0e00; count=-1; }\r
+ // As long as count is not 8, use the same opcode for all shift counts:\r
+ if (usereg==0 && count!=8 && !(count==1&&type==2)) { use|=0x0e00; count=-1; }\r
if (usereg) { use&=~0x0e00; count=-1; } // Use same opcode for all Dn\r
\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op); Cycles=size<2?6:8;\r
+ OpStart(op,ea,0,count<0); Cycles=size<2?6:8;\r
\r
- EaCalc(10,0x0007, ea,size);\r
- EaRead(10, 0, ea,size,1);\r
+ EaCalc(11,0x0007, ea,size,1);\r
+ EaRead(11, 0, ea,size,0x0007,1);\r
\r
EmitAsr(op,type,dir,count, size,usereg);\r
\r
- EaWrite(10, 0, ea,size,1);\r
+ EaWrite(11, 0, ea,size,0x0007,1);\r
\r
- OpEnd();\r
+ opend_op_changes_cycles = (count<0);\r
+ OpEnd(ea,0);\r
\r
return 0;\r
}\r
\r
-// Asr/l/Ror/l etc EA - 11100ttd 11eeeeee \r
+// Asr/Lsr/Roxr/Ror etc EA - 11100ttd 11eeeeee \r
int OpAsrEa(int op)\r
{\r
int use=0,type=0,dir=0,ea=0,size=1;\r
if (EaCanRead(ea,0)==0) return 1;\r
if (EaCanWrite(ea)==0) return 1;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op); Cycles=8;\r
+ OpStart(op,ea); Cycles=6; // EmitAsr() will add 2\r
\r
- EaCalc (10,0x003f,ea,size);\r
- EaRead (10, 0,ea,size,1);\r
+ EaCalc (11,0x003f,ea,size,1);\r
+ EaRead (11, 0,ea,size,0x003f,1);\r
\r
- EmitAsr(op,type,dir,1, size,0);\r
+ EmitAsr(op,type,dir,1,size,0);\r
\r
- ot(";@ Save shifted value back to EA:\n");\r
- ot(" mov r1,r0\n");\r
- EaWrite(10, 1,ea,size,1);\r
+ EaWrite(11, 0,ea,size,0x003f,1);\r
\r
- OpEnd();\r
+ OpEnd(ea);\r
return 0;\r
}\r
+\r
+int OpTas(int op, int gen_special)\r
+{\r
+ int ea=0;\r
+ int use=0;\r
+\r
+ ea=op&0x003f;\r
+\r
+ // See if we can do this opcode:\r
+ if (EaCanWrite(ea)==0 || EaAn(ea)) return 1;\r
+\r
+ use=OpBase(op,0);\r
+ if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
+\r
+ if (!gen_special) OpStart(op,ea);\r
+ else\r
+ ot("Op%.4x_%s\n", op, ms?"":":");\r
+\r
+ Cycles=4;\r
+ if(ea>=8) Cycles+=10;\r
+\r
+ EaCalc (11,0x003f,ea,0,1);\r
+ EaRead (11, 1,ea,0,0x003f,1);\r
+\r
+ ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
+ OpGetFlags(0,0);\r
+ ot("\n");\r
+\r
+#if CYCLONE_FOR_GENESIS\r
+ // the original Sega hardware ignores write-back phase (to memory only)\r
+ if (ea < 0x10 || gen_special) {\r
+#endif\r
+ ot(" orr r1,r1,#0x80000000 ;@ set bit7\n");\r
+\r
+ EaWrite(11, 1,ea,0,0x003f,1);\r
+#if CYCLONE_FOR_GENESIS\r
+ }\r
+#endif\r
+\r
+ OpEnd(ea);\r
+\r
+#if (CYCLONE_FOR_GENESIS == 2)\r
+ if (!gen_special && ea >= 0x10) {\r
+ OpTas(op, 1);\r
+ }\r
+#endif\r
+\r
+ return 0;\r
+}\r
+\r
\r
// This file is part of the Cyclone 68000 Emulator\r
\r
-// Copyright (c) 2011 FinalDave (emudave (at) gmail.com)\r
+// Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)\r
+// Copyright (c) 2005-2011 Gražvydas "notaz" Ignotas (notasas (at) gmail.com)\r
\r
// This code is licensed under the GNU General Public License version 2.0 and the MAME License.\r
// You can choose the license that has the most advantages for you.\r
\r
// SVN repository can be found at http://code.google.com/p/cyclone68000/\r
\r
+\r
#include "app.h"\r
\r
+// Pack our flags into r1, in SR/CCR register format\r
+// trashes r0,r2\r
+void OpFlagsToReg(int high)\r
+{\r
+ ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");\r
+ ot(" mov r1,r10,lsr #28 ;@ ____NZCV\n");\r
+ ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");\r
+ ot(" tst r2,#1 ;@ 1 if C!=V\n");\r
+ ot(" eorne r1,r1,#3 ;@ ____NZVC\n");\r
+ ot("\n");\r
+ if (high) ot(" ldrb r2,[r7,#0x44] ;@ Include SR high\n");\r
+ ot(" and r0,r0,#0x20000000\n");\r
+ ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");\r
+ if (high) ot(" orr r1,r1,r2,lsl #8\n");\r
+ ot("\n");\r
+}\r
+\r
+// Convert SR/CRR register in r0 to our flags\r
+// trashes r0,r1\r
+void OpRegToFlags(int high, int srh_reg)\r
+{\r
+ ot(" eor r1,r0,r0,ror #1 ;@ Bit 0=C^V\n");\r
+ ot(" mov r2,r0,lsl #25\n");\r
+ ot(" tst r1,#1 ;@ 1 if C!=V\n");\r
+ ot(" eorne r0,r0,#3 ;@ ___XNZCV\n");\r
+ ot(" str r2,[r7,#0x4c] ;@ Store X bit\n");\r
+ ot(" mov r10,r0,lsl #28 ;@ r10=NZCV...\n");\r
+\r
+ if (high)\r
+ {\r
+ int mask=EMULATE_TRACE?0xa7:0x27;\r
+ ot(" mov r%i,r0,ror #8\n",srh_reg);\r
+ ot(" and r%i,r%i,#0x%02x ;@ only take defined bits\n",srh_reg,srh_reg,mask);\r
+ ot(" strb r%i,[r7,#0x44] ;@ Store SR high\n",srh_reg);\r
+ }\r
+ ot("\n");\r
+}\r
+\r
+void SuperEnd(void)\r
+{\r
+ ot(";@ ----------\n");\r
+ ot(";@ tried execute privileged instruction in user mode\n");\r
+ ot("WrongPrivilegeMode%s\n",ms?"":":");\r
+#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
+ ot(" ldr r1,[r7,#0x58]\n");\r
+ ot(" sub r4,r4,#2 ;@ last opcode wasn't executed - go back\n");\r
+ ot(" orr r1,r1,#4 ;@ set activity bit: 'not processing instruction'\n");\r
+ ot(" str r1,[r7,#0x58]\n");\r
+#else\r
+ ot(" sub r4,r4,#2 ;@ last opcode wasn't executed - go back\n");\r
+#endif\r
+ ot(" mov r0,#8 ;@ privilege violation\n");\r
+ ot(" bl Exception\n");\r
+ Cycles=34;\r
+ OpEnd(0);\r
+}\r
+\r
+// does OSP and A7 swapping if needed\r
+// new or old SR (not the one already in [r7,#0x44]) should be passed in r11\r
+// uses srh from srh_reg (loads if < 0), trashes r0,r11\r
+void SuperChange(int op,int srh_reg)\r
+{\r
+ ot(";@ A7 <-> OSP?\n");\r
+ if (srh_reg < 0) {\r
+ ot(" ldr r0,[r7,#0x44] ;@ Get other SR high\n");\r
+ srh_reg=0;\r
+ }\r
+ ot(" eor r0,r%i,r11\n",srh_reg);\r
+ ot(" tst r0,#0x20\n");\r
+ ot(" beq no_sp_swap%.4x\n",op);\r
+ ot(" ;@ swap OSP and A7:\n");\r
+ ot(" ldr r11,[r7,#0x3C] ;@ Get A7\n");\r
+ ot(" ldr r0, [r7,#0x48] ;@ Get OSP\n");\r
+ ot(" str r11,[r7,#0x48]\n");\r
+ ot(" str r0, [r7,#0x3C]\n");\r
+ ot("no_sp_swap%.4x%s\n", op, ms?"":":");\r
+}\r
+\r
+\r
+\r
// --------------------- Opcodes 0x1000+ ---------------------\r
// Emit a Move opcode, 00xxdddd ddssssss\r
int OpMove(int op)\r
case 0x2000: size=2; break;\r
}\r
\r
- if (movea && size<1) return 1; // movea.b is invalid\r
+ if (size<1 && (movea || EaAn(sea))) return 1; // move.b An,* and movea.b * are invalid\r
\r
// See if we can do this opcode:\r
if (EaCanRead (sea,size)==0) return 1;\r
if (EaCanWrite(tea )==0) return 1;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
if (tea<0x38) use&=~0x0e00; // Use same handler for register ?0-7\r
\r
- if (tea>=0x18 && tea<0x28 && (tea&7)==7) use|=0x0e00; // Specific handler for (a7)+ and -(a7)\r
+ if (tea==0x1f || tea==0x27) use|=0x0e00; // Specific handler for (a7)+ and -(a7)\r
\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op); Cycles=4;\r
+ OpStart(op,sea,tea); Cycles=4;\r
\r
- EaCalc(0,0x003f,sea,size);\r
- EaRead(0, 0,sea,size);\r
-\r
- ot(" adds r1,r0,#0 ;@ Defines NZ, clears CV\n");\r
+ if (movea==0)\r
+ {\r
+ EaCalcRead(-1,0,sea,size,0x003f);\r
+ ot(" adds r1,r0,#0 ;@ Defines NZ, clears CV\n");\r
+ ot(" mrs r10,cpsr ;@ r10=NZCV flags\n");\r
+ ot("\n");\r
+ }\r
+ else\r
+ {\r
+ EaCalcRead(-1,1,sea,size,0x003f);\r
+ size=2; // movea always expands to 32-bits\r
+ }\r
\r
- if (movea==0) ot(" mrs r9,cpsr ;@ r9=NZCV flags\n");\r
- ot("\n");\r
+ eawrite_check_addrerr=1;\r
+#if SPLIT_MOVEL_PD\r
+ if ((tea&0x38)==0x20 && size==2) { // -(An)\r
+ EaCalc (8,0x0e00,tea,size,0,0);\r
+ ot(" mov r11,r1\n");\r
+ ot(" add r0,r8,#2\n");\r
+ EaWrite(0, 1,tea,1,0x0e00,0,0);\r
+ EaWrite(8, 11,tea,1,0x0e00,1);\r
+ }\r
+ else\r
+#endif\r
+ {\r
+ EaCalc (0,0x0e00,tea,size,0,0);\r
+ EaWrite(0, 1,tea,size,0x0e00,0,0);\r
+ }\r
\r
- if (movea) size=2; // movea always expands to 32-bits\r
+#if CYCLONE_FOR_GENESIS && !MEMHANDLERS_CHANGE_CYCLES\r
+ // this is a bit hacky (device handlers might modify cycles)\r
+ if (tea==0x39||((0x10<=tea&&tea<0x30)&&size>=1))\r
+ ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
+#endif\r
\r
- EaCalc (0,0x0e00,tea,size);\r
- EaWrite(0, 1,tea,size);\r
+ if((tea&0x38)==0x20) Cycles-=2; // less cycles when dest is -(An)\r
\r
- OpEnd();\r
+ OpEnd(sea,tea);\r
return 0;\r
}\r
\r
sea= op&0x003f;\r
tea=(op&0x0e00)>>9; tea|=8;\r
\r
- if (EaCanRead(sea,-1)==0) return 1; // See if we can do this opcode:\r
+ if (EaCanRead(sea,-1)==0) return 1; // See if we can do this opcode\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,0);\r
use&=~0x0e00; // Also use 1 handler for target ?0-7\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op); Cycles=4;\r
+ OpStart(op,sea,tea);\r
\r
+ eawrite_check_addrerr=1;\r
EaCalc (1,0x003f,sea,0); // Lea\r
EaCalc (0,0x0e00,tea,2);\r
- EaWrite(0, 1,tea,2);\r
+ EaWrite(0, 1,tea,2,0x0e00);\r
\r
- if (Amatch)\r
- {\r
- // Correct?\r
- if (sea< 0x18) Cycles+=4;\r
- else if (sea==0x30) Cycles+=12;\r
- else Cycles+=8;\r
- }\r
+ Cycles=Ea_add_ns(g_lea_cycle_table,sea);\r
\r
- OpEnd();\r
+ OpEnd(sea,tea);\r
\r
return 0;\r
}\r
\r
// --------------------- Opcodes 0x40c0+ ---------------------\r
-\r
-// Pack our flags into r1, in SR/CCR register format\r
-// trashes r0,r2\r
-void OpFlagsToReg(int high)\r
-{\r
- ot(" mov r1,r9,lsr #28 ;@ ____NZCV\n");\r
- ot(" eor r0,r1,r1,ror #1 ;@ Bit 0=C^V\n");\r
- ot(" tst r0,#1 ;@ 1 if C!=V\n");\r
- ot(" eorne r1,r1,#3 ;@ ____NZVC\n");\r
- ot("\n");\r
- ot(" ldrb r0,[r7,#0x45] ;@ X bit\n");\r
- if (high) ot(" ldrb r2,[r7,#0x44] ;@ Include SR high\n");\r
- ot(" and r0,r0,#0x02\n");\r
- if (high) ot(" orr r1,r1,r2,lsl #8\n");\r
- ot(" orr r1,r1,r0,lsl #3 ;@ ___XNZVC\n");\r
- ot("\n");\r
-}\r
-\r
-// Convert SR/CRR register in r0 to our flags\r
-// trashes r0,r1\r
-void OpRegToFlags(int high)\r
-{\r
- ot(" eor r1,r0,r0,ror #1 ;@ Bit 0=C^V\n");\r
- ot(" mov r2,r0,lsr #3 ;@ r2=___XN\n");\r
- ot(" tst r1,#1 ;@ 1 if C!=V\n");\r
- ot(" eorne r0,r0,#3 ;@ ___XNZCV\n");\r
- ot(" strb r2,[r7,#0x45] ;@ Store X bit\n");\r
- ot(" mov r9,r0,lsl #28 ;@ r9=NZCV...\n");\r
-\r
- if (high)\r
- {\r
- ot(" mov r0,r0,ror #8\n");\r
- ot(" strb r0,[r7,#0x44] ;@ Store SR high\n");\r
- }\r
- ot("\n");\r
-}\r
-\r
-static void SuperCheck(int op)\r
-{\r
- ot(" ldrb r0,[r7,#0x44] ;@ Get SR high\n");\r
- ot(" tst r0,#0x20 ;@ Check we are in supervisor mode\n");\r
- ot(" beq WrongMode%.4x ;@ No\n",op);\r
- ot("\n");\r
-}\r
-\r
-static void SuperEnd(int op)\r
-{\r
- ot("WrongMode%.4x%s\n",op,ms?"":":");\r
- ot(";@ todo - cause an exception\n");\r
- OpEnd();\r
-}\r
-\r
-// Move SR opcode, 01000tt0 11aaaaaa move to SR\r
+// Move SR opcode, 01000tt0 11aaaaaa move SR\r
int OpMoveSr(int op)\r
{\r
int type=0,ea=0;\r
int use=0,size=1;\r
\r
- type=(op>>9)&3;\r
+ type=(op>>9)&3; // from SR, from CCR, to CCR, to SR\r
ea=op&0x3f;\r
\r
+ if(EaAn(ea)) return 1; // can't use An regs\r
+\r
switch(type)\r
{\r
- case 0: case 1:\r
+ case 0:\r
if (EaCanWrite(ea)==0) return 1; // See if we can do this opcode:\r
- break;\r
+ break;\r
\r
- default: return 1; // todo\r
+ case 1:\r
+ return 1; // no such op in 68000\r
\r
case 2: case 3:\r
if (EaCanRead(ea,size)==0) return 1; // See if we can do this opcode:\r
- break;\r
+ break;\r
}\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op);\r
- if (type==0) Cycles=8;\r
- else if (type==1) Cycles=6;\r
- else Cycles=12;\r
-\r
- if (Amatch && ea==0x3c) Cycles-=4; // Correct?\r
-\r
- if (type==0 || type==3) SuperCheck(op);\r
+ // 68000 model allows reading whole SR in user mode (but newer models don't)\r
+ OpStart(op,ea,0,0,type==3);\r
+ Cycles=12;\r
+ if (type==0) Cycles=(ea>=8)?8:6;\r
\r
if (type==0 || type==1)\r
{\r
+ eawrite_check_addrerr=1;\r
OpFlagsToReg(type==0);\r
- EaCalc (0,0x003f,ea,size);\r
- EaWrite(0, 1,ea,size);\r
+ EaCalc (0,0x003f,ea,size,0,0);\r
+ EaWrite(0, 1,ea,size,0x003f,0,0);\r
}\r
\r
if (type==2 || type==3)\r
{\r
- EaCalc(0,0x003f,ea,size);\r
- EaRead(0, 0,ea,size);\r
- OpRegToFlags(type==3);\r
- if (type==3) CheckInterrupt();\r
+ EaCalcReadNoSE(-1,0,ea,size,0x003f);\r
+ OpRegToFlags(type==3,1);\r
+ if (type==3) {\r
+ SuperChange(op,1);\r
+ opend_check_interrupt = 1;\r
+ opend_check_trace = 1;\r
+ OpEnd(ea);\r
+ return 0;\r
+ }\r
}\r
\r
- OpEnd();\r
-\r
- if (type==0 || type==3) SuperEnd(op);\r
+ OpEnd(ea);\r
\r
return 0;\r
}\r
{\r
int type=0,ea=0;\r
int use=0,size=0;\r
+ int sr_mask=EMULATE_TRACE?0xa7:0x27;\r
\r
type=(op>>9)&5; if (type==4) return 1;\r
- size=(op>>6)&1;\r
+ size=(op>>6)&1; // ccr or sr?\r
ea=0x3c;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op); Cycles=16;\r
+ OpStart(op,ea,0,0,size!=0); Cycles=16;\r
+\r
+ EaCalcRead(-1,0,ea,size,0x003f);\r
\r
- SuperCheck(op);\r
+ ot(" eor r1,r0,r0,ror #1 ;@ Bit 0=C^V\n");\r
+ ot(" tst r1,#1 ;@ 1 if C!=V\n");\r
+ ot(" eorne r0,r0,#3 ;@ ___XNZCV\n");\r
+ ot(" ldr r2,[r7,#0x4c] ;@ Load old X bit\n");\r
+\r
+ // note: old srh is already in r11 (done by OpStart)\r
+ if (type==0) {\r
+ ot(" orr r10,r10,r0,lsl #28\n");\r
+ ot(" orr r2,r2,r0,lsl #25 ;@ X bit\n");\r
+ if (size!=0) {\r
+ ot(" orr r1,r11,r0,lsr #8\n");\r
+ ot(" and r1,r1,#0x%02x ;@ mask-out unused bits\n",sr_mask);\r
+ }\r
+ }\r
+ if (type==1) {\r
+ ot(" and r10,r10,r0,lsl #28\n");\r
+ ot(" and r2,r2,r0,lsl #25 ;@ X bit\n");\r
+ if (size!=0)\r
+ ot(" and r1,r11,r0,lsr #8\n");\r
+ }\r
+ if (type==5) {\r
+ ot(" eor r10,r10,r0,lsl #28\n");\r
+ ot(" eor r2,r2,r0,lsl #25 ;@ X bit\n");\r
+ if (size!=0) {\r
+ ot(" eor r1,r11,r0,lsr #8\n");\r
+ ot(" and r1,r1,#0x%02x ;@ mask-out unused bits\n",sr_mask);\r
+ }\r
+ }\r
\r
- EaCalc(0,0x003f,ea,size);\r
- EaRead(0, 10,ea,size);\r
+ ot(" str r2,[r7,#0x4c] ;@ Save X bit\n");\r
+ if (size!=0)\r
+ ot(" strb r1,[r7,#0x44]\n");\r
+ ot("\n");\r
\r
- OpFlagsToReg(size);\r
- if (type==0) ot(" orr r0,r1,r10\n");\r
- if (type==1) ot(" and r0,r1,r10\n");\r
- if (type==5) ot(" eor r0,r1,r10\n");\r
- OpRegToFlags(size);\r
- if (size) CheckInterrupt();\r
+ // we can't enter supervisor mode, nor unmask irqs just by using OR\r
+ if (size!=0 && type!=0) {\r
+ SuperChange(op,1);\r
+ ot("\n");\r
+ opend_check_interrupt = 1;\r
+ }\r
+ // also can't set trace bit with AND\r
+ if (size!=0 && type!=1)\r
+ opend_check_trace = 1;\r
\r
- OpEnd();\r
- SuperEnd(op);\r
+ OpEnd(ea);\r
\r
return 0;\r
}\r
ea=op&0x003f; if (ea<0x10) return 1; // Swap opcode\r
if (EaCanRead(ea,-1)==0) return 1; // See if we can do this opcode:\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,0);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op); Cycles=20;\r
+ OpStart(op,ea);\r
\r
+ ot(" ldr r11,[r7,#0x3c]\n");\r
EaCalc (1,0x003f, ea,0);\r
ot("\n");\r
- ot(" ldr r0,[r7,#0x3c]\n");\r
- ot(" sub r0,r0,#4 ;@ Predecrement A7\n");\r
+ ot(" sub r0,r11,#4 ;@ Predecrement A7\n");\r
ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
ot("\n");\r
MemHandler(1,2); // Write 32-bit\r
ot("\n");\r
\r
- OpEnd();\r
+ Cycles=6+Ea_add_ns(g_pea_cycle_table,ea);\r
+\r
+ OpEnd(ea);\r
\r
return 0;\r
}\r
int size=0,ea=0,cea=0,dir=0;\r
int use=0,decr=0,change=0;\r
\r
- size=((op>>6)&1)+1;\r
+ size=((op>>6)&1)+1; // word, long\r
ea=op&0x003f;\r
- dir=(op>>10)&1; // Direction\r
+ dir=(op>>10)&1; // Direction (1==ea2reg)\r
+\r
+ if (dir) {\r
+ if (ea<0x10 || ea>0x3b || (ea&0x38)==0x20) return 1; // Invalid EA\r
+ } else {\r
+ if (ea<0x10 || ea>0x39 || (ea&0x38)==0x18) return 1;\r
+ }\r
\r
- if (ea<0x10 || ea>0x39) return 1; // Invalid EA\r
if ((ea&0x38)==0x18 || (ea&0x38)==0x20) change=1;\r
if ((ea&0x38)==0x20) decr=1; // -(An), bitfield is decr\r
\r
- // See if we can do this opcode:\r
- if (EaCanWrite(ea)==0) return 1;\r
-\r
cea=ea; if (change) cea=0x10;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op);\r
+ OpStart(op,ea,0,1);\r
\r
- ot(" stmdb sp!,{r9} ;@ Push r9\n");\r
ot(" ldrh r11,[r4],#2 ;@ r11=register mask\n");\r
-\r
ot("\n");\r
- ot(";@ Get the address into r9:\n");\r
- EaCalc(9,0x003f,cea,size);\r
+ ot(";@ Get the address into r6:\n");\r
+ EaCalc(6,0x003f,cea,size);\r
\r
- ot(";@ r10=Register Index*4:\n");\r
- if (decr) ot(" mov r10,#0x3c ;@ order reversed for -(An)\n");\r
- else ot(" mov r10,#0\n");\r
+#if !MEMHANDLERS_NEED_PREV_PC\r
+ // must save PC, need a spare register\r
+ ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
+#endif\r
+\r
+ ot(";@ r4=Register Index*4:\n");\r
+ if (decr) ot(" mov r4,#0x40 ;@ order reversed for -(An)\n");\r
+ else ot(" mov r4,#-4\n");\r
\r
ot("\n");\r
- ot("MoreReg%.4x%s\n",op, ms?"":":");\r
+ ot(" tst r11,r11\n"); // sanity check\r
+ ot(" beq NoRegs%.4x\n",op);\r
\r
- ot(" tst r11,#1\n");\r
- ot(" beq SkipReg%.4x\n",op);\r
+#if EMULATE_ADDRESS_ERRORS_IO\r
ot("\n");\r
+ ot(" tst r6,#1 ;@ address error?\n");\r
+ ot(" movne r0,r6\n");\r
+ ot(" bne ExceptionAddressError_%c_data\n",dir?'r':'w');\r
+#endif\r
\r
- if (decr) ot(" sub r9,r9,#%d ;@ Pre-decrement address\n",1<<size);\r
+ ot("\n");\r
+ ot("Movemloop%.4x%s\n",op, ms?"":":");\r
+ ot(" add r4,r4,#%d ;@ r4=Next Register\n",decr?-4:4);\r
+ ot(" movs r11,r11,lsr #1\n");\r
+ ot(" bcc Movemloop%.4x\n",op);\r
+ ot("\n");\r
+\r
+ if (decr) ot(" sub r6,r6,#%d ;@ Pre-decrement address\n",1<<size);\r
\r
if (dir)\r
{\r
ot(" ;@ Copy memory to register:\n",1<<size);\r
- EaRead (9,0,ea,size);\r
- ot(" str r0,[r7,r10] ;@ Save value into Dn/An\n");\r
+ earead_check_addrerr=0; // already checked\r
+ EaRead (6,0,ea,size,0x003f);\r
+ ot(" str r0,[r7,r4] ;@ Save value into Dn/An\n");\r
}\r
else\r
{\r
ot(" ;@ Copy register to memory:\n",1<<size);\r
- ot(" ldr r1,[r7,r10] ;@ Load value from Dn/An\n");\r
- EaWrite(9,1,ea,size);\r
+ ot(" ldr r1,[r7,r4] ;@ Load value from Dn/An\n");\r
+#if SPLIT_MOVEL_PD\r
+ if (decr && size==2) { // -(An)\r
+ ot(" add r0,r6,#2\n");\r
+ EaWrite(0,1,ea,1,0x003f,0,0);\r
+ ot(" ldr r1,[r7,r4] ;@ Load value from Dn/An\n");\r
+ ot(" mov r0,r6\n");\r
+ EaWrite(0,1,ea,1,0x003f,1);\r
+ }\r
+ else\r
+#endif\r
+ {\r
+ EaWrite(6,1,ea,size,0x003f);\r
+ }\r
}\r
\r
- if (decr==0) ot(" add r9,r9,#%d ;@ Post-increment address\n",1<<size);\r
+ if (decr==0) ot(" add r6,r6,#%d ;@ Post-increment address\n",1<<size);\r
\r
ot(" sub r5,r5,#%d ;@ Take some cycles\n",2<<size);\r
- ot("\n");\r
- ot("SkipReg%.4x%s\n",op, ms?"":":");\r
- ot(" movs r11,r11,lsr #1;@ Shift mask:\n");\r
- ot(" add r10,r10,#%d ;@ r10=Next Register\n",decr?-4:4);\r
- ot(" bne MoreReg%.4x\n",op);\r
+ ot(" tst r11,r11\n");\r
+ ot(" bne Movemloop%.4x\n",op);\r
ot("\n");\r
\r
if (change)\r
{\r
ot(";@ Write back address:\n");\r
EaCalc (0,0x0007,8|(ea&7),2);\r
- EaWrite(0, 9,8|(ea&7),2);\r
+ EaWrite(0, 6,8|(ea&7),2,0x0007);\r
}\r
\r
- ot(" ldmia sp!,{r9} ;@ Pop r9\n");\r
+ ot("NoRegs%.4x%s\n",op, ms?"":":");\r
+ ot(" ldr r4,[r7,#0x40]\n");\r
+ ot(" ldr r6,[r7,#0x54] ;@ restore Opcode Jump table\n");\r
ot("\n");\r
\r
- if (ea<0x10) { }\r
- else if (ea<0x18) Cycles=16; // (a0)\r
- else if (ea<0x20) Cycles= 0; // (a0)+ ?\r
- else if (ea<0x28) Cycles= 8; //-(a0)\r
- else if (ea<0x30) Cycles=24; // ($3333,a0)\r
- else if (ea<0x38) Cycles=28; // ($33,a0,d3.w*2)\r
- else if (ea<0x39) Cycles=24; // $3333.w\r
- else if (ea<0x3a) Cycles=28; // $33333333.l\r
+ if(dir) { // er\r
+ if (ea==0x3a) Cycles=16; // ($nn,PC)\r
+ else if (ea==0x3b) Cycles=18; // ($nn,pc,Rn)\r
+ else Cycles=12;\r
+ } else {\r
+ Cycles=8;\r
+ }\r
\r
- OpEnd();\r
+ Cycles+=Ea_add_ns(g_movem_cycle_table,ea);\r
+\r
+ opend_op_changes_cycles = 1;\r
+ OpEnd(ea);\r
+ ot("\n");\r
\r
return 0;\r
}\r
\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op); Cycles=4;\r
-\r
- ot(" ldrb r0,[r7,#0x44] ;@ Get SR\n");\r
- ot(" tst r0,#0x20 ;@ Check we are in supervisor mode\n");\r
- ot(" beq WrongMode%.4x ;@ No\n",op);\r
- ot("\n");\r
+ OpStart(op,0,0,0,1); Cycles=4;\r
\r
if (dir)\r
{\r
- EaCalc (0,0x0007,8,2);\r
+ eawrite_check_addrerr=1;\r
ot(" ldr r1,[r7,#0x48] ;@ Get from USP\n\n");\r
- EaWrite(0, 1,8,2);\r
+ EaCalc (0,0x000f,8,2,1);\r
+ EaWrite(0, 1,8,2,0x000f,1);\r
}\r
else\r
{\r
- EaCalc (0,0x0007,8,2);\r
- EaRead (0, 0,8,2);\r
+ EaCalc (0,0x000f,8,2,1);\r
+ EaRead (0, 0,8,2,0x000f,1);\r
ot(" str r0,[r7,#0x48] ;@ Put in USP\n\n");\r
}\r
\r
OpEnd();\r
\r
- ot("WrongMode%.4x%s\n",op,ms?"":":");\r
- ot(";@ todo - cause an exception\n");\r
- OpEnd();\r
-\r
return 0;\r
}\r
\r
ot(" movs r0,r8,asl #24\n");\r
ot(" and r1,r8,#0x0e00\n");\r
ot(" mov r0,r0,asr #24 ;@ Sign extended Quick value\n");\r
- ot(" mrs r9,cpsr ;@ r9=NZ flags\n");\r
+ ot(" mrs r10,cpsr ;@ r10=NZ flags\n");\r
ot(" str r0,[r7,r1,lsr #7] ;@ Store into Dn\n");\r
ot("\n");\r
\r
\r
OpStart(op); Cycles=6;\r
\r
- ot(" and r10,r8,#0x0e00 ;@ Find T register\n");\r
- ot(" and r11,r8,#0x000f ;@ Find S register\n");\r
- if (type==0x48) ot(" orr r10,r10,#0x1000 ;@ T is an address register\n");\r
+ ot(" and r2,r8,#0x0e00 ;@ Find T register\n");\r
+ ot(" and r3,r8,#0x000f ;@ Find S register\n");\r
+ if (type==0x48) ot(" orr r2,r2,#0x1000 ;@ T is an address register\n");\r
ot("\n");\r
- ot(" ldr r0,[r7,r10,lsr #7] ;@ Get T\n");\r
- ot(" ldr r1,[r7,r11,lsl #2] ;@ Get S\n");\r
+ ot(" ldr r0,[r7,r2,lsr #7] ;@ Get T\n");\r
+ ot(" ldr r1,[r7,r3,lsl #2] ;@ Get S\n");\r
ot("\n");\r
- ot(" str r0,[r7,r11,lsl #2] ;@ T->S\n");\r
- ot(" str r1,[r7,r10,lsr #7] ;@ S->T\n"); \r
+ ot(" str r0,[r7,r3,lsl #2] ;@ T->S\n");\r
+ ot(" str r1,[r7,r2,lsr #7] ;@ S->T\n"); \r
ot("\n");\r
\r
OpEnd();\r
\r
return 0;\r
}\r
+\r
+// ------------------------- movep -------------------------------\r
+// 0000ddd1 0z001sss\r
+// 0000sss1 1z001ddd (to mem)\r
+int OpMovep(int op)\r
+{\r
+ int ea=0,rea=0;\r
+ int size=1,use=0,dir,aadd=0;\r
+\r
+ use=op&0xf1f8;\r
+ if (op!=use) { OpUse(op,use); return 0; } // Use existing handler (for all dests, srcs)\r
+\r
+ // Get EA\r
+ ea = (op&0x0007)|0x28;\r
+ rea= (op&0x0e00)>>9;\r
+ dir = (op>>7)&1;\r
+\r
+ // Find size extension\r
+ if(op&0x0040) size=2;\r
+\r
+ OpStart(op,ea);\r
+ \r
+ if(dir) // reg to mem\r
+ {\r
+ EaCalcReadNoSE(-1,11,rea,size,0x0e00);\r
+\r
+ EaCalc(8,0x000f,ea,size);\r
+ if(size==2) { // if operand is long\r
+ ot(" mov r1,r11,lsr #24 ;@ first byte\n");\r
+ EaWrite(8,1,ea,0,0x000f); // store first byte\r
+ ot(" add r0,r8,#%i\n",(aadd+=2));\r
+ ot(" mov r1,r11,lsr #16 ;@ second byte\n");\r
+ EaWrite(0,1,ea,0,0x000f); // store second byte\r
+ ot(" add r0,r8,#%i\n",(aadd+=2));\r
+ } else {\r
+ ot(" mov r0,r8\n");\r
+ }\r
+ ot(" mov r1,r11,lsr #8 ;@ first or third byte\n");\r
+ EaWrite(0,1,ea,0,0x000f);\r
+ ot(" add r0,r8,#%i\n",(aadd+=2));\r
+ ot(" and r1,r11,#0xff\n");\r
+ EaWrite(0,1,ea,0,0x000f);\r
+ }\r
+ else // mem to reg\r
+ {\r
+ EaCalc(6,0x000f,ea,size,1);\r
+ EaRead(6,11,ea,0,0x000f,1); // read first byte\r
+ ot(" add r0,r6,#2\n");\r
+ EaRead(0,1,ea,0,0x000f,1); // read second byte\r
+ if(size==2) { // if operand is long\r
+ ot(" orr r11,r11,r1,lsr #8 ;@ second byte\n");\r
+ ot(" add r0,r6,#4\n");\r
+ EaRead(0,1,ea,0,0x000f,1);\r
+ ot(" orr r11,r11,r1,lsr #16 ;@ third byte\n");\r
+ ot(" add r0,r6,#6\n");\r
+ EaRead(0,1,ea,0,0x000f,1);\r
+ ot(" orr r1,r11,r1,lsr #24 ;@ fourth byte\n");\r
+ } else {\r
+ ot(" orr r1,r11,r1,lsr #8 ;@ second byte\n");\r
+ }\r
+ // store the result\r
+ EaCalc(0,0x0e00,rea,size,1);\r
+ EaWrite(0,1,rea,size,0x0e00,1);\r
+ ot(" ldr r6,[r7,#0x54]\n");\r
+ }\r
+\r
+ Cycles=(size==2)?24:16;\r
+ OpEnd(ea);\r
+\r
+ return 0;\r
+}\r
+\r
+// Emit a Stop/Reset opcodes, 01001110 011100t0 imm\r
+int OpStopReset(int op)\r
+{\r
+ int type=(op>>1)&1; // stop/reset\r
+\r
+ OpStart(op,0,0,0,1);\r
+\r
+ if(type) {\r
+ // copy immediate to SR, stop the CPU and eat all remaining cycles.\r
+ ot(" ldrh r0,[r4],#2 ;@ Fetch the immediate\n");\r
+ OpRegToFlags(1);\r
+ SuperChange(op,0);\r
+\r
+ ot("\n");\r
+\r
+ ot(" ldr r0,[r7,#0x58]\n");\r
+ ot(" mov r5,#0 ;@ eat cycles\n");\r
+ ot(" orr r0,r0,#1 ;@ stopped\n");\r
+ ot(" str r0,[r7,#0x58]\n");\r
+ ot("\n");\r
+\r
+ Cycles = 4;\r
+ ot("\n");\r
+ }\r
+ else\r
+ {\r
+ Cycles = 132;\r
+#if USE_RESET_CALLBACK\r
+ ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
+ ot(" mov r1,r10,lsr #28\n");\r
+ ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
+ ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
+ ot(" ldr r11,[r7,#0x90] ;@ ResetCallback\n");\r
+ ot(" tst r11,r11\n");\r
+ ot(" movne lr,pc\n");\r
+ ot(" bxne r11 ;@ call ResetCallback if it is defined\n");\r
+ ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");\r
+ ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
+ ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
+ ot(" mov r10,r10,lsl #28\n");\r
+ ot("\n");\r
+#endif\r
+ }\r
+\r
+ OpEnd();\r
+\r
+ return 0;\r
+}\r
+\r
\r
// This file is part of the Cyclone 68000 Emulator\r
\r
-// Copyright (c) 2011 FinalDave (emudave (at) gmail.com)\r
+// Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)\r
+// Copyright (c) 2005-2011 Gražvydas "notaz" Ignotas (notasas (at) gmail.com)\r
\r
// This code is licensed under the GNU General Public License version 2.0 and the MAME License.\r
// You can choose the license that has the most advantages for you.\r
\r
// SVN repository can be found at http://code.google.com/p/cyclone68000/\r
\r
+\r
#include <stdio.h>\r
#include <stdarg.h>\r
#include <stdlib.h>\r
#include <string.h>\r
\r
+#ifndef CONFIG_FILE\r
+#define CONFIG_FILE "config.h"\r
+#endif\r
+#include CONFIG_FILE\r
+\r
// Disa.c\r
-#include "../Pico/Disa.h"\r
+#include "Disa/Disa.h"\r
\r
// Ea.cpp\r
-int EaCalc(int a,int mask,int ea,int size);\r
-int EaRead(int a,int v,int ea,int size,int top=0);\r
+extern int earead_check_addrerr;\r
+extern int eawrite_check_addrerr;\r
+extern int g_jmp_cycle_table[];\r
+extern int g_jsr_cycle_table[];\r
+extern int g_lea_cycle_table[];\r
+extern int g_pea_cycle_table[];\r
+extern int g_movem_cycle_table[];\r
+int Ea_add_ns(int *tab, int ea); // add nonstandard EA cycles\r
+int EaCalc(int a,int mask,int ea,int size,int top=0,int sign_extend=1); // 6\r
+int EaRead(int a,int v,int ea,int size,int mask,int top=0,int sign_extend=1); // 7\r
+int EaCalcRead(int r_ea,int r,int ea,int size,int mask,int sign_extend=1); // 6\r
+int EaCalcReadNoSE(int r_ea,int r,int ea,int size,int mask);\r
int EaCanRead(int ea,int size);\r
-int EaWrite(int a,int v,int ea,int size,int top=0);\r
+int EaWrite(int a,int v,int ea,int size,int mask,int top=0,int sign_extend_ea=1);\r
int EaCanWrite(int ea);\r
+int EaAn(int ea);\r
\r
// Main.cpp\r
-extern int *CyJump; // Jump table\r
-extern int ms; // If non-zero, output in Microsoft ARMASM format\r
-extern char *Narm[4]; // Normal ARM Extensions for operand sizes 0,1,2\r
-extern char *Sarm[4]; // Sign-extend ARM Extensions for operand sizes 0,1,2\r
-extern int Cycles; // Current cycles for opcode\r
-extern int Amatch; // If one, try to match A68K timing\r
-extern int Accu; // Accuracy\r
-extern int Debug; // Debug info\r
+extern int *CyJump; // Jump table\r
+extern int ms; // If non-zero, output in Microsoft ARMASM format\r
+extern const char * const Narm[4]; // Normal ARM Extensions for operand sizes 0,1,2\r
+extern const char * const Sarm[4]; // Sign-extend ARM Extensions for operand sizes 0,1,2\r
+extern int Cycles; // Current cycles for opcode\r
+extern int pc_dirty; // something changed PC during processing\r
+extern int arm_op_count; // for stats\r
void ot(const char *format, ...);\r
void ltorg();\r
-void CheckInterrupt();\r
-int MemHandler(int type,int size);\r
+int MemHandler(int type,int size,int addrreg=0,int need_addrerr_check=1);\r
+void FlushPC(void);\r
\r
// OpAny.cpp\r
-int OpGetFlags(int subtract,int xbit);\r
+extern int g_op;\r
+extern int opend_op_changes_cycles, opend_check_interrupt, opend_check_trace;\r
+int OpGetFlags(int subtract,int xbit,int sprecialz=0);\r
void OpUse(int op,int use);\r
-void OpFirst();\r
-void OpStart(int op);\r
-void OpEnd();\r
-int OpBase(int op);\r
+void OpStart(int op,int sea=0,int tea=0,int op_changes_cycles=0,int supervisor_check=0);\r
+void OpEnd(int sea=0,int tea=0);\r
+int OpBase(int op,int size,int sepa=0);\r
void OpAny(int op);\r
\r
//----------------------\r
int OpArithReg(int op);\r
int OpMul(int op);\r
int OpAbcd(int op);\r
+int OpNbcd(int op);\r
int OpAritha(int op);\r
int OpAddx(int op);\r
int OpCmpEor(int op);\r
+int OpCmpm(int op);\r
+int OpChk(int op);\r
+int GetXBit(int subtract);\r
\r
// OpBranch.cpp\r
void OpPush32();\r
int OpSet(int op);\r
int OpAsr(int op);\r
int OpAsrEa(int op);\r
+int OpTas(int op, int gen_special=0);\r
\r
// OpMove.cpp\r
int OpMove(int op);\r
int OpLea(int op);\r
void OpFlagsToReg(int high);\r
-void OpRegToFlags(int high);\r
+void OpRegToFlags(int high,int srh_reg=0);\r
int OpMoveSr(int op);\r
int OpArithSr(int op);\r
int OpPea(int op);\r
int OpMoveq(int op);\r
int OpMoveUsp(int op);\r
int OpExg(int op);\r
+int OpMovep(int op);\r
+int OpStopReset(int op);\r
+void SuperEnd(void);\r
+void SuperChange(int op,int srh_reg=-1);\r
+\r
--- /dev/null
+\r
+\r
+/**\r
+ * Cyclone 68000 configuration file\r
+**/\r
+\r
+\r
+/*\r
+ * If this option is enabled, Microsoft ARMASM compatible output is generated\r
+ * (output file - Cyclone.asm). Otherwise GNU as syntax is used (Cyclone.s).\r
+ */\r
+#define USE_MS_SYNTAX 0\r
+\r
+/*\r
+ * Enable this option if you are going to use Cyclone to emulate Genesis /\r
+ * Mega Drive system. As VDP chip in these systems had control of the bus,\r
+ * several instructions were acting differently, for example TAS did'n have\r
+ * the write-back phase. That will be emulated, if this option is enabled.\r
+ */\r
+#define CYCLONE_FOR_GENESIS 0\r
+\r
+/*\r
+ * This option compresses Cyclone's jumptable. Because of this the executable\r
+ * will be smaller and load slightly faster and less relocations will be needed.\r
+ * This also fixes the crash problem with 0xfffe and 0xffff opcodes.\r
+ * Warning: if you enable this, you MUST call CycloneInit() before calling\r
+ * CycloneRun(), or else it will crash.\r
+ */\r
+#define COMPRESS_JUMPTABLE 1\r
+\r
+/*\r
+ * Address mask for memory hadlers. The bits set will be masked out of address\r
+ * parameter, which is passed to r/w memory handlers.\r
+ * Using 0xff000000 means that only 24 least significant bits should be used.\r
+ * Set to 0 if you want to mask unused address bits in the memory handlers yourself.\r
+ */\r
+#define MEMHANDLERS_ADDR_MASK 0\r
+\r
+/*\r
+ * Cyclone keeps the 4 least significant bits of SR, PC+membase and it's cycle\r
+ * counter in ARM registers instead of the context for performance reasons. If you for\r
+ * any reason need to access them in your memory handlers, enable the options below,\r
+ * otherwise disable them to improve performance.\r
+ *\r
+ * MEMHANDLERS_NEED_PC updates .pc context field with PC value effective at the time\r
+ * when memhandler was called (opcode address + 2-10 bytes).\r
+ * MEMHANDLERS_NEED_PREV_PC updates .prev_pc context field to currently executed\r
+ * opcode address + 2.\r
+ * Note that .pc and .prev_pc values are always real pointers to memory, so you must\r
+ * subtract .membase to get M68k PC value.\r
+ *\r
+ * Warning: updating PC in memhandlers is dangerous, as Cyclone may internally\r
+ * increment the PC before fetching the next instruction and continue executing\r
+ * at wrong location. It's better to wait until Cyclone CycloneRun() finishes.\r
+ *\r
+ * Warning: if you enable MEMHANDLERS_CHANGE_CYCLES, you must also enable\r
+ * MEMHANDLERS_NEED_CYCLES, or else Cyclone will keep reloading the same cycle\r
+ * count and this will screw timing (if not cause a deadlock).\r
+ */\r
+#define MEMHANDLERS_NEED_PC 0\r
+#define MEMHANDLERS_NEED_PREV_PC 0\r
+#define MEMHANDLERS_NEED_FLAGS 0\r
+#define MEMHANDLERS_NEED_CYCLES 0\r
+#define MEMHANDLERS_CHANGE_PC 0\r
+#define MEMHANDLERS_CHANGE_FLAGS 0\r
+#define MEMHANDLERS_CHANGE_CYCLES 0\r
+\r
+/*\r
+ * If the following macro is defined, Cyclone no longer calls read*, write*,\r
+ * fetch* and checkpc from it's context, it calls these functions directly\r
+ * instead, prefixed with prefix selected below. For example, if\r
+ * MEMHANDLERS_DIRECT_PREFIX is set to cyclone_, it will call cyclone_read8\r
+ * on byte reads.\r
+ * This is to avoid indirect jumps, which are slower. It also saves one ARM\r
+ * instruction.\r
+ */\r
+/* MEMHANDLERS_DIRECT_PREFIX "cyclone_" */\r
+\r
+/*\r
+ * If enabled, Cyclone will call .IrqCallback routine from it's context whenever it\r
+ * acknowledges an IRQ. IRQ level (.irq) is not cleared automatically, do this in your\r
+ * handler if needed.\r
+ * This function must either return vector number to use for interrupt exception,\r
+ * CYCLONE_INT_ACK_AUTOVECTOR to use autovector (this is the most common case), or\r
+ * CYCLONE_INT_ACK_SPURIOUS (least common case).\r
+ * If disabled, it simply uses appropriate autovector, clears the IRQ level and\r
+ * continues execution.\r
+ */\r
+#define USE_INT_ACK_CALLBACK 0\r
+\r
+/*\r
+ * Enable this if you need old PC, flags or cycles;\r
+ * or you change cycles in your IrqCallback function.\r
+ */\r
+#define INT_ACK_NEEDS_STUFF 0\r
+#define INT_ACK_CHANGES_CYCLES 0\r
+\r
+/*\r
+ * If enabled, .ResetCallback is called from the context, whenever RESET opcode is\r
+ * encountered. All context members are valid and can be changed.\r
+ * If disabled, RESET opcode acts as an NOP.\r
+ */\r
+#define USE_RESET_CALLBACK 0\r
+\r
+/*\r
+ * If enabled, UnrecognizedCallback is called if an invalid opcode is\r
+ * encountered. All context members are valid and can be changed. The handler\r
+ * should return zero if you want Cyclone to gererate "Illegal Instruction"\r
+ * exception after this, or nonzero if not. In the later case you should change\r
+ * the PC by yourself, or else Cyclone will keep executing that opcode all over\r
+ * again.\r
+ * If disabled, "Illegal Instruction" exception is generated and execution is\r
+ * continued.\r
+ */\r
+#define USE_UNRECOGNIZED_CALLBACK 0\r
+\r
+/*\r
+ * This option will also call UnrecognizedCallback for a-line and f-line\r
+ * (0xa*** and 0xf***) opcodes the same way as described above, only appropriate\r
+ * exceptions will be generated.\r
+ */\r
+#define USE_AFLINE_CALLBACK 0\r
+\r
+/*\r
+ * This makes Cyclone to call checkpc from it's context whenever it changes the PC\r
+ * by a large value. It takes and should return the PC value in PC+membase form.\r
+ * The flags and cycle counter are not valid in this function.\r
+ */\r
+#define USE_CHECKPC_CALLBACK 1\r
+\r
+/*\r
+ * This determines if checkpc() should be called after jumps when 8 and 16 bit\r
+ * displacement values were used.\r
+ */\r
+#define USE_CHECKPC_OFFSETBITS_16 1\r
+#define USE_CHECKPC_OFFSETBITS_8 0\r
+\r
+/*\r
+ * Call checkpc() after DBcc jumps (which use 16bit displacement). Cyclone prior to\r
+ * 0.0087 never did that.\r
+ */\r
+#define USE_CHECKPC_DBRA 0\r
+\r
+/*\r
+ * When this option is enabled Cyclone will do two word writes instead of one\r
+ * long write when handling MOVE.L or MOVEM.L with pre-decrementing destination,\r
+ * as described in Bart Trzynadlowski's doc (http://www.trzy.org/files/68knotes.txt).\r
+ * Enable this if you are emulating a 16 bit system.\r
+ */\r
+#define SPLIT_MOVEL_PD 1\r
+\r
+/*\r
+ * Enable emulation of trace mode. Shouldn't cause any performance decrease, so it\r
+ * should be safe to keep this ON.\r
+ */\r
+#define EMULATE_TRACE 1\r
+\r
+/*\r
+ * If enabled, address error exception will be generated if 68k code jumps to an\r
+ * odd address. Causes very small performance hit (2 ARM instructions for every\r
+ * emulated jump/return/exception in normal case).\r
+ * Note: checkpc() must not clear least significant bit of rebased address\r
+ * for this to work, as checks are performed after calling checkpc().\r
+ */\r
+#define EMULATE_ADDRESS_ERRORS_JUMP 1\r
+\r
+/*\r
+ * If enabled, address error exception will be generated if 68k code tries to\r
+ * access a word or longword at an odd address. The performance cost is also 2 ARM\r
+ * instructions per access (for address error checks).\r
+ */\r
+#define EMULATE_ADDRESS_ERRORS_IO 0\r
+\r
+/*\r
+ * If an address error happens during another address error processing,\r
+ * the processor halts until it is reset (catastrophic system failure, as the manual\r
+ * states). This option enables halt emulation.\r
+ * Note that this might be not desired if it is known that emulated system should\r
+ * never reach this state.\r
+ */\r
+#define EMULATE_HALT 0\r
+\r
notaz.gp2x.de / cyclone68000.git / commitdiff