first debug version of ncpu
[fceu.git] / boards / sachen.c
CommitLineData
c62d2810 1/* FCE Ultra - NES/Famicom Emulator
2 *
3 * Copyright notice for this file:
4 * Copyright (C) 2002 Ben Parnell
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include "mapinc.h"
22
23static uint8 cmd;
24static uint8 latch[8];
25#define CHRRAM (GameMemBlock)
26
27static void S74LS374NSynco(void)
28{
29 setprg32(0x8000,latch[0]);
30 setchr8(latch[1]);
31 setmirror(latch[2]&1);
32// setchr8(6);
33}
34
35static DECLFW(S74LS374NWrite)
36{
37 //printf("$%04x:$%02x\n",A,V);
38 A&=0x4101;
39 if(A==0x4100)
40 cmd=V&7;
41 else
42 {
43 switch(cmd)
44 {
45 case 0:latch[0]=0;latch[1]=3;break;
46 case 4:latch[1]&=3;latch[1]|=(V<<2);break;
47 case 5:latch[0]=V&0x7;break;
48 case 6:latch[1]&=0x1C;latch[1]|=V&3;break;
49 case 7:latch[2]=V&1;break;
50 }
51 S74LS374NSynco();
52 }
53}
54
55static void S74LS374NReset(void)
56{
57 latch[0]=latch[2]=0;
58 latch[1]=3;
59 S74LS374NSynco();
60 SetReadHandler(0x8000,0xFFFF,CartBR);
61 SetWriteHandler(0x4100,0x7FFF,S74LS374NWrite);
62}
63
64static void S74LS374NRestore(int version)
65{
66 S74LS374NSynco();
67}
68
69void S74LS374N_Init(void)
70{
71 BoardPower=S74LS374NReset;
72 GameStateRestore=S74LS374NRestore;
73 AddExState(latch, 3, 0, "LATC");
74 AddExState(&cmd, 1, 0, "CMD");
75}
76
77static int type;
78static void S8259Synco(void)
79{
80 int x;
81
82 setprg32(0x8000,latch[5]&7);
83
84 if(!UNIFchrrama) // No CHR RAM? Then BS'ing is ok.
85 {
86 if(!type)
87 {
88 for(x=0;x<4;x++)
89 setchr2(0x800*x,(x&1)|((latch[x]&7)<<1)|((latch[4]&7)<<4));
90 }
91 else
92 {
93 for(x=0;x<4;x++)
94 setchr2(0x800*x,(latch[x]&0x7)|((latch[4]&7)<<3));
95 }
96 }
97 switch((latch[7]>>1)&3)
98 {
99 case 0:setmirrorw(0,0,0,1);break;
100 case 1:setmirror(MI_H);break;
101 case 2:setmirror(MI_V);break;
102 case 3:setmirror(MI_0);break;
103 }
104}
105
106static DECLFW(S8259Write)
107{
108 A&=0x4101;
109 if(A==0x4100) cmd=V;
110 else
111 {
112 latch[cmd&7]=V;
113 S8259Synco();
114 }
115}
116
117static void S8259Reset(void)
118{
119 int x;
120 cmd=0;
121
122 for(x=0;x<8;x++) latch[x]=0;
123 if(UNIFchrrama) setchr8(0);
124
125 S8259Synco();
126 SetReadHandler(0x8000,0xFFFF,CartBR);
127 SetWriteHandler(0x4100,0x7FFF,S8259Write);
128}
129
130static void S8259Restore(int version)
131{
132 S8259Synco();
133}
134
135void S8259A_Init(void)
136{
137 BoardPower=S8259Reset;
138 GameStateRestore=S8259Restore;
139 AddExState(latch, 8, 0, "LATC");
140 AddExState(&cmd, 1, 0, "CMD");
141 type=0;
142
143 //if(!CHRsize[0])
144 //{
145 // SetupCartCHRMapping(0,CHRRAM,8192,1);
146 // AddExState(CHRRAM, 8192, 0, "CHRR");
147 //}
148}
149
150void S8259B_Init(void)
151{
152 BoardPower=S8259Reset;
153 GameStateRestore=S8259Restore;
154 AddExState(latch, 8, 0, "LATC");
155 AddExState(&cmd, 1, 0, "CMD");
156 type=1;
157}
158
159static void(*WSync)(void);
160
161static void SA0161MSynco()
162{
163 setprg32(0x8000,(latch[0]>>3)&1);
164 setchr8(latch[0]&7);
165}
166
167static DECLFW(SAWrite)
168{
169 if(A&0x100)
170 {
171 latch[0]=V;
172 WSync();
173 }
174}
175
176static void SAReset(void)
177{
178 latch[0]=0;
179 WSync();
180 SetReadHandler(0x8000,0xFFFF,CartBR);
181 SetWriteHandler(0x4100,0x5FFF,SAWrite);
182}
183
184void SA0161M_Init(void)
185{
186 WSync=SA0161MSynco;
187 GameStateRestore=SA0161MSynco;
188 BoardPower=SAReset;
189 AddExState(&latch[0], 1, 0, "LATC");
190}
191
192static void SA72007Synco()
193{
194 setprg32(0x8000,0);
195 setchr8(latch[0]>>7);
196}
197
198void SA72007_Init(void)
199{
200 WSync=SA72007Synco;
201 GameStateRestore=SA72007Synco;
202 BoardPower=SAReset;
203 AddExState(&latch[0], 1, 0, "LATC");
204}
205
206static void SA72008Synco()
207{
208 setprg32(0x8000,(latch[0]>>2)&1);
209 setchr8(latch[0]&3);
210}
211
212void SA72008_Init(void)
213{
214 WSync=SA72008Synco;
215 GameStateRestore=SA72008Synco;
216 BoardPower=SAReset;
217 AddExState(&latch[0], 1, 0, "LATC");
218}
219
220static DECLFW(SADWrite)
221{
222 latch[0]=V;
223 WSync();
224}
225
226static void SADReset(void)
227{
228 latch[0]=0;
229 WSync();
230 SetReadHandler(0x8000,0xFFFF,CartBR);
231 SetWriteHandler(0x8000,0xFFFF,SADWrite);
232}
233
234static void SA0036Synco()
235{
236 setprg32(0x8000,0);
237 setchr8(latch[0]>>7);
238}
239
240static void SA0037Synco()
241{
242 setprg32(0x8000,(latch[0]>>3)&1);
243 setchr8(latch[0]&7);
244}
245
246void SA0036_Init(void)
247{
248 WSync=SA0036Synco;
249 GameStateRestore=SA0036Synco;
250 BoardPower=SADReset;
251 AddExState(&latch[0], 1, 0, "LATC");
252}
253
254void SA0037_Init(void)
255{
256 WSync=SA0037Synco;
257 GameStateRestore=SA0037Synco;
258 BoardPower=SADReset;
259 AddExState(&latch[0], 1, 0, "LATC");
260}
261
262static void TCU01Synco()
263{
264 setprg32(0x8000,(latch[0]>>2)&1);
265 setchr8((latch[0]>>3)&0xF);
266}
267
268static DECLFW(TCWrite)
269{
270 if((A&0x103)==0x102)
271 latch[0]=V;
272 TCU01Synco();
273}
274
275static void TCU01Reset(void)
276{
277 latch[0]=0;
278 SetReadHandler(0x8000,0xFFFF,CartBR);
279 SetWriteHandler(0x4100,0xFFFF,TCWrite);
280 TCU01Synco();
281}
282
283void TCU01_Init(void)
284{
285 GameStateRestore=TCU01Synco;
286 BoardPower=TCU01Reset;
287 AddExState(&latch[0], 1, 0, "LATC");
288}
289