--- /dev/null
+/* FCE Ultra - NES/Famicom Emulator\r
+ *\r
+ * Copyright notice for this file:\r
+ * Copyright (C) 1998 BERO\r
+ * Copyright (C) 2002 Xodnizel\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; either version 2 of the License, or\r
+ * (at your option) any later version.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+ */\r
+\r
+#include "mapinc.h"\r
+\r
+static void GenMMC1Power(void);\r
+static void GenMMC1Init(CartInfo *info, int prg, int chr, int wram, int battery);\r
+\r
+static uint8 DRegs[4];\r
+static uint8 Buffer,BufferShift;\r
+\r
+static int mmc1opts;\r
+\r
+static void (*MMC1CHRHook4)(uint32 A, uint8 V);\r
+static void (*MMC1PRGHook16)(uint32 A, uint8 V);\r
+\r
+static uint8 *WRAM=NULL;\r
+static uint8 *CHRRAM=NULL;\r
+static int is155;\r
+\r
+static DECLFW(MBWRAM)\r
+{\r
+ if(!(DRegs[3]&0x10)||is155)\r
+ Page[A>>11][A]=V; // WRAM is enabled.\r
+}\r
+\r
+static DECLFR(MAWRAM)\r
+{\r
+ if((DRegs[3]&0x10)&&!is155)\r
+ return X.DB; // WRAM is disabled\r
+ return(Page[A>>11][A]);\r
+}\r
+\r
+static void MMC1CHR(void)\r
+{\r
+ if(mmc1opts&4)\r
+ {\r
+ if(DRegs[0]&0x10)\r
+ setprg8r(0x10,0x6000,(DRegs[1]>>4)&1);\r
+ else\r
+ setprg8r(0x10,0x6000,(DRegs[1]>>3)&1);\r
+ }\r
+ if(MMC1CHRHook4)\r
+ {\r
+ if(DRegs[0]&0x10)\r
+ {\r
+ MMC1CHRHook4(0x0000,DRegs[1]);\r
+ MMC1CHRHook4(0x1000,DRegs[2]);\r
+ }\r
+ else\r
+ {\r
+ MMC1CHRHook4(0x0000,(DRegs[1]&0xFE));\r
+ MMC1CHRHook4(0x1000,DRegs[1]|1);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if(DRegs[0]&0x10)\r
+ {\r
+ setchr4(0x0000,DRegs[1]);\r
+ setchr4(0x1000,DRegs[2]);\r
+ }\r
+ else\r
+ setchr8(DRegs[1]>>1);\r
+ }\r
+}\r
+\r
+static void MMC1PRG(void)\r
+{\r
+ uint8 offs=DRegs[1]&0x10;\r
+\r
+ if(MMC1PRGHook16)\r
+ {\r
+ switch(DRegs[0]&0xC)\r
+ {\r
+ case 0xC: MMC1PRGHook16(0x8000,(DRegs[3]+offs));\r
+ MMC1PRGHook16(0xC000,0xF+offs);\r
+ break;\r
+ case 0x8: MMC1PRGHook16(0xC000,(DRegs[3]+offs));\r
+ MMC1PRGHook16(0x8000,offs);\r
+ break;\r
+ case 0x0:\r
+ case 0x4:\r
+ MMC1PRGHook16(0x8000,((DRegs[3]&~1)+offs));\r
+ MMC1PRGHook16(0xc000,((DRegs[3]&~1)+offs+1));\r
+ break;\r
+ }\r
+ }\r
+ else switch(DRegs[0]&0xC)\r
+ {\r
+ case 0xC: setprg16(0x8000,(DRegs[3]+offs));\r
+ setprg16(0xC000,0xF+offs);\r
+ break;\r
+ case 0x8: setprg16(0xC000,(DRegs[3]+offs));\r
+ setprg16(0x8000,offs);\r
+ break;\r
+ case 0x0:\r
+ case 0x4:\r
+ setprg16(0x8000,((DRegs[3]&~1)+offs));\r
+ setprg16(0xc000,((DRegs[3]&~1)+offs+1));\r
+ break;\r
+ }\r
+}\r
+\r
+static void MMC1MIRROR(void)\r
+{\r
+ switch(DRegs[0]&3)\r
+ {\r
+ case 2: setmirror(MI_V); break;\r
+ case 3: setmirror(MI_H); break;\r
+ case 0: setmirror(MI_0); break;\r
+ case 1: setmirror(MI_1); break;\r
+ }\r
+}\r
+\r
+\r
+static uint64 lreset;\r
+static DECLFW(MMC1_write)\r
+{\r
+ int n=(A>>13)-4;\r
+ //FCEU_DispMessage("%016x",timestampbase+timestamp);\r
+ //printf("$%04x:$%02x, $%04x\n",A,V,X.PC);\r
+ //DumpMem("out",0xe000,0xffff);\r
+\r
+ /* The MMC1 is busy so ignore the write. */\r
+ /* As of version FCE Ultra 0.81, the timestamp is only\r
+ increased before each instruction is executed(in other words\r
+ precision isn't that great), but this should still work to\r
+ deal with 2 writes in a row from a single RMW instruction. */\r
+ if((timestampbase+timestamp)<(lreset+2)) return;\r
+\r
+ if(V&0x80)\r
+ {\r
+ DRegs[0]|=0xC;\r
+ BufferShift=Buffer=0;\r
+ MMC1PRG();\r
+ lreset=timestampbase+timestamp;\r
+ return;\r
+ }\r
+ Buffer|=(V&1)<<(BufferShift++);\r
+ if(BufferShift==5)\r
+ {\r
+ DRegs[n] = Buffer;\r
+ BufferShift = Buffer = 0;\r
+ switch(n)\r
+ {\r
+ case 0: MMC1MIRROR(); MMC1CHR(); MMC1PRG(); break;\r
+ case 1: MMC1CHR(); MMC1PRG(); break;\r
+ case 2: MMC1CHR(); break;\r
+ case 3: MMC1PRG(); break;\r
+ }\r
+ }\r
+}\r
+\r
+static void MMC1_Restore(int version)\r
+{\r
+ MMC1MIRROR();\r
+ MMC1CHR();\r
+ MMC1PRG();\r
+ //lreset=0; /* timestamp(base) is not stored in save states. */ // it is now!\r
+}\r
+\r
+static void MMC1CMReset(void)\r
+{\r
+ int i;\r
+ for(i=0;i<4;i++)\r
+ DRegs[i]=0;\r
+ Buffer = BufferShift = 0;\r
+ DRegs[0]=0x1F;\r
+ DRegs[1]=0;\r
+ DRegs[2]=0; // Should this be something other than 0?\r
+ DRegs[3]=0;\r
+\r
+ MMC1MIRROR();\r
+ MMC1CHR();\r
+ MMC1PRG();\r
+}\r
+\r
+static int DetectMMC1WRAMSize(uint32 crc32)\r
+{\r
+ switch(crc32)\r
+ {\r
+ case 0xc6182024: /* Romance of the 3 Kingdoms */\r
+ case 0x2225c20f: /* Genghis Khan */\r
+ case 0x4642dda6: /* Nobunaga's Ambition */\r
+ case 0x29449ba9: /* "" "" (J) */\r
+ case 0x2b11e0b0: /* "" "" (J) */\r
+ FCEU_printf(" >8KB external WRAM present. Use UNIF if you hack the ROM image.\n");\r
+ return(16);\r
+ break;\r
+ default:return(8);\r
+ }\r
+}\r
+\r
+static uint32 NWCIRQCount;\r
+static uint8 NWCRec;\r
+#define NWCDIP 0xE\r
+\r
+static void FP_FASTAPASS(1) NWCIRQHook(int a)\r
+{\r
+ if(!(NWCRec&0x10))\r
+ {\r
+ NWCIRQCount+=a;\r
+ if((NWCIRQCount|(NWCDIP<<25))>=0x3e000000)\r
+ {\r
+ NWCIRQCount=0;\r
+ X6502_IRQBegin(FCEU_IQEXT);\r
+ }\r
+ }\r
+}\r
+\r
+static void NWCCHRHook(uint32 A, uint8 V)\r
+{\r
+ if((V&0x10)) // && !(NWCRec&0x10))\r
+ {\r
+ NWCIRQCount=0;\r
+ X6502_IRQEnd(FCEU_IQEXT);\r
+ }\r
+ NWCRec=V;\r
+ if(V&0x08)\r
+ MMC1PRG();\r
+ else\r
+ setprg32(0x8000,(V>>1)&3);\r
+}\r
+\r
+static void NWCPRGHook(uint32 A, uint8 V)\r
+{\r
+ if(NWCRec&0x8)\r
+ setprg16(A,8|(V&0x7));\r
+ else\r
+ setprg32(0x8000,(NWCRec>>1)&3);\r
+}\r
+\r
+static void NWCPower(void)\r
+{\r
+ GenMMC1Power();\r
+ setchr8r(0,0);\r
+}\r
+\r
+void Mapper105_Init(CartInfo *info)\r
+{\r
+ GenMMC1Init(info, 256, 256, 8, 0);\r
+ MMC1CHRHook4=NWCCHRHook;\r
+ MMC1PRGHook16=NWCPRGHook;\r
+ MapIRQHook=NWCIRQHook;\r
+ info->Power=NWCPower;\r
+}\r
+\r
+static void GenMMC1Power(void)\r
+{\r
+ lreset=0;\r
+ if(mmc1opts&1)\r
+ {\r
+ FCEU_CheatAddRAM(8,0x6000,WRAM);\r
+ if(mmc1opts&4)\r
+ FCEU_dwmemset(WRAM,0,8192)\r
+ else if(!(mmc1opts&2))\r
+ FCEU_dwmemset(WRAM,0,8192);\r
+ }\r
+ SetWriteHandler(0x8000,0xFFFF,MMC1_write);\r
+ SetReadHandler(0x8000,0xFFFF,CartBR);\r
+\r
+ if(mmc1opts&1)\r
+ {\r
+ SetReadHandler(0x6000,0x7FFF,MAWRAM);\r
+ SetWriteHandler(0x6000,0x7FFF,MBWRAM);\r
+ setprg8r(0x10,0x6000,0);\r
+ }\r
+\r
+ MMC1CMReset();\r
+}\r
+\r
+static void GenMMC1Close(void)\r
+{\r
+ if(CHRRAM)\r
+ FCEU_gfree(CHRRAM);\r
+ if(WRAM)\r
+ FCEU_gfree(WRAM);\r
+ CHRRAM=WRAM=NULL;\r
+}\r
+\r
+static void GenMMC1Init(CartInfo *info, int prg, int chr, int wram, int battery)\r
+{\r
+ is155=0;\r
+\r
+ info->Close=GenMMC1Close;\r
+ MMC1PRGHook16=MMC1CHRHook4=0;\r
+ mmc1opts=0;\r
+ PRGmask16[0]&=(prg>>14)-1;\r
+ CHRmask4[0]&=(chr>>12)-1;\r
+ CHRmask8[0]&=(chr>>13)-1;\r
+\r
+ if(wram)\r
+ {\r
+ WRAM=(uint8*)FCEU_gmalloc(wram*1024);\r
+ mmc1opts|=1;\r
+ if(wram>8) mmc1opts|=4;\r
+ SetupCartPRGMapping(0x10,WRAM,wram*1024,1);\r
+ AddExState(WRAM, wram*1024, 0, "WRAM");\r
+ if(battery)\r
+ {\r
+ mmc1opts|=2;\r
+ info->SaveGame[0]=WRAM+((mmc1opts&4)?8192:0);\r
+ info->SaveGameLen[0]=8192;\r
+ }\r
+ }\r
+ if(!chr)\r
+ {\r
+ CHRRAM=(uint8*)FCEU_gmalloc(8192);\r
+ SetupCartCHRMapping(0, CHRRAM, 8192, 1);\r
+ AddExState(CHRRAM, 8192, 0, "CHRR");\r
+ }\r
+ AddExState(DRegs, 4, 0, "DREG");\r
+\r
+ info->Power=GenMMC1Power;\r
+ GameStateRestore=MMC1_Restore;\r
+ AddExState(&lreset, 8, 1, "LRST");\r
+ AddExState(&Buffer, 1, 1, "BFFR");\r
+ AddExState(&BufferShift, 1, 1, "BFRS");\r
+}\r
+\r
+void Mapper1_Init(CartInfo *info)\r
+{\r
+ int ws=DetectMMC1WRAMSize(info->CRC32);\r
+ GenMMC1Init(info, 512, 256, ws, info->battery);\r
+}\r
+\r
+/* Same as mapper 1, without respect for WRAM enable bit. */\r
+void Mapper155_Init(CartInfo *info)\r
+{\r
+ GenMMC1Init(info,512,256,8,info->battery);\r
+ is155=1;\r
+}\r
+\r
+void SAROM_Init(CartInfo *info)\r
+{\r
+ GenMMC1Init(info, 128, 64, 8, info->battery);\r
+}\r
+\r
+void SBROM_Init(CartInfo *info)\r
+{\r
+ GenMMC1Init(info, 128, 64, 0, 0);\r
+}\r
+\r
+void SCROM_Init(CartInfo *info)\r
+{\r
+ GenMMC1Init(info, 128, 128, 0, 0);\r
+}\r
+\r
+void SEROM_Init(CartInfo *info)\r
+{\r
+ GenMMC1Init(info, 32, 64, 0, 0);\r
+}\r
+\r
+void SGROM_Init(CartInfo *info)\r
+{\r
+ GenMMC1Init(info, 256, 0, 0, 0);\r
+}\r
+\r
+void SKROM_Init(CartInfo *info)\r
+{\r
+ GenMMC1Init(info, 256, 64, 8, info->battery);\r
+}\r
+\r
+void SLROM_Init(CartInfo *info)\r
+{\r
+ GenMMC1Init(info, 256, 128, 0, 0);\r
+}\r
+\r
+void SL1ROM_Init(CartInfo *info)\r
+{\r
+ GenMMC1Init(info, 128, 128, 0, 0);\r
+}\r
+\r
+/* Begin unknown - may be wrong - perhaps they use different MMC1s from the\r
+ similarly functioning boards?\r
+*/\r
+\r
+void SL2ROM_Init(CartInfo *info)\r
+{\r
+ GenMMC1Init(info, 256, 256, 0, 0);\r
+}\r
+\r
+void SFROM_Init(CartInfo *info)\r
+{\r
+ GenMMC1Init(info, 256, 256, 0, 0);\r
+}\r
+\r
+void SHROM_Init(CartInfo *info)\r
+{\r
+ GenMMC1Init(info, 256, 256, 0, 0);\r
+}\r
+\r
+/* End unknown */\r
+/* */\r
+/* */\r
+\r
+void SNROM_Init(CartInfo *info)\r
+{\r
+ GenMMC1Init(info, 256, 0, 8, info->battery);\r
+}\r
+\r
+void SOROM_Init(CartInfo *info)\r
+{\r
+ GenMMC1Init(info, 256, 0, 16, info->battery);\r
+}\r
+\r
+\r
notaz.gp2x.de / fceu.git / blobdiff