--- /dev/null
+/* FCE Ultra - NES/Famicom Emulator\r
+ *\r
+ * Copyright notice for this file:\r
+ * Copyright (C) 2007-2010 CaH4e3\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; either version 2 of the License, or\r
+ * (at your option) any later version.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA\r
+ *\r
+ * OneBus system\r
+ * Street Dance (Dance pad) (Unl)\r
+ * 101-in-1 Arcade Action II\r
+ * DreamGEAR 75-in-1\r
+ */\r
+\r
+#include "mapinc.h"\r
+\r
+static uint8 isDance;\r
+static uint8 regs[16],regc[6];\r
+static uint8 IRQCount,IRQLatch,IRQa, IRQReload, pcm_enable = 0, pcm_irq = 0;\r
+static int16 pcm_addr, pcm_size, pcm_latch, pcm_clock = 0xF6;\r
+static writefunc old4011write, old4012write, old4013write, old4015write;\r
+static readfunc old4015read;\r
+\r
+static SFORMAT StateRegs[]=\r
+{\r
+ {regc, 6, "REGC"},\r
+ {regs, 16, "REGS"},\r
+ {&IRQReload, 1, "IRQR"},\r
+ {&IRQCount, 1, "IRQC"},\r
+ {&IRQLatch, 1, "IRQL"},\r
+ {&IRQa, 1, "IRQA"},\r
+ {&pcm_enable, 1, "PCME"},\r
+ {&pcm_irq, 1, "PCMIRQ"},\r
+ {&pcm_addr, 2, "PCMADDR"},\r
+ {&pcm_size, 2, "PCMSIZE"},\r
+ {&pcm_latch, 2, "PCMLATCH"},\r
+ {&pcm_clock, 2, "PCMCLOCK"},\r
+ {0}\r
+};\r
+\r
+static void Sync(void)\r
+{\r
+ uint16 cswap = (regs[0xf] & 0x80) << 5;\r
+ uint16 pswap = (regs[0xd]&1)?((regs[0xf] & 0x40) << 8):0;\r
+ uint16 pbase = (regs[0]&0xf0)<<4;\r
+ uint16 cbase = (((regs[0]&0x0f)<<8)|(regs[0xc]<<1)|((regs[0xd]&0xf8)>>3))<<3;\r
+ uint16 pmask = 0x3f>>(regs[0xb]&0xf);\r
+\r
+ setchr1(cswap^0x0000,cbase|(regc[0]&(~1)));\r
+ setchr1(cswap^0x0400,cbase|(regc[0]|1));\r
+ setchr1(cswap^0x0800,cbase|(regc[1]&(-1)));\r
+ setchr1(cswap^0x0c00,cbase|(regc[1]|1));\r
+ setchr1(cswap^0x1000,cbase|(regc[2]));\r
+ setchr1(cswap^0x1400,cbase|(regc[3]));\r
+ setchr1(cswap^0x1800,cbase|(regc[4]));\r
+ setchr1(cswap^0x1c00,cbase|(regc[5]));\r
+\r
+ if(regs[0xd]&2)\r
+ {\r
+ setprg8(pswap^0x8000, pbase|(regs[0x7]&pmask)|(regs[0xa]&(~pmask)));\r
+ setprg8( 0xA000, pbase|(regs[0x8]&pmask)|(regs[0xa]&(~pmask)));\r
+ setprg8(pswap^0xC000, pbase|(regs[0x9]&pmask)|(regs[0xa]&(~pmask)));\r
+ setprg8( 0xE000, pbase|regs[0xa]);\r
+ }\r
+ else\r
+ {\r
+ setprg8(pswap^0x8000, pbase|(regs[0x7]&pmask)|(regs[0xa]&(~pmask)));\r
+ setprg8( 0xA000, pbase|(regs[0x8]&pmask)|(regs[0xa]&(~pmask)));\r
+ setprg8(pswap^0xC000, pbase|((~1)&pmask)|(regs[0xa]&(~pmask)));\r
+ setprg8( 0xE000, pbase|((~0)&pmask)|(regs[0xa]&(~pmask)));\r
+ }\r
+\r
+ setmirror(regs[0xe]);\r
+}\r
+\r
+static DECLFW(UNLOneBusWrite20XX)\r
+{\r
+// FCEU_printf("PPU %04x:%04x\n",A,V);\r
+ if(A == 0x201A)\r
+ regs[0xd] = V;\r
+ else if(A == 0x2018)\r
+ regs[0xc] = V;\r
+ Sync();\r
+}\r
+\r
+static DECLFW(UNLOneBusWriteExp)\r
+{\r
+// FCEU_printf("EXP %04x:%04x\n",A,V);\r
+// switch(A & 0x0F)\r
+// {\r
+// case 2: pcm_latch = pcm_clock; FCEU_printf("write %04x:%04x\n",A,V); break;\r
+// case 3: pcm_irqa = 0; X6502_IRQEnd(FCEU_IQEXT); pcm_irq = 0; FCEU_printf("write %04x:%04x\n",A,V); break;\r
+// case 4: pcm_irqa = 1; FCEU_printf("write %04x:%04x\n",A,V); break;\r
+// default:\r
+ regs[A & 0x0F] = V;\r
+ Sync();\r
+// }\r
+}\r
+\r
+static DECLFW(UNLOneBusWriteDebug)\r
+{\r
+// FCEU_printf("write %04x:%04x\n",A,V);\r
+}\r
+\r
+static DECLFW(UNLOneBusWriteMMC)\r
+{\r
+// FCEU_printf("MMC %04x:%04x\n",A,V);\r
+ switch(A&0xE001)\r
+ {\r
+ case 0x8000: regs[0xf] = V; Sync(); break;\r
+ case 0x8001:\r
+ {\r
+ uint8 mask = 0xff, mmc3cmd = regs[0xf]&7;\r
+ switch(mmc3cmd)\r
+ {\r
+ case 0:\r
+ case 1:\r
+ case 2:\r
+ case 3:\r
+ case 4:\r
+ case 5:\r
+ if(regs[0xd]&4)\r
+ mask = 0x0f;\r
+ else\r
+ mask >>= ((regs[0xb]&0xf0)>>4);\r
+ regc[mmc3cmd] = V&mask;\r
+ break;\r
+ case 6:\r
+ case 7:\r
+ mask = (mask&0x3f)>>(regs[0xb]&0xf);\r
+ regs[mmc3cmd+1] = (regs[mmc3cmd+1]&(~mask))|(V&mask);\r
+ break;\r
+ }\r
+\r
+ Sync();\r
+ break;\r
+ }\r
+ case 0xA000: regs[0xe] = (V & 1)^1; Sync(); break;\r
+ case 0xC000: IRQLatch = V&0xfe; break;\r
+ case 0xC001: IRQReload = 1; break;\r
+ case 0xE000: X6502_IRQEnd(FCEU_IQEXT); IRQa = 0; break;\r
+ case 0xE001: IRQa = 1; break;\r
+ }\r
+}\r
+\r
+static void UNLOneBusIRQHook(void)\r
+{\r
+ int count = IRQCount;\r
+ if(!count || IRQReload)\r
+ {\r
+ IRQCount = IRQLatch;\r
+ IRQReload = 0;\r
+ }\r
+ else\r
+ IRQCount--;\r
+ if(count && !IRQCount)\r
+ {\r
+ if(IRQa)\r
+ X6502_IRQBegin(FCEU_IQEXT);\r
+ }\r
+}\r
+\r
+static DECLFW(UNLOneBusWriteAPU2)\r
+{\r
+// FCEU_printf("APU2 %04x:%04x\n",A,V);\r
+ CartBW(A&0xffdf,V);\r
+}\r
+\r
+static DECLFW(UNLOneBusWrite4012)\r
+{\r
+// FCEU_printf("write %04x:%04x\n",A,V);\r
+ pcm_addr = V << 6;\r
+ old4012write(A,V);\r
+}\r
+\r
+static DECLFW(UNLOneBusWrite4013)\r
+{\r
+// FCEU_printf("write %04x:%04x\n",A,V);\r
+ pcm_size = (V << 4) + 1;\r
+ old4013write(A,V);\r
+}\r
+\r
+static DECLFW(UNLOneBusWrite4015)\r
+{\r
+// FCEU_printf("write %04x:%04x\n",A,V);\r
+ pcm_enable = V&0x10;\r
+ if(pcm_irq)\r
+ {\r
+ X6502_IRQEnd(FCEU_IQEXT);\r
+ pcm_irq = 0;\r
+ }\r
+ if(pcm_enable)\r
+ pcm_latch = pcm_clock;\r
+ old4015write(A,V&0xEF);\r
+}\r
+\r
+static DECLFR(UNLOneBusRead4015)\r
+{\r
+ uint8 result = (old4015read(A) & 0x7F)|pcm_irq;\r
+// FCEU_printf("read %04x, %02x\n",A,result);\r
+ return result;\r
+}\r
+\r
+static void UNLOneBusCpuHook(int a)\r
+{\r
+ if(pcm_enable)\r
+ {\r
+ pcm_latch-=a;\r
+ if(pcm_latch<=0)\r
+ {\r
+ pcm_latch+=pcm_clock;\r
+ pcm_size--;\r
+ if(pcm_size<0)\r
+ {\r
+ pcm_irq = 0x80;\r
+ pcm_enable = 0;\r
+ X6502_IRQBegin(FCEU_IQEXT);\r
+ }\r
+ else\r
+ {\r
+ uint8 raw_pcm = ARead[pcm_addr](pcm_addr) >> 1;\r
+ old4011write(0x4011,raw_pcm);\r
+ pcm_addr++;\r
+ pcm_addr&=0x7FFF;\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+static void UNLOneBusPower(void)\r
+{\r
+ IRQCount=IRQLatch=IRQa==0;\r
+ regs[0]=regs[1]=regs[1]=regs[2]=regs[3]=regs[4]=regs[5]=regs[6]=0;\r
+ regs[7]=regs[8]=regs[11]=regs[12]=regs[13]=regs[14]=regs[15]=0;\r
+ regs[0x09]=0x3E;\r
+ regs[0x0A]=0x3F;\r
+\r
+ SetupCartCHRMapping(0,PRGptr[0],4096 * 1024,0);\r
+\r
+ if(isDance) // quick workaround, TODO: figure out how it works together\r
+ {\r
+ old4015read=GetReadHandler(0x4015);\r
+ SetReadHandler(0x4015,0x4015,UNLOneBusRead4015);\r
+ old4011write=GetWriteHandler(0x4011);\r
+ old4012write=GetWriteHandler(0x4012);\r
+ SetWriteHandler(0x4012,0x4012,UNLOneBusWrite4012);\r
+ old4013write=GetWriteHandler(0x4013);\r
+ SetWriteHandler(0x4013,0x4013,UNLOneBusWrite4013);\r
+ old4015write=GetWriteHandler(0x4015);\r
+ SetWriteHandler(0x4015,0x4015,UNLOneBusWrite4015);\r
+ }\r
+\r
+ SetReadHandler(0x8000,0xFFFF,CartBR);\r
+ SetWriteHandler(0x2009,0x2fff,UNLOneBusWrite20XX);\r
+// SetWriteHandler(0x4020,0xffff,UNLOneBusWriteDebug);\r
+// SetWriteHandler(0x4020,0x4040,UNLOneBusWriteAPU2);\r
+ SetWriteHandler(0x4100,0x410f,UNLOneBusWriteExp);\r
+ SetWriteHandler(0x8000,0xefff,UNLOneBusWriteMMC);\r
+ Sync();\r
+}\r
+\r
+static void UNLOneBusReset(void)\r
+{\r
+ IRQCount=IRQLatch=IRQa=0;\r
+ regs[0]=regs[1]=regs[1]=regs[2]=regs[3]=regs[4]=regs[5]=regs[6]=0;\r
+ regs[7]=regs[8]=regs[11]=regs[12]=regs[13]=regs[14]=regs[15]=0;\r
+ regs[0x09]=0x3E;\r
+ regs[0x0A]=0x3F;\r
+ Sync();\r
+}\r
+\r
+static void StateRestore(int version)\r
+{\r
+ Sync();\r
+}\r
+\r
+void UNLOneBus_Init(CartInfo *info)\r
+{\r
+ isDance = 0;\r
+ info->Power=UNLOneBusPower;\r
+ info->Reset=UNLOneBusReset;\r
+ GameHBIRQHook=UNLOneBusIRQHook;\r
+// MapIRQHook=UNLOneBusCpuHook;\r
+ GameStateRestore=StateRestore;\r
+ AddExState(&StateRegs, ~0, 0, 0);\r
+}\r
+\r
+void UNLDANCE_Init(CartInfo *info)\r
+{\r
+ isDance = 1;\r
+ info->Power=UNLOneBusPower;\r
+ info->Reset=UNLOneBusReset;\r
+ GameHBIRQHook=UNLOneBusIRQHook;\r
+ MapIRQHook=UNLOneBusCpuHook;\r
+ GameStateRestore=StateRestore;\r
+ AddExState(&StateRegs, ~0, 0, 0);\r
+}\r
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