*\r
* You should have received a copy of the GNU General Public License\r
* along with this program; if not, write to the Free Software\r
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+ *\r
+ * VR02/VT03 Console and OneBus System\r
*\r
- * OneBus system\r
* Street Dance (Dance pad) (Unl)\r
* 101-in-1 Arcade Action II\r
- * DreamGEAR 75-in-1\r
+ * DreamGEAR 75-in-1, etc.\r
+ *\r
*/\r
\r
#include "mapinc.h"\r
\r
-static uint8 isDance;\r
-static uint8 regs[16],regc[6];\r
-static uint8 IRQCount,IRQLatch,IRQa, IRQReload, pcm_enable = 0, pcm_irq = 0;\r
+// General Purpose Registers\r
+static uint8 cpu410x[16], ppu201x[16], apu40xx[64];\r
+\r
+// IRQ Registers\r
+static uint8 IRQCount, IRQa, IRQReload;\r
+#define IRQLatch cpu410x[0x1]\r
+\r
+// MMC3 Registers\r
+static uint8 inv_hack = 0; // some OneBus Systems have swapped PRG reg commans in MMC3 inplementation,\r
+ // trying to autodetect unusual behavior, due not to add a new mapper.\r
+#define mmc3cmd cpu410x[0x5]\r
+#define mirror cpu410x[0x6]\r
+\r
+// APU Registers\r
+static uint8 pcm_enable = 0, pcm_irq = 0;\r
static int16 pcm_addr, pcm_size, pcm_latch, pcm_clock = 0xF6;\r
-static writefunc old4011write, old4012write, old4013write, old4015write;\r
-static readfunc old4015read;\r
+\r
+static writefunc defapuwrite[64];\r
+static readfunc defapuread[64];\r
\r
static SFORMAT StateRegs[]=\r
{\r
- {regc, 6, "REGC"},\r
- {regs, 16, "REGS"},\r
+ {cpu410x, 16, "REGC"},\r
+ {ppu201x, 16, "REGS"},\r
+ {apu40xx, 64, "REGA"},\r
{&IRQReload, 1, "IRQR"},\r
{&IRQCount, 1, "IRQC"},\r
- {&IRQLatch, 1, "IRQL"},\r
{&IRQa, 1, "IRQA"},\r
{&pcm_enable, 1, "PCME"},\r
- {&pcm_irq, 1, "PCMIRQ"},\r
- {&pcm_addr, 2, "PCMADDR"},\r
- {&pcm_size, 2, "PCMSIZE"},\r
- {&pcm_latch, 2, "PCMLATCH"},\r
- {&pcm_clock, 2, "PCMCLOCK"},\r
+ {&pcm_irq, 1, "PCMI"},\r
+ {&pcm_addr, 2, "PCMA"},\r
+ {&pcm_size, 2, "PCMS"},\r
+ {&pcm_latch, 2, "PCML"},\r
+ {&pcm_clock, 2, "PCMC"},\r
{0}\r
};\r
\r
-static void Sync(void)\r
+static void PSync(void)\r
{\r
- uint16 cswap = (regs[0xf] & 0x80) << 5;\r
- uint16 pswap = (regs[0xd]&1)?((regs[0xf] & 0x40) << 8):0;\r
- uint16 pbase = (regs[0]&0xf0)<<4;\r
- uint16 cbase = (((regs[0]&0x0f)<<8)|(regs[0xc]<<1)|((regs[0xd]&0xf8)>>3))<<3;\r
- uint16 pmask = 0x3f>>(regs[0xb]&0xf);\r
-\r
- setchr1(cswap^0x0000,cbase|(regc[0]&(~1)));\r
- setchr1(cswap^0x0400,cbase|(regc[0]|1));\r
- setchr1(cswap^0x0800,cbase|(regc[1]&(-1)));\r
- setchr1(cswap^0x0c00,cbase|(regc[1]|1));\r
- setchr1(cswap^0x1000,cbase|(regc[2]));\r
- setchr1(cswap^0x1400,cbase|(regc[3]));\r
- setchr1(cswap^0x1800,cbase|(regc[4]));\r
- setchr1(cswap^0x1c00,cbase|(regc[5]));\r
-\r
- if(regs[0xd]&2)\r
- {\r
- setprg8(pswap^0x8000, pbase|(regs[0x7]&pmask)|(regs[0xa]&(~pmask)));\r
- setprg8( 0xA000, pbase|(regs[0x8]&pmask)|(regs[0xa]&(~pmask)));\r
- setprg8(pswap^0xC000, pbase|(regs[0x9]&pmask)|(regs[0xa]&(~pmask)));\r
- setprg8( 0xE000, pbase|regs[0xa]);\r
- }\r
- else\r
- {\r
- setprg8(pswap^0x8000, pbase|(regs[0x7]&pmask)|(regs[0xa]&(~pmask)));\r
- setprg8( 0xA000, pbase|(regs[0x8]&pmask)|(regs[0xa]&(~pmask)));\r
- setprg8(pswap^0xC000, pbase|((~1)&pmask)|(regs[0xa]&(~pmask)));\r
- setprg8( 0xE000, pbase|((~0)&pmask)|(regs[0xa]&(~pmask)));\r
- }\r
+ uint8 bankmode = cpu410x[0xb] & 7;\r
+ uint8 mask = (bankmode == 0x7)?(0xff):(0x3f >> bankmode);\r
+ uint32 block = ((cpu410x[0x0] & 0xf0) << 4) + (cpu410x[0xa] & (~mask));\r
+ uint32 pswap = (mmc3cmd & 0x40) << 8;\r
+\r
+// uint8 bank0 = (cpu410x[0xb] & 0x40)?(~1):(cpu410x[0x7]);\r
+// uint8 bank1 = cpu410x[0x8];\r
+// uint8 bank2 = (cpu410x[0xb] & 0x40)?(cpu410x[0x9]):(~1);\r
+// uint8 bank3 = ~0;\r
+ uint8 bank0 = cpu410x[0x7^inv_hack];\r
+ uint8 bank1 = cpu410x[0x8^inv_hack];\r
+ uint8 bank2 = (cpu410x[0xb] & 0x40)?(cpu410x[0x9]):(~1);\r
+ uint8 bank3 = ~0;\r
\r
- setmirror(regs[0xe]);\r
+// FCEU_printf(" PRG: %04x [%02x]",0x8000^pswap,block | (bank0 & mask));\r
+ setprg8(0x8000^pswap, block | (bank0 & mask));\r
+// FCEU_printf(" %04x [%02x]",0xa000^pswap,block | (bank1 & mask));\r
+ setprg8(0xa000, block | (bank1 & mask));\r
+// FCEU_printf(" %04x [%02x]",0xc000^pswap,block | (bank2 & mask));\r
+ setprg8(0xc000^pswap, block | (bank2 & mask));\r
+// FCEU_printf(" %04x [%02x]\n",0xe000^pswap,block | (bank3 & mask));\r
+ setprg8(0xe000, block | (bank3 & mask));\r
}\r
\r
-static DECLFW(UNLOneBusWrite20XX)\r
+static void CSync(void)\r
{\r
-// FCEU_printf("PPU %04x:%04x\n",A,V);\r
- if(A == 0x201A)\r
- regs[0xd] = V;\r
- else if(A == 0x2018)\r
- regs[0xc] = V;\r
- Sync();\r
+ static const uint8 midx[8] = {0, 1, 2, 0, 3, 4, 5, 0 };\r
+ uint8 mask = 0xff >> midx[ppu201x[0xa] & 7];\r
+ uint32 block = ((cpu410x[0x0] & 0x0f) << 11) + ((ppu201x[0x8] & 0x70) << 4) + (ppu201x[0xa] & (~mask));\r
+ uint32 cswap = (mmc3cmd & 0x80) << 5;\r
+\r
+ uint8 bank0 = ppu201x[0x6]&(~1);\r
+ uint8 bank1 = ppu201x[0x6]|1;\r
+ uint8 bank2 = ppu201x[0x7]&(~1);\r
+ uint8 bank3 = ppu201x[0x7]|1;\r
+ uint8 bank4 = ppu201x[0x2];\r
+ uint8 bank5 = ppu201x[0x3];\r
+ uint8 bank6 = ppu201x[0x4];\r
+ uint8 bank7 = ppu201x[0x5];\r
+\r
+ setchr1(0x0000^cswap, block | (bank0 & mask));\r
+ setchr1(0x0400^cswap, block | (bank1 & mask));\r
+ setchr1(0x0800^cswap, block | (bank2 & mask));\r
+ setchr1(0x0c00^cswap, block | (bank3 & mask));\r
+ setchr1(0x1000^cswap, block | (bank4 & mask));\r
+ setchr1(0x1400^cswap, block | (bank5 & mask));\r
+ setchr1(0x1800^cswap, block | (bank6 & mask));\r
+ setchr1(0x1c00^cswap, block | (bank7 & mask));\r
+\r
+ setmirror((mirror & 1) ^ 1);\r
}\r
\r
-static DECLFW(UNLOneBusWriteExp)\r
+static void Sync(void)\r
{\r
-// FCEU_printf("EXP %04x:%04x\n",A,V);\r
-// switch(A & 0x0F)\r
-// {\r
-// case 2: pcm_latch = pcm_clock; FCEU_printf("write %04x:%04x\n",A,V); break;\r
-// case 3: pcm_irqa = 0; X6502_IRQEnd(FCEU_IQEXT); pcm_irq = 0; FCEU_printf("write %04x:%04x\n",A,V); break;\r
-// case 4: pcm_irqa = 1; FCEU_printf("write %04x:%04x\n",A,V); break;\r
-// default:\r
- regs[A & 0x0F] = V;\r
- Sync();\r
-// }\r
+ PSync();\r
+ CSync();\r
}\r
\r
-static DECLFW(UNLOneBusWriteDebug)\r
+static DECLFW(UNLOneBusWriteCPU410X)\r
{\r
-// FCEU_printf("write %04x:%04x\n",A,V);\r
+// FCEU_printf("CPU %04x:%04x\n",A,V);\r
+ switch(A & 0xf)\r
+ {\r
+ case 0x1: IRQLatch = V & 0xfe; break;\r
+ case 0x2: IRQReload = 1; break;\r
+ case 0x3: X6502_IRQEnd(FCEU_IQEXT); IRQa = 0; break;\r
+ case 0x4: IRQa = 1; break;\r
+ default:\r
+ cpu410x[A & 0xf] = V;\r
+ Sync();\r
+ }\r
}\r
\r
-static DECLFW(UNLOneBusWriteMMC)\r
+static DECLFW(UNLOneBusWritePPU201X)\r
+{\r
+// FCEU_printf("PPU %04x:%04x\n",A,V);\r
+ ppu201x[A & 0x0f] = V;\r
+ Sync();\r
+}\r
+\r
+static DECLFW(UNLOneBusWriteMMC3)\r
{\r
// FCEU_printf("MMC %04x:%04x\n",A,V);\r
- switch(A&0xE001)\r
+ switch(A&0xe001)\r
{\r
- case 0x8000: regs[0xf] = V; Sync(); break;\r
+ case 0x8000: mmc3cmd = (mmc3cmd & 0x38) | (V & 0xc7); Sync(); break;\r
case 0x8001:\r
{\r
- uint8 mask = 0xff, mmc3cmd = regs[0xf]&7;\r
- switch(mmc3cmd)\r
+ switch(mmc3cmd & 7)\r
{\r
- case 0:\r
- case 1:\r
- case 2:\r
- case 3:\r
- case 4:\r
- case 5:\r
- if(regs[0xd]&4)\r
- mask = 0x0f;\r
- else\r
- mask >>= ((regs[0xb]&0xf0)>>4);\r
- regc[mmc3cmd] = V&mask;\r
- break;\r
- case 6:\r
- case 7:\r
- mask = (mask&0x3f)>>(regs[0xb]&0xf);\r
- regs[mmc3cmd+1] = (regs[mmc3cmd+1]&(~mask))|(V&mask);\r
- break;\r
+ case 0: ppu201x[0x6] = V; CSync(); break;\r
+ case 1: ppu201x[0x7] = V; CSync(); break;\r
+ case 2: ppu201x[0x2] = V; CSync(); break;\r
+ case 3: ppu201x[0x3] = V; CSync(); break;\r
+ case 4: ppu201x[0x4] = V; CSync(); break;\r
+ case 5: ppu201x[0x5] = V; CSync(); break;\r
+ case 6: cpu410x[0x7] = V; PSync(); break;\r
+ case 7: cpu410x[0x8] = V; PSync(); break;\r
}\r
-\r
- Sync();\r
break;\r
}\r
- case 0xA000: regs[0xe] = (V & 1)^1; Sync(); break;\r
- case 0xC000: IRQLatch = V&0xfe; break;\r
- case 0xC001: IRQReload = 1; break;\r
- case 0xE000: X6502_IRQEnd(FCEU_IQEXT); IRQa = 0; break;\r
- case 0xE001: IRQa = 1; break;\r
+ case 0xa000: mirror = V; CSync(); break;\r
+ case 0xc000: IRQLatch = V & 0xfe; break;\r
+ case 0xc001: IRQReload = 1; break;\r
+ case 0xe000: X6502_IRQEnd(FCEU_IQEXT); IRQa = 0; break;\r
+ case 0xe001: IRQa = 1; break;\r
}\r
}\r
\r
}\r
}\r
\r
-static DECLFW(UNLOneBusWriteAPU2)\r
-{\r
-// FCEU_printf("APU2 %04x:%04x\n",A,V);\r
- CartBW(A&0xffdf,V);\r
-}\r
-\r
-static DECLFW(UNLOneBusWrite4012)\r
-{\r
-// FCEU_printf("write %04x:%04x\n",A,V);\r
- pcm_addr = V << 6;\r
- old4012write(A,V);\r
-}\r
-\r
-static DECLFW(UNLOneBusWrite4013)\r
+static DECLFW(UNLOneBusWriteAPU40XX)\r
{\r
-// FCEU_printf("write %04x:%04x\n",A,V);\r
- pcm_size = (V << 4) + 1;\r
- old4013write(A,V);\r
-}\r
-\r
-static DECLFW(UNLOneBusWrite4015)\r
-{\r
-// FCEU_printf("write %04x:%04x\n",A,V);\r
- pcm_enable = V&0x10;\r
- if(pcm_irq)\r
+// FCEU_printf("APU %04x:%04x\n",A,V);\r
+ apu40xx[A & 0x3f] = V;\r
+ switch(A & 0x3f)\r
{\r
- X6502_IRQEnd(FCEU_IQEXT);\r
- pcm_irq = 0;\r
+ case 0x12:\r
+ if(apu40xx[0x30] & 0x10)\r
+ {\r
+ pcm_addr = V << 6;\r
+ }\r
+ case 0x13:\r
+ if(apu40xx[0x30] & 0x10)\r
+ {\r
+ pcm_size = (V << 4) + 1;\r
+ }\r
+ case 0x15:\r
+ if(apu40xx[0x30] & 0x10)\r
+ {\r
+ pcm_enable = V&0x10;\r
+ if(pcm_irq)\r
+ {\r
+ X6502_IRQEnd(FCEU_IQEXT);\r
+ pcm_irq = 0;\r
+ }\r
+ if(pcm_enable)\r
+ pcm_latch = pcm_clock;\r
+ V &= 0xef;\r
+ }\r
}\r
- if(pcm_enable)\r
- pcm_latch = pcm_clock;\r
- old4015write(A,V&0xEF);\r
+ defapuwrite[A & 0x3f](A, V);\r
}\r
\r
-static DECLFR(UNLOneBusRead4015)\r
+static DECLFR(UNLOneBusReadAPU40XX)\r
{\r
- uint8 result = (old4015read(A) & 0x7F)|pcm_irq;\r
+ uint8 result = defapuread[A & 0x3f](A);\r
// FCEU_printf("read %04x, %02x\n",A,result);\r
+ switch(A & 0x3f)\r
+ {\r
+ case 0x15:\r
+ if(apu40xx[0x30] & 0x10)\r
+ {\r
+ result = (result & 0x7f) | pcm_irq;\r
+ }\r
+ }\r
return result;\r
}\r
\r
else\r
{\r
uint8 raw_pcm = ARead[pcm_addr](pcm_addr) >> 1;\r
- old4011write(0x4011,raw_pcm);\r
+ defapuwrite[0x11](0x4011,raw_pcm);\r
pcm_addr++;\r
pcm_addr&=0x7FFF;\r
}\r
\r
static void UNLOneBusPower(void)\r
{\r
- IRQCount=IRQLatch=IRQa==0;\r
- regs[0]=regs[1]=regs[1]=regs[2]=regs[3]=regs[4]=regs[5]=regs[6]=0;\r
- regs[7]=regs[8]=regs[11]=regs[12]=regs[13]=regs[14]=regs[15]=0;\r
- regs[0x09]=0x3E;\r
- regs[0x0A]=0x3F;\r
+ uint32 i;\r
+ IRQReload = IRQCount = IRQa = 0;\r
+\r
+ memset(cpu410x, 0x00, sizeof(cpu410x));\r
+ memset(ppu201x, 0x00, sizeof(ppu201x));\r
+ memset(apu40xx, 0x00, sizeof(apu40xx));\r
\r
- SetupCartCHRMapping(0,PRGptr[0],4096 * 1024,0);\r
+ SetupCartCHRMapping(0, PRGptr[0], PRGsize[0], 0);\r
\r
- if(isDance) // quick workaround, TODO: figure out how it works together\r
+ for(i=0; i<64; i++)\r
{\r
- old4015read=GetReadHandler(0x4015);\r
- SetReadHandler(0x4015,0x4015,UNLOneBusRead4015);\r
- old4011write=GetWriteHandler(0x4011);\r
- old4012write=GetWriteHandler(0x4012);\r
- SetWriteHandler(0x4012,0x4012,UNLOneBusWrite4012);\r
- old4013write=GetWriteHandler(0x4013);\r
- SetWriteHandler(0x4013,0x4013,UNLOneBusWrite4013);\r
- old4015write=GetWriteHandler(0x4015);\r
- SetWriteHandler(0x4015,0x4015,UNLOneBusWrite4015);\r
+ defapuread[i] = GetReadHandler(0x4000|i);\r
+ defapuwrite[i] = GetWriteHandler(0x4000|i);\r
}\r
+ SetReadHandler(0x4000,0x403f,UNLOneBusReadAPU40XX);\r
+ SetWriteHandler(0x4000,0x403f,UNLOneBusWriteAPU40XX);\r
\r
SetReadHandler(0x8000,0xFFFF,CartBR);\r
- SetWriteHandler(0x2009,0x2fff,UNLOneBusWrite20XX);\r
-// SetWriteHandler(0x4020,0xffff,UNLOneBusWriteDebug);\r
-// SetWriteHandler(0x4020,0x4040,UNLOneBusWriteAPU2);\r
- SetWriteHandler(0x4100,0x410f,UNLOneBusWriteExp);\r
- SetWriteHandler(0x8000,0xefff,UNLOneBusWriteMMC);\r
+ SetWriteHandler(0x2010,0x201f,UNLOneBusWritePPU201X);\r
+ SetWriteHandler(0x4100,0x410f,UNLOneBusWriteCPU410X);\r
+ SetWriteHandler(0x8000,0xffff,UNLOneBusWriteMMC3);\r
+\r
Sync();\r
}\r
\r
static void UNLOneBusReset(void)\r
{\r
- IRQCount=IRQLatch=IRQa=0;\r
- regs[0]=regs[1]=regs[1]=regs[2]=regs[3]=regs[4]=regs[5]=regs[6]=0;\r
- regs[7]=regs[8]=regs[11]=regs[12]=regs[13]=regs[14]=regs[15]=0;\r
- regs[0x09]=0x3E;\r
- regs[0x0A]=0x3F;\r
+ IRQReload = IRQCount = IRQa = 0;\r
+\r
+ memset(cpu410x, 0x00, sizeof(cpu410x));\r
+ memset(ppu201x, 0x00, sizeof(ppu201x));\r
+ memset(apu40xx, 0x00, sizeof(apu40xx));\r
+\r
Sync();\r
}\r
\r
\r
void UNLOneBus_Init(CartInfo *info)\r
{\r
- isDance = 0;\r
info->Power=UNLOneBusPower;\r
info->Reset=UNLOneBusReset;\r
- GameHBIRQHook=UNLOneBusIRQHook;\r
-// MapIRQHook=UNLOneBusCpuHook;\r
- GameStateRestore=StateRestore;\r
- AddExState(&StateRegs, ~0, 0, 0);\r
-}\r
\r
-void UNLDANCE_Init(CartInfo *info)\r
-{\r
- isDance = 1;\r
- info->Power=UNLOneBusPower;\r
- info->Reset=UNLOneBusReset;\r
+ if(((*(uint32*)&(info->MD5)) == 0x305fcdc3) || // PowerJoy Supermax Carts\r
+ ((*(uint32*)&(info->MD5)) == 0x6abfce8e) )\r
+ inv_hack = 0xf;\r
+\r
GameHBIRQHook=UNLOneBusIRQHook;\r
MapIRQHook=UNLOneBusCpuHook;\r
GameStateRestore=StateRestore;\r
notaz.gp2x.de / fceu.git / blobdiff