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[fceu.git] / drivers / gp2x / cpuctrl.c

diff --git a/drivers/gp2x/cpuctrl.c b/drivers/gp2x/cpuctrl.c
new file mode 100644 (file)
index 0000000..7bbdb67
--- /dev/null
+++ b/drivers/gp2x/cpuctrl.c
@@ -0,0 +1,156 @@
+/*  cpuctrl for GP2X
+    Copyright (C) 2005  Hermes/PS2Reality 
+       the gamma-routine was provided by theoddbot
+       parts (c) Rlyehs Work & (C) 2006 god_at_hell 
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+
+*/
+
+
+#include <sys/mman.h>
+#include <math.h>
+#include "cpuctrl.h"
+
+
+/* system registers */
+static struct 
+{
+       unsigned short SYSCLKENREG,SYSCSETREG,FPLLVSETREG,DUALINT920,DUALINT940,DUALCTRL940,MEMTIMEX0,MEMTIMEX1;
+}
+system_reg;
+
+static unsigned short dispclockdiv;
+
+static volatile unsigned short *MEM_REG;
+
+#define SYS_CLK_FREQ 7372800
+
+
+void cpuctrl_init(void)
+{
+       extern volatile unsigned short *gp2x_memregs; /* from minimal library rlyeh */
+       MEM_REG=&gp2x_memregs[0];
+       system_reg.SYSCSETREG=MEM_REG[0x91c>>1];
+       system_reg.FPLLVSETREG=MEM_REG[0x912>>1];
+       system_reg.SYSCLKENREG=MEM_REG[0x904>>1];
+       system_reg.DUALINT920=MEM_REG[0x3B40>>1];
+       system_reg.DUALINT940=MEM_REG[0x3B42>>1];
+       system_reg.DUALCTRL940=MEM_REG[0x3B48>>1];
+       system_reg.MEMTIMEX0=MEM_REG[0x3802>>1];
+       system_reg.MEMTIMEX1=MEM_REG[0x3804>>1];
+       dispclockdiv=MEM_REG[0x924>>1];
+}
+
+
+void cpuctrl_deinit(void)
+{
+       MEM_REG[0x91c>>1]=system_reg.SYSCSETREG;
+       MEM_REG[0x910>>1]=system_reg.FPLLVSETREG;
+       MEM_REG[0x3B40>>1]=system_reg.DUALINT920;
+       MEM_REG[0x3B42>>1]=system_reg.DUALINT940;
+       MEM_REG[0x3B48>>1]=system_reg.DUALCTRL940;
+       MEM_REG[0x904>>1]=system_reg.SYSCLKENREG;
+       MEM_REG[0x924>>1]=dispclockdiv;
+       MEM_REG[0x3802>>1]=system_reg.MEMTIMEX0;
+       MEM_REG[0x3804>>1]=system_reg.MEMTIMEX1 /*| 0x9000*/;
+}
+
+
+void set_display_clock_div(unsigned div)
+{
+       div=((div & 63) | 64)<<8;
+       MEM_REG[0x924>>1]=(MEM_REG[0x924>>1] & ~(255<<8)) | div;
+}
+
+
+void set_FCLK(unsigned MHZ)
+{
+       unsigned v;
+       unsigned mdiv,pdiv=3,scale=0;
+       MHZ*=1000000;
+       mdiv=(MHZ*pdiv)/SYS_CLK_FREQ;
+       mdiv=((mdiv-8)<<8) & 0xff00;
+       pdiv=((pdiv-2)<<2) & 0xfc;
+       scale&=3;
+       v=mdiv | pdiv | scale;
+       MEM_REG[0x910>>1]=v;
+}
+
+
+void set_920_Div(unsigned short div)
+{
+       unsigned short v;
+       v = MEM_REG[0x91c>>1] & (~0x3);
+       MEM_REG[0x91c>>1] = (div & 0x7) | v; 
+}
+
+
+void set_DCLK_Div( unsigned short div )
+{
+       unsigned short v;
+       v = (unsigned short)( MEM_REG[0x91c>>1] & (~(0x7 << 6)) );
+       MEM_REG[0x91c>>1] = ((div & 0x7) << 6) | v; 
+}
+
+/*
+void Disable_940(void)
+{
+       MEM_REG[0x3B42>>1];
+       MEM_REG[0x3B42>>1]=0;
+       MEM_REG[0x3B46>>1]=0xffff;      
+       MEM_REG[0x3B48>>1]|= (1 << 7);
+       MEM_REG[0x904>>1]&=0xfffe;
+}
+*/
+
+void set_RAM_Timings(int tRC, int tRAS, int tWR, int tMRD, int tRFC, int tRP, int tRCD)
+{
+       tRC -= 1; tRAS -= 1; tWR -= 1; tMRD -= 1; tRFC -= 1; tRP -= 1; tRCD -= 1; // ???
+       MEM_REG[0x3802>>1] = ((tMRD & 0xF) << 12) | ((tRFC & 0xF) << 8) | ((tRP & 0xF) << 4) | (tRCD & 0xF);
+       MEM_REG[0x3804>>1] = /*0x9000 |*/ ((tRC & 0xF) << 8) | ((tRAS & 0xF) << 4) | (tWR & 0xF);
+}
+
+
+/*
+void gp2x_video_wait_vsync(void)
+{
+       MEM_REG[0x2846>>1]=(MEM_REG[0x2846>>1] | 0x20) & ~2;
+       while(!(MEM_REG[0x2846>>1] & 2));
+}
+*/
+
+void set_gamma(int g100)
+{
+       float gamma = (float) g100 / 100;
+       int i;
+       //printf ("set gamma = %f\r\n",gamma);
+       gamma = 1/gamma;
+
+    //enable gamma
+    MEM_REG[0x2880>>1]&=~(1<<12);
+
+    MEM_REG[0x295C>>1]=0;
+    for(i=0; i<256; i++)
+    {
+               unsigned char g;
+        unsigned short s;
+        g =(unsigned char)(255.0*pow(i/255.0,gamma));
+        s = (g<<8) | g;
+               MEM_REG[0x295E>>1]= s;
+        MEM_REG[0x295E>>1]= g;
+    }
+}
+