perfect vsync, bugfixes

[fceu.git] / drivers / gp2x / cpuctrl.h

diff --git a/drivers/gp2x/cpuctrl.h b/drivers/gp2x/cpuctrl.h
index 5b482a5..d537f4e 100644 (file)
--- a/drivers/gp2x/cpuctrl.h
+++ b/drivers/gp2x/cpuctrl.h
@@ -9,8 +9,19 @@ extern void set_FCLK(unsigned MHZ); /* adjust the clock frequency (in Mhz units)
 extern void set_920_Div(unsigned short div); /* 0 to 7 divider (freq=FCLK/(1+div)) */
 extern void set_DCLK_Div(unsigned short div); /* 0 to 7 divider (freq=FCLK/(1+div)) */
 //extern void Disable_940(void); /* 940t down */
-//extern void gp2x_video_wait_vsync(void);
+
 extern void set_RAM_Timings(int tRC, int tRAS, int tWR, int tMRD, int tRFC, int tRP, int tRCD);
 extern void set_gamma(int g100);
 
+typedef enum
+{
+       LCDR_60 = 0,    /* as close as possible to 60.00Hz, currently only managed to set to ~59.998Hz, has interlacing problems */
+       LCDR_50,        /* 50Hz, has interlacing problems */
+       LCDR_120_20,    /* ~60.10*2Hz, used by FCE Ultra */
+       LCDR_100_02,    /* ~50.01*2Hz, used by FCE Ultra */
+} lcd_rate_t;
+
+extern void set_LCD_custom_rate(lcd_rate_t rate);
+extern void unset_LCD_custom_rate(void);
+
 #endif