/*
bbbb:
-.ascii "lsr_a: %02x"
+.ascii "ab_a: %04x"
.byte 0x0a,0
.align 4
stmfd sp!,{r0-r3,r12,lr}
@ updates fceu "timestamp" variable
-@ loads cycles to reg, reg!=r1, trashes r1
+@ loads cycles to reg, reg!=r1, trashes r1, kills flags
.macro FLUSH_TIMESTAMP reg
+ ands \reg, REG_CYCLE, #0xff
+ beq 1f
ldr r1, [REG_OP_TABLE, #OTOFFS_TIMESTAMP]
- and \reg, REG_CYCLE, #0xff
+ orr REG_CYCLE, REG_CYCLE, \reg, lsl #8 @ put cycles for do_irq_hook
add r1, r1, \reg
bic REG_CYCLE, REG_CYCLE, #0xff
str r1, [REG_OP_TABLE, #OTOFFS_TIMESTAMP]
+1:
.endm
@@@
@@@ ¤Ê¤ó¤«Ì¾Á°¤¬ÊѤÀ¤Ê(¤É¡¼¤Ç¤â¤¤¡¼¤±¤É¡¼
@@@
-.macro CYCLE_NEXT n, hook_check=1
+.macro CYCLE_NEXT n, hook_check=1, do_cyc_add=1
@@DEBUG_INFO
+.if \do_cyc_add
add REG_CYCLE, REG_CYCLE, #\n
+.endif
subs REG_CYCLE, REG_CYCLE, #\n*48<<16
ble cpu_exec_end
.if \hook_check
b do_int
.endm
+@ fceu needs timestamp cycles to be inremented before doing actual opcode.
+@ this is only needed for ops which do memory i/o
+.macro CYCLE_PRE n
+ add REG_CYCLE, REG_CYCLE, #\n
+.endm
+
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@ Read byte
@@@
-.macro READ
- adr lr, 1f
- tst REG_ADDR, #0x8000
- bne read_rom_byte
+.macro READ unused_param
tst REG_ADDR, #0xe000
- bne read_byte
@ RAM
- bic r0, REG_ADDR, #0x1800
- add r0, r0, #OTOFFS_NES_RAM
- ldrb r0, [r0, REG_OP_TABLE]
- @@ ¤È¤¤¤¦¤ï¤±¤Ç¥¸¥ã¥ó¥×¤¹¤ëɬÍפϤʤ¤
-1:
+ biceq r0, REG_ADDR, #0x1800
+ addeq r0, r0, #OTOFFS_NES_RAM
+ ldreqb r0, [r0, REG_OP_TABLE]
+ blne read_byte
.endm
@@@
@@@ OP¤Ç¤Ïr3¤òÊݸ¤·¤Ê¤±¤ì¤Ð¤Ê¤é¤Ê¤¤
.macro READ_WRITE_1
- adr lr, 9999f
- tst REG_ADDR, #0x8000
- bne read_rom_byte
tst REG_ADDR, #0xe000
+ adrne lr, 9999f
bne read_byte
@ RAM
bic REG_ADDR, REG_ADDR, #0x1800
@@@ REG_ADDR¤òÊѹ¹¤¹¤ë¤¬µ¤¤Ë¤¹¤ë¤Ê
@@@
.macro READ_WORD
- READ
+ READ 0
mov REG_PC, r0
add REG_ADDR, REG_ADDR, #1
- READ
+ READ 0
orr r0, REG_PC, r0, lsl #8
.endm
CYCLE_NEXT 4
opAD: @ LDA $nnnn
+ CYCLE_PRE 4
ABS_ADDR
READ
OP_LDA
- CYCLE_NEXT 4
+ CYCLE_NEXT 4,1,0
opBD: @ LDA $nnnn, X
+ CYCLE_PRE 4
ABSX_ADDR
READ
OP_LDA
- CYCLE_NEXT 4
+ CYCLE_NEXT 4,1,0
opB9: @ LDA $nnnn, Y
+ CYCLE_PRE 4
ABSY_ADDR
READ
OP_LDA
- CYCLE_NEXT 4
+ CYCLE_NEXT 4,1,0
opA1: @ LDA ($nn, X)
+ CYCLE_PRE 6
INDX_ADDR
READ
OP_LDA
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
opB1: @ LDA ($nn), Y
+ CYCLE_PRE 5
INDY_ADDR
READ
OP_LDA
- CYCLE_NEXT 5
+ CYCLE_NEXT 5,1,0
opA2: @ LDX #$nn
IMM_VALUE
CYCLE_NEXT 4
opAE: @ LDX $nnnn
+ CYCLE_PRE 4
ABS_ADDR
READ
OP_LDX
- CYCLE_NEXT 4
+ CYCLE_NEXT 4,1,0
opBE: @ LDX $nnnn, Y
+ CYCLE_PRE 4
ABSY_ADDR
READ
OP_LDX
- CYCLE_NEXT 4
+ CYCLE_NEXT 4,1,0
opAC: @ LDY $nnnn
+ CYCLE_PRE 4
ABS_ADDR
READ
OP_LDY
- CYCLE_NEXT 4
+ CYCLE_NEXT 4,1,0
opBC: @ LDY $nnnn, X
+ CYCLE_PRE 4
ABSX_ADDR
READ
OP_LDY
- CYCLE_NEXT 4
+ CYCLE_NEXT 4,1,0
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
CYCLE_NEXT 4
op8D: @ STA $nnnn
+ CYCLE_PRE 4
ABS_ADDR
OP_STA
WRITE_1
- CYCLE_NEXT 4
+ CYCLE_NEXT 4,1,0
op9D: @ STA $nnnn, X
+ CYCLE_PRE 5
ABSX_ADDR_W
OP_STA
WRITE_1
- CYCLE_NEXT 5
+ CYCLE_NEXT 5,1,0
op99: @ STA $nnnn, Y
+ CYCLE_PRE 5
ABSY_ADDR_W
OP_STA
WRITE_1
- CYCLE_NEXT 5
+ CYCLE_NEXT 5,1,0
op81: @ STA ($nn, X)
+ CYCLE_PRE 6
INDX_ADDR
OP_STA
WRITE_1
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
op91: @ STA ($nn), Y
+ CYCLE_PRE 6
INDY_ADDR_W
OP_STA
WRITE_1
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
op86: @ STX $nn
CYCLE_NEXT 4
op8E: @ STX $nnnn
+ CYCLE_PRE 4
ABS_ADDR
mov r0, REG_X
WRITE_1
- CYCLE_NEXT 4
+ CYCLE_NEXT 4,1,0
op84: @ STY $nn
CYCLE_NEXT 4
op8C: @ STY $nnnn
+ CYCLE_PRE 4
ABS_ADDR
mov r0, REG_Y
WRITE_1
- CYCLE_NEXT 4
+ CYCLE_NEXT 4,1,0
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
CYCLE_NEXT 6
opEE: @ INC $nnnn
+ CYCLE_PRE 6
ABS_ADDR
READ_WRITE_1
OP_INC
READ_WRITE_2
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
READ_WRITE_3
OP_INC
READ_WRITE_4
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
opFE: @ INC $nnnn, X
+ CYCLE_PRE 7
ABSX_ADDR_W
READ_WRITE_1
OP_INC
READ_WRITE_2
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
READ_WRITE_3
OP_INC
READ_WRITE_4
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
opE8: @ INX
IMPLIED
CYCLE_NEXT 6
opCE: @ DEC $nnnn
+ CYCLE_PRE 6
ABS_ADDR
READ_WRITE_1
OP_DEC
READ_WRITE_2
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
READ_WRITE_3
OP_DEC
READ_WRITE_4
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
opDE: @ DEC $nnnn, X
+ CYCLE_PRE 7
ABSX_ADDR_W
READ_WRITE_1
OP_DEC
READ_WRITE_2
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
READ_WRITE_3
OP_DEC
READ_WRITE_4
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
opCA: @ DEX
IMPLIED
CYCLE_NEXT 4
op6D: @ ADC $nnnn
+ CYCLE_PRE 4
ABS_ADDR
READ
OP_ADC
- CYCLE_NEXT 4
+ CYCLE_NEXT 4,1,0
op7D: @ ADC $nnnn, X
+ CYCLE_PRE 4
ABSX_ADDR
READ
OP_ADC
- CYCLE_NEXT 4
+ CYCLE_NEXT 4,1,0
op79: @ ADC $nnnn, Y
+ CYCLE_PRE 4
ABSY_ADDR
READ
OP_ADC
- CYCLE_NEXT 4
+ CYCLE_NEXT 4,1,0
op61: @ ADC ($nn, X)
+ CYCLE_PRE 6
INDX_ADDR
READ
OP_ADC
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
op71: @ ADC ($nn), Y
+ CYCLE_PRE 5
INDY_ADDR
READ
OP_ADC
- CYCLE_NEXT 5
+ CYCLE_NEXT 5,1,0
opEB: @ USBC #$nn
opE9: @ SBC #$nn
CYCLE_NEXT 4
opED: @ SBC $nnnn
+ CYCLE_PRE 4
ABS_ADDR
READ
OP_SBC
- CYCLE_NEXT 4
+ CYCLE_NEXT 4,1,0
opFD: @ SBC $nnnn, X
+ CYCLE_PRE 4
ABSX_ADDR
READ
OP_SBC
- CYCLE_NEXT 4
+ CYCLE_NEXT 4,1,0
opF9: @ SBC $nnnn, Y
+ CYCLE_PRE 4
ABSY_ADDR
READ
OP_SBC
- CYCLE_NEXT 4
+ CYCLE_NEXT 4,1,0
opE1: @ SBC ($nn, X)
+ CYCLE_PRE 6
INDX_ADDR
READ
OP_SBC
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
opF1: @ SBC ($nn), Y
+ CYCLE_PRE 5
INDY_ADDR
READ
OP_SBC
- CYCLE_NEXT 5
+ CYCLE_NEXT 5,1,0
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
CYCLE_NEXT 4
op2D: @ AND $nnnn
+ CYCLE_PRE 4
ABS_ADDR
READ
OP_AND
- CYCLE_NEXT 4
+ CYCLE_NEXT 4,1,0
op3D: @ AND $nnnn, X
+ CYCLE_PRE 4
ABSX_ADDR
READ
OP_AND
- CYCLE_NEXT 4
+ CYCLE_NEXT 4,1,0
op39: @ AND $nnnn, Y
+ CYCLE_PRE 4
ABSY_ADDR
READ
OP_AND
- CYCLE_NEXT 4
+ CYCLE_NEXT 4,1,0
op21: @ AND ($nn, X)
+ CYCLE_PRE 6
INDX_ADDR
READ
OP_AND
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
op31: @ AND ($nn), Y
+ CYCLE_PRE 5
INDY_ADDR
READ
OP_AND
- CYCLE_NEXT 5
+ CYCLE_NEXT 5,1,0
op49: @ EOR #$nn
CYCLE_NEXT 4
op4D: @ EOR $nnnn
+ CYCLE_PRE 4
ABS_ADDR
READ
OP_EOR
- CYCLE_NEXT 4
+ CYCLE_NEXT 4,1,0
op5D: @ EOR $nnnn, X
+ CYCLE_PRE 4
ABSX_ADDR
READ
OP_EOR
- CYCLE_NEXT 4
+ CYCLE_NEXT 4,1,0
op59: @ EOR $nnnn, Y
+ CYCLE_PRE 4
ABSY_ADDR
READ
OP_EOR
- CYCLE_NEXT 4
+ CYCLE_NEXT 4,1,0
op41: @ EOR ($nn, X)
+ CYCLE_PRE 6
INDX_ADDR
READ
OP_EOR
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
op51: @ EOR ($nn), Y
+ CYCLE_PRE 5
INDY_ADDR
READ
OP_EOR
- CYCLE_NEXT 5
+ CYCLE_NEXT 5,1,0
op09: @ ORA #$nn
CYCLE_NEXT 4
op0D: @ ORA $nnnn
+ CYCLE_PRE 4
ABS_ADDR
READ
OP_ORA
- CYCLE_NEXT 4
+ CYCLE_NEXT 4,1,0
op1D: @ ORA $nnnn, X
+ CYCLE_PRE 4
ABSX_ADDR
READ
OP_ORA
- CYCLE_NEXT 4
+ CYCLE_NEXT 4,1,0
op19: @ ORA $nnnn, Y
+ CYCLE_PRE 4
ABSY_ADDR
READ
OP_ORA
- CYCLE_NEXT 4
+ CYCLE_NEXT 4,1,0
op01: @ ORA ($nn, X)
+ CYCLE_PRE 6
INDX_ADDR
READ
OP_ORA
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
op11: @ ORA ($nn), Y
+ CYCLE_PRE 5
INDY_ADDR
READ
OP_ORA
- CYCLE_NEXT 5
+ CYCLE_NEXT 5,1,0
CYCLE_NEXT 4
opCD: @ CMP $nnnn
+ CYCLE_PRE 4
ABS_ADDR
READ
OP_CMP
- CYCLE_NEXT 4
+ CYCLE_NEXT 4,1,0
opDD: @ CMP $nnnn, X
+ CYCLE_PRE 4
ABSX_ADDR
READ
OP_CMP
- CYCLE_NEXT 4
+ CYCLE_NEXT 4,1,0
opD9: @ CMP $nnnn, Y
+ CYCLE_PRE 4
ABSY_ADDR
READ
OP_CMP
- CYCLE_NEXT 4
+ CYCLE_NEXT 4,1,0
opC1: @ CMP ($nn, X)
+ CYCLE_PRE 6
INDX_ADDR
READ
OP_CMP
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
opD1: @ CMP ($nn), Y
+ CYCLE_PRE 5
INDY_ADDR
READ
OP_CMP
- CYCLE_NEXT 5
+ CYCLE_NEXT 5,1,0
opE0: @ CPX #$nn
CYCLE_NEXT 3
opEC: @ CPX $nnnn
+ CYCLE_PRE 4
ABS_ADDR
READ
OP_CPX
- CYCLE_NEXT 4
+ CYCLE_NEXT 4,1,0
opC0: @ CPY #$nn
CYCLE_NEXT 3
opCC: @ CPY $nnnn
+ CYCLE_PRE 4
ABS_ADDR
READ
OP_CPY
- CYCLE_NEXT 4
+ CYCLE_NEXT 4,1,0
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
CYCLE_NEXT 3
op2C: @ BIT $nnnn
+ CYCLE_PRE 4
ABS_ADDR
READ
OP_BIT
- CYCLE_NEXT 4
+ CYCLE_NEXT 4,1,0
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
CYCLE_NEXT 6
op0E: @ ASL $nnnn
+ CYCLE_PRE 6
ABS_ADDR
READ_WRITE_1
OP_ASL
READ_WRITE_2
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
READ_WRITE_3
OP_ASL
READ_WRITE_4
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
op1E: @ ASL $nnnn, X
+ CYCLE_PRE 7
ABSX_ADDR_W
READ_WRITE_1
OP_ASL
READ_WRITE_2
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
READ_WRITE_3
OP_ASL
READ_WRITE_4
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
op4A: @ LSR A
CYCLE_NEXT 6
op4E: @ LSR $nnnn
+ CYCLE_PRE 6
ABS_ADDR
READ_WRITE_1
OP_LSR
READ_WRITE_2
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
READ_WRITE_3
OP_LSR
READ_WRITE_4
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
op5E: @ LSR $nnnn, X
+ CYCLE_PRE 7
ABSX_ADDR_W
READ_WRITE_1
OP_LSR
READ_WRITE_2
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
READ_WRITE_3
OP_LSR
READ_WRITE_4
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
CYCLE_NEXT 6
op2E: @ ROL $nnnn
+ CYCLE_PRE 6
ABS_ADDR
READ_WRITE_1
OP_ROL
READ_WRITE_2
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
READ_WRITE_3
OP_ROL
READ_WRITE_4
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
op3E: @ ROL $nnnn, X
+ CYCLE_PRE 7
ABSX_ADDR_W
READ_WRITE_1
OP_ROL
READ_WRITE_2
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
READ_WRITE_3
OP_ROL
READ_WRITE_4
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
op6A: @ ROR A
CYCLE_NEXT 6
op6E: @ ROR $nnnn
+ CYCLE_PRE 6
ABS_ADDR
READ_WRITE_1
OP_ROR
READ_WRITE_2
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
READ_WRITE_3
OP_ROR
READ_WRITE_4
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
op7E: @ ROR $nnnn, X
+ CYCLE_PRE 7
ABSX_ADDR_W
READ_WRITE_1
OP_ROR
READ_WRITE_2
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
READ_WRITE_3
OP_ROR
READ_WRITE_4
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
CYCLE_NEXT 6
op4F: @ SRE $nnnn
+ CYCLE_PRE 6
ABS_ADDR
READ_WRITE_1
OP_SRE
READ_WRITE_2
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
READ_WRITE_3
OP_SRE
READ_WRITE_4
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
op5F: @ SRE $nnnn, X
+ CYCLE_PRE 7
ABSX_ADDR
READ_WRITE_1
OP_SRE
READ_WRITE_2
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
READ_WRITE_3
OP_SRE
READ_WRITE_4
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
op5B: @ SRE $nnnn, Y
+ CYCLE_PRE 7
ABSY_ADDR
READ_WRITE_1
OP_SRE
READ_WRITE_2
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
READ_WRITE_3
OP_SRE
READ_WRITE_4
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
op43: @ SRE ($nn, X)
+ CYCLE_PRE 8
INDX_ADDR
READ_WRITE_1
OP_SRE
READ_WRITE_2
- CYCLE_NEXT 8
+ CYCLE_NEXT 8,1,0
READ_WRITE_3
OP_SRE
READ_WRITE_4
- CYCLE_NEXT 8
+ CYCLE_NEXT 8,1,0
op53: @ SRE ($nn), Y
+ CYCLE_PRE 8
INDY_ADDR_W
READ_WRITE_1
OP_SRE
READ_WRITE_2
- CYCLE_NEXT 8
+ CYCLE_NEXT 8,1,0
READ_WRITE_3
OP_SRE
READ_WRITE_4
- CYCLE_NEXT 8
+ CYCLE_NEXT 8,1,0
op9C: @ SHY $nnnn, X
+ CYCLE_PRE 5
ABSX_ADDR_W
OP_SHY
WRITE_1
- CYCLE_NEXT 5
+ CYCLE_NEXT 5,1,0
opE7: @ ISB $nn
ZERO_ADDR
CYCLE_NEXT 6
opEF: @ ISB $nnnn
+ CYCLE_PRE 6
ABS_ADDR
READ_WRITE_1
OP_ISB
READ_WRITE_2
OP_SBC
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
READ_WRITE_3
OP_ISB
READ_WRITE_4
OP_SBC
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
opFF: @ ISB $nnnn,X
+ CYCLE_PRE 7
ABSX_ADDR
READ_WRITE_1
OP_ISB
READ_WRITE_2
OP_SBC
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
READ_WRITE_3
OP_ISB
READ_WRITE_4
OP_SBC
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
opFB: @ ISB $nnnn, Y
+ CYCLE_PRE 7
ABSY_ADDR
READ_WRITE_1
OP_ISB
READ_WRITE_2
OP_SBC
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
READ_WRITE_3
OP_ISB
READ_WRITE_4
OP_SBC
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
opE3: @ ISB ($nn, X)
+ CYCLE_PRE 7
INDX_ADDR
READ_WRITE_1
OP_ISB
READ_WRITE_2
OP_SBC
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
READ_WRITE_3
OP_ISB
READ_WRITE_4
OP_SBC
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
opF3: @ ISB ($nn), Y
+ CYCLE_PRE 7
INDY_ADDR
READ_WRITE_1
OP_ISB
READ_WRITE_2
OP_SBC
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
READ_WRITE_3
OP_ISB
READ_WRITE_4
OP_SBC
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
opA7: @ LAX $nn
ZERO_ADDR
CYCLE_NEXT 4
opAF: @ LAX $nnnn
+ CYCLE_PRE 4
ABS_ADDR
READ
OP_LAX
- CYCLE_NEXT 4
+ CYCLE_NEXT 4,1,0
opBF: @ LAX $nnnn, Y
+ CYCLE_PRE 4
ABSY_ADDR
READ
OP_LAX
- CYCLE_NEXT 4
+ CYCLE_NEXT 4,1,0
opA3: @ LAX ($nn, X)
+ CYCLE_PRE 6
INDX_ADDR
READ
OP_LAX
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
opB3: @ LAX ($nn), Y
+ CYCLE_PRE 5
INDY_ADDR
READ
OP_LAX
- CYCLE_NEXT 5
+ CYCLE_NEXT 5,1,0
op07: @ SLO $nn
+ CYCLE_PRE 5
ZERO_ADDR
ZP_READ_W
OP_SLO
ZP_WRITE_W
- CYCLE_NEXT 5
+ CYCLE_NEXT 5,1,0
op17: @ SLO $nn, X
ZEROX_ADDR
CYCLE_NEXT 6
op0F: @ SLO $nnnn
+ CYCLE_PRE 6
ABS_ADDR
READ_WRITE_1
OP_SLO
READ_WRITE_2
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
READ_WRITE_3
OP_SLO
READ_WRITE_4
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
op1F: @ SLO $nnnn, X
+ CYCLE_PRE 7
ABSX_ADDR
READ_WRITE_1
OP_SLO
READ_WRITE_2
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
READ_WRITE_3
OP_SLO
READ_WRITE_4
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
op1B: @ SLO $nnnn, Y
+ CYCLE_PRE 7
ABSY_ADDR_W
READ_WRITE_1
OP_SLO
READ_WRITE_2
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
READ_WRITE_3
OP_SLO
READ_WRITE_4
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
op03: @ SLO ($nn, X)
+ CYCLE_PRE 8
INDX_ADDR
READ_WRITE_1
OP_SLO
READ_WRITE_2
- CYCLE_NEXT 8
+ CYCLE_NEXT 8,1,0
READ_WRITE_3
OP_SLO
READ_WRITE_4
- CYCLE_NEXT 8
+ CYCLE_NEXT 8,1,0
op13: @ SLO ($nn), Y
+ CYCLE_PRE 8
INDY_ADDR_W
READ_WRITE_1
OP_SLO
READ_WRITE_2
- CYCLE_NEXT 8
+ CYCLE_NEXT 8,1,0
READ_WRITE_3
OP_SLO
READ_WRITE_4
- CYCLE_NEXT 8
+ CYCLE_NEXT 8,1,0
opCB: @ SBX #$nn
IMM_VALUE
CYCLE_NEXT 6
opCF: @ DCP $nnnn
+ CYCLE_PRE 6
ABS_ADDR
READ_WRITE_1
OP_DCP
READ_WRITE_2
OP_CMP
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
READ_WRITE_3
OP_DCP
READ_WRITE_4
OP_CMP
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
opDF: @ DCP $nnnn, X
+ CYCLE_PRE 7
ABSX_ADDR
READ_WRITE_1
OP_DCP
READ_WRITE_2
OP_CMP
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
READ_WRITE_3
OP_DCP
READ_WRITE_4
OP_CMP
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
opDB: @ DCP $nnnn, Y
+ CYCLE_PRE 7
ABSY_ADDR
READ_WRITE_1
OP_DCP
READ_WRITE_2
OP_CMP
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
READ_WRITE_3
OP_DCP
READ_WRITE_4
OP_CMP
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
opC3: @ DCP ($nn, X)
+ CYCLE_PRE 8
INDX_ADDR
READ_WRITE_1
OP_DCP
READ_WRITE_2
OP_CMP
- CYCLE_NEXT 8
+ CYCLE_NEXT 8,1,0
READ_WRITE_3
OP_DCP
READ_WRITE_4
OP_CMP
- CYCLE_NEXT 8
+ CYCLE_NEXT 8,1,0
opD3: @ DCP ($nn), Y
+ CYCLE_PRE 8
INDY_ADDR
READ_WRITE_1
OP_DCP
READ_WRITE_2
OP_CMP
- CYCLE_NEXT 8
+ CYCLE_NEXT 8,1,0
READ_WRITE_3
OP_DCP
READ_WRITE_4
OP_CMP
- CYCLE_NEXT 8
+ CYCLE_NEXT 8,1,0
op27: @ RLA $nn
ZERO_ADDR
CYCLE_NEXT 6
op2F: @ RLA $nnnn
+ CYCLE_PRE 6
ABS_ADDR
READ_WRITE_1
OP_RLA
READ_WRITE_2
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
READ_WRITE_3
OP_RLA
READ_WRITE_4
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
op3F: @ RLA $nnnn, X
+ CYCLE_PRE 7
ABSX_ADDR_W
READ_WRITE_1
OP_RLA
READ_WRITE_2
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
READ_WRITE_3
OP_RLA
READ_WRITE_4
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
op3B: @ RLA $nnnn, Y
+ CYCLE_PRE 7
ABSY_ADDR_W
READ_WRITE_1
OP_RLA
READ_WRITE_2
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
READ_WRITE_3
OP_RLA
READ_WRITE_4
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
op23: @ RLA ($nn, X)
+ CYCLE_PRE 8
INDX_ADDR
READ_WRITE_1
OP_RLA
READ_WRITE_2
- CYCLE_NEXT 8
+ CYCLE_NEXT 8,1,0
READ_WRITE_3
OP_RLA
READ_WRITE_4
- CYCLE_NEXT 8
+ CYCLE_NEXT 8,1,0
op33: @ RLA ($nn), Y
+ CYCLE_PRE 8
INDY_ADDR_W
READ_WRITE_1
OP_RLA
READ_WRITE_2
- CYCLE_NEXT 8
+ CYCLE_NEXT 8,1,0
READ_WRITE_3
OP_RLA
READ_WRITE_4
- CYCLE_NEXT 8
+ CYCLE_NEXT 8,1,0
op67: @ RRA $nn
ZERO_ADDR
CYCLE_NEXT 6
op6F: @ RRA $nnnn
+ CYCLE_PRE 6
ABS_ADDR
READ_WRITE_1
OP_RRA
READ_WRITE_2
OP_ADC
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
READ_WRITE_3
OP_RRA
READ_WRITE_4
OP_ADC
- CYCLE_NEXT 6
+ CYCLE_NEXT 6,1,0
op7F: @ RRA $nnnn, X
+ CYCLE_PRE 7
ABSX_ADDR_W
READ_WRITE_1
OP_RRA
READ_WRITE_2
OP_ADC
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
READ_WRITE_3
OP_RRA
READ_WRITE_4
OP_ADC
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
op7B: @ RRA $nnnn, Y
+ CYCLE_PRE 7
ABSY_ADDR_W
READ_WRITE_1
OP_RRA
READ_WRITE_2
OP_ADC
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
READ_WRITE_3
OP_RRA
READ_WRITE_4
OP_ADC
- CYCLE_NEXT 7
+ CYCLE_NEXT 7,1,0
op63: @ RRA ($nn, X)
+ CYCLE_PRE 8
INDX_ADDR
READ_WRITE_1
OP_RRA
READ_WRITE_2
OP_ADC
- CYCLE_NEXT 8
+ CYCLE_NEXT 8,1,0
READ_WRITE_3
OP_RRA
READ_WRITE_4
OP_ADC
- CYCLE_NEXT 8
+ CYCLE_NEXT 8,1,0
op73: @ RRA ($nn), Y
+ CYCLE_PRE 8
INDY_ADDR_W
READ_WRITE_1
OP_RRA
READ_WRITE_2
OP_ADC
- CYCLE_NEXT 8
+ CYCLE_NEXT 8,1,0
READ_WRITE_3
OP_RRA
READ_WRITE_4
OP_ADC
- CYCLE_NEXT 8
+ CYCLE_NEXT 8,1,0
op04: @ NOP $nn
@@@ ----
@ JMP ($nnnn)
op6C:
+ CYCLE_PRE 5
ABS_ADDR
and r0, REG_ADDR, #0xFF
teq r0, #0xFF
beq jmp_indirect_bug
READ_WORD
REBASE_PC
- CYCLE_NEXT 5
+ CYCLE_NEXT 5,1,0
jmp_indirect_bug:
@@
@@ BUG is : to not read word at REG_ADDR, because it loops
@@ but read low part at REG_ADDR and high part at REG_ADDR&0xFF00 instead of REG_ADDR+1
@@
- READ
+ READ 0
mov REG_PC, r0
and REG_ADDR, REG_ADDR, #0xff00
- READ
+ READ 0
orr r0, REG_PC, r0, lsl #8
REBASE_PC
- CYCLE_NEXT 5
+ CYCLE_NEXT 5,1,0
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@ WARNING: decrements REG_PC
@@@
do_int:
+ add REG_CYCLE, REG_CYCLE, #7
ldr r0, [REG_OP_TABLE, #OTOFFS_PC_BASE]
sub REG_PC, REG_PC, #1
sub r0, REG_PC, r0
REBASE_PC
@ CYCLE_NEXT 7
- add REG_CYCLE, REG_CYCLE, #7
subs REG_CYCLE, REG_CYCLE, #7*48<<16
ble cpu_exec_end
ldrb r0, [REG_PC], #1
@@@ low-level memhandlers
@@@
+/*
+@ disabled because no improvements noticed, only causes trouble (with gg for example)
read_rom_byte:
-#ifndef DEBUG_ASM_6502
+@ try to avoid lookup of every address at least for ROM and RAM areas
+@ I've verified that if ARead[0xfff0] points to CartBR, it is always normal ROM read.
ldr r0, =CartBR
ldr r2, =ARead
mov r1, #0xff00
ldr r2, [r2, r1, lsl #2]
ldrb r0, [r2, REG_ADDR]
bx lr
-#endif
+*/
read_byte:
@ must preserve r3 for the callers too
@ TODO: check if all of saves are needed, _DB (is full needed?)
+ FLUSH_TIMESTAMP r2 @ needed for TryFixit1
str REG_PC, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x0c)] @ might get rebased
str REG_P_REST, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x10)] @ might set irq
str REG_CYCLE, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x1c)] @ might get used
str r1, [r3]
ldrsh r1, [r2, #0x1e]
mvn r3, #47 @ r3=-48
- mla r0, r3, r0, r1
- strh r0, [r2, #0x1e]
- bx lr
+ mla r3, r0, r3, r1
+ ldr r1, =MapIRQHook @ hack..
+ strh r3, [r2, #0x1e]
+ ldr r1, [r1]
+ tst r1, r1
+ bxeq lr
+ bx r1
@ rebase PC when not executing or in memhandlers
FLUSH_TIMESTAMP r0
do_irq_hook_noflushts:
+ @ get irqhook cycles
+ and r0, REG_CYCLE, #0xff00
+ bic REG_CYCLE, REG_CYCLE, #0xff00
+ mov r0, r0, lsr #8
#ifndef DEBUG_ASM_6502
@ I have reviewed all MapIRQHook functions, they only seem to cause IRQs, not messing cycles or something
str REG_P_REST, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x10)] @ might set irq
notaz.gp2x.de / fceu.git / blobdiff