+ if ((a & 0xfff00000) == 0x7f000000) {
+ u32 a_ = a & 0xffff;
+ switch (a_) {
+ // GP2X
+ case 0x295a: // MLC_STL_PALLT_D
+ // special unaligned 32bit write, allegro seems to rely on it
+ mmsp2.mlc_stl_pallt_d[mmsp2.mlc_stl_pallt_a++ & 0x1ff] = d;
+ mmsp2.mlc_stl_pallt_d[mmsp2.mlc_stl_pallt_a++ & 0x1ff] = d >> 16;
+ mmsp2.mlc_stl_pallt_a &= 0x1ff;
+ mmsp2.v.dirty_pal = DIRTY_PAL_MMSP2;
+ return;
+ // Wiz
+ case 0x4024: // MLCCONTROL0
+ case 0x4058: // MLCCONTROL1
+ pollux.mlccontrol = d;
+ if (!(d & 0x20))
+ return; // layer not enabled
+ if ((d >> 16) == 0x443A)
+ pollux.v.bpp = 8;
+ else
+ pollux.v.bpp = 16;
+ return;
+ case 0x402c: // MLCVSTRIDE0
+ case 0x4060: // MLCVSTRIDE1
+ pollux.v.stride = d;
+ return;
+ case 0x4038: // MLCADDRESS0
+ case 0x406c: // MLCADDRESS1
+ pollux.mlc_stl_adr = d;
+ if (d != mmsp2.old_mlc_stl_adr) {
+ // ask for refresh
+ fb_sync_thread_futex = 1;
+ g_futex_raw(&fb_sync_thread_futex, FUTEX_WAKE, 1, NULL);
+ }
+ mmsp2.old_mlc_stl_adr = d;
+ return;
+ case 0x403c: // MLCPALETTE0
+ case 0x4070: // MLCPALETTE1
+ pollux.mlcpalette[d >> 24] = d;
+ pollux.v.dirty_pal = DIRTY_PAL_POLLUX;
+ return;
+ }
+ }