#include "header.h"
#include "sys_cacheflush.h"
-//#define iolog printf
+//#define LOG_IO
+//#define LOG_IO_UNH
+//#define LOG_SEGV
+
+#ifdef LOG_IO
+#define iolog log_io
+#else
#define iolog(...)
-//#define segvlog printf
+#endif
+
+#ifdef LOG_IO_UNH
+#define iolog_unh log_io
+#else
+#define iolog_unh(...)
+#endif
+
+#ifdef LOG_SEGV
+#define segvlog printf
+#else
#define segvlog(...)
+#endif
+
+#if defined(LOG_IO) || defined(LOG_IO_UNH)
+#include "mmsp2-regs.h"
+#endif
typedef unsigned int u32;
typedef unsigned short u16;
#define CTRL_TRANSPARENCYENB (1 << 11)
static struct {
+ u16 mlc_stl_cntl;
union {
- u32 mlc_stl_eadr;
+ u32 mlc_stl_adr;
struct {
- u16 mlc_stl_eadrl;
- u16 mlc_stl_eadrh;
+ u16 mlc_stl_adrl;
+ u16 mlc_stl_adrh;
};
};
+ u16 mlc_stl_pallt_a;
+ union {
+ u16 mlc_stl_pallt_d[256*2];
+ u32 mlc_stl_pallt_d32[256];
+ };
+
+ // state
+ u16 host_pal[256];
+ u32 old_mlc_stl_adr;
+ u32 btn_state; // as seen through /dev/GPIO
+ u16 dirty_pal:1;
} mmsp2;
static u16 *host_screen;
static int host_stride;
+#if defined(LOG_IO) || defined(LOG_IO_UNH)
+static void log_io(const char *pfx, u32 a, u32 d, int size)
+{
+ const char *fmt, *reg = "";
+ switch (size) {
+ case 8: fmt = "%s %08x %02x %s\n"; break;
+ case 32: fmt = "%s %08x %08x %s\n"; break;
+ default: fmt = "%s %08x %04x %s\n"; break;
+ }
+
+ if ((a & ~0xffff) == 0x7f000000)
+ reg = regnames[a & 0xffff];
+
+ printf(fmt, pfx, a, d, reg);
+}
+#endif
+
static void memset16(void *dst, u32 pattern, int count)
{
u32 *dl;
} \
}
-static void *upper_lookup(u32 addr, u8 **mem_end, int *stride_override)
+static void *uppermem_lookup(u32 addr, u8 **mem_end)
{
struct uppermem_block *ub;
- // maybe the screen?
- if (mmsp2.mlc_stl_eadr <= addr && addr < mmsp2.mlc_stl_eadr + 320*240*2) {
- host_screen = host_video_flip(); // HACK
- *mem_end = (u8 *)host_screen + host_stride * 240;
- *stride_override = host_stride;
- return (u8 *)host_screen + addr - mmsp2.mlc_stl_eadr;
- }
-
for (ub = upper_mem; ub != NULL; ub = ub->next) {
if (ub->addr <= addr && addr < ub->addr + ub->size) {
*mem_end = (u8 *)ub->mem + ub->size;
return NULL;
}
+static void *blitter_mem_lookup(u32 addr, u8 **mem_end, int *stride_override, int *to_screen)
+{
+ // maybe the screen?
+ if (mmsp2.mlc_stl_adr <= addr && addr < mmsp2.mlc_stl_adr + 320*240*2) {
+ *mem_end = (u8 *)host_screen + host_stride * 240;
+ *stride_override = host_stride;
+ *to_screen = 1;
+ return (u8 *)host_screen + addr - mmsp2.mlc_stl_adr;
+ }
+
+ return uppermem_lookup(addr, mem_end);
+}
+
static void blitter_do(void)
{
u8 *dst, *dste, *src = NULL, *srce = NULL;
int w, h, sstrd, dstrd;
+ int to_screen = 0;
u32 addr;
w = blitter.size & 0x7ff;
// XXX: need to confirm this..
addr = (blitter.dstaddr & ~3) | ((blitter.dstctrl & 0x1f) >> 3);
- dst = upper_lookup(addr, &dste, &dstrd);
+ dst = blitter_mem_lookup(addr, &dste, &dstrd, &to_screen);
if (dst == NULL)
goto bad_blit;
goto bad_blit;
addr = (blitter.srcaddr & ~3) | ((blitter.srcctrl & 0x1f) >> 3);
- src = upper_lookup(addr, &srce, &sstrd);
+ src = blitter_mem_lookup(addr, &srce, &sstrd, &to_screen);
if (src == NULL)
goto bad_blit;
if (src + sstrd * h > srce) {
- printf("blit %08x->%08x %dx%d did not fit src\n",
+ err("blit %08x->%08x %dx%d did not fit src\n",
blitter.srcaddr, blitter.dstaddr, w, h);
h = (srce - src) / sstrd;
}
}
if (dst + dstrd * h > dste) {
- printf("blit %08x->%08x %dx%d did not fit dst\n",
+ err("blit %08x->%08x %dx%d did not fit dst\n",
blitter.srcaddr, blitter.dstaddr, w, h);
h = (dste - dst) / dstrd;
}
for (; h > 0; h--, dst += dstrd)
memset16(dst, bgc, w);
}
+
+ if (to_screen)
+ host_screen = host_video_flip();
return;
bad_blit:
- printf("blit %08x->%08x %dx%d translated to %p->%p\n",
+ err("blit %08x->%08x %dx%d translated to %p->%p\n",
blitter.srcaddr, blitter.dstaddr, w, h, src, dst);
dump_blitter();
}
+// TODO: hw scaler stuff
+static void mlc_flip(u32 addr)
+{
+ int mode = (mmsp2.mlc_stl_cntl >> 9) & 3;
+ int bpp = mode ? mode * 8 : 4;
+ u16 *dst = host_screen;
+ u16 *hpal = mmsp2.host_pal;
+ u8 *src, *src_end;
+ int i, u;
+
+ src = uppermem_lookup(addr, &src_end);
+ if (src == NULL || src + 320*240 * bpp / 8 > src_end) {
+ err("mlc_flip: %08x is out of range\n", addr);
+ return;
+ }
+
+ if (bpp <= 8 && mmsp2.dirty_pal) {
+ u32 *srcp = mmsp2.mlc_stl_pallt_d32;
+ u16 *dstp = hpal;
+
+ for (i = 0; i < 256; i++, srcp++, dstp++) {
+ u32 t = *srcp;
+ *dstp = ((t >> 8) & 0xf800) | ((t >> 5) & 0x07e0) | ((t >> 3) & 0x001f);
+ }
+ mmsp2.dirty_pal = 0;
+ }
+
+ switch (bpp) {
+ case 4:
+ for (i = 0; i < 240; i++, dst += host_stride / 2 - 320) {
+ for (u = 320 / 2; u > 0; u--, src++) {
+ *dst++ = hpal[*src >> 4];
+ *dst++ = hpal[*src & 0x0f];
+ }
+ }
+ break;
+
+ case 8:
+ for (i = 0; i < 240; i++, dst += host_stride / 2 - 320) {
+ for (u = 320 / 4; u > 0; u--) {
+ *dst++ = hpal[*src++];
+ *dst++ = hpal[*src++];
+ *dst++ = hpal[*src++];
+ *dst++ = hpal[*src++];
+ }
+ }
+ break;
+
+ case 16:
+ for (i = 0; i < 240; i++, dst += host_stride / 2, src += 320*2)
+ memcpy(dst, src, 320*2);
+ break;
+
+ case 24:
+ // TODO
+ break;
+ }
+
+ host_screen = host_video_flip();
+}
+
static u32 xread8(u32 a)
{
- iolog("r8 %08x\n", a);
+ iolog("r8 ", a, 0, 8);
+ iolog_unh("r8 ", a, 0, 8);
return 0;
}
static u32 xread16(u32 a)
{
-// if ((a & 0xfff00000) == 0x7f100000) { static int a; a ^= ~1; return a & 0xffff; }
- iolog("r16 %08x\n", a);
- return 0;
+ static u32 fudge, old_a;
+ u32 d = 0, t;
+
+ if ((a & 0xffff0000) == 0x7f000000) {
+ u32 a_ = a & 0xffff;
+ switch (a_) {
+ case 0x0910: // FPLL
+ case 0x0912:
+ d = 0x9407;
+ break;
+ // minilib reads as:
+ // 0000 P000 VuVd00 0000 YXBA RLSeSt 0R0D 0L0U
+ // | GPIOD |GPIOC[8:15]|GPIOM[0:7]|
+ // /dev/GPIO:
+ // ... 0PVdVu ...
+ case 0x1184: // GPIOC
+ d = ~mmsp2.btn_state & 0xff00;
+ d |= 0x00ff;
+ break;
+ case 0x1186: // GPIOD
+ t = ~mmsp2.btn_state;
+ d = (t >> 9) & 0x0080;
+ d |= (t >> 11) & 0x0040;
+ d |= (t >> 7) & 0x0800;
+ d |= 0x373b;
+ break;
+ case 0x1198: // GPIOM
+ mmsp2.btn_state = host_read_btns();
+ d = ~mmsp2.btn_state & 0xff;
+ d |= 0x01aa;
+ break;
+ case 0x28da:
+ d = mmsp2.mlc_stl_cntl;
+ break;
+ case 0x2958:
+ d = mmsp2.mlc_stl_pallt_a;
+ break;
+ default:
+ goto unh;
+ }
+ goto out;
+ }
+
+unh:
+ if (a == old_a) {
+ d = fudge;
+ fudge = ~fudge;
+ }
+ old_a = a;
+ iolog_unh("r16", a, d & 0xffff, 16);
+
+out:
+ d &= 0xffff;
+ iolog("r16", a, d, 16);
+ return d;
}
static u32 xread32(u32 a)
u32 d = 0;
if ((a & 0xfff00000) == 0x7f100000) {
u32 *bl = &blitter.dstctrl;
- a &= 0xfff;
- if (a < 0x40)
- d = bl[a / 4];
- if (a == 0x34)
- d = 0; // not busy
+ u32 a_ = a & 0xfff;
+ if (a_ < 0x40) {
+ d = bl[a_ / 4];
+ if (a_ == 0x34)
+ d = 0; // not busy
+ goto out;
+ }
}
- iolog("r32 %08x\n", a);
+ iolog_unh("r32", a, d, 32);
+
+out:
+ iolog("r32", a, d, 32);
return d;
}
static void xwrite8(u32 a, u32 d)
{
- iolog("w8 %08x %08x\n", a, d);
+ iolog("w8 ", a, d, 8);
+ iolog_unh("w8 ", a, d, 8);
}
static void xwrite16(u32 a, u32 d)
{
- iolog("w16 %08x %08x\n", a, d);
+ iolog("w16", a, d, 16);
if ((a & 0xfff00000) == 0x7f000000) {
- a &= 0xffff;
- switch (a) {
- case 0x2912: mmsp2.mlc_stl_eadrl = d; break;
- case 0x2914: mmsp2.mlc_stl_eadrh = d; break;
+ u32 a_ = a & 0xffff;
+ switch (a_) {
+ case 0x28da:
+ mmsp2.mlc_stl_cntl = d | 0xaa;
+ break;
+ case 0x290e:
+ case 0x2910:
+ // odd addresses don't affect LCD. What about TV?
+ return;
+ case 0x2912:
+ mmsp2.mlc_stl_adrl = d;
+ return;
+ case 0x2914:
+ mmsp2.mlc_stl_adrh = d;
+ if (mmsp2.mlc_stl_adr != mmsp2.old_mlc_stl_adr)
+ mlc_flip(mmsp2.mlc_stl_adr);
+ mmsp2.old_mlc_stl_adr = mmsp2.mlc_stl_adr;
+ return;
+ case 0x2958:
+ mmsp2.mlc_stl_pallt_a = d & 0x1ff;
+ return;
+ case 0x295a:
+ mmsp2.mlc_stl_pallt_d[mmsp2.mlc_stl_pallt_a++] = d;
+ mmsp2.mlc_stl_pallt_a &= 0x1ff;
+ mmsp2.dirty_pal = 1;
+ return;
}
- //printf("w16 %08x %08x\n", a, d);
}
+ iolog_unh("w16", a, d, 16);
}
static void xwrite32(u32 a, u32 d)
{
- iolog("w32 %08x %08x\n", a, d);
- if ((a & 0xfff00000) == 0x7f000000) {
- printf("w32 %08x %08x\n", a, d);
- return;
- }
+ iolog("w32", a, d, 32);
+
if ((a & 0xfff00000) == 0x7f100000) {
u32 *bl = &blitter.dstctrl;
- a &= 0xfff;
- if (a < 0x40)
- bl[a / 4] = d;
- if (a == 0x34 && (d & 1))
- blitter_do();
- return;
+ u32 a_ = a & 0xfff;
+ if (a_ < 0x40) {
+ bl[a_ / 4] = d;
+ if (a_ == 0x34 && (d & 1))
+ blitter_do();
+ return;
+ }
}
+ iolog_unh("w32", a, d, 32);
}
+#define LINKPAGE_SIZE 0x1000
+#define LINKPAGE_COUNT 4
+#define LINKPAGE_ALLOC (LINKPAGE_SIZE * LINKPAGE_COUNT)
+
+struct op_context {
+ u32 pc;
+ u32 op;
+ u32 code[0];
+};
+
+struct linkpage {
+ u32 saved_regs[15];
+ u32 cpsr;
+ u32 *handler_stack;
+ void (*handler)(struct op_context *op_ctx);
+ u32 code[0];
+};
+
+static struct linkpage *g_linkpage;
+static u32 *g_code_ptr;
+static int g_linkpage_count;
+
+#define HANDLER_STACK_SIZE 4096
+static void *g_handler_stack_end;
+
#define BIT_SET(v, b) (v & (1 << (b)))
-static void handle_op(u32 pc, u32 op, u32 *regs, u32 addr_check)
+static void handle_op(struct op_context *op_ctx)
{
+ u32 *regs = g_linkpage->saved_regs;
+ u32 op = op_ctx->op;
u32 t, shift, ret, addr;
int rn, rd;
return;
unhandled:
- fprintf(stderr, "unhandled IO op %08x @ %08x\n", op, pc);
-}
-
-#define LINKPAGE_SIZE 0x1000
-#define LINKPAGE_COUNT 4
-#define LINKPAGE_ALLOC (LINKPAGE_SIZE * LINKPAGE_COUNT)
-
-struct linkpage {
- u32 saved_regs[15];
- u32 *lp_r1;
- void (*handler)(u32 addr_pc, u32 op, u32 *regs, u32 addr_check);
- u32 code[0];
-};
-
-static struct linkpage *g_linkpage;
-static u32 *g_code_ptr;
-static int g_linkpage_count;
-
-static void init_linkpage(void)
-{
- g_linkpage->lp_r1 = &g_linkpage->saved_regs[1];
- g_linkpage->handler = handle_op;
- g_code_ptr = g_linkpage->code;
+ err("unhandled IO op %08x @ %08x\n", op, op_ctx->pc);
}
static u32 make_offset12(u32 *pc, u32 *target)
u = 0;
}
if (lp_offs >= LINKPAGE_SIZE) {
- fprintf(stderr, "linkpage too far: %d\n", lp_offs);
+ err("linkpage too far: %d\n", lp_offs);
abort();
}
return (u << 23) | lp_offs;
}
-static u32 make_jmp(u32 *pc, u32 *target)
+static u32 make_jmp(u32 *pc, u32 *target, int bl)
{
int jmp_val;
jmp_val = target - pc - 2;
if (jmp_val < (int)0xff000000 || jmp_val > 0x00ffffff) {
- fprintf(stderr, "jump out of range (%p -> %p)\n", pc, target);
+ err("jump out of range (%p -> %p)\n", pc, target);
abort();
}
- return 0xea000000 | (jmp_val & 0x00ffffff);
+ return 0xea000000 | (bl << 24) | (jmp_val & 0x00ffffff);
}
static void emit_op(u32 op)
emit_op(op);
}
+static void init_linkpage(void)
+{
+ g_linkpage->handler = handle_op;
+ g_linkpage->handler_stack = g_handler_stack_end;
+ g_code_ptr = g_linkpage->code;
+
+ // common_code.
+ // r0 and r14 must be saved by caller, r0 is arg for handle_op
+ // on return everything is restored except lr, which is used to return
+ emit_op_io(0xe50f1000, &g_linkpage->saved_regs[1]); // str r1, [->saved_regs[1]] @ save r1
+ emit_op (0xe24f1000 + // sub r1, pc, =offs(saved_regs[2])
+ (g_code_ptr - &g_linkpage->saved_regs[2] + 2) * 4);
+ emit_op (0xe8813ffc); // stmia r1, {r2-r13}
+ emit_op_io(0xe51fd000, // ldr sp, [->handler_stack]
+ (u32 *)&g_linkpage->handler_stack);
+ emit_op (0xe2414008); // sub r4, r1, #4*2
+ emit_op (0xe10f1000); // mrs r1, cpsr
+ emit_op_io(0xe50f1000, &g_linkpage->cpsr); // str r1, [->cpsr]
+ emit_op (0xe1a0500e); // mov r5, lr
+ emit_op (0xe1a0e00f); // mov lr, pc
+ emit_op_io(0xe51ff000, (u32 *)&g_linkpage->handler); // ldr pc, =handle_op
+ emit_op_io(0xe51f1000, &g_linkpage->cpsr); // ldr r1, [->cpsr]
+ emit_op (0xe128f001); // msr cpsr_f, r1
+ emit_op (0xe1a0e005); // mov lr, r5
+ emit_op (0xe8943fff); // ldmia r4, {r0-r13}
+ emit_op (0xe12fff1e); // bx lr @ return
+}
+
static void segv_sigaction(int num, siginfo_t *info, void *ctx)
{
struct ucontext *context = ctx;
u32 *regs = (u32 *)&context->uc_mcontext.arm_r0;
u32 *pc = (u32 *)regs[15];
- u32 old_op = *pc;
- u32 *pc_ptr, *old_op_ptr;
+ struct op_context *op_ctx;
int lp_size;
- if (((regs[15] ^ (u32)&segv_sigaction) & 0xff000000) == 0 || // PC is in our segment or
- (((regs[15] ^ (u32)g_linkpage) & ~(LINKPAGE_ALLOC - 1)) == 0)) // .. in linkpage
+ if (((regs[15] ^ (u32)&segv_sigaction) & 0xff000000) == 0 || // PC is in our segment or
+ (((regs[15] ^ (u32)g_linkpage) & ~(LINKPAGE_ALLOC - 1)) == 0) || // .. in linkpage
+ ((long)info->si_addr & 0xffe00000) != 0x7f000000) // faulting not where expected
{
// real crash - time to die
- printf("segv %d %p @ %08x\n", info->si_code, info->si_addr, regs[15]);
+ err("segv %d %p @ %08x\n", info->si_code, info->si_addr, regs[15]);
signal(num, SIG_DFL);
raise(num);
}
segvlog("segv %d %p @ %08x\n", info->si_code, info->si_addr, regs[15]);
// spit PC and op
- pc_ptr = g_code_ptr++;
- old_op_ptr = g_code_ptr++;
- *pc_ptr = (u32)pc;
- *old_op_ptr = old_op;
+ op_ctx = (void *)g_code_ptr;
+ op_ctx->pc = (u32)pc;
+ op_ctx->op = *pc;
+ g_code_ptr = &op_ctx->code[0];
// emit jump to code ptr
- *pc = make_jmp(pc, g_code_ptr);
+ *pc = make_jmp(pc, g_code_ptr, 0);
// generate code:
- // TODO: our own stack
- emit_op_io(0xe50f0000, &g_linkpage->saved_regs[0]); // str r0, [saved_regs[0]] @ save r0
- emit_op_io(0xe51f0000, (u32 *)&g_linkpage->lp_r1); // ldr r0, =lp_r1
- emit_op (0xe8807ffe); // stmia r0, {r1-r14}
- emit_op (0xe2402004); // sub r2, r0, #4
- emit_op_io(0xe51f0000, pc_ptr); // ldr r0, =pc
- emit_op_io(0xe51f1000, old_op_ptr); // ldr r1, =old_op
- emit_op (0xe1a04002); // mov r4, r2
- emit_op (0xe1a0e00f); // mov lr, pc
- emit_op_io(0xe51ff000, (u32 *)&g_linkpage->handler); // ldr pc, =handle_op
- emit_op (0xe8947fff); // ldmia r4, {r0-r14}
- emit_op (make_jmp(g_code_ptr, pc + 1)); // jmp <back>
+ // TODO: multithreading
+ emit_op_io(0xe50f0000, &g_linkpage->saved_regs[0]); // str r0, [->saved_regs[0]] @ save r0
+ emit_op_io(0xe50fe000, &g_linkpage->saved_regs[14]); // str r14, [->saved_regs[14]]
+ emit_op (0xe24f0000 + (g_code_ptr - (u32 *)op_ctx + 2) * 4); // sub r0, pc, #op_ctx
+ emit_op (make_jmp(g_code_ptr, &g_linkpage->code[0], 1)); // bl common_code
+ emit_op_io(0xe51fe000, &g_linkpage->saved_regs[14]); // ldr r14, [->saved_regs[14]]
+ emit_op (make_jmp(g_code_ptr, pc + 1, 0)); // jmp <back>
// sync caches
sys_cacheflush(pc, pc + 1);
if (lp_size + 13*4 > LINKPAGE_SIZE) {
g_linkpage_count++;
if (g_linkpage_count >= LINKPAGE_COUNT) {
- fprintf(stderr, "too many linkpages needed\n");
+ err("too many linkpages needed\n");
abort();
}
g_linkpage = (void *)((char *)g_linkpage + LINKPAGE_SIZE);
.sa_sigaction = segv_sigaction,
.sa_flags = SA_SIGINFO,
};
- void *ret;
+ void *pret;
+ int ret;
sigemptyset(&segv_action.sa_mask);
sigaction(SIGSEGV, &segv_action, NULL);
+ pret = mmap(NULL, HANDLER_STACK_SIZE + 4096, PROT_NONE, MAP_PRIVATE|MAP_ANONYMOUS|MAP_NORESERVE, -1, 0);
+ if (pret == MAP_FAILED) {
+ perror(PFX "mmap handler_stack");
+ exit(1);
+ }
+ ret = mprotect((char *)pret + 4096, HANDLER_STACK_SIZE, PROT_READ | PROT_WRITE);
+ if (ret != 0) {
+ perror(PFX "mprotect handler_stack");
+ exit(1);
+ }
+ g_handler_stack_end = (char *)pret + HANDLER_STACK_SIZE + 4096;
+
g_linkpage = (void *)(((u32)map_bottom - LINKPAGE_ALLOC) & ~0xfff);
- ret = mmap(g_linkpage, LINKPAGE_ALLOC, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0);
- if (ret != g_linkpage) {
- perror("mmap linkpage");
+ pret = mmap(g_linkpage, LINKPAGE_ALLOC, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0);
+ if (pret != g_linkpage) {
+ perror(PFX "mmap linkpage");
exit(1);
}
printf("linkpages @ %p\n", g_linkpage);
// host stuff
ret = host_video_init(&host_stride, 0);
if (ret != 0) {
- printf("can't alloc screen\n");
+ err("can't alloc screen\n");
exit(1);
}
host_screen = host_video_flip();
unsigned int btns;
if (count < 4) {
- printf("gpiodev read %d?\n", count);
+ err("gpiodev read %d?\n", count);
return -1;
}
}
// upper mem
if ((offset & 0xfe000000) != 0x02000000)
- printf("unexpected devmem mmap @ %08x\n", offset);
+ err("unexpected devmem mmap @ %08x\n", offset);
// return mmap(NULL, length, prot, flags, memdev, offset);
umem->mem = mmap(NULL, length, prot, MAP_SHARED, fd, 0);
if (umem->mem == MAP_FAILED) {
- printf("failed, giving up\n");
+ err("failed, giving up\n");
close(fd);
free(umem);
return MAP_FAILED;
#include "../common/host_fb.h"
+#define PFX "ginge: "
+#define err(f, ...) fprintf(stderr, PFX f, ##__VA_ARGS__)
+
void do_entry(unsigned long entry, void *stack_frame, int stack_frame_cnt, void *exitf);
void do_patches(void *ptr, unsigned int size);
#include "header.h"
-static int ifd = -1;
+static int ifds[2] = { -1, -1 };
+static int init_done;
static int keystate;
static void init(void)
{
char buff[64];
- int i;
+ int i, ifd, ret;
- for (ifd = -1, i = 0; ; i++) {
+ for (ifd = -1, i = 0; ifds[0] == -1 || ifds[1] == -1; i++) {
snprintf(buff, sizeof(buff), "/dev/input/event%i", i);
ifd = open(buff, O_RDONLY | O_NONBLOCK);
if (ifd == -1)
break;
- ioctl(ifd, EVIOCGNAME(sizeof(buff)), buff);
-
- if (strcasestr(buff, "gpio") != NULL)
+ ret = ioctl(ifd, EVIOCGNAME(sizeof(buff)), buff);
+ if (ret < 0)
break;
+
+ if (strcasestr(buff, "gpio") != NULL) {
+ ifds[0] = ifd;
+ continue;
+ }
+ if (strcasestr(buff, "keypad") != NULL) {
+ ifds[1] = ifd;
+ continue;
+ }
close(ifd);
}
- if (ifd < 0)
- printf("no input device\n");
+ if (ifds[0] < 0)
+ fprintf(stderr, PFX "missing buttons\n");
+ if (ifds[1] < 0)
+ fprintf(stderr, PFX "missing keypad\n");
+ init_done = 1;
}
static const struct {
{ BTN_START, GP2X_START },
{ KEY_LEFTCTRL, GP2X_SELECT },
{ BTN_SELECT, GP2X_SELECT },
+ { KEY_COMMA, GP2X_VOL_DOWN },
+ { KEY_DOT, GP2X_VOL_UP },
+ { KEY_Q, GP2X_PUSH },
};
int host_read_btns(void)
struct input_event ev;
int i, ret;
- if (ifd < 0)
+ if (!init_done)
init();
- if (ifd < 0)
- return keystate;
while (1)
{
- ret = read(ifd, &ev, sizeof(ev));
+ ret = read(ifds[0], &ev, sizeof(ev));
if (ret < (int) sizeof(ev)) {
if (errno != EAGAIN && errno != EWOULDBLOCK)
- perror("evtest: read error");
+ perror(PFX "read error");
- return keystate;
+ ret = read(ifds[1], &ev, sizeof(ev));
+ if (ret < (int) sizeof(ev))
+ if (errno != EAGAIN && errno != EWOULDBLOCK)
+ perror(PFX "read error");
}
+ if (ret < (int) sizeof(ev))
+ return keystate;
+
if (ev.type != EV_KEY)
continue;
--- /dev/null
+/*
+ * include/asm-arm/arch-mmsp2/mmsp2-regs.h
+ *
+ * Copyright (C) 2004,2005 DIGNSYS Inc. (www.dignsys.com)
+ * Kane Ahn < hbahn@dignsys.com >
+ * hhsong < hhsong@dignsys.com >
+ */
+
+#ifndef _MMSP2_H
+#define _MMSP2_H
+
+static const char * const regnames[0x10000] = {
+
+/*
+ * BANK C (Static) Memory Control Register
+ */
+[0x3a00] = "MEMCFG", /* BANK C configuration */
+[0x3a02] = "MEMTIME0", /* BANK C Timing #0 */
+[0x3a04] = "MEMTIME1", /* BANK C Timing #1 */
+[0x3a06] = "MEMTIME2", /* BANK C Timing #2 */
+[0x3a08] = "MEMTIME3", /* BANK C Timing #3 */
+[0x3a0a] = "MEMTIME4", /* BANK C Timing #4 */
+[0x3a0e] = "MEMWAITCTRL", /* BANK C Wait Control */
+[0x3a10] = "MEMPAGE", /* BANK C Page Control */
+[0x3a12] = "MEMIDETIME", /* BANK C IDE Timing Control */
+
+[0x3a14] = "MEMPCMCIAM", /* BANK C PCMCIA Timing */
+[0x3a16] = "MEMPCMCIAA", /* PCMCIA Attribute Timing */
+[0x3a18] = "MEMPCMCIAI", /* PCMCIA I/O Timing */
+[0x3a1a] = "MEMPCMCIAWAIT", /* PCMCIA Wait Timing */
+
+[0x3a1c] = "MEMEIDEWAIT", /* IDE Wait Timing */
+
+[0x3a20] = "MEMDTIMEOUT", /* DMA Timeout */
+[0x3a22] = "MEMDMACTRL", /* DMA Control */
+[0x3a24] = "MEMDMAPOL", /* DMA Polarity */
+[0x3a26] = "MEMDMATIME0", /* DMA Timing #0 */
+[0x3a28] = "MEMDMATIME1", /* DMA Timing #1 */
+[0x3a2a] = "MEMDMATIME2", /* DMA Timing #2 */
+[0x3a2c] = "MEMDMATIME3", /* DMA Timing #3 */
+[0x3a2e] = "MEMDMATIME4", /* DMA Timing #4 */
+[0x3a30] = "MEMDMATIME5", /* DMA Timing #5 */
+[0x3a32] = "MEMDMATIME6", /* DMA Timing #6 */
+[0x3a34] = "MEMDMATIME7", /* DMA Timing #7 */
+[0x3a36] = "MEMDMATIME8", /* DMA Timing #8 */
+[0x3a38] = "MEMDMASTRB", /* DMA Strobe Control */
+
+[0x3a3a] = "MEMNANDCTRL", /* NAND FLASH Control */
+[0x3a3c] = "MEMNANDTIME", /* NAND FLASH Timing */
+[0x3a3e] = "MEMNANDECC0", /* NAND FLASH ECC0 */
+[0x3a40] = "MEMNANDECC1", /* NAND FLASH ECC1 */
+[0x3a42] = "MEMNANDECC2", /* NAND FLASH ECC2 */
+[0x3a44] = "MEMNANDCNT", /* NAND FLASH Data Counter */
+
+/* Bank A Memory (SDRAM) Control Register */
+[0x3800] = "MEMCFGX", /* SDRAM Configuration */
+[0x3802] = "MEMTIMEX0", /* SDRAM Timing #0 */
+[0x3804] = "MEMTIMEX1", /* SDRAM Timing #1 */
+[0x3806] = "MEMACTPWDX", /* Active Power Down Ctrl */
+[0x3808] = "MEMREFX", /* Refresh Ctrl */
+
+/*
+ * Chapter 5
+ * Clocks and Power Manager
+ */
+[0x0900] = "PWMODE", /* Power Mode */
+[0x0902] = "CLKCHGST", /* Clock Change Status */
+[0x0904] = "SYSCLKEN", /* System Clock Enable */
+[0x0908] = "COMCLKEN", /* Communication Device Clk En */
+[0x090a] = "VGCLKEN", /* Video & Graphic Device Clk En */
+[0x090c] = "ASCLKEN", /* Audio & Storage Device Clk En */
+[0x0910] = "FPLLSETV", /* FCLK PLL Setting Value Write */
+[0x0912] = "FPLLVSET", /* FCLK PLL Value Setting */
+[0x0914] = "UPLLSETV", /* UCLK PLL Setting Value Write */
+[0x0916] = "UPLLVSET", /* UCLK PLL Value Setting */
+[0x0918] = "APLLSETV", /* ACLK PLL Setting Value Write */
+[0x091a] = "APLLVSET", /* ACLK PLL Value Setting */
+[0x091c] = "SYSCSET", /* System CLK PLL Divide Value */
+[0x091e] = "ESYSCSET", /* External System Clk Time Set */
+[0x0920] = "UIRMCSET", /* USB/IRDA/MMC Clk Gen */
+[0x0922] = "AUDICSET", /* Audio Ctrl Clk Gen */
+[0x092e] = "SPDICSET", /* SPDIF Ctrl Clk Gen */
+[0x0924] = "DISPCSET", /* Display Clk Gen */
+[0x0926] = "IMAGCSET", /* Image Pixel Clk Gen */
+[0x0928] = "URT0CSET", /* UART 0/1 Clk Gen */
+[0x092a] = "UAR1CSET", /* UART 2/3 Clk Gen */
+[0x092c] = "A940TMODE", /* ARM940T CPU Power Manage Mode */
+
+/*
+ * Interrupt
+ */
+[0x0800] = "SRCPEND",
+[0x0804] = "INTMOD",
+[0x0808] = "INTMASK",
+[0x080c] = "IPRIORITY",
+[0x0810] = "INTPEND",
+[0x0814] = "INTOFFSET",
+
+/*
+ * DMA
+ */
+[0x0000] = "DMAINT",
+
+/*
+ * UART
+ */
+
+[0x1200] = "ULCON0",
+[0x1202] = "UCON0",
+[0x1204] = "UFCON0",
+[0x1206] = "UMCON0",
+[0x1208] = "UTRSTAT0",
+[0x120a] = "UERRSTAT0",
+[0x120c] = "UFIFOSTAT0",
+[0x120e] = "UMODEMSTAT0",
+[0x1210] = "UTHB0",
+[0x1212] = "URHB0",
+[0x1214] = "UBRD0",
+[0x1216] = "UTIMEOUTREG0",
+
+[0x1220] = "ULCON1",
+[0x1222] = "UCON1",
+[0x1224] = "UFCON1",
+[0x1226] = "UMCON1",
+[0x1228] = "UTRSTAT1",
+[0x122a] = "UERRSTAT1",
+[0x122c] = "UFIFOSTAT1",
+[0x122e] = "UMODEMSTAT1",
+[0x1230] = "UTHB1",
+[0x1232] = "URHB1",
+[0x1234] = "UBRD1",
+[0x1236] = "UTIMEOUTREG1",
+
+[0x1240] = "ULCON2",
+[0x1242] = "UCON2",
+[0x1244] = "UFCON2",
+[0x1246] = "UMCON2",
+[0x1248] = "UTRSTAT2",
+[0x124a] = "UERRSTAT2",
+[0x124c] = "UFIFOSTAT2",
+[0x124e] = "UMODEMSTAT2",
+[0x1250] = "UTHB2",
+[0x1252] = "URHB2",
+[0x1254] = "UBRD2",
+[0x1256] = "UTIMEOUTREG2",
+
+[0x1260] = "ULCON3",
+[0x1262] = "UCON3",
+[0x1264] = "UFCON3",
+[0x1266] = "UMCON3",
+[0x1268] = "UTRSTAT3",
+[0x126a] = "UERRSTAT3",
+[0x126c] = "UFIFOSTAT3",
+[0x126e] = "UMODEMSTAT3",
+[0x1270] = "UTHB3",
+[0x1272] = "URHB3",
+[0x1274] = "UBRD3",
+[0x1276] = "UTIMEOUTREG3",
+
+[0x1280] = "UINTSTAT",
+[0x1282] = "UPORTCON",
+
+/*
+ * Timer / Watch-dog
+ */
+[0x0a00] = "TCOUNT",
+[0x0a04] = "TMATCH0",
+[0x0a08] = "TMATCH1",
+[0x0a0c] = "TMATCH2",
+[0x0a10] = "TMATCH3",
+[0x0a14] = "TCONTROL",
+[0x0a16] = "TSTATUS",
+[0x0a18] = "TINTEN",
+
+/*
+ * Real Time Clock (RTC)
+ */
+[0x0c00] = "RTCTSET",
+[0x0c04] = "RTCTCNT",
+[0x0c08] = "RTCSTCNT",
+[0x0c0a] = "TICKSET",
+[0x0c0c] = "ALARMT",
+[0x0c10] = "PWRMGR",
+[0x0c12] = "CLKMGR",
+[0x0c14] = "RSTCTRL",
+[0x0c16] = "RSTST",
+[0x0c18] = "BOOTCTRL",
+[0x0c1a] = "LOCKTIME",
+[0x0c1c] = "RSTTIME",
+[0x0c1e] = "EXTCTRL",
+[0x0c20] = "STOPTSET",
+[0x0c22] = "RTCCTRL",
+[0x0c24] = "RTSTRL",
+
+/*
+ * I2C
+ */
+[0x0d00] = "IICCON",
+[0x0d02] = "IICSTAT",
+[0x0d04] = "IICADD",
+[0x0d06] = "IICDS",
+
+/*
+ * AC97
+ */
+[0x0E00] = "AC_CTL", /* Control Register */
+[0x0E02] = "AC_CONFIG", /* Config Register */
+[0x0E04] = "AC_STA_EN", /* Status Enable Register */
+[0x0E06] = "AC_GSR", /* Global Status Register */
+[0x0E08] = "AC_ST_MCH", /* State Machine */
+[0x0E0C] = "AC_ADDR", /* Codec Address Register */
+[0x0E0E] = "AC_DATA", /* Codec Read Data Register */
+[0x0E10] = "AC_CAR", /* Codec Access Register */
+[0x0F00] = "AC_REG_BASE", /* AC97 Codec Register Base */
+
+/* USB Device */
+[0x1400] = "FUNC_ADDR_REG",
+[0x1402] = "PWR_REG",
+[0x1404] = "EP_INT_REG",
+[0x140C] = "USB_INT_REG",
+[0x140E] = "EP_INT_EN_REG",
+[0x1416] = "USB_INT_EN_REG",
+[0x1418] = "FRAME_NUM1_REG",
+[0x141A] = "FRAME_NUM2_REG",
+[0x141C] = "INDEX_REG",
+[0x1440] = "EP0_FIFO_REG",
+[0x1442] = "EP1_FIFO_REG",
+[0x1444] = "EP2_FIFO_REG",
+[0x1446] = "EP3_FIFO_REG",
+[0x1448] = "EP4_FIFO_REG",
+[0x1460] = "EP1_DMA_CON",
+[0x1464] = "EP1_DMA_FIFO",
+[0x1466] = "EP1_DMA_TTC_L",
+[0x1468] = "EP1_DMA_TTC_M",
+[0x146A] = "EP1_DMA_TTC_H",
+[0x146C] = "EP2_DMA_CON",
+[0x1470] = "EP2_DMA_FIFO",
+[0x1472] = "EP2_DMA_TTC_L",
+[0x1474] = "EP2_DMA_TTC_M",
+[0x1476] = "EP2_DMA_TTC_H",
+[0x1480] = "EP3_DMA_CON",
+[0x1484] = "EP3_DMA_FIFO",
+[0x1486] = "EP3_DMA_TTC_L",
+[0x1488] = "EP3_DMA_TTC_M",
+[0x148A] = "EP3_DMA_TTC_H",
+[0x148C] = "EP4_DMA_CON",
+[0x1490] = "EP4_DMA_FIFO",
+[0x1492] = "EP4_DMA_TTC_L",
+[0x1494] = "EP4_DMA_TTC_M",
+[0x1496] = "EP4_DMA_TTC_H",
+[0x1420] = "MAXP_REG",
+[0x1426] = "OUT_MAXP_REG",
+[0x1422] = "EP0_CSR",
+[0x1422] = "IN_CSR1_REG",
+[0x1424] = "IN_CSR2_REG",
+[0x1428] = "OUT_CSR1_REG",
+[0x142A] = "OUT_CSR2_REG",
+[0x142C] = "OUT_FIFO_CNT1_REG",
+[0x142E] = "OUT_FIFO_CNT2_REG",
+
+/* ADC/TP */
+[0x4600] = "TPC_ADCCON",
+[0x4604] = "TPC_ADCDAT",
+[0x4640] = "TPC_CNTL",
+[0x4644] = "TPC_INTR",
+[0x4648] = "TPC_COMP_TP",
+[0x464c] = "TPC_COMP_U1",
+[0x4650] = "TPC_COMP_U2",
+[0x4654] = "TPC_CLK_CNTL",
+[0x4658] = "TPC_CH_SEL",
+[0x465c] = "TPC_TIME_PARM1",
+[0x4660] = "TPC_TIME_PARM2",
+[0x4664] = "TPC_TIME_PARM3",
+[0x4668] = "TPC_X_VALUE",
+[0x466c] = "TPC_Y_VALUE",
+[0x4670] = "TPC_AZ_VALUE",
+[0x4674] = "TPC_U1_VALUE",
+[0x4678] = "TPC_U2_VALUE",
+
+/* Dual CPU Interface: mmsp20_type.h */
+[0x3B40] = "DINT920",
+[0x3B42] = "DINT940",
+[0x3B44] = "DPEND920",
+[0x3B46] = "DPEND940",
+[0x3B48] = "DCTRL940",
+
+/* FDC: mmsp20_type.h */
+[0x1838] = "DFDC_CNTL",
+[0x183A] = "DFDC_FRAME_SIZE",
+[0x183C] = "DFDC_LUMA_OFFSET",
+[0x183E] = "DFDC_CB_OFFSET",
+[0x1840] = "DFDC_CR_OFFSET",
+[0x1842] = "DFDC_DST_BASE_L",
+[0x1844] = "DFDC_DST_BASE_H",
+[0x1846] = "DFDC_STATUS",
+[0x1848] = "DFDC_DERING",
+[0x184A] = "DFDC_OCC_CNTL",
+
+/*
+ * Chapter 11
+ * General Purpose I/O (GPIO)
+ */
+[0x1020] = "GPIOAALTFNLOW",
+[0x1022] = "GPIOBALTFNLOW",
+[0x1024] = "GPIOCALTFNLOW",
+[0x1026] = "GPIODALTFNLOW",
+[0x1028] = "GPIOEALTFNLOW",
+[0x102a] = "GPIOFALTFNLOW",
+[0x102c] = "GPIOGALTFNLOW",
+[0x102e] = "GPIOHALTFNLOW",
+[0x1030] = "GPIOIALTFNLOW",
+[0x1032] = "GPIOJALTFNLOW",
+[0x1034] = "GPIOKALTFNLOW",
+[0x1036] = "GPIOLALTFNLOW",
+[0x1038] = "GPIOMALTFNLOW",
+[0x103a] = "GPIONALTFNLOW",
+[0x103c] = "GPIOOALTFNLOW",
+
+[0x1040] = "GPIOAALTFNHI",
+[0x1042] = "GPIOBALTFNHI",
+[0x1044] = "GPIOCALTFNHI",
+[0x1046] = "GPIODALTFNHI",
+[0x1048] = "GPIOEALTFNHI",
+[0x104a] = "GPIOFALTFNHI",
+[0x104c] = "GPIOGALTFNHI",
+[0x104e] = "GPIOHALTFNHI",
+[0x1050] = "GPIOIALTFNHI",
+[0x1052] = "GPIOJALTFNHI",
+[0x1054] = "GPIOKALTFNHI",
+[0x1056] = "GPIOLALTFNHI",
+[0x1058] = "GPIOMALTFNHI",
+[0x105a] = "GPIONALTFNHI",
+[0x105c] = "GPIOOALTFNHI",
+
+[0x1180] = "GPIOAPINLVL",
+[0x1182] = "GPIOBPINLVL",
+[0x1184] = "GPIOCPINLVL",
+[0x1186] = "GPIODPINLVL",
+[0x1188] = "GPIOEPINLVL",
+[0x118a] = "GPIOFPINLVL",
+[0x118c] = "GPIOGPINLVL",
+[0x118e] = "GPIOHPINLVL",
+[0x1190] = "GPIOIPINLVL",
+[0x1192] = "GPIOJPINLVL",
+[0x1194] = "GPIOKPINLVL",
+[0x1196] = "GPIOLPINLVL",
+[0x1198] = "GPIOMPINLVL",
+[0x119a] = "GPIONPINLVL",
+[0x119c] = "GPIOOPINLVL",
+
+/* DPC */
+[0x2800] = "DPC_CNTL",
+[0x2802] = "DPC_FPICNTL",
+[0x2804] = "DPC_FPIPOL1",
+[0x2806] = "DPC_FPIPOL2",
+[0x280a] = "DPC_FPIATV1",
+[0x280c] = "DPC_FPIATV2",
+[0x280e] = "DPC_FPIATV3",
+[0x2816] = "DPC_X_MAX",
+[0x2818] = "DPC_Y_MAX",
+[0x281a] = "DPC_HS_WIDTH",
+[0x281c] = "DPC_HS_STR",
+[0x281e] = "DPC_HS_END",
+[0x2820] = "DPC_V_SYNC",
+[0x2822] = "DPC_V_END",
+[0x2826] = "DPC_DE",
+[0x2828] = "DPC_PS",
+[0x282a] = "DPC_FG",
+[0x282c] = "DPC_LP",
+[0x2830] = "DPC_CLKV2",
+[0x2832] = "DPC_POL",
+[0x2834] = "DPC_CISSYNC",
+[0x283a] = "DPC_Y_BLANK",
+[0x283c] = "DPC_C_BLANK",
+[0x283e] = "DPC_YP_CSYNC",
+[0x2840] = "DPC_YN_CSYNC",
+[0x2842] = "DPC_CP_CSYNC",
+[0x2844] = "DPC_CN_CSYNC",
+[0x2846] = "DPC_INTR",
+[0x2848] = "DPC_CLKCNTL",
+
+/* MLC */
+[0X2884] = "MLC_YUV_CNTL",
+[0X2886] = "MLC_YUVA_TP_HSC",
+[0X2888] = "MLC_YUVA_BT_HSC",
+[0X2898] = "MLC_VLA_ENDX",
+[0X288a] = "MLC_VLA_TP_VSCL",
+[0X288c] = "MLC_VLA_TP_VSCH",
+[0X2892] = "MLC_YUVA_TP_PXW",
+[0X2894] = "MLC_YUVA_BT_PXW",
+[0X28da] = "MLC_STL_CNTL",
+[0X28dc] = "MLC_STL_MIXMUX",
+[0X28de] = "MLC_STL_ALPHAL",
+[0X28e0] = "MLC_STL_ALPHAH",
+[0X28e2] = "MLC_STL1_STX",
+[0X28e4] = "MLC_STL1_ENDX",
+[0X28e6] = "MLC_STL1_STY",
+[0X28e8] = "MLC_STL1_ENDY",
+[0X28ea] = "MLC_STL2_STX",
+[0X28ec] = "MLC_STL2_ENDX",
+[0X28ee] = "MLC_STL2_STY",
+[0X28f0] = "MLC_STL2_ENDY",
+[0X28f2] = "MLC_STL3_STX",
+[0X28f4] = "MLC_STL3_ENDX",
+[0X28f6] = "MLC_STL3_STY",
+[0X28f8] = "MLC_STL3_ENDY",
+[0X28fa] = "MLC_STL4_STX",
+[0X28fc] = "MLC_STL4_ENDX",
+[0X28fe] = "MLC_STL4_STY",
+[0X2900] = "MLC_STL4_ENDY",
+[0X2902] = "MLC_STL_CKEY_GB",
+[0X2904] = "MLC_STL_CKEY_R",
+[0X2906] = "MLC_STL_HSC",
+[0X2908] = "MLC_STL_VSCL",
+[0X290a] = "MLC_STL_VSCH",
+[0X290c] = "MLC_STL_HW",
+[0X290e] = "MLC_STL_OADRL",
+[0X2910] = "MLC_STL_OADRH",
+[0X2912] = "MLC_STL_EADRL",
+[0X2914] = "MLC_STL_EADRH",
+[0X291e] = "MLC_HWC_CNTL",
+[0X2920] = "MLC_HWC_STX",
+[0X2922] = "MLC_HWC_STY",
+[0X2924] = "MLC_HWC_FGR",
+[0X2926] = "MLC_HWC_FB",
+[0X2928] = "MLC_HWC_BGR",
+[0X292a] = "MLC_HWC_BB",
+[0X292c] = "MLC_HWC_OADRL",
+[0X292e] = "MLC_HWC_OADRH",
+[0X2930] = "MLC_HWC_EADRL",
+[0X2932] = "MLC_HWC_EADRH",
+[0X2958] = "MLC_STL_PALLT_A",
+[0X295a] = "MLC_STL_PALLT_D",
+
+};
+
+#endif /* _MMSP2_H */
notaz.gp2x.de / ginge.git / commitdiff