arm/arm_emit.h

   1 /* gameplaySP
   2  *
   3  * Copyright (C) 2006 Exophase <exophase@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
  18  */
  19
  20 #ifndef ARM_EMIT_H
  21 #define ARM_EMIT_H
  22
  23 #include "arm_codegen.h"
  24
  25 u32 arm_update_gba_arm(u32 pc);
  26 u32 arm_update_gba_thumb(u32 pc);
  27 u32 arm_update_gba_idle_arm(u32 pc);
  28 u32 arm_update_gba_idle_thumb(u32 pc);
  29
  30 // Although these are defined as a function, don't call them as
  31 // such (jump to it instead)
  32 void arm_indirect_branch_arm(u32 address);
  33 void arm_indirect_branch_thumb(u32 address);
  34 void arm_indirect_branch_dual_arm(u32 address);
  35 void arm_indirect_branch_dual_thumb(u32 address);
  36
  37 void execute_store_cpsr(u32 new_cpsr, u32 store_mask, u32 address);
  38 u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address);
  39 void execute_store_spsr(u32 new_cpsr, u32 store_mask);
  40 u32 execute_read_spsr();
  41 u32 execute_spsr_restore(u32 address);
  42
  43 void execute_swi_arm(u32 pc);
  44 void execute_swi_thumb(u32 pc);
  45
  46 void function_cc execute_store_u32_safe(u32 address, u32 source);
  47
  48 void step_debug_arm(u32 pc);
  49
  50
  51 #define write32(value)                                                        \
  52   *((u32 *)translation_ptr) = value;                                          \
  53   translation_ptr += 4                                                        \
  54
  55 #define arm_relative_offset(source, offset)                                   \
  56   (((((u32)offset - (u32)source) - 8) >> 2) & 0xFFFFFF)                       \
  57
  58
  59 // reg_base_offset is the amount of bytes after reg_base where the registers
  60 // actually begin.
  61
  62 #define reg_base_offset 1024
  63
  64
  65 #define reg_a0          ARMREG_R0
  66 #define reg_a1          ARMREG_R1
  67 #define reg_a2          ARMREG_R2
  68
  69 #define reg_s0          ARMREG_R9
  70 #define reg_base        ARMREG_SP
  71 #define reg_flags       ARMREG_R11
  72
  73 #define reg_cycles      ARMREG_R12
  74
  75 #define reg_rv          ARMREG_R0
  76
  77 #define reg_rm          ARMREG_R0
  78 #define reg_rn          ARMREG_R1
  79 #define reg_rs          ARMREG_R14
  80 #define reg_rd          ARMREG_R0
  81
  82
  83 // Register allocation layout for ARM and Thumb:
  84 // Map from a GBA register to a host ARM register. -1 means load it
  85 // from memory into one of the temp registers.
  86
  87 // The following registers are chosen based on statistical analysis
  88 // of a few games (see below), but might not be the best ones. Results
  89 // vary tremendously between ARM and Thumb (for obvious reasons), so
  90 // two sets are used. Take care to not call any function which can
  91 // overwrite any of these registers from the dynarec - only call
  92 // trusted functions in arm_stub.S which know how to save/restore
  93 // them and know how to transfer them to the C functions it calls
  94 // if necessary.
  95
  96 // The following define the actual registers available for allocation.
  97 // As registers are freed up add them to this list.
  98
  99 // Note that r15 is linked to the a0 temp reg - this register will
 100 // be preloaded with a constant upon read, and used to link to
 101 // indirect branch functions upon write.
 102
 103 #define reg_x0         ARMREG_R3
 104 #define reg_x1         ARMREG_R4
 105 #define reg_x2         ARMREG_R5
 106 #define reg_x3         ARMREG_R6
 107 #define reg_x4         ARMREG_R7
 108 #define reg_x5         ARMREG_R8
 109
 110 #define mem_reg        -1
 111
 112 /*
 113
 114 ARM register usage (38.775138% ARM instructions):
 115 r00: 18.263814% (-- 18.263814%)
 116 r12: 11.531477% (-- 29.795291%)
 117 r09: 11.500162% (-- 41.295453%)
 118 r14: 9.063440% (-- 50.358893%)
 119 r06: 7.837682% (-- 58.196574%)
 120 r01: 7.401049% (-- 65.597623%)
 121 r07: 6.778340% (-- 72.375963%)
 122 r05: 5.445009% (-- 77.820973%)
 123 r02: 5.427288% (-- 83.248260%)
 124 r03: 5.293743% (-- 88.542003%)
 125 r04: 3.601103% (-- 92.143106%)
 126 r11: 3.207311% (-- 95.350417%)
 127 r10: 2.334864% (-- 97.685281%)
 128 r08: 1.708207% (-- 99.393488%)
 129 r15: 0.311270% (-- 99.704757%)
 130 r13: 0.295243% (-- 100.000000%)
 131
 132 Thumb register usage (61.224862% Thumb instructions):
 133 r00: 34.788858% (-- 34.788858%)
 134 r01: 26.564083% (-- 61.352941%)
 135 r03: 10.983500% (-- 72.336441%)
 136 r02: 8.303127% (-- 80.639567%)
 137 r04: 4.900381% (-- 85.539948%)
 138 r05: 3.941292% (-- 89.481240%)
 139 r06: 3.257582% (-- 92.738822%)
 140 r07: 2.644851% (-- 95.383673%)
 141 r13: 1.408824% (-- 96.792497%)
 142 r08: 0.906433% (-- 97.698930%)
 143 r09: 0.679693% (-- 98.378623%)
 144 r10: 0.656446% (-- 99.035069%)
 145 r12: 0.453668% (-- 99.488737%)
 146 r14: 0.248909% (-- 99.737646%)
 147 r11: 0.171066% (-- 99.908713%)
 148 r15: 0.091287% (-- 100.000000%)
 149
 150 */
 151
 152 s32 arm_register_allocation[] =
 153 {
 154   reg_x0,       // GBA r0
 155   reg_x1,       // GBA r1
 156   mem_reg,      // GBA r2
 157   mem_reg,      // GBA r3
 158   mem_reg,      // GBA r4
 159   mem_reg,      // GBA r5
 160   reg_x2,       // GBA r6
 161   mem_reg,      // GBA r7
 162   mem_reg,      // GBA r8
 163   reg_x3,       // GBA r9
 164   mem_reg,      // GBA r10
 165   mem_reg,      // GBA r11
 166   reg_x4,       // GBA r12
 167   mem_reg,      // GBA r13
 168   reg_x5,       // GBA r14
 169   reg_a0        // GBA r15
 170
 171   mem_reg,
 172   mem_reg,
 173   mem_reg,
 174   mem_reg,
 175   mem_reg,
 176   mem_reg,
 177   mem_reg,
 178   mem_reg,
 179   mem_reg,
 180   mem_reg,
 181   mem_reg,
 182   mem_reg,
 183   mem_reg,
 184   mem_reg,
 185   mem_reg,
 186   mem_reg,
 187 };
 188
 189 s32 thumb_register_allocation[] =
 190 {
 191   reg_x0,       // GBA r0
 192   reg_x1,       // GBA r1
 193   reg_x2,       // GBA r2
 194   reg_x3,       // GBA r3
 195   reg_x4,       // GBA r4
 196   reg_x5,       // GBA r5
 197   mem_reg,      // GBA r6
 198   mem_reg,      // GBA r7
 199   mem_reg,      // GBA r8
 200   mem_reg,      // GBA r9
 201   mem_reg,      // GBA r10
 202   mem_reg,      // GBA r11
 203   mem_reg,      // GBA r12
 204   mem_reg,      // GBA r13
 205   mem_reg,      // GBA r14
 206   reg_a0        // GBA r15
 207
 208   mem_reg,
 209   mem_reg,
 210   mem_reg,
 211   mem_reg,
 212   mem_reg,
 213   mem_reg,
 214   mem_reg,
 215   mem_reg,
 216   mem_reg,
 217   mem_reg,
 218   mem_reg,
 219   mem_reg,
 220   mem_reg,
 221   mem_reg,
 222   mem_reg,
 223   mem_reg,
 224 };
 225
 226
 227
 228 #define arm_imm_lsl_to_rot(value)                                             \
 229   (32 - value)                                                                \
 230
 231
 232 u32 arm_disect_imm_32bit(u32 imm, u32 *stores, u32 *rotations)
 233 {
 234   u32 store_count = 0;
 235   u32 left_shift = 0;
 236
 237   // Otherwise it'll return 0 things to store because it'll never
 238   // find anything.
 239   if(imm == 0)
 240   {
 241     rotations[0] = 0;
 242     stores[0] = 0;
 243     return 1;
 244   }
 245
 246   // Find chunks of non-zero data at 2 bit alignments.
 247   while(1)
 248   {
 249     for(; left_shift < 32; left_shift += 2)
 250     {
 251       if((imm >> left_shift) & 0x03)
 252         break;
 253     }
 254
 255     if(left_shift == 32)
 256     {
 257       // We've hit the end of the useful data.
 258       return store_count;
 259     }
 260
 261     // Hit the end, it might wrap back around to the beginning.
 262     if(left_shift >= 24)
 263     {
 264       // Make a mask for the residual bits. IE, if we have
 265       // 5 bits of data at the end we can wrap around to 3
 266       // bits of data in the beginning. Thus the first
 267       // thing, after being shifted left, has to be less
 268       // than 111b, 0x7, or (1 << 3) - 1.
 269       u32 top_bits = 32 - left_shift;
 270       u32 residual_bits = 8 - top_bits;
 271       u32 residual_mask = (1 << residual_bits) - 1;
 272
 273       if((store_count > 1) && (left_shift > 24) &&
 274        ((stores[0] << ((32 - rotations[0]) & 0x1F)) < residual_mask))
 275       {
 276         // Then we can throw out the last bit and tack it on
 277         // to the first bit.
 278         stores[0] =
 279          (stores[0] << ((top_bits + (32 - rotations[0])) & 0x1F)) |
 280          ((imm >> left_shift) & 0xFF);
 281         rotations[0] = top_bits;
 282
 283         return store_count;
 284       }
 285       else
 286       {
 287         // There's nothing to wrap over to in the beginning
 288         stores[store_count] = (imm >> left_shift) & 0xFF;
 289         rotations[store_count] = (32 - left_shift) & 0x1F;
 290         return store_count + 1;
 291       }
 292       break;
 293     }
 294
 295     stores[store_count] = (imm >> left_shift) & 0xFF;
 296     rotations[store_count] = (32 - left_shift) & 0x1F;
 297
 298     store_count++;
 299     left_shift += 8;
 300   }
 301 }
 302
 303 #define arm_load_imm_32bit(ireg, imm)                                         \
 304 {                                                                             \
 305   u32 stores[4];                                                              \
 306   u32 rotations[4];                                                           \
 307   u32 store_count = arm_disect_imm_32bit(imm, stores, rotations);             \
 308   u32 i;                                                                      \
 309                                                                               \
 310   ARM_MOV_REG_IMM(0, ireg, stores[0], rotations[0]);                          \
 311                                                                               \
 312   for(i = 1; i < store_count; i++)                                            \
 313   {                                                                           \
 314     ARM_ORR_REG_IMM(0, ireg, ireg, stores[i], rotations[i]);                  \
 315   }                                                                           \
 316 }                                                                             \
 317
 318
 319 #define generate_load_pc(ireg, new_pc)                                        \
 320   arm_load_imm_32bit(ireg, new_pc)                                            \
 321
 322 #define generate_load_imm(ireg, imm, imm_ror)                                 \
 323   ARM_MOV_REG_IMM(0, ireg, imm, imm_ror)                                      \
 324
 325
 326
 327 #define generate_shift_left(ireg, imm)                                        \
 328   ARM_MOV_REG_IMMSHIFT(0, ireg, ireg, ARMSHIFT_LSL, imm)                      \
 329
 330 #define generate_shift_right(ireg, imm)                                       \
 331   ARM_MOV_REG_IMMSHIFT(0, ireg, ireg, ARMSHIFT_LSR, imm)                      \
 332
 333 #define generate_shift_right_arithmetic(ireg, imm)                            \
 334   ARM_MOV_REG_IMMSHIFT(0, ireg, ireg, ARMSHIFT_ASR, imm)                      \
 335
 336 #define generate_rotate_right(ireg, imm)                                      \
 337   ARM_MOV_REG_IMMSHIFT(0, ireg, ireg, ARMSHIFT_ROR, imm)                      \
 338
 339 #define generate_add(ireg_dest, ireg_src)                                     \
 340   ARM_ADD_REG_REG(0, ireg_dest, ireg_dest, ireg_src)                          \
 341
 342 #define generate_sub(ireg_dest, ireg_src)                                     \
 343   ARM_SUB_REG_REG(0, ireg_dest, ireg_dest, ireg_src)                          \
 344
 345 #define generate_or(ireg_dest, ireg_src)                                      \
 346   ARM_ORR_REG_REG(0, ireg_dest, ireg_dest, ireg_src)                          \
 347
 348 #define generate_xor(ireg_dest, ireg_src)                                     \
 349   ARM_EOR_REG_REG(0, ireg_dest, ireg_dest, ireg_src)                          \
 350
 351 #define generate_add_imm(ireg, imm, imm_ror)                                  \
 352   ARM_ADD_REG_IMM(0, ireg, ireg, imm, imm_ror)                                \
 353
 354 #define generate_sub_imm(ireg, imm, imm_ror)                                  \
 355   ARM_SUB_REG_IMM(0, ireg, ireg, imm, imm_ror)                                \
 356
 357 #define generate_xor_imm(ireg, imm, imm_ror)                                  \
 358   ARM_EOR_REG_IMM(0, ireg, ireg, imm, imm_ror)                                \
 359
 360 #define generate_add_reg_reg_imm(ireg_dest, ireg_src, imm, imm_ror)           \
 361   ARM_ADD_REG_IMM(0, ireg_dest, ireg_src, imm, imm_ror)                       \
 362
 363 #define generate_and_imm(ireg, imm, imm_ror)                                  \
 364   ARM_AND_REG_IMM(0, ireg, ireg, imm, imm_ror)                                \
 365
 366 #define generate_mov(ireg_dest, ireg_src)                                     \
 367   if(ireg_dest != ireg_src)                                                   \
 368   {                                                                           \
 369     ARM_MOV_REG_REG(0, ireg_dest, ireg_src);                                  \
 370   }                                                                           \
 371
 372 #define generate_function_call(function_location)                             \
 373   ARM_BL(0, arm_relative_offset(translation_ptr, function_location))          \
 374
 375 #define generate_exit_block()                                                 \
 376   ARM_BX(0, ARMREG_LR)                                                        \
 377
 378 // The branch target is to be filled in later (thus a 0 for now)
 379
 380 #define generate_branch_filler(condition_code, writeback_location)            \
 381   (writeback_location) = translation_ptr;                                     \
 382   ARM_B_COND(0, condition_code, 0)                                            \
 383
 384 #define generate_update_pc(new_pc)                                            \
 385   generate_load_pc(reg_a0, new_pc)                                            \
 386
 387 #define generate_cycle_update()                                               \
 388   if(cycle_count)                                                             \
 389   {                                                                           \
 390     if(cycle_count >> 8)                                                      \
 391     {                                                                         \
 392       ARM_ADD_REG_IMM(0, reg_cycles, reg_cycles, (cycle_count >> 8) & 0xFF,   \
 393        arm_imm_lsl_to_rot(8));                                                \
 394     }                                                                         \
 395     ARM_ADD_REG_IMM(0, reg_cycles, reg_cycles, (cycle_count & 0xFF), 0);      \
 396     cycle_count = 0;                                                          \
 397   }                                                                           \
 398
 399 #define generate_cycle_update_flag_set()                                      \
 400   if(cycle_count >> 8)                                                        \
 401   {                                                                           \
 402     ARM_ADD_REG_IMM(0, reg_cycles, reg_cycles, (cycle_count >> 8) & 0xFF,     \
 403      arm_imm_lsl_to_rot(8));                                                  \
 404   }                                                                           \
 405   generate_save_flags();                                                      \
 406   ARM_ADDS_REG_IMM(0, reg_cycles, reg_cycles, (cycle_count & 0xFF), 0);       \
 407   cycle_count = 0                                                             \
 408
 409 #define generate_branch_patch_conditional(dest, offset)                       \
 410   *((u32 *)(dest)) = (*((u32 *)dest) & 0xFF000000) |                          \
 411    arm_relative_offset(dest, offset)                                          \
 412
 413 #define generate_branch_patch_unconditional(dest, offset)                     \
 414   *((u32 *)(dest)) = (*((u32 *)dest) & 0xFF000000) |                          \
 415    arm_relative_offset(dest, offset)                                          \
 416
 417 // A different function is called for idle updates because of the relative
 418 // location of the embedded PC. The idle version could be optimized to put
 419 // the CPU into halt mode too, however.
 420
 421 #define generate_branch_idle_eliminate(writeback_location, new_pc, mode)      \
 422   generate_function_call(arm_update_gba_idle_##mode);                         \
 423   write32(new_pc);                                                            \
 424   generate_branch_filler(ARMCOND_AL, writeback_location)                      \
 425
 426 #define generate_branch_update(writeback_location, new_pc, mode)              \
 427   ARM_MOV_REG_IMMSHIFT(0, reg_a0, reg_cycles, ARMSHIFT_LSR, 31);              \
 428   ARM_ADD_REG_IMMSHIFT(0, ARMREG_PC, ARMREG_PC, reg_a0, ARMSHIFT_LSL, 2);     \
 429   write32(new_pc);                                                            \
 430   generate_function_call(arm_update_gba_##mode);                              \
 431   generate_branch_filler(ARMCOND_AL, writeback_location)                      \
 432
 433
 434 #define generate_branch_no_cycle_update(writeback_location, new_pc, mode)     \
 435   if(pc == idle_loop_target_pc)                                               \
 436   {                                                                           \
 437     generate_branch_idle_eliminate(writeback_location, new_pc, mode);         \
 438   }                                                                           \
 439   else                                                                        \
 440   {                                                                           \
 441     generate_branch_update(writeback_location, new_pc, mode);                 \
 442   }                                                                           \
 443
 444 #define generate_branch_cycle_update(writeback_location, new_pc, mode)        \
 445   generate_cycle_update();                                                    \
 446   generate_branch_no_cycle_update(writeback_location, new_pc, mode)           \
 447
 448 // a0 holds the destination
 449
 450 #define generate_indirect_branch_no_cycle_update(type)                        \
 451   ARM_B(0, arm_relative_offset(translation_ptr, arm_indirect_branch_##type))  \
 452
 453 #define generate_indirect_branch_cycle_update(type)                           \
 454   generate_cycle_update();                                                    \
 455   generate_indirect_branch_no_cycle_update(type)                              \
 456
 457 #define generate_block_prologue()                                             \
 458
 459 #define generate_block_extra_vars_arm()                                       \
 460   void generate_indirect_branch_arm()                                         \
 461   {                                                                           \
 462     if(condition == 0x0E)                                                     \
 463     {                                                                         \
 464       generate_cycle_update();                                                \
 465     }                                                                         \
 466     generate_indirect_branch_no_cycle_update(arm);                            \
 467   }                                                                           \
 468                                                                               \
 469   void generate_indirect_branch_dual()                                        \
 470   {                                                                           \
 471     if(condition == 0x0E)                                                     \
 472     {                                                                         \
 473       generate_cycle_update();                                                \
 474     }                                                                         \
 475     generate_indirect_branch_no_cycle_update(dual_arm);                       \
 476   }                                                                           \
 477                                                                               \
 478   u32 prepare_load_reg(u32 scratch_reg, u32 reg_index)                        \
 479   {                                                                           \
 480     u32 reg_use = arm_register_allocation[reg_index];                         \
 481     if(reg_use == mem_reg)                                                    \
 482     {                                                                         \
 483       ARM_LDR_IMM(0, scratch_reg, reg_base,                                   \
 484        (reg_base_offset + (reg_index * 4)));                                  \
 485       return scratch_reg;                                                     \
 486     }                                                                         \
 487                                                                               \
 488     return reg_use;                                                           \
 489   }                                                                           \
 490                                                                               \
 491   u32 prepare_load_reg_pc(u32 scratch_reg, u32 reg_index, u32 pc_offset)      \
 492   {                                                                           \
 493     if(reg_index == 15)                                                       \
 494     {                                                                         \
 495       generate_load_pc(scratch_reg, pc + pc_offset);                          \
 496       return scratch_reg;                                                     \
 497     }                                                                         \
 498     return prepare_load_reg(scratch_reg, reg_index);                          \
 499   }                                                                           \
 500                                                                               \
 501   u32 prepare_store_reg(u32 scratch_reg, u32 reg_index)                       \
 502   {                                                                           \
 503     u32 reg_use = arm_register_allocation[reg_index];                         \
 504     if(reg_use == mem_reg)                                                    \
 505       return scratch_reg;                                                     \
 506                                                                               \
 507     return reg_use;                                                           \
 508   }                                                                           \
 509                                                                               \
 510   void complete_store_reg(u32 scratch_reg, u32 reg_index)                     \
 511   {                                                                           \
 512     if(arm_register_allocation[reg_index] == mem_reg)                         \
 513     {                                                                         \
 514       ARM_STR_IMM(0, scratch_reg, reg_base,                                   \
 515        (reg_base_offset + (reg_index * 4)));                                  \
 516     }                                                                         \
 517   }                                                                           \
 518                                                                               \
 519   void complete_store_reg_pc_no_flags(u32 scratch_reg, u32 reg_index)         \
 520   {                                                                           \
 521     if(reg_index == 15)                                                       \
 522     {                                                                         \
 523       generate_indirect_branch_arm();                                         \
 524     }                                                                         \
 525     else                                                                      \
 526     {                                                                         \
 527       complete_store_reg(scratch_reg, reg_index);                             \
 528     }                                                                         \
 529   }                                                                           \
 530                                                                               \
 531   void complete_store_reg_pc_flags(u32 scratch_reg, u32 reg_index)            \
 532   {                                                                           \
 533     if(reg_index == 15)                                                       \
 534     {                                                                         \
 535       if(condition == 0x0E)                                                   \
 536       {                                                                       \
 537         generate_cycle_update();                                              \
 538       }                                                                       \
 539       generate_function_call(execute_spsr_restore);                           \
 540     }                                                                         \
 541     else                                                                      \
 542     {                                                                         \
 543       complete_store_reg(scratch_reg, reg_index);                             \
 544     }                                                                         \
 545   }                                                                           \
 546                                                                               \
 547   void generate_load_reg(u32 ireg, u32 reg_index)                             \
 548   {                                                                           \
 549     s32 load_src = arm_register_allocation[reg_index];                        \
 550     if(load_src != mem_reg)                                                   \
 551     {                                                                         \
 552       ARM_MOV_REG_REG(0, ireg, load_src);                                     \
 553     }                                                                         \
 554     else                                                                      \
 555     {                                                                         \
 556       ARM_LDR_IMM(0, ireg, reg_base, (reg_base_offset + (reg_index * 4)));    \
 557     }                                                                         \
 558   }                                                                           \
 559                                                                               \
 560   void generate_store_reg(u32 ireg, u32 reg_index)                            \
 561   {                                                                           \
 562     s32 store_dest = arm_register_allocation[reg_index];                      \
 563     if(store_dest != mem_reg)                                                 \
 564     {                                                                         \
 565       ARM_MOV_REG_REG(0, store_dest, ireg);                                   \
 566     }                                                                         \
 567     else                                                                      \
 568     {                                                                         \
 569       ARM_STR_IMM(0, ireg, reg_base, (reg_base_offset + (reg_index * 4)));    \
 570     }                                                                         \
 571   }                                                                           \
 572
 573
 574 #define generate_block_extra_vars_thumb()                                     \
 575   u32 prepare_load_reg(u32 scratch_reg, u32 reg_index)                        \
 576   {                                                                           \
 577     u32 reg_use = thumb_register_allocation[reg_index];                       \
 578     if(reg_use == mem_reg)                                                    \
 579     {                                                                         \
 580       ARM_LDR_IMM(0, scratch_reg, reg_base,                                   \
 581        (reg_base_offset + (reg_index * 4)));                                  \
 582       return scratch_reg;                                                     \
 583     }                                                                         \
 584                                                                               \
 585     return reg_use;                                                           \
 586   }                                                                           \
 587                                                                               \
 588   u32 prepare_load_reg_pc(u32 scratch_reg, u32 reg_index, u32 pc_offset)      \
 589   {                                                                           \
 590     if(reg_index == 15)                                                       \
 591     {                                                                         \
 592       generate_load_pc(scratch_reg, pc + pc_offset);                          \
 593       return scratch_reg;                                                     \
 594     }                                                                         \
 595     return prepare_load_reg(scratch_reg, reg_index);                          \
 596   }                                                                           \
 597                                                                               \
 598   u32 prepare_store_reg(u32 scratch_reg, u32 reg_index)                       \
 599   {                                                                           \
 600     u32 reg_use = thumb_register_allocation[reg_index];                       \
 601     if(reg_use == mem_reg)                                                    \
 602       return scratch_reg;                                                     \
 603                                                                               \
 604     return reg_use;                                                           \
 605   }                                                                           \
 606                                                                               \
 607   void complete_store_reg(u32 scratch_reg, u32 reg_index)                     \
 608   {                                                                           \
 609     if(thumb_register_allocation[reg_index] == mem_reg)                       \
 610     {                                                                         \
 611       ARM_STR_IMM(0, scratch_reg, reg_base,                                   \
 612        (reg_base_offset + (reg_index * 4)));                                  \
 613     }                                                                         \
 614   }                                                                           \
 615                                                                               \
 616   void generate_load_reg(u32 ireg, u32 reg_index)                             \
 617   {                                                                           \
 618     s32 load_src = thumb_register_allocation[reg_index];                      \
 619     if(load_src != mem_reg)                                                   \
 620     {                                                                         \
 621       ARM_MOV_REG_REG(0, ireg, load_src);                                     \
 622     }                                                                         \
 623     else                                                                      \
 624     {                                                                         \
 625       ARM_LDR_IMM(0, ireg, reg_base, (reg_base_offset + (reg_index * 4)));    \
 626     }                                                                         \
 627   }                                                                           \
 628                                                                               \
 629   void generate_store_reg(u32 ireg, u32 reg_index)                            \
 630   {                                                                           \
 631     s32 store_dest = thumb_register_allocation[reg_index];                    \
 632     if(store_dest != mem_reg)                                                 \
 633     {                                                                         \
 634       ARM_MOV_REG_REG(0, store_dest, ireg);                                   \
 635     }                                                                         \
 636     else                                                                      \
 637     {                                                                         \
 638       ARM_STR_IMM(0, ireg, reg_base, (reg_base_offset + (reg_index * 4)));    \
 639     }                                                                         \
 640   }                                                                           \
 641
 642 u8 *last_rom_translation_ptr = rom_translation_cache;
 643 u8 *last_ram_translation_ptr = ram_translation_cache;
 644 u8 *last_bios_translation_ptr = bios_translation_cache;
 645
 646 #define translate_invalidate_dcache_one(which)                                \
 647   if (which##_translation_ptr > last_##which##_translation_ptr)               \
 648   {                                                                           \
 649     warm_cache_op_range(WOP_D_CLEAN, last_##which##_translation_ptr,          \
 650       which##_translation_ptr - last_##which##_translation_ptr);              \
 651     warm_cache_op_range(WOP_I_INVALIDATE, last_##which##_translation_ptr, 32);\
 652     last_##which##_translation_ptr = which##_translation_ptr;                 \
 653   }
 654
 655 #define translate_invalidate_dcache()                                         \
 656 {                                                                             \
 657   translate_invalidate_dcache_one(rom)                                        \
 658   translate_invalidate_dcache_one(ram)                                        \
 659   translate_invalidate_dcache_one(bios)                                       \
 660 }
 661
 662 #define invalidate_icache_region(addr, size)                                  \
 663   warm_cache_op_range(WOP_I_INVALIDATE, addr, size)
 664
 665
 666 #define block_prologue_size 0
 667
 668
 669 // It should be okay to still generate result flags, spsr will overwrite them.
 670 // This is pretty infrequent (returning from interrupt handlers, et al) so
 671 // probably not worth optimizing for.
 672
 673 #define check_for_interrupts()                                                \
 674   if((io_registers[REG_IE] & io_registers[REG_IF]) &&                         \
 675    io_registers[REG_IME] && ((reg[REG_CPSR] & 0x80) == 0))                    \
 676   {                                                                           \
 677     reg_mode[MODE_IRQ][6] = pc + 4;                                           \
 678     spsr[MODE_IRQ] = reg[REG_CPSR];                                           \
 679     reg[REG_CPSR] = 0xD2;                                                     \
 680     pc = 0x00000018;                                                          \
 681     set_cpu_mode(MODE_IRQ);                                                   \
 682   }                                                                           \
 683
 684 #define generate_load_reg_pc(ireg, reg_index, pc_offset)                      \
 685   if(reg_index == 15)                                                         \
 686   {                                                                           \
 687     generate_load_pc(ireg, pc + pc_offset);                                   \
 688   }                                                                           \
 689   else                                                                        \
 690   {                                                                           \
 691     generate_load_reg(ireg, reg_index);                                       \
 692   }                                                                           \
 693
 694 #define generate_store_reg_pc_no_flags(ireg, reg_index)                       \
 695   generate_store_reg(ireg, reg_index);                                        \
 696   if(reg_index == 15)                                                         \
 697   {                                                                           \
 698     generate_indirect_branch_arm();                                           \
 699   }                                                                           \
 700
 701
 702 u32 function_cc execute_spsr_restore_body(u32 pc)
 703 {
 704   set_cpu_mode(cpu_modes[reg[REG_CPSR] & 0x1F]);
 705   check_for_interrupts();
 706
 707   return pc;
 708 }
 709
 710
 711 #define generate_store_reg_pc_flags(ireg, reg_index)                          \
 712   generate_store_reg(ireg, reg_index);                                        \
 713   if(reg_index == 15)                                                         \
 714   {                                                                           \
 715     if(condition == 0x0E)                                                     \
 716     {                                                                         \
 717       generate_cycle_update();                                                \
 718     }                                                                         \
 719     generate_function_call(execute_spsr_restore);                             \
 720   }                                                                           \
 721
 722
 723 #define generate_load_flags()                                                 \
 724 /*  ARM_MSR_REG(0, ARM_PSR_F, reg_flags, ARM_CPSR) */                         \
 725
 726 #define generate_store_flags()                                                \
 727 /*  ARM_MRS_CPSR(0, reg_flags) */                                             \
 728
 729 #define generate_save_flags()                                                 \
 730   ARM_MRS_CPSR(0, reg_flags)                                                  \
 731
 732 #define generate_restore_flags()                                              \
 733   ARM_MSR_REG(0, ARM_PSR_F, reg_flags, ARM_CPSR)                              \
 734
 735
 736 #define condition_opposite_eq ARMCOND_NE
 737 #define condition_opposite_ne ARMCOND_EQ
 738 #define condition_opposite_cs ARMCOND_CC
 739 #define condition_opposite_cc ARMCOND_CS
 740 #define condition_opposite_mi ARMCOND_PL
 741 #define condition_opposite_pl ARMCOND_MI
 742 #define condition_opposite_vs ARMCOND_VC
 743 #define condition_opposite_vc ARMCOND_VS
 744 #define condition_opposite_hi ARMCOND_LS
 745 #define condition_opposite_ls ARMCOND_HI
 746 #define condition_opposite_ge ARMCOND_LT
 747 #define condition_opposite_lt ARMCOND_GE
 748 #define condition_opposite_gt ARMCOND_LE
 749 #define condition_opposite_le ARMCOND_GT
 750 #define condition_opposite_al ARMCOND_NV
 751 #define condition_opposite_nv ARMCOND_AL
 752
 753 #define generate_branch(mode)                                                 \
 754 {                                                                             \
 755   generate_branch_cycle_update(                                               \
 756    block_exits[block_exit_position].branch_source,                            \
 757    block_exits[block_exit_position].branch_target, mode);                     \
 758   block_exit_position++;                                                      \
 759 }                                                                             \
 760
 761
 762 #define generate_op_and_reg_immshift(_rd, _rn, _rm, shift_type, shift)        \
 763   ARM_AND_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift)                   \
 764
 765 #define generate_op_orr_reg_immshift(_rd, _rn, _rm, shift_type, shift)        \
 766   ARM_ORR_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift)                   \
 767
 768 #define generate_op_eor_reg_immshift(_rd, _rn, _rm, shift_type, shift)        \
 769   ARM_EOR_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift)                   \
 770
 771 #define generate_op_bic_reg_immshift(_rd, _rn, _rm, shift_type, shift)        \
 772   ARM_BIC_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift)                   \
 773
 774 #define generate_op_sub_reg_immshift(_rd, _rn, _rm, shift_type, shift)        \
 775   ARM_SUB_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift)                   \
 776
 777 #define generate_op_rsb_reg_immshift(_rd, _rn, _rm, shift_type, shift)        \
 778   ARM_RSB_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift)                   \
 779
 780 #define generate_op_sbc_reg_immshift(_rd, _rn, _rm, shift_type, shift)        \
 781   ARM_SBC_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift)                   \
 782
 783 #define generate_op_rsc_reg_immshift(_rd, _rn, _rm, shift_type, shift)        \
 784   ARM_RSC_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift)                   \
 785
 786 #define generate_op_add_reg_immshift(_rd, _rn, _rm, shift_type, shift)        \
 787   ARM_ADD_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift)                   \
 788
 789 #define generate_op_adc_reg_immshift(_rd, _rn, _rm, shift_type, shift)        \
 790   ARM_ADC_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift)                   \
 791
 792 #define generate_op_mov_reg_immshift(_rd, _rn, _rm, shift_type, shift)        \
 793   ARM_MOV_REG_IMMSHIFT(0, _rd, _rm, shift_type, shift)                        \
 794
 795 #define generate_op_mvn_reg_immshift(_rd, _rn, _rm, shift_type, shift)        \
 796   ARM_MVN_REG_IMMSHIFT(0, _rd, _rm, shift_type, shift)                        \
 797
 798
 799 #define generate_op_and_reg_regshift(_rd, _rn, _rm, shift_type, _rs)          \
 800   ARM_AND_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs)                     \
 801
 802 #define generate_op_orr_reg_regshift(_rd, _rn, _rm, shift_type, _rs)          \
 803   ARM_ORR_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs)                     \
 804
 805 #define generate_op_eor_reg_regshift(_rd, _rn, _rm, shift_type, _rs)          \
 806   ARM_EOR_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs)                     \
 807
 808 #define generate_op_bic_reg_regshift(_rd, _rn, _rm, shift_type, _rs)          \
 809   ARM_BIC_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs)                     \
 810
 811 #define generate_op_sub_reg_regshift(_rd, _rn, _rm, shift_type, _rs)          \
 812   ARM_SUB_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs)                     \
 813
 814 #define generate_op_rsb_reg_regshift(_rd, _rn, _rm, shift_type, _rs)          \
 815   ARM_RSB_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs)                     \
 816
 817 #define generate_op_sbc_reg_regshift(_rd, _rn, _rm, shift_type, _rs)          \
 818   ARM_SBC_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs)                     \
 819
 820 #define generate_op_rsc_reg_regshift(_rd, _rn, _rm, shift_type, _rs)          \
 821   ARM_RSC_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs)                     \
 822
 823 #define generate_op_add_reg_regshift(_rd, _rn, _rm, shift_type, _rs)          \
 824   ARM_ADD_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs)                     \
 825
 826 #define generate_op_adc_reg_regshift(_rd, _rn, _rm, shift_type, _rs)          \
 827   ARM_ADC_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs)                     \
 828
 829 #define generate_op_mov_reg_regshift(_rd, _rn, _rm, shift_type, _rs)          \
 830   ARM_MOV_REG_REGSHIFT(0, _rd, _rm, shift_type, _rs)                          \
 831
 832 #define generate_op_mvn_reg_regshift(_rd, _rn, _rm, shift_type, _rs)          \
 833   ARM_MVN_REG_REGSHIFT(0, _rd, _rm, shift_type, _rs)                          \
 834
 835
 836 #define generate_op_and_imm(_rd, _rn)                                         \
 837   ARM_AND_REG_IMM(0, _rd, _rn, imm, imm_ror)                                  \
 838
 839 #define generate_op_orr_imm(_rd, _rn)                                         \
 840   ARM_ORR_REG_IMM(0, _rd, _rn, imm, imm_ror)                                  \
 841
 842 #define generate_op_eor_imm(_rd, _rn)                                         \
 843   ARM_EOR_REG_IMM(0, _rd, _rn, imm, imm_ror)                                  \
 844
 845 #define generate_op_bic_imm(_rd, _rn)                                         \
 846   ARM_BIC_REG_IMM(0, _rd, _rn, imm, imm_ror)                                  \
 847
 848 #define generate_op_sub_imm(_rd, _rn)                                         \
 849   ARM_SUB_REG_IMM(0, _rd, _rn, imm, imm_ror)                                  \
 850
 851 #define generate_op_rsb_imm(_rd, _rn)                                         \
 852   ARM_RSB_REG_IMM(0, _rd, _rn, imm, imm_ror)                                  \
 853
 854 #define generate_op_sbc_imm(_rd, _rn)                                         \
 855   ARM_SBC_REG_IMM(0, _rd, _rn, imm, imm_ror)                                  \
 856
 857 #define generate_op_rsc_imm(_rd, _rn)                                         \
 858   ARM_RSC_REG_IMM(0, _rd, _rn, imm, imm_ror)                                  \
 859
 860 #define generate_op_add_imm(_rd, _rn)                                         \
 861   ARM_ADD_REG_IMM(0, _rd, _rn, imm, imm_ror)                                  \
 862
 863 #define generate_op_adc_imm(_rd, _rn)                                         \
 864   ARM_ADC_REG_IMM(0, _rd, _rn, imm, imm_ror)                                  \
 865
 866 #define generate_op_mov_imm(_rd, _rn)                                         \
 867   ARM_MOV_REG_IMM(0, _rd, imm, imm_ror)                                       \
 868
 869 #define generate_op_mvn_imm(_rd, _rn)                                         \
 870   ARM_MVN_REG_IMM(0, _rd, imm, imm_ror)                                       \
 871
 872
 873 #define generate_op_reg_immshift_lflags(name, _rd, _rn, _rm, st, shift)       \
 874   ARM_##name##_REG_IMMSHIFT(0, _rd, _rn, _rm, st, shift)                      \
 875
 876 #define generate_op_reg_immshift_aflags(name, _rd, _rn, _rm, st, shift)       \
 877   ARM_##name##_REG_IMMSHIFT(0, _rd, _rn, _rm, st, shift)                      \
 878
 879 #define generate_op_reg_immshift_aflags_load_c(name, _rd, _rn, _rm, st, sh)   \
 880   ARM_##name##_REG_IMMSHIFT(0, _rd, _rn, _rm, st, sh)                         \
 881
 882 #define generate_op_reg_immshift_uflags(name, _rd, _rm, shift_type, shift)    \
 883   ARM_##name##_REG_IMMSHIFT(0, _rd, _rm, shift_type, shift)                   \
 884
 885 #define generate_op_reg_immshift_tflags(name, _rn, _rm, shift_type, shift)    \
 886   ARM_##name##_REG_IMMSHIFT(0, _rn, _rm, shift_type, shift)                   \
 887
 888
 889 #define generate_op_reg_regshift_lflags(name, _rd, _rn, _rm, shift_type, _rs) \
 890   ARM_##name##_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs)                \
 891
 892 #define generate_op_reg_regshift_aflags(name, _rd, _rn, _rm, st, _rs)         \
 893   ARM_##name##_REG_REGSHIFT(0, _rd, _rn, _rm, st, _rs)                        \
 894
 895 #define generate_op_reg_regshift_aflags_load_c(name, _rd, _rn, _rm, st, _rs)  \
 896   ARM_##name##_REG_REGSHIFT(0, _rd, _rn, _rm, st, _rs)                        \
 897
 898 #define generate_op_reg_regshift_uflags(name, _rd, _rm, shift_type, _rs)      \
 899   ARM_##name##_REG_REGSHIFT(0, _rd, _rm, shift_type, _rs)                     \
 900
 901 #define generate_op_reg_regshift_tflags(name, _rn, _rm, shift_type, _rs)      \
 902   ARM_##name##_REG_REGSHIFT(0, _rn, _rm, shift_type, _rs)                     \
 903
 904
 905 #define generate_op_imm_lflags(name, _rd, _rn)                                \
 906   ARM_##name##_REG_IMM(0, _rd, _rn, imm, imm_ror)                             \
 907
 908 #define generate_op_imm_aflags(name, _rd, _rn)                                \
 909   ARM_##name##_REG_IMM(0, _rd, _rn, imm, imm_ror)                             \
 910
 911 #define generate_op_imm_aflags_load_c(name, _rd, _rn)                         \
 912   ARM_##name##_REG_IMM(0, _rd, _rn, imm, imm_ror)                             \
 913
 914 #define generate_op_imm_uflags(name, _rd)                                     \
 915   ARM_##name##_REG_IMM(0, _rd, imm, imm_ror)                                  \
 916
 917 #define generate_op_imm_tflags(name, _rn)                                     \
 918   ARM_##name##_REG_IMM(0, _rn, imm, imm_ror)                                  \
 919
 920
 921 #define generate_op_ands_reg_immshift(_rd, _rn, _rm, shift_type, shift)       \
 922   generate_op_reg_immshift_lflags(ANDS, _rd, _rn, _rm, shift_type, shift)     \
 923
 924 #define generate_op_orrs_reg_immshift(_rd, _rn, _rm, shift_type, shift)       \
 925   generate_op_reg_immshift_lflags(ORRS, _rd, _rn, _rm, shift_type, shift)     \
 926
 927 #define generate_op_eors_reg_immshift(_rd, _rn, _rm, shift_type, shift)       \
 928   generate_op_reg_immshift_lflags(EORS, _rd, _rn, _rm, shift_type, shift)     \
 929
 930 #define generate_op_bics_reg_immshift(_rd, _rn, _rm, shift_type, shift)       \
 931   generate_op_reg_immshift_lflags(BICS, _rd, _rn, _rm, shift_type, shift)     \
 932
 933 #define generate_op_subs_reg_immshift(_rd, _rn, _rm, shift_type, shift)       \
 934   generate_op_reg_immshift_aflags(SUBS, _rd, _rn, _rm, shift_type, shift)     \
 935
 936 #define generate_op_rsbs_reg_immshift(_rd, _rn, _rm, shift_type, shift)       \
 937   generate_op_reg_immshift_aflags(RSBS, _rd, _rn, _rm, shift_type, shift)     \
 938
 939 #define generate_op_sbcs_reg_immshift(_rd, _rn, _rm, st, shift)               \
 940   generate_op_reg_immshift_aflags_load_c(SBCS, _rd, _rn, _rm, st, shift)      \
 941
 942 #define generate_op_rscs_reg_immshift(_rd, _rn, _rm, st, shift)               \
 943   generate_op_reg_immshift_aflags_load_c(RSCS, _rd, _rn, _rm, st, shift)      \
 944
 945 #define generate_op_adds_reg_immshift(_rd, _rn, _rm, shift_type, shift)       \
 946   generate_op_reg_immshift_aflags(ADDS, _rd, _rn, _rm, shift_type, shift)     \
 947
 948 #define generate_op_adcs_reg_immshift(_rd, _rn, _rm, st, shift)               \
 949   generate_op_reg_immshift_aflags_load_c(ADCS, _rd, _rn, _rm, st, shift)      \
 950
 951 #define generate_op_movs_reg_immshift(_rd, _rn, _rm, shift_type, shift)       \
 952   generate_op_reg_immshift_uflags(MOVS, _rd, _rm, shift_type, shift)          \
 953
 954 #define generate_op_mvns_reg_immshift(_rd, _rn, _rm, shift_type, shift)       \
 955   generate_op_reg_immshift_uflags(MVNS, _rd, _rm, shift_type, shift)          \
 956
 957 // The reg operand is in reg_rm, not reg_rn like expected, so rsbs isn't
 958 // being used here. When rsbs is fully inlined it can be used with the
 959 // apropriate operands.
 960
 961 #define generate_op_neg_reg_immshift(_rd, _rn, _rm, shift_type, shift)        \
 962 {                                                                             \
 963   generate_load_imm(reg_rn, 0, 0);                                            \
 964   generate_op_subs_reg_immshift(_rd, reg_rn, _rm, ARMSHIFT_LSL, 0);           \
 965 }                                                                             \
 966
 967 #define generate_op_muls_reg_immshift(_rd, _rn, _rm, shift_type, shift)       \
 968   generate_load_flags();                                                      \
 969   ARM_MULS(0, _rd, _rn, _rm);                                                 \
 970   generate_store_flags()                                                      \
 971
 972 #define generate_op_cmp_reg_immshift(_rd, _rn, _rm, shift_type, shift)        \
 973   generate_op_reg_immshift_tflags(CMP, _rn, _rm, shift_type, shift)           \
 974
 975 #define generate_op_cmn_reg_immshift(_rd, _rn, _rm, shift_type, shift)        \
 976   generate_op_reg_immshift_tflags(CMN, _rn, _rm, shift_type, shift)           \
 977
 978 #define generate_op_tst_reg_immshift(_rd, _rn, _rm, shift_type, shift)        \
 979   generate_op_reg_immshift_tflags(TST, _rn, _rm, shift_type, shift)           \
 980
 981 #define generate_op_teq_reg_immshift(_rd, _rn, _rm, shift_type, shift)        \
 982   generate_op_reg_immshift_tflags(TEQ, _rn, _rm, shift_type, shift)           \
 983
 984
 985 #define generate_op_ands_reg_regshift(_rd, _rn, _rm, shift_type, _rs)         \
 986   generate_op_reg_regshift_lflags(ANDS, _rd, _rn, _rm, shift_type, _rs)       \
 987
 988 #define generate_op_orrs_reg_regshift(_rd, _rn, _rm, shift_type, _rs)         \
 989   generate_op_reg_regshift_lflags(ORRS, _rd, _rn, _rm, shift_type, _rs)       \
 990
 991 #define generate_op_eors_reg_regshift(_rd, _rn, _rm, shift_type, _rs)         \
 992   generate_op_reg_regshift_lflags(EORS, _rd, _rn, _rm, shift_type, _rs)       \
 993
 994 #define generate_op_bics_reg_regshift(_rd, _rn, _rm, shift_type, _rs)         \
 995   generate_op_reg_regshift_lflags(BICS, _rd, _rn, _rm, shift_type, _rs)       \
 996
 997 #define generate_op_subs_reg_regshift(_rd, _rn, _rm, shift_type, _rs)         \
 998   generate_op_reg_regshift_aflags(SUBS, _rd, _rn, _rm, shift_type, _rs)       \
 999
1000 #define generate_op_rsbs_reg_regshift(_rd, _rn, _rm, shift_type, _rs)         \
1001   generate_op_reg_regshift_aflags(RSBS, _rd, _rn, _rm, shift_type, _rs)       \
1002
1003 #define generate_op_sbcs_reg_regshift(_rd, _rn, _rm, st, _rs)                 \
1004   generate_op_reg_regshift_aflags_load_c(SBCS, _rd, _rn, _rm, st, _rs)        \
1005
1006 #define generate_op_rscs_reg_regshift(_rd, _rn, _rm, st, _rs)                 \
1007   generate_op_reg_regshift_aflags_load_c(RSCS, _rd, _rn, _rm, st, _rs)        \
1008
1009 #define generate_op_adds_reg_regshift(_rd, _rn, _rm, shift_type, _rs)         \
1010   generate_op_reg_regshift_aflags(ADDS, _rd, _rn, _rm, shift_type, _rs)       \
1011
1012 #define generate_op_adcs_reg_regshift(_rd, _rn, _rm, st, _rs)                 \
1013   generate_op_reg_regshift_aflags_load_c(ADCS, _rd, _rn, _rm, st, _rs)        \
1014
1015 #define generate_op_movs_reg_regshift(_rd, _rn, _rm, shift_type, _rs)         \
1016   generate_op_reg_regshift_uflags(MOVS, _rd, _rm, shift_type, _rs)            \
1017
1018 #define generate_op_mvns_reg_regshift(_rd, _rn, _rm, shift_type, _rs)         \
1019   generate_op_reg_regshift_uflags(MVNS, _rd, _rm, shift_type, _rs)            \
1020
1021 #define generate_op_cmp_reg_regshift(_rd, _rn, _rm, shift_type, _rs)          \
1022   generate_op_reg_regshift_tflags(CMP, _rn, _rm, shift_type, _rs)             \
1023
1024 #define generate_op_cmn_reg_regshift(_rd, _rn, _rm, shift_type, _rs)          \
1025   generate_op_reg_regshift_tflags(CMN, _rn, _rm, shift_type, _rs)             \
1026
1027 #define generate_op_tst_reg_regshift(_rd, _rn, _rm, shift_type, _rs)          \
1028   generate_op_reg_regshift_tflags(TST, _rn, _rm, shift_type, _rs)             \
1029
1030 #define generate_op_teq_reg_regshift(_rd, _rn, _rm, shift_type, _rs)          \
1031   generate_op_reg_regshift_tflags(TEQ, _rn, _rm, shift_type, _rs)             \
1032
1033
1034 #define generate_op_ands_imm(_rd, _rn)                                        \
1035   generate_op_imm_lflags(ANDS, _rd, _rn)                                      \
1036
1037 #define generate_op_orrs_imm(_rd, _rn)                                        \
1038   generate_op_imm_lflags(ORRS, _rd, _rn)                                      \
1039
1040 #define generate_op_eors_imm(_rd, _rn)                                        \
1041   generate_op_imm_lflags(EORS, _rd, _rn)                                      \
1042
1043 #define generate_op_bics_imm(_rd, _rn)                                        \
1044   generate_op_imm_lflags(BICS, _rd, _rn)                                      \
1045
1046 #define generate_op_subs_imm(_rd, _rn)                                        \
1047   generate_op_imm_aflags(SUBS, _rd, _rn)                                      \
1048
1049 #define generate_op_rsbs_imm(_rd, _rn)                                        \
1050   generate_op_imm_aflags(RSBS, _rd, _rn)                                      \
1051
1052 #define generate_op_sbcs_imm(_rd, _rn)                                        \
1053   generate_op_imm_aflags_load_c(SBCS, _rd, _rn)                               \
1054
1055 #define generate_op_rscs_imm(_rd, _rn)                                        \
1056   generate_op_imm_aflags_load_c(RSCS, _rd, _rn)                               \
1057
1058 #define generate_op_adds_imm(_rd, _rn)                                        \
1059   generate_op_imm_aflags(ADDS, _rd, _rn)                                      \
1060
1061 #define generate_op_adcs_imm(_rd, _rn)                                        \
1062   generate_op_imm_aflags_load_c(ADCS, _rd, _rn)                               \
1063
1064 #define generate_op_movs_imm(_rd, _rn)                                        \
1065   generate_op_imm_uflags(MOVS, _rd)                                           \
1066
1067 #define generate_op_mvns_imm(_rd, _rn)                                        \
1068   generate_op_imm_uflags(MVNS, _rd)                                           \
1069
1070 #define generate_op_cmp_imm(_rd, _rn)                                         \
1071   generate_op_imm_tflags(CMP, _rn)                                            \
1072
1073 #define generate_op_cmn_imm(_rd, _rn)                                         \
1074   generate_op_imm_tflags(CMN, _rn)                                            \
1075
1076 #define generate_op_tst_imm(_rd, _rn)                                         \
1077   generate_op_imm_tflags(TST, _rn)                                            \
1078
1079 #define generate_op_teq_imm(_rd, _rn)                                         \
1080   generate_op_imm_tflags(TEQ, _rn)                                            \
1081
1082
1083 #define prepare_load_rn_yes()                                                 \
1084   u32 _rn = prepare_load_reg_pc(reg_rn, rn, 8)                                \
1085
1086 #define prepare_load_rn_no()                                                  \
1087
1088 #define prepare_store_rd_yes()                                                \
1089   u32 _rd = prepare_store_reg(reg_rd, rd)                                     \
1090
1091 #define prepare_store_rd_no()                                                 \
1092
1093 #define complete_store_rd_yes(flags_op)                                       \
1094   complete_store_reg_pc_##flags_op(_rd, rd)                                   \
1095
1096 #define complete_store_rd_no(flags_op)                                        \
1097
1098 #define arm_generate_op_reg(name, load_op, store_op, flags_op)                \
1099   u32 shift_type = (opcode >> 5) & 0x03;                                      \
1100   arm_decode_data_proc_reg();                                                 \
1101   prepare_load_rn_##load_op();                                                \
1102   prepare_store_rd_##store_op();                                              \
1103                                                                               \
1104   if((opcode >> 4) & 0x01)                                                    \
1105   {                                                                           \
1106     u32 rs = ((opcode >> 8) & 0x0F);                                          \
1107     u32 _rs = prepare_load_reg(reg_rs, rs);                                   \
1108     u32 _rm = prepare_load_reg_pc(reg_rm, rm, 12);                            \
1109     generate_op_##name##_reg_regshift(_rd, _rn, _rm, shift_type, _rs);        \
1110   }                                                                           \
1111   else                                                                        \
1112   {                                                                           \
1113     u32 shift_imm = ((opcode >> 7) & 0x1F);                                   \
1114     u32 _rm = prepare_load_reg_pc(reg_rm, rm, 8);                             \
1115     generate_op_##name##_reg_immshift(_rd, _rn, _rm, shift_type, shift_imm);  \
1116   }                                                                           \
1117   complete_store_rd_##store_op(flags_op)                                      \
1118
1119 #define arm_generate_op_reg_flags(name, load_op, store_op, flags_op)          \
1120   arm_generate_op_reg(name, load_op, store_op, flags_op)                      \
1121
1122 // imm will be loaded by the called function if necessary.
1123
1124 #define arm_generate_op_imm(name, load_op, store_op, flags_op)                \
1125   arm_decode_data_proc_imm();                                                 \
1126   prepare_load_rn_##load_op();                                                \
1127   prepare_store_rd_##store_op();                                              \
1128   generate_op_##name##_imm(_rd, _rn);                                         \
1129   complete_store_rd_##store_op(flags_op)                                      \
1130
1131 #define arm_generate_op_imm_flags(name, load_op, store_op, flags_op)          \
1132   arm_generate_op_imm(name, load_op, store_op, flags_op)                      \
1133
1134 #define arm_data_proc(name, type, flags_op)                                   \
1135 {                                                                             \
1136   arm_generate_op_##type(name, yes, yes, flags_op);                           \
1137 }                                                                             \
1138
1139 #define arm_data_proc_test(name, type)                                        \
1140 {                                                                             \
1141   arm_generate_op_##type(name, yes, no, no);                                  \
1142 }                                                                             \
1143
1144 #define arm_data_proc_unary(name, type, flags_op)                             \
1145 {                                                                             \
1146   arm_generate_op_##type(name, no, yes, flags_op);                            \
1147 }                                                                             \
1148
1149
1150 #define arm_multiply_add_no_flags_no()                                        \
1151   ARM_MUL(0, _rd, _rm, _rs)                                                   \
1152
1153 #define arm_multiply_add_yes_flags_no()                                       \
1154   u32 _rn = prepare_load_reg(reg_a2, rn);                                     \
1155   ARM_MLA(0, _rd, _rm, _rs, _rn)                                              \
1156
1157 #define arm_multiply_add_no_flags_yes()                                       \
1158   generate_load_flags();                                                      \
1159   ARM_MULS(0, reg_a0, reg_a0, reg_a1)                                         \
1160   generate_store_flags()                                                      \
1161
1162 #define arm_multiply_add_yes_flags_yes()                                      \
1163   u32 _rn = prepare_load_reg(reg_a2, rn);                                     \
1164   generate_load_flags();                                                      \
1165   ARM_MLAS(0, _rd, _rm, _rs, _rn);                                            \
1166   generate_store_flags()
1167
1168
1169 #define arm_multiply(add_op, flags)                                           \
1170 {                                                                             \
1171   arm_decode_multiply();                                                      \
1172   u32 _rm = prepare_load_reg(reg_a0, rm);                                     \
1173   u32 _rs = prepare_load_reg(reg_a1, rs);                                     \
1174   u32 _rd = prepare_store_reg(reg_a0, rd);                                    \
1175   arm_multiply_add_##add_op##_flags_##flags();                                \
1176   complete_store_reg(_rd, rd);                                                \
1177 }                                                                             \
1178
1179
1180 #define arm_multiply_long_name_s64     SMULL
1181 #define arm_multiply_long_name_u64     UMULL
1182 #define arm_multiply_long_name_s64_add SMLAL
1183 #define arm_multiply_long_name_u64_add UMLAL
1184
1185
1186 #define arm_multiply_long_flags_no(name)                                      \
1187   ARM_##name(0, _rdlo, _rdhi, _rm, _rs)                                       \
1188
1189 #define arm_multiply_long_flags_yes(name)                                     \
1190   generate_load_flags();                                                      \
1191   ARM_##name##S(0, _rdlo, _rdhi, _rm, _rs);                                   \
1192   generate_store_flags()                                                      \
1193
1194
1195 #define arm_multiply_long_add_no(name)                                        \
1196
1197 #define arm_multiply_long_add_yes(name)                                       \
1198   prepare_load_reg(reg_a0, rdlo);                                             \
1199   prepare_load_reg(reg_a1, rdhi)                                              \
1200
1201
1202 #define arm_multiply_long_op(flags, name)                                     \
1203   arm_multiply_long_flags_##flags(name)                                       \
1204
1205 #define arm_multiply_long(name, add_op, flags)                                \
1206 {                                                                             \
1207   arm_decode_multiply_long();                                                 \
1208   u32 _rm = prepare_load_reg(reg_a2, rm);                                     \
1209   u32 _rs = prepare_load_reg(reg_rs, rs);                                     \
1210   u32 _rdlo = prepare_store_reg(reg_a0, rdlo);                                \
1211   u32 _rdhi = prepare_store_reg(reg_a1, rdhi);                                \
1212   arm_multiply_long_add_##add_op(name);                                       \
1213   arm_multiply_long_op(flags, arm_multiply_long_name_##name);                 \
1214   complete_store_reg(_rdlo, rdlo);                                            \
1215   complete_store_reg(_rdhi, rdhi);                                            \
1216 }                                                                             \
1217
1218 #define arm_psr_read_cpsr()                                                   \
1219   u32 _rd = prepare_store_reg(reg_a0, rd);                                    \
1220   generate_load_reg(_rd, REG_CPSR);                                           \
1221   ARM_BIC_REG_IMM(0, _rd, _rd, 0xF0, arm_imm_lsl_to_rot(24));                 \
1222   ARM_AND_REG_IMM(0, reg_flags, reg_flags, 0xF0, arm_imm_lsl_to_rot(24));     \
1223   ARM_ORR_REG_REG(0, _rd, _rd, reg_flags);                                    \
1224   complete_store_reg(_rd, rd)                                                 \
1225
1226 #define arm_psr_read_spsr()                                                   \
1227   generate_function_call(execute_read_spsr)                                   \
1228   generate_store_reg(reg_a0, rd)                                              \
1229
1230 #define arm_psr_read(op_type, psr_reg)                                        \
1231   arm_psr_read_##psr_reg()                                                    \
1232
1233 // This function's okay because it's called from an ASM function that can
1234 // wrap it correctly.
1235
1236 u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
1237 {
1238   reg[REG_CPSR] = _cpsr;
1239   if(store_mask & 0xFF)
1240   {
1241     set_cpu_mode(cpu_modes[_cpsr & 0x1F]);
1242     if((io_registers[REG_IE] & io_registers[REG_IF]) &&
1243      io_registers[REG_IME] && ((_cpsr & 0x80) == 0))
1244     {
1245       reg_mode[MODE_IRQ][6] = address + 4;
1246       spsr[MODE_IRQ] = _cpsr;
1247       reg[REG_CPSR] = 0xD2;
1248       set_cpu_mode(MODE_IRQ);
1249       return 0x00000018;
1250     }
1251   }
1252
1253   return 0;
1254 }
1255
1256 #define arm_psr_load_new_reg()                                                \
1257   generate_load_reg(reg_a0, rm)                                               \
1258
1259 #define arm_psr_load_new_imm()                                                \
1260   generate_load_imm(reg_a0, imm, imm_ror)                                     \
1261
1262 #define arm_psr_store_cpsr()                                                  \
1263   arm_load_imm_32bit(reg_a1, psr_masks[psr_field]);                           \
1264   generate_function_call(execute_store_cpsr);                                 \
1265   write32(pc)                                                                 \
1266
1267 #define arm_psr_store_spsr()                                                  \
1268   generate_function_call(execute_store_spsr)                                  \
1269
1270 #define arm_psr_store(op_type, psr_reg)                                       \
1271   arm_psr_load_new_##op_type();                                               \
1272   arm_psr_store_##psr_reg()                                                   \
1273
1274
1275 #define arm_psr(op_type, transfer_type, psr_reg)                              \
1276 {                                                                             \
1277   arm_decode_psr_##op_type();                                                 \
1278   arm_psr_##transfer_type(op_type, psr_reg);                                  \
1279 }                                                                             \
1280
1281 // TODO: loads will need the PC passed as well for open address, however can
1282 // eventually be rectified with a hash table on the memory accesses
1283 // (same with the stores)
1284
1285 #define arm_access_memory_load(mem_type)                                      \
1286   cycle_count += 2;                                                           \
1287   generate_function_call(execute_load_##mem_type);                            \
1288   write32((pc + 8));                                                          \
1289   generate_store_reg_pc_no_flags(reg_rv, rd)                                  \
1290
1291 #define arm_access_memory_store(mem_type)                                     \
1292   cycle_count++;                                                              \
1293   generate_load_reg_pc(reg_a1, rd, 12);                                       \
1294   generate_function_call(execute_store_##mem_type);                           \
1295   write32((pc + 4))                                                           \
1296
1297 // Calculate the address into a0 from _rn, _rm
1298
1299 #define arm_access_memory_adjust_reg_sh_up(ireg)                              \
1300   ARM_ADD_REG_IMMSHIFT(0, ireg, _rn, _rm, ((opcode >> 5) & 0x03),             \
1301    ((opcode >> 7) & 0x1F))                                                    \
1302
1303 #define arm_access_memory_adjust_reg_sh_down(ireg)                            \
1304   ARM_SUB_REG_IMMSHIFT(0, ireg, _rn, _rm, ((opcode >> 5) & 0x03),             \
1305    ((opcode >> 7) & 0x1F))                                                    \
1306
1307 #define arm_access_memory_adjust_reg_up(ireg)                                 \
1308   ARM_ADD_REG_REG(0, ireg, _rn, _rm)                                          \
1309
1310 #define arm_access_memory_adjust_reg_down(ireg)                               \
1311   ARM_SUB_REG_REG(0, ireg, _rn, _rm)                                          \
1312
1313 #define arm_access_memory_adjust_imm(op, ireg)                                \
1314 {                                                                             \
1315   u32 stores[4];                                                              \
1316   u32 rotations[4];                                                           \
1317   u32 store_count = arm_disect_imm_32bit(offset, stores, rotations);          \
1318                                                                               \
1319   if(store_count > 1)                                                         \
1320   {                                                                           \
1321     ARM_##op##_REG_IMM(0, ireg, _rn, stores[0], rotations[0]);                \
1322     ARM_##op##_REG_IMM(0, ireg, ireg, stores[1], rotations[1]);               \
1323   }                                                                           \
1324   else                                                                        \
1325   {                                                                           \
1326     ARM_##op##_REG_IMM(0, ireg, _rn, stores[0], rotations[0]);                \
1327   }                                                                           \
1328 }                                                                             \
1329
1330 #define arm_access_memory_adjust_imm_up(ireg)                                 \
1331   arm_access_memory_adjust_imm(ADD, ireg)                                     \
1332
1333 #define arm_access_memory_adjust_imm_down(ireg)                               \
1334   arm_access_memory_adjust_imm(SUB, ireg)                                     \
1335
1336
1337 #define arm_access_memory_pre(type, direction)                                \
1338   arm_access_memory_adjust_##type##_##direction(reg_a0)                       \
1339
1340 #define arm_access_memory_pre_wb(type, direction)                             \
1341   arm_access_memory_adjust_##type##_##direction(reg_a0);                      \
1342   generate_store_reg(reg_a0, rn)                                              \
1343
1344 #define arm_access_memory_post(type, direction)                               \
1345   u32 _rn_dest = prepare_store_reg(reg_a1, rn);                               \
1346   if(_rn != reg_a0)                                                           \
1347   {                                                                           \
1348     generate_load_reg(reg_a0, rn);                                            \
1349   }                                                                           \
1350   arm_access_memory_adjust_##type##_##direction(_rn_dest);                    \
1351   complete_store_reg(_rn_dest, rn)                                            \
1352
1353
1354 #define arm_data_trans_reg(adjust_op, direction)                              \
1355   arm_decode_data_trans_reg();                                                \
1356   u32 _rn = prepare_load_reg_pc(reg_a0, rn, 8);                               \
1357   u32 _rm = prepare_load_reg(reg_a1, rm);                                     \
1358   arm_access_memory_##adjust_op(reg_sh, direction)                            \
1359
1360 #define arm_data_trans_imm(adjust_op, direction)                              \
1361   arm_decode_data_trans_imm();                                                \
1362   u32 _rn = prepare_load_reg_pc(reg_a0, rn, 8);                               \
1363   arm_access_memory_##adjust_op(imm, direction)                               \
1364
1365
1366 #define arm_data_trans_half_reg(adjust_op, direction)                         \
1367   arm_decode_half_trans_r();                                                  \
1368   u32 _rn = prepare_load_reg_pc(reg_a0, rn, 8);                               \
1369   u32 _rm = prepare_load_reg(reg_a1, rm);                                     \
1370   arm_access_memory_##adjust_op(reg, direction)                               \
1371
1372 #define arm_data_trans_half_imm(adjust_op, direction)                         \
1373   arm_decode_half_trans_of();                                                 \
1374   u32 _rn = prepare_load_reg_pc(reg_a0, rn, 8);                               \
1375   arm_access_memory_##adjust_op(imm, direction)                               \
1376
1377
1378 #define arm_access_memory(access_type, direction, adjust_op, mem_type,        \
1379  offset_type)                                                                 \
1380 {                                                                             \
1381   arm_data_trans_##offset_type(adjust_op, direction);                         \
1382   arm_access_memory_##access_type(mem_type);                                  \
1383 }                                                                             \
1384
1385
1386 #define word_bit_count(word)                                                  \
1387   (bit_count[word >> 8] + bit_count[word & 0xFF])                             \
1388
1389 #define sprint_no(access_type, pre_op, post_op, wb)                           \
1390
1391 #define sprint_yes(access_type, pre_op, post_op, wb)                          \
1392   printf("sbit on %s %s %s %s\n", #access_type, #pre_op, #post_op, #wb)       \
1393
1394
1395 // TODO: Make these use cached registers. Implement iwram_stack_optimize.
1396
1397 #define arm_block_memory_load()                                               \
1398   generate_function_call(execute_load_u32);                                   \
1399   write32((pc + 8));                                                          \
1400   generate_store_reg(reg_rv, i)                                               \
1401
1402 #define arm_block_memory_store()                                              \
1403   generate_load_reg_pc(reg_a1, i, 8);                                         \
1404   generate_function_call(execute_store_u32_safe)                              \
1405
1406 #define arm_block_memory_final_load()                                         \
1407   arm_block_memory_load()                                                     \
1408
1409 #define arm_block_memory_final_store()                                        \
1410   generate_load_reg_pc(reg_a1, i, 12);                                        \
1411   generate_function_call(execute_store_u32);                                  \
1412   write32((pc + 4))                                                           \
1413
1414 #define arm_block_memory_adjust_pc_store()                                    \
1415
1416 #define arm_block_memory_adjust_pc_load()                                     \
1417   if(reg_list & 0x8000)                                                       \
1418   {                                                                           \
1419     generate_mov(reg_a0, reg_rv);                                             \
1420     generate_indirect_branch_arm();                                           \
1421   }                                                                           \
1422
1423 #define arm_block_memory_offset_down_a()                                      \
1424   generate_sub_imm(reg_s0, ((word_bit_count(reg_list) * 4) - 4), 0)           \
1425
1426 #define arm_block_memory_offset_down_b()                                      \
1427   generate_sub_imm(reg_s0, (word_bit_count(reg_list) * 4), 0)                 \
1428
1429 #define arm_block_memory_offset_no()                                          \
1430
1431 #define arm_block_memory_offset_up()                                          \
1432   generate_add_imm(reg_s0, 4, 0)                                              \
1433
1434 #define arm_block_memory_writeback_down()                                     \
1435   generate_load_reg(reg_a0, rn);                                              \
1436   generate_sub_imm(reg_a0, (word_bit_count(reg_list) * 4), 0);                \
1437   generate_store_reg(reg_a0, rn)                                              \
1438
1439 #define arm_block_memory_writeback_up()                                       \
1440   generate_load_reg(reg_a0, rn);                                              \
1441   generate_add_imm(reg_a0, (word_bit_count(reg_list) * 4), 0);                \
1442   generate_store_reg(reg_a0, rn)                                              \
1443
1444 #define arm_block_memory_writeback_no()
1445
1446 // Only emit writeback if the register is not in the list
1447
1448 #define arm_block_memory_writeback_load(writeback_type)                       \
1449   if(!((reg_list >> rn) & 0x01))                                              \
1450   {                                                                           \
1451     arm_block_memory_writeback_##writeback_type();                            \
1452   }                                                                           \
1453
1454 #define arm_block_memory_writeback_store(writeback_type)                      \
1455   arm_block_memory_writeback_##writeback_type()                               \
1456
1457 #define arm_block_memory(access_type, offset_type, writeback_type, s_bit)     \
1458 {                                                                             \
1459   arm_decode_block_trans();                                                   \
1460   u32 offset = 0;                                                             \
1461   u32 i;                                                                      \
1462                                                                               \
1463   generate_load_reg(reg_s0, rn);                                              \
1464   arm_block_memory_offset_##offset_type();                                    \
1465   arm_block_memory_writeback_##access_type(writeback_type);                   \
1466   ARM_BIC_REG_IMM(0, reg_s0, reg_s0, 0x03, 0);                                \
1467                                                                               \
1468   for(i = 0; i < 16; i++)                                                     \
1469   {                                                                           \
1470     if((reg_list >> i) & 0x01)                                                \
1471     {                                                                         \
1472       cycle_count++;                                                          \
1473       generate_add_reg_reg_imm(reg_a0, reg_s0, offset, 0);                    \
1474       if(reg_list & ~((2 << i) - 1))                                          \
1475       {                                                                       \
1476         arm_block_memory_##access_type();                                     \
1477         offset += 4;                                                          \
1478       }                                                                       \
1479       else                                                                    \
1480       {                                                                       \
1481         arm_block_memory_final_##access_type();                               \
1482         break;                                                                \
1483       }                                                                       \
1484     }                                                                         \
1485   }                                                                           \
1486                                                                               \
1487   arm_block_memory_adjust_pc_##access_type();                                 \
1488 }                                                                             \
1489
1490 #define arm_swap(type)                                                        \
1491 {                                                                             \
1492   arm_decode_swap();                                                          \
1493   cycle_count += 3;                                                           \
1494   generate_load_reg(reg_a0, rn);                                              \
1495   generate_function_call(execute_load_##type);                                \
1496   write32((pc + 8));                                                          \
1497   generate_mov(reg_s0, reg_rv);                                               \
1498   generate_load_reg(reg_a0, rn);                                              \
1499   generate_load_reg(reg_a1, rm);                                              \
1500   generate_function_call(execute_store_##type);                               \
1501   write32((pc + 4));                                                          \
1502   generate_store_reg(reg_s0, rd);                                             \
1503 }                                                                             \
1504
1505
1506 #define thumb_generate_op_reg(name, _rd, _rs, _rn)                            \
1507   u32 __rm = prepare_load_reg(reg_rm, _rn);                                   \
1508   generate_op_##name##_reg_immshift(__rd, __rn, __rm, ARMSHIFT_LSL, 0)        \
1509
1510 #define thumb_generate_op_imm(name, _rd, _rs, imm_)                           \
1511 {                                                                             \
1512   u32 imm_ror = 0;                                                            \
1513   generate_op_##name##_imm(__rd, __rn);                                       \
1514 }                                                                             \
1515
1516
1517 #define thumb_data_proc(type, name, op_type, _rd, _rs, _rn)                   \
1518 {                                                                             \
1519   thumb_decode_##type();                                                      \
1520   u32 __rn = prepare_load_reg(reg_rn, _rs);                                   \
1521   u32 __rd = prepare_store_reg(reg_rd, _rd);                                  \
1522   generate_load_reg(reg_rn, _rs);                                             \
1523   thumb_generate_op_##op_type(name, _rd, _rs, _rn);                           \
1524   complete_store_reg(__rd, _rd);                                              \
1525 }                                                                             \
1526
1527 #define thumb_data_proc_test(type, name, op_type, _rd, _rs)                   \
1528 {                                                                             \
1529   thumb_decode_##type();                                                      \
1530   u32 __rn = prepare_load_reg(reg_rn, _rd);                                   \
1531   thumb_generate_op_##op_type(name, 0, _rd, _rs);                             \
1532 }                                                                             \
1533
1534 #define thumb_data_proc_unary(type, name, op_type, _rd, _rs)                  \
1535 {                                                                             \
1536   thumb_decode_##type();                                                      \
1537   u32 __rd = prepare_store_reg(reg_rd, _rd);                                  \
1538   thumb_generate_op_##op_type(name, _rd, 0, _rs);                             \
1539   complete_store_reg(__rd, _rd);                                              \
1540 }                                                                             \
1541
1542
1543 #define complete_store_reg_pc_thumb()                                         \
1544   if(rd == 15)                                                                \
1545   {                                                                           \
1546     generate_indirect_branch_cycle_update(thumb);                             \
1547   }                                                                           \
1548   else                                                                        \
1549   {                                                                           \
1550     complete_store_reg(_rd, rd);                                              \
1551   }                                                                           \
1552
1553 #define thumb_data_proc_hi(name)                                              \
1554 {                                                                             \
1555   thumb_decode_hireg_op();                                                    \
1556   u32 _rd = prepare_load_reg_pc(reg_rd, rd, 4);                               \
1557   u32 _rs = prepare_load_reg_pc(reg_rn, rs, 4);                               \
1558   generate_op_##name##_reg_immshift(_rd, _rd, _rs, ARMSHIFT_LSL, 0);          \
1559   complete_store_reg_pc_thumb();                                              \
1560 }                                                                             \
1561
1562 #define thumb_data_proc_test_hi(name)                                         \
1563 {                                                                             \
1564   thumb_decode_hireg_op();                                                    \
1565   u32 _rd = prepare_load_reg_pc(reg_rd, rd, 4);                               \
1566   u32 _rs = prepare_load_reg_pc(reg_rn, rs, 4);                               \
1567   generate_op_##name##_reg_immshift(0, _rd, _rs, ARMSHIFT_LSL, 0);            \
1568 }                                                                             \
1569
1570 #define thumb_data_proc_mov_hi()                                              \
1571 {                                                                             \
1572   thumb_decode_hireg_op();                                                    \
1573   u32 _rs = prepare_load_reg_pc(reg_rn, rs, 4);                               \
1574   u32 _rd = prepare_store_reg(reg_rd, rd);                                    \
1575   ARM_MOV_REG_REG(0, _rd, _rs);                                               \
1576   complete_store_reg_pc_thumb();                                              \
1577 }                                                                             \
1578
1579
1580
1581 #define thumb_load_pc(_rd)                                                    \
1582 {                                                                             \
1583   thumb_decode_imm();                                                         \
1584   u32 __rd = prepare_store_reg(reg_rd, _rd);                                  \
1585   generate_load_pc(__rd, (((pc & ~2) + 4) + (imm * 4)));                      \
1586   complete_store_reg(__rd, _rd);                                              \
1587 }                                                                             \
1588
1589 #define thumb_load_sp(_rd)                                                    \
1590 {                                                                             \
1591   thumb_decode_imm();                                                         \
1592   u32 __sp = prepare_load_reg(reg_a0, REG_SP);                                \
1593   u32 __rd = prepare_store_reg(reg_a0, _rd);                                  \
1594   ARM_ADD_REG_IMM(0, __rd, __sp, imm, arm_imm_lsl_to_rot(2));                 \
1595   complete_store_reg(__rd, _rd);                                              \
1596 }                                                                             \
1597
1598 #define thumb_adjust_sp_up()                                                  \
1599   ARM_ADD_REG_IMM(0, _sp, _sp, imm, arm_imm_lsl_to_rot(2))                    \
1600
1601 #define thumb_adjust_sp_down()                                                \
1602   ARM_SUB_REG_IMM(0, _sp, _sp, imm, arm_imm_lsl_to_rot(2))                    \
1603
1604 #define thumb_adjust_sp(direction)                                            \
1605 {                                                                             \
1606   thumb_decode_add_sp();                                                      \
1607   u32 _sp = prepare_load_reg(reg_a0, REG_SP);                                 \
1608   thumb_adjust_sp_##direction();                                              \
1609   complete_store_reg(_sp, REG_SP);                                            \
1610 }                                                                             \
1611
1612 #define generate_op_lsl_reg(_rd, _rm, _rs)                                    \
1613   generate_op_movs_reg_regshift(_rd, 0, _rm, ARMSHIFT_LSL, _rs)               \
1614
1615 #define generate_op_lsr_reg(_rd, _rm, _rs)                                    \
1616   generate_op_movs_reg_regshift(_rd, 0, _rm, ARMSHIFT_LSR, _rs)               \
1617
1618 #define generate_op_asr_reg(_rd, _rm, _rs)                                    \
1619   generate_op_movs_reg_regshift(_rd, 0, _rm, ARMSHIFT_ASR, _rs)               \
1620
1621 #define generate_op_ror_reg(_rd, _rm, _rs)                                    \
1622   generate_op_movs_reg_regshift(_rd, 0, _rm, ARMSHIFT_ROR, _rs)               \
1623
1624
1625 #define generate_op_lsl_imm(_rd, _rm)                                         \
1626   generate_op_movs_reg_immshift(_rd, 0, _rm, ARMSHIFT_LSL, imm)               \
1627
1628 #define generate_op_lsr_imm(_rd, _rm)                                         \
1629   generate_op_movs_reg_immshift(_rd, 0, _rm, ARMSHIFT_LSR, imm)               \
1630
1631 #define generate_op_asr_imm(_rd, _rm)                                         \
1632   generate_op_movs_reg_immshift(_rd, 0, _rm, ARMSHIFT_ASR, imm)               \
1633
1634 #define generate_op_ror_imm(_rd, _rm)                                         \
1635   generate_op_movs_reg_immshift(_rd, 0, _rm, ARMSHIFT_ROR, imm)               \
1636
1637
1638 #define generate_shift_reg(op_type)                                           \
1639   u32 __rm = prepare_load_reg(reg_rd, rd);                                    \
1640   u32 __rs = prepare_load_reg(reg_rs, rs);                                    \
1641   generate_op_##op_type##_reg(__rd, __rm, __rs)                               \
1642
1643 #define generate_shift_imm(op_type)                                           \
1644   u32 __rs = prepare_load_reg(reg_rs, rs);                                    \
1645   generate_op_##op_type##_imm(__rd, __rs)                                     \
1646
1647
1648 #define thumb_shift(decode_type, op_type, value_type)                         \
1649 {                                                                             \
1650   thumb_decode_##decode_type();                                               \
1651   u32 __rd = prepare_store_reg(reg_rd, rd);                                   \
1652   generate_shift_##value_type(op_type);                                       \
1653   complete_store_reg(__rd, rd);                                               \
1654 }                                                                             \
1655
1656 // Operation types: imm, mem_reg, mem_imm
1657
1658 #define thumb_access_memory_load(mem_type, _rd)                               \
1659   cycle_count += 2;                                                           \
1660   generate_function_call(execute_load_##mem_type);                            \
1661   write32((pc + 4));                                                          \
1662   generate_store_reg(reg_rv, _rd)                                             \
1663
1664 #define thumb_access_memory_store(mem_type, _rd)                              \
1665   cycle_count++;                                                              \
1666   generate_load_reg(reg_a1, _rd);                                             \
1667   generate_function_call(execute_store_##mem_type);                           \
1668   write32((pc + 2))                                                           \
1669
1670 #define thumb_access_memory_generate_address_pc_relative(offset, _rb, _ro)    \
1671   generate_load_pc(reg_a0, (offset))                                          \
1672
1673 #define thumb_access_memory_generate_address_reg_imm(offset, _rb, _ro)        \
1674   u32 __rb = prepare_load_reg(reg_a0, _rb);                                   \
1675   ARM_ADD_REG_IMM(0, reg_a0, __rb, offset, 0)                                 \
1676
1677 #define thumb_access_memory_generate_address_reg_imm_sp(offset, _rb, _ro)     \
1678   u32 __rb = prepare_load_reg(reg_a0, _rb);                                   \
1679   ARM_ADD_REG_IMM(0, reg_a0, __rb, offset, arm_imm_lsl_to_rot(2))             \
1680
1681 #define thumb_access_memory_generate_address_reg_reg(offset, _rb, _ro)        \
1682   u32 __rb = prepare_load_reg(reg_a0, _rb);                                   \
1683   u32 __ro = prepare_load_reg(reg_a1, _ro);                                   \
1684   ARM_ADD_REG_REG(0, reg_a0, __rb, __ro)                                      \
1685
1686 #define thumb_access_memory(access_type, op_type, _rd, _rb, _ro,              \
1687  address_type, offset, mem_type)                                              \
1688 {                                                                             \
1689   thumb_decode_##op_type();                                                   \
1690   thumb_access_memory_generate_address_##address_type(offset, _rb, _ro);      \
1691   thumb_access_memory_##access_type(mem_type, _rd);                           \
1692 }                                                                             \
1693
1694 // TODO: Make these use cached registers. Implement iwram_stack_optimize.
1695
1696 #define thumb_block_address_preadjust_up()                                    \
1697   generate_add_imm(reg_s0, (bit_count[reg_list] * 4), 0)                      \
1698
1699 #define thumb_block_address_preadjust_down()                                  \
1700   generate_sub_imm(reg_s0, (bit_count[reg_list] * 4), 0)                      \
1701
1702 #define thumb_block_address_preadjust_push_lr()                               \
1703   generate_sub_imm(reg_s0, ((bit_count[reg_list] + 1) * 4), 0)                \
1704
1705 #define thumb_block_address_preadjust_no()                                    \
1706
1707 #define thumb_block_address_postadjust_no(base_reg)                           \
1708   generate_store_reg(reg_s0, base_reg)                                        \
1709
1710 #define thumb_block_address_postadjust_up(base_reg)                           \
1711   generate_add_reg_reg_imm(reg_a0, reg_s0, (bit_count[reg_list] * 4), 0);     \
1712   generate_store_reg(reg_a0, base_reg)                                        \
1713
1714 #define thumb_block_address_postadjust_down(base_reg)                         \
1715   generate_mov(reg_a0, reg_s0);                                               \
1716   generate_sub_imm(reg_a0, (bit_count[reg_list] * 4), 0);                     \
1717   generate_store_reg(reg_a0, base_reg)                                        \
1718
1719 #define thumb_block_address_postadjust_pop_pc(base_reg)                       \
1720   generate_add_reg_reg_imm(reg_a0, reg_s0,                                    \
1721    ((bit_count[reg_list] + 1) * 4), 0);                                       \
1722   generate_store_reg(reg_a0, base_reg)                                        \
1723
1724 #define thumb_block_address_postadjust_push_lr(base_reg)                      \
1725   generate_store_reg(reg_s0, base_reg)                                        \
1726
1727 #define thumb_block_memory_extra_no()                                         \
1728
1729 #define thumb_block_memory_extra_up()                                         \
1730
1731 #define thumb_block_memory_extra_down()                                       \
1732
1733 #define thumb_block_memory_extra_pop_pc()                                     \
1734   generate_add_reg_reg_imm(reg_a0, reg_s0, (bit_count[reg_list] * 4), 0);     \
1735   generate_function_call(execute_load_u32);                                   \
1736   write32((pc + 4));                                                          \
1737   generate_mov(reg_a0, reg_rv);                                               \
1738   generate_indirect_branch_cycle_update(thumb)                                \
1739
1740 #define thumb_block_memory_extra_push_lr(base_reg)                            \
1741   generate_add_reg_reg_imm(reg_a0, reg_s0, (bit_count[reg_list] * 4), 0);     \
1742   generate_load_reg(reg_a1, REG_LR);                                          \
1743   generate_function_call(execute_store_u32_safe)                              \
1744
1745 #define thumb_block_memory_load()                                             \
1746   generate_function_call(execute_load_u32);                                   \
1747   write32((pc + 4));                                                          \
1748   generate_store_reg(reg_rv, i)                                               \
1749
1750 #define thumb_block_memory_store()                                            \
1751   generate_load_reg(reg_a1, i);                                               \
1752   generate_function_call(execute_store_u32_safe)                              \
1753
1754 #define thumb_block_memory_final_load()                                       \
1755   thumb_block_memory_load()                                                   \
1756
1757 #define thumb_block_memory_final_store()                                      \
1758   generate_load_reg(reg_a1, i);                                               \
1759   generate_function_call(execute_store_u32);                                  \
1760   write32((pc + 2))                                                           \
1761
1762 #define thumb_block_memory_final_no(access_type)                              \
1763   thumb_block_memory_final_##access_type()                                    \
1764
1765 #define thumb_block_memory_final_up(access_type)                              \
1766   thumb_block_memory_final_##access_type()                                    \
1767
1768 #define thumb_block_memory_final_down(access_type)                            \
1769   thumb_block_memory_final_##access_type()                                    \
1770
1771 #define thumb_block_memory_final_push_lr(access_type)                         \
1772   thumb_block_memory_##access_type()                                          \
1773
1774 #define thumb_block_memory_final_pop_pc(access_type)                          \
1775   thumb_block_memory_##access_type()                                          \
1776
1777 #define thumb_block_memory(access_type, pre_op, post_op, base_reg)            \
1778 {                                                                             \
1779   thumb_decode_rlist();                                                       \
1780   u32 i;                                                                      \
1781   u32 offset = 0;                                                             \
1782                                                                               \
1783   generate_load_reg(reg_s0, base_reg);                                        \
1784   ARM_BIC_REG_IMM(0, reg_s0, reg_s0, 0x03, 0);                                \
1785   thumb_block_address_preadjust_##pre_op();                                   \
1786   thumb_block_address_postadjust_##post_op(base_reg);                         \
1787                                                                               \
1788   for(i = 0; i < 8; i++)                                                      \
1789   {                                                                           \
1790     if((reg_list >> i) & 0x01)                                                \
1791     {                                                                         \
1792       cycle_count++;                                                          \
1793       generate_add_reg_reg_imm(reg_a0, reg_s0, offset, 0);                    \
1794       if(reg_list & ~((2 << i) - 1))                                          \
1795       {                                                                       \
1796         thumb_block_memory_##access_type();                                   \
1797         offset += 4;                                                          \
1798       }                                                                       \
1799       else                                                                    \
1800       {                                                                       \
1801         thumb_block_memory_final_##post_op(access_type);                      \
1802         break;                                                                \
1803       }                                                                       \
1804     }                                                                         \
1805   }                                                                           \
1806                                                                               \
1807   thumb_block_memory_extra_##post_op();                                       \
1808 }                                                                             \
1809
1810 #define thumb_conditional_branch(condition)                                   \
1811 {                                                                             \
1812   generate_cycle_update();                                                    \
1813   generate_load_flags();                                                      \
1814   generate_branch_filler(condition_opposite_##condition, backpatch_address);  \
1815   generate_branch_no_cycle_update(                                            \
1816    block_exits[block_exit_position].branch_source,                            \
1817    block_exits[block_exit_position].branch_target, thumb);                    \
1818   generate_branch_patch_conditional(backpatch_address, translation_ptr);      \
1819   block_exit_position++;                                                      \
1820 }                                                                             \
1821
1822
1823 #define arm_conditional_block_header()                                        \
1824   generate_cycle_update();                                                    \
1825   generate_load_flags();                                                      \
1826   /* This will choose the opposite condition */                               \
1827   condition ^= 0x01;                                                          \
1828   generate_branch_filler(condition, backpatch_address)                        \
1829
1830 #define arm_b()                                                               \
1831   generate_branch(arm)                                                        \
1832
1833 #define arm_bl()                                                              \
1834   generate_update_pc((pc + 4));                                               \
1835   generate_store_reg(reg_a0, REG_LR);                                         \
1836   generate_branch(arm)                                                        \
1837
1838 #define arm_bx()                                                              \
1839   arm_decode_branchx();                                                       \
1840   generate_load_reg(reg_a0, rn);                                              \
1841   generate_indirect_branch_dual();                                            \
1842
1843 #define arm_swi()                                                             \
1844   generate_swi_hle_handler((opcode >> 16) & 0xFF, arm);                       \
1845   generate_function_call(execute_swi_arm);                                    \
1846   write32((pc + 4));                                                          \
1847   generate_branch(arm)                                                        \
1848
1849 #define thumb_b()                                                             \
1850   generate_branch(thumb)                                                      \
1851
1852 #define thumb_bl()                                                            \
1853   generate_update_pc(((pc + 2) | 0x01));                                      \
1854   generate_store_reg(reg_a0, REG_LR);                                         \
1855   generate_branch(thumb)                                                      \
1856
1857 #define thumb_blh()                                                           \
1858 {                                                                             \
1859   thumb_decode_branch();                                                      \
1860   generate_update_pc(((pc + 2) | 0x01));                                      \
1861   generate_load_reg(reg_a1, REG_LR);                                          \
1862   generate_store_reg(reg_a0, REG_LR);                                         \
1863   generate_mov(reg_a0, reg_a1);                                               \
1864   generate_add_imm(reg_a0, (offset * 2), 0);                                  \
1865   generate_indirect_branch_cycle_update(thumb);                               \
1866 }                                                                             \
1867
1868 #define thumb_bx()                                                            \
1869 {                                                                             \
1870   thumb_decode_hireg_op();                                                    \
1871   generate_load_reg_pc(reg_a0, rs, 4);                                        \
1872   generate_indirect_branch_cycle_update(dual_thumb);                          \
1873 }                                                                             \
1874
1875 #define thumb_swi()                                                           \
1876   generate_swi_hle_handler(opcode & 0xFF, thumb);                             \
1877   generate_function_call(execute_swi_thumb);                                  \
1878   write32((pc + 2));                                                          \
1879   /* We're in ARM mode now */                                                 \
1880   generate_branch(arm)                                                        \
1881
1882 u8 swi_hle_handle[256] =
1883 {
1884   0x0,    // SWI 0:  SoftReset
1885   0x0,    // SWI 1:  RegisterRAMReset
1886   0x0,    // SWI 2:  Halt
1887   0x0,    // SWI 3:  Stop/Sleep
1888   0x0,    // SWI 4:  IntrWait
1889   0x0,    // SWI 5:  VBlankIntrWait
1890   0x1,    // SWI 6:  Div
1891   0x0,    // SWI 7:  DivArm
1892   0x0,    // SWI 8:  Sqrt
1893   0x0,    // SWI 9:  ArcTan
1894   0x0,    // SWI A:  ArcTan2
1895   0x0,    // SWI B:  CpuSet
1896   0x0,    // SWI C:  CpuFastSet
1897   0x0,    // SWI D:  GetBIOSCheckSum
1898   0x0,    // SWI E:  BgAffineSet
1899   0x0,    // SWI F:  ObjAffineSet
1900   0x0,    // SWI 10: BitUnpack
1901   0x0,    // SWI 11: LZ77UnCompWram
1902   0x0,    // SWI 12: LZ77UnCompVram
1903   0x0,    // SWI 13: HuffUnComp
1904   0x0,    // SWI 14: RLUnCompWram
1905   0x0,    // SWI 15: RLUnCompVram
1906   0x0,    // SWI 16: Diff8bitUnFilterWram
1907   0x0,    // SWI 17: Diff8bitUnFilterVram
1908   0x0,    // SWI 18: Diff16bitUnFilter
1909   0x0,    // SWI 19: SoundBias
1910   0x0,    // SWI 1A: SoundDriverInit
1911   0x0,    // SWI 1B: SoundDriverMode
1912   0x0,    // SWI 1C: SoundDriverMain
1913   0x0,    // SWI 1D: SoundDriverVSync
1914   0x0,    // SWI 1E: SoundChannelClear
1915   0x0,    // SWI 1F: MidiKey2Freq
1916   0x0,    // SWI 20: SoundWhatever0
1917   0x0,    // SWI 21: SoundWhatever1
1918   0x0,    // SWI 22: SoundWhatever2
1919   0x0,    // SWI 23: SoundWhatever3
1920   0x0,    // SWI 24: SoundWhatever4
1921   0x0,    // SWI 25: MultiBoot
1922   0x0,    // SWI 26: HardReset
1923   0x0,    // SWI 27: CustomHalt
1924   0x0,    // SWI 28: SoundDriverVSyncOff
1925   0x0,    // SWI 29: SoundDriverVSyncOn
1926   0x0     // SWI 2A: SoundGetJumpList
1927 };
1928
1929 void execute_swi_hle_div_arm();
1930 void execute_swi_hle_div_thumb();
1931
1932 void execute_swi_hle_div_c()
1933 {
1934   if (reg[1] == 0)
1935     // real BIOS supposedly locks up, but game can recover on interrupt
1936     return;
1937   s32 result = (s32)reg[0] / (s32)reg[1];
1938   reg[1] = (s32)reg[0] % (s32)reg[1];
1939   reg[0] = result;
1940
1941   reg[3] = (result ^ (result >> 31)) - (result >> 31);
1942 }
1943
1944 #define generate_swi_hle_handler(_swi_number, mode)                           \
1945 {                                                                             \
1946   u32 swi_number = _swi_number;                                               \
1947   if(swi_hle_handle[swi_number])                                              \
1948   {                                                                           \
1949     /* Div */                                                                 \
1950     if(swi_number == 0x06)                                                    \
1951     {                                                                         \
1952       generate_function_call(execute_swi_hle_div_##mode);                     \
1953     }                                                                         \
1954     break;                                                                    \
1955   }                                                                           \
1956 }                                                                             \
1957
1958 #define generate_translation_gate(type)                                       \
1959   generate_update_pc(pc);                                                     \
1960   generate_indirect_branch_no_cycle_update(type)                              \
1961
1962 #define generate_step_debug()                                                 \
1963   generate_function_call(step_debug_arm);                                     \
1964   write32(pc)                                                                 \
1965
1966 #endif
1967