2 # --register-prefix-optional --bitwise-or
4 .macro ldarg arg, stacksz, reg
5 move.l (4 + \arg * 4 + \stacksz)(%sp), \reg
8 .macro ldargw arg, stacksz, reg
9 move.w (4 + \arg * 4 + 2 + \stacksz)(%sp), \reg
12 .global burn10 /* u16 val */
20 .global write16_x16 /* u32 a, u16 count, u16 d */
41 # read single phase from controller
46 move.b #0x40,(0xa10003)
51 move.b #0x00,(0xa10003)
52 andi.w #0x3f,d1 /* 00CB RLDU */
56 andi.w #0xc0,d0 /* SA00 0000 */
62 eor.w d0,d1 /* changed btns */
63 move.w d0,d7 /* old val */
65 and.w d0,d1 /* what changed now */
69 .global write_and_read1 /* u32 a, u16 d, void *dst */
88 .global move_sr /* u16 sr */
94 .global move_sr_and_read /* u16 sr, u32 a */
107 .global memcpy_ /* void *dst, const void *src, u16 size */
114 move.b (a1)+, (a0)+ /* not in a hurry */
118 .global memset_ /* void *dst, int d, u16 size */
125 move.b d1, (a0)+ /* not in a hurry */
133 movem.l d2-d7/a2, -(sp)
134 movea.l #0xc00007, a0
135 movea.l #0xc00008, a1
136 movea.l #0xff0000, a2
137 moveq.l #0, d4 /* d4 = count */
138 moveq.l #0, d5 /* d5 = vcnt_expect */
140 move.l #1<<(3+16), d7 /* d7 = SR_VB */
143 beq 0b /* not blanking */
146 bne 0b /* blanking */
151 bne 0b /* not line 0 */
155 move.l d6, (a2)+ /* d0 = old */
158 move.b (a1), d2 /* 8 d2 = vcnt */
159 cmp.b (a1), d2 /* 8 reread for corruption */
160 bne 0b /* 10 on changing vcounter? */
161 cmp.b d2, d5 /* 4 vcnt == vcnt_expect? */
163 move.l (a0), d0 /* 12 */
167 addq.l #1, d4 /* count++ */
170 bne 2f /* vcnt == vcnt_expect + 1 */
173 and.l d7, d1 /* (old ^ val) & vb */
175 move.l d0, d6 /* old = val */
178 2: /* vcnt jump or vb change */
179 move.l d6, (a2)+ /* *ram++ = old */
180 move.l d0, (a2)+ /* *ram++ = val */
181 move.b d2, d5 /* vcnt_expect = vcnt */
182 move.l d0, d6 /* old = val */
188 bne 1b /* still in VB */
190 move.l d0, (a2)+ /* *ram++ = val */
191 move.l d4, (a2)+ /* *ram++ = count */
193 movem.l (sp)+, d2-d7/a2
198 move.w d0, -(sp) /* 8 */
199 move.w (0xc00008).l, d0 /* 16 */
200 addq.w #1, (0xf000).w /* 16 */
201 tst.w (0xf002).w /* 12 */
203 move.w d0, (0xf002).w /* 12 */
205 move.w d0, (0xf004).w /* 12 */
206 move.w (sp)+, d0 /* 8 */
208 .global test_hint_end
213 move.w d0, -(sp) /* 8 */
214 move.w (0xc00008).l, d0 /* 16 */
215 addq.w #1, (0xf008).w /* 16 */
216 tst.w (0xf00a).w /* 12 */
218 move.w d0, (0xf00a).w /* 12 */
220 move.w d0, (0xf00c).w /* 12 */
221 move.w (sp)+, d0 /* 8 */
223 .global test_vint_end
228 movea.l #0xa15100, a0
229 movea.l #0xa15122, a1
230 move.w #1, (a0) /* ADEN */
231 # wait for min(20_sh2_cycles, pll_setup_time)
232 # pll time is unclear, icd_mars.prg mentions 10ms which sounds
233 # way too much. Hope 40 68k cycles is enough
237 move.w #3, (a0) /* ADEN, nRES */
239 move.w #0xffff, d0 /* waste some cycles */
241 beq 0b /* master BIOS busy */
243 0: /* for slave, use a limit, as it */
244 tst.w 4(a1) /* won't respond on master error. */
245 dbne d0, 0b /* slave BIOS busy */
247 or.w #1, 6(a0) /* RV */
249 .global x32x_enable_end
252 .global test_32x_b_c0
256 jsr (0xc0).l /* move.b d0, (a1); RV=0 */
257 bset #0, (0xa15107).l
259 .global test_32x_b_c0_end
262 # some nastyness from Fatal Rewind
266 move.w #0x8014, (0xFFC00004).l
267 move.w #0x8164, (0xFFC00004).l
277 movea.l #0xc00004, a0
280 move.w #480/2/10-1, d0
283 move.w #0x8164, (0xFFC00004).l
284 move.w #0x8014, (0xFFC00004).l
292 .global test_f_vint_end
297 movea.l #0xc00005, a0
298 movea.l #0xc00004, a1
306 movem.l d2-d7/a2, -(sp)
314 movea.l #0xff0000, a0
317 .macro test_lb_s sr, dr
328 movem.l (sp)+, d2-d7/a2
334 movea.l #0xc00004, a0
335 movea.l #0xc00008, a1
346 movea.l #0xff0000, a1
347 movea.l #0xff0000, a1
366 # vim:filetype=asmM68k:ts=4:sw=4:expandtab