451ab91e |
1 | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * |
2 | * Mupen64plus - new_dynarec.c * |
3 | * Copyright (C) 2009-2011 Ari64 * |
4 | * * |
5 | * This program is free software; you can redistribute it and/or modify * |
6 | * it under the terms of the GNU General Public License as published by * |
7 | * the Free Software Foundation; either version 2 of the License, or * |
8 | * (at your option) any later version. * |
9 | * * |
10 | * This program is distributed in the hope that it will be useful, * |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * |
13 | * GNU General Public License for more details. * |
14 | * * |
15 | * You should have received a copy of the GNU General Public License * |
16 | * along with this program; if not, write to the * |
17 | * Free Software Foundation, Inc., * |
18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * |
19 | * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */ |
20 | |
21 | #include <stdio.h> |
22 | #include <string.h> |
23 | #include <stdarg.h> |
24 | #include <stdlib.h> |
25 | #include <stdint.h> //include for uint64_t |
26 | #include <assert.h> |
ce68e3b9 |
27 | //#define assert(a) {} |
451ab91e |
28 | |
29 | #include "../recomp.h" |
30 | #include "../recomph.h" //include for function prototypes |
31 | #include "../macros.h" |
32 | #include "../r4300.h" |
33 | #include "../ops.h" |
34 | #include "../interupt.h" |
35 | #include "new_dynarec.h" |
36 | |
37 | #include "../../memory/memory.h" |
38 | #include "../../main/rom.h" |
39 | |
40 | #include <sys/mman.h> |
41 | |
42 | #if NEW_DYNAREC == NEW_DYNAREC_X86 |
43 | #include "assem_x86.h" |
44 | #elif NEW_DYNAREC == NEW_DYNAREC_ARM |
45 | #include "assem_arm.h" |
46 | #else |
47 | #error Unsupported dynarec architecture |
48 | #endif |
49 | |
50 | #define MAXBLOCK 4096 |
51 | #define MAX_OUTPUT_BLOCK_SIZE 262144 |
52 | #define CLOCK_DIVIDER 2 |
53 | |
54 | void *base_addr; |
55 | |
56 | struct regstat |
57 | { |
58 | signed char regmap_entry[HOST_REGS]; |
59 | signed char regmap[HOST_REGS]; |
60 | uint64_t was32; |
61 | uint64_t is32; |
62 | uint64_t wasdirty; |
63 | uint64_t dirty; |
64 | uint64_t u; |
65 | uint64_t uu; |
66 | u_int wasconst; |
67 | u_int isconst; |
68 | uint64_t constmap[HOST_REGS]; |
69 | }; |
70 | |
71 | struct ll_entry |
72 | { |
73 | u_int vaddr; |
74 | u_int reg32; |
75 | void *addr; |
76 | struct ll_entry *next; |
77 | }; |
78 | |
79 | static u_int start; |
80 | static u_int *source; |
81 | static u_int pagelimit; |
82 | static char insn[MAXBLOCK][10]; |
83 | static u_char itype[MAXBLOCK]; |
84 | static u_char opcode[MAXBLOCK]; |
85 | static u_char opcode2[MAXBLOCK]; |
86 | static u_char bt[MAXBLOCK]; |
87 | static u_char rs1[MAXBLOCK]; |
88 | static u_char rs2[MAXBLOCK]; |
89 | static u_char rt1[MAXBLOCK]; |
90 | static u_char rt2[MAXBLOCK]; |
91 | static u_char us1[MAXBLOCK]; |
92 | static u_char us2[MAXBLOCK]; |
93 | static u_char dep1[MAXBLOCK]; |
94 | static u_char dep2[MAXBLOCK]; |
95 | static u_char lt1[MAXBLOCK]; |
96 | static int imm[MAXBLOCK]; |
97 | static u_int ba[MAXBLOCK]; |
98 | static char likely[MAXBLOCK]; |
99 | static char is_ds[MAXBLOCK]; |
100 | static char ooo[MAXBLOCK]; |
101 | static uint64_t unneeded_reg[MAXBLOCK]; |
102 | static uint64_t unneeded_reg_upper[MAXBLOCK]; |
103 | static uint64_t branch_unneeded_reg[MAXBLOCK]; |
104 | static uint64_t branch_unneeded_reg_upper[MAXBLOCK]; |
105 | static uint64_t p32[MAXBLOCK]; |
106 | static uint64_t pr32[MAXBLOCK]; |
107 | static signed char regmap_pre[MAXBLOCK][HOST_REGS]; |
108 | #ifdef ASSEM_DEBUG |
109 | static signed char regmap[MAXBLOCK][HOST_REGS]; |
110 | static signed char regmap_entry[MAXBLOCK][HOST_REGS]; |
111 | #endif |
112 | static uint64_t constmap[MAXBLOCK][HOST_REGS]; |
113 | static struct regstat regs[MAXBLOCK]; |
114 | static struct regstat branch_regs[MAXBLOCK]; |
115 | static signed char minimum_free_regs[MAXBLOCK]; |
116 | static u_int needed_reg[MAXBLOCK]; |
117 | static uint64_t requires_32bit[MAXBLOCK]; |
118 | static u_int wont_dirty[MAXBLOCK]; |
119 | static u_int will_dirty[MAXBLOCK]; |
120 | static int ccadj[MAXBLOCK]; |
121 | static int slen; |
122 | static u_int instr_addr[MAXBLOCK]; |
123 | static u_int link_addr[MAXBLOCK][3]; |
124 | static int linkcount; |
125 | static u_int stubs[MAXBLOCK*3][8]; |
126 | static int stubcount; |
127 | static int literalcount; |
128 | static int is_delayslot; |
129 | static int cop1_usable; |
130 | u_char *out; |
131 | struct ll_entry *jump_in[4096]; |
132 | static struct ll_entry *jump_out[4096]; |
133 | struct ll_entry *jump_dirty[4096]; |
134 | u_int hash_table[65536][4] __attribute__((aligned(16))); |
135 | static char shadow[2097152] __attribute__((aligned(16))); |
136 | static void *copy; |
137 | static int expirep; |
138 | u_int using_tlb; |
139 | static u_int stop_after_jal; |
140 | extern u_char restore_candidate[512]; |
141 | extern int cycle_count; |
142 | |
143 | /* registers that may be allocated */ |
144 | /* 1-31 gpr */ |
145 | #define HIREG 32 // hi |
146 | #define LOREG 33 // lo |
147 | #define FSREG 34 // FPU status (FCSR) |
148 | #define CSREG 35 // Coprocessor status |
149 | #define CCREG 36 // Cycle count |
150 | #define INVCP 37 // Pointer to invalid_code |
151 | #define MMREG 38 // Pointer to memory_map |
152 | #define ROREG 39 // ram offset (if rdram!=0x80000000) |
153 | #define TEMPREG 40 |
154 | #define FTEMP 40 // FPU temporary register |
155 | #define PTEMP 41 // Prefetch temporary register |
156 | #define TLREG 42 // TLB mapping offset |
157 | #define RHASH 43 // Return address hash |
158 | #define RHTBL 44 // Return address hash table address |
159 | #define RTEMP 45 // JR/JALR address register |
160 | #define MAXREG 45 |
161 | #define AGEN1 46 // Address generation temporary register |
162 | #define AGEN2 47 // Address generation temporary register |
163 | #define MGEN1 48 // Maptable address generation temporary register |
164 | #define MGEN2 49 // Maptable address generation temporary register |
165 | #define BTREG 50 // Branch target temporary register |
166 | |
167 | /* instruction types */ |
168 | #define NOP 0 // No operation |
169 | #define LOAD 1 // Load |
170 | #define STORE 2 // Store |
171 | #define LOADLR 3 // Unaligned load |
172 | #define STORELR 4 // Unaligned store |
173 | #define MOV 5 // Move |
174 | #define ALU 6 // Arithmetic/logic |
175 | #define MULTDIV 7 // Multiply/divide |
176 | #define SHIFT 8 // Shift by register |
177 | #define SHIFTIMM 9// Shift by immediate |
178 | #define IMM16 10 // 16-bit immediate |
179 | #define RJUMP 11 // Unconditional jump to register |
180 | #define UJUMP 12 // Unconditional jump |
181 | #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ) |
182 | #define SJUMP 14 // Conditional branch (regimm format) |
183 | #define COP0 15 // Coprocessor 0 |
184 | #define COP1 16 // Coprocessor 1 |
185 | #define C1LS 17 // Coprocessor 1 load/store |
186 | #define FJUMP 18 // Conditional branch (floating point) |
187 | #define FLOAT 19 // Floating point unit |
188 | #define FCONV 20 // Convert integer to float |
189 | #define FCOMP 21 // Floating point compare (sets FSREG) |
190 | #define SYSCALL 22// SYSCALL |
191 | #define OTHER 23 // Other |
192 | #define SPAN 24 // Branch/delay slot spans 2 pages |
193 | #define NI 25 // Not implemented |
194 | |
195 | /* stubs */ |
196 | #define CC_STUB 1 |
197 | #define FP_STUB 2 |
198 | #define LOADB_STUB 3 |
199 | #define LOADH_STUB 4 |
200 | #define LOADW_STUB 5 |
201 | #define LOADD_STUB 6 |
202 | #define LOADBU_STUB 7 |
203 | #define LOADHU_STUB 8 |
204 | #define STOREB_STUB 9 |
205 | #define STOREH_STUB 10 |
206 | #define STOREW_STUB 11 |
207 | #define STORED_STUB 12 |
208 | #define STORELR_STUB 13 |
209 | #define INVCODE_STUB 14 |
210 | |
211 | /* branch codes */ |
212 | #define TAKEN 1 |
213 | #define NOTTAKEN 2 |
214 | #define NULLDS 3 |
215 | |
216 | /* bug-fix to implement __clear_cache (missing in Android; http://code.google.com/p/android/issues/detail?id=1803) */ |
217 | void __clear_cache_bugfix(char* begin, char *end); |
218 | #ifdef ANDROID |
219 | #define __clear_cache __clear_cache_bugfix |
220 | #endif |
221 | |
222 | // asm linkage |
223 | int new_recompile_block(int addr); |
224 | void *get_addr_ht(u_int vaddr); |
225 | static void remove_hash(int vaddr); |
226 | void dyna_linker(); |
227 | void dyna_linker_ds(); |
228 | void verify_code(); |
229 | void verify_code_vm(); |
230 | void verify_code_ds(); |
231 | void cc_interrupt(); |
232 | void fp_exception(); |
233 | void fp_exception_ds(); |
234 | void jump_syscall(); |
235 | void jump_eret(); |
236 | #if NEW_DYNAREC == NEW_DYNAREC_ARM |
237 | static void invalidate_addr(u_int addr); |
238 | #endif |
239 | |
240 | // TLB |
241 | void TLBWI_new(); |
242 | void TLBWR_new(); |
243 | void read_nomem_new(); |
244 | void read_nomemb_new(); |
245 | void read_nomemh_new(); |
246 | void read_nomemd_new(); |
247 | void write_nomem_new(); |
248 | void write_nomemb_new(); |
249 | void write_nomemh_new(); |
250 | void write_nomemd_new(); |
251 | void write_rdram_new(); |
252 | void write_rdramb_new(); |
253 | void write_rdramh_new(); |
254 | void write_rdramd_new(); |
255 | extern u_int memory_map[1048576]; |
256 | |
257 | // Needed by assembler |
258 | static void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32); |
259 | static void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty); |
260 | static void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr); |
261 | static void load_all_regs(signed char i_regmap[]); |
262 | static void load_needed_regs(signed char i_regmap[],signed char next_regmap[]); |
263 | static void load_regs_entry(int t); |
264 | static void load_all_consts(signed char regmap[],int is32,u_int dirty,int i); |
265 | |
266 | static void add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e); |
267 | static void add_to_linker(int addr,int target,int ext); |
268 | static int verify_dirty(void *addr); |
269 | |
270 | //static int tracedebug=0; |
271 | |
272 | //#define DEBUG_CYCLE_COUNT 1 |
273 | |
274 | // Uncomment these two lines to generate debug output: |
275 | //#define ASSEM_DEBUG 1 |
276 | //#define INV_DEBUG 1 |
277 | |
278 | // Uncomment this line to output the number of NOTCOMPILED blocks as they occur: |
279 | //#define COUNT_NOTCOMPILEDS 1 |
280 | |
281 | #if defined (COUNT_NOTCOMPILEDS ) |
282 | int notcompiledCount = 0; |
283 | #endif |
284 | static void nullf() {} |
285 | |
286 | #if defined( ASSEM_DEBUG ) |
287 | #define assem_debug(...) DebugMessage(M64MSG_VERBOSE, __VA_ARGS__) |
288 | #else |
289 | #define assem_debug nullf |
290 | #endif |
291 | #if defined( INV_DEBUG ) |
292 | #define inv_debug(...) DebugMessage(M64MSG_VERBOSE, __VA_ARGS__) |
293 | #else |
294 | #define inv_debug nullf |
295 | #endif |
296 | |
297 | #define log_message(...) DebugMessage(M64MSG_VERBOSE, __VA_ARGS__) |
298 | |
299 | static void tlb_hacks() |
300 | { |
301 | // Goldeneye hack |
302 | if (strncmp((char *) ROM_HEADER.Name, "GOLDENEYE",9) == 0) |
303 | { |
304 | u_int addr; |
305 | int n; |
306 | switch (ROM_HEADER.Country_code&0xFF) |
307 | { |
308 | case 0x45: // U |
309 | addr=0x34b30; |
310 | break; |
311 | case 0x4A: // J |
312 | addr=0x34b70; |
313 | break; |
314 | case 0x50: // E |
315 | addr=0x329f0; |
316 | break; |
317 | default: |
318 | // Unknown country code |
319 | addr=0; |
320 | break; |
321 | } |
322 | u_int rom_addr=(u_int)rom; |
323 | #ifdef ROM_COPY |
324 | // Since memory_map is 32-bit, on 64-bit systems the rom needs to be |
325 | // in the lower 4G of memory to use this hack. Copy it if necessary. |
326 | if((void *)rom>(void *)0xffffffff) { |
327 | munmap(ROM_COPY, 67108864); |
328 | if(mmap(ROM_COPY, 12582912, |
329 | PROT_READ | PROT_WRITE, |
330 | MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS, |
331 | -1, 0) <= 0) {DebugMessage(M64MSG_ERROR, "mmap() failed");} |
332 | memcpy(ROM_COPY,rom,12582912); |
333 | rom_addr=(u_int)ROM_COPY; |
334 | } |
335 | #endif |
336 | if(addr) { |
337 | for(n=0x7F000;n<0x80000;n++) { |
338 | memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000; |
339 | } |
340 | } |
341 | } |
342 | } |
343 | |
344 | // Get address from virtual address |
345 | // This is called from the recompiled JR/JALR instructions |
346 | void *get_addr(u_int vaddr) |
347 | { |
348 | u_int page=(vaddr^0x80000000)>>12; |
349 | u_int vpage=page; |
350 | if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12; |
351 | if(page>2048) page=2048+(page&2047); |
352 | if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead |
353 | if(vpage>2048) vpage=2048+(vpage&2047); |
354 | struct ll_entry *head; |
355 | //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr %x,page %d)",Count,next_interupt,vaddr,page); |
356 | head=jump_in[page]; |
357 | while(head!=NULL) { |
358 | if(head->vaddr==vaddr&&head->reg32==0) { |
359 | //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr match %x: %x)",Count,next_interupt,vaddr,(int)head->addr); |
360 | u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; |
361 | ht_bin[3]=ht_bin[1]; |
362 | ht_bin[2]=ht_bin[0]; |
363 | ht_bin[1]=(int)head->addr; |
364 | ht_bin[0]=vaddr; |
365 | return head->addr; |
366 | } |
367 | head=head->next; |
368 | } |
369 | head=jump_dirty[vpage]; |
370 | while(head!=NULL) { |
371 | if(head->vaddr==vaddr&&head->reg32==0) { |
372 | //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr match dirty %x: %x)",Count,next_interupt,vaddr,(int)head->addr); |
373 | // Don't restore blocks which are about to expire from the cache |
374 | if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) |
375 | if(verify_dirty(head->addr)) { |
376 | //DebugMessage(M64MSG_VERBOSE, "restore candidate: %x (%d) d=%d",vaddr,page,invalid_code[vaddr>>12]); |
377 | invalid_code[vaddr>>12]=0; |
378 | memory_map[vaddr>>12]|=0x40000000; |
379 | if(vpage<2048) { |
380 | if(tlb_LUT_r[vaddr>>12]) { |
381 | invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0; |
382 | memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000; |
383 | } |
384 | restore_candidate[vpage>>3]|=1<<(vpage&7); |
385 | } |
386 | else restore_candidate[page>>3]|=1<<(page&7); |
387 | u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; |
388 | if(ht_bin[0]==vaddr) { |
389 | ht_bin[1]=(int)head->addr; // Replace existing entry |
390 | } |
391 | else |
392 | { |
393 | ht_bin[3]=ht_bin[1]; |
394 | ht_bin[2]=ht_bin[0]; |
395 | ht_bin[1]=(int)head->addr; |
396 | ht_bin[0]=vaddr; |
397 | } |
398 | return head->addr; |
399 | } |
400 | } |
401 | head=head->next; |
402 | } |
403 | //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr no-match %x)",Count,next_interupt,vaddr); |
404 | int r=new_recompile_block(vaddr); |
405 | if(r==0) return get_addr(vaddr); |
406 | // Execute in unmapped page, generate pagefault execption |
407 | Status|=2; |
408 | Cause=(vaddr<<31)|0x8; |
409 | EPC=(vaddr&1)?vaddr-5:vaddr; |
410 | BadVAddr=(vaddr&~1); |
411 | Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0); |
412 | EntryHi=BadVAddr&0xFFFFE000; |
413 | return get_addr_ht(0x80000000); |
414 | } |
415 | // Look up address in hash table first |
416 | void *get_addr_ht(u_int vaddr) |
417 | { |
418 | //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr_ht %x)",Count,next_interupt,vaddr); |
419 | u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; |
420 | if(ht_bin[0]==vaddr) return (void *)ht_bin[1]; |
421 | if(ht_bin[2]==vaddr) return (void *)ht_bin[3]; |
422 | return get_addr(vaddr); |
423 | } |
424 | |
425 | void *get_addr_32(u_int vaddr,u_int flags) |
426 | { |
427 | //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr_32 %x,flags %x)",Count,next_interupt,vaddr,flags); |
428 | u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; |
429 | if(ht_bin[0]==vaddr) return (void *)ht_bin[1]; |
430 | if(ht_bin[2]==vaddr) return (void *)ht_bin[3]; |
431 | u_int page=(vaddr^0x80000000)>>12; |
432 | u_int vpage=page; |
433 | if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12; |
434 | if(page>2048) page=2048+(page&2047); |
435 | if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead |
436 | if(vpage>2048) vpage=2048+(vpage&2047); |
437 | struct ll_entry *head; |
438 | head=jump_in[page]; |
439 | while(head!=NULL) { |
440 | if(head->vaddr==vaddr&&(head->reg32&flags)==0) { |
441 | //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr_32 match %x: %x)",Count,next_interupt,vaddr,(int)head->addr); |
442 | if(head->reg32==0) { |
443 | u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; |
444 | if(ht_bin[0]==-1) { |
445 | ht_bin[1]=(int)head->addr; |
446 | ht_bin[0]=vaddr; |
447 | }else if(ht_bin[2]==-1) { |
448 | ht_bin[3]=(int)head->addr; |
449 | ht_bin[2]=vaddr; |
450 | } |
451 | //ht_bin[3]=ht_bin[1]; |
452 | //ht_bin[2]=ht_bin[0]; |
453 | //ht_bin[1]=(int)head->addr; |
454 | //ht_bin[0]=vaddr; |
455 | } |
456 | return head->addr; |
457 | } |
458 | head=head->next; |
459 | } |
460 | head=jump_dirty[vpage]; |
461 | while(head!=NULL) { |
462 | if(head->vaddr==vaddr&&(head->reg32&flags)==0) { |
463 | //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)",Count,next_interupt,vaddr,(int)head->addr); |
464 | // Don't restore blocks which are about to expire from the cache |
465 | if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) |
466 | if(verify_dirty(head->addr)) { |
467 | //DebugMessage(M64MSG_VERBOSE, "restore candidate: %x (%d) d=%d",vaddr,page,invalid_code[vaddr>>12]); |
468 | invalid_code[vaddr>>12]=0; |
469 | memory_map[vaddr>>12]|=0x40000000; |
470 | if(vpage<2048) { |
471 | if(tlb_LUT_r[vaddr>>12]) { |
472 | invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0; |
473 | memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000; |
474 | } |
475 | restore_candidate[vpage>>3]|=1<<(vpage&7); |
476 | } |
477 | else restore_candidate[page>>3]|=1<<(page&7); |
478 | if(head->reg32==0) { |
479 | u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; |
480 | if(ht_bin[0]==-1) { |
481 | ht_bin[1]=(int)head->addr; |
482 | ht_bin[0]=vaddr; |
483 | }else if(ht_bin[2]==-1) { |
484 | ht_bin[3]=(int)head->addr; |
485 | ht_bin[2]=vaddr; |
486 | } |
487 | //ht_bin[3]=ht_bin[1]; |
488 | //ht_bin[2]=ht_bin[0]; |
489 | //ht_bin[1]=(int)head->addr; |
490 | //ht_bin[0]=vaddr; |
491 | } |
492 | return head->addr; |
493 | } |
494 | } |
495 | head=head->next; |
496 | } |
497 | //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)",Count,next_interupt,vaddr,flags); |
498 | int r=new_recompile_block(vaddr); |
499 | if(r==0) return get_addr(vaddr); |
500 | // Execute in unmapped page, generate pagefault execption |
501 | Status|=2; |
502 | Cause=(vaddr<<31)|0x8; |
503 | EPC=(vaddr&1)?vaddr-5:vaddr; |
504 | BadVAddr=(vaddr&~1); |
505 | Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0); |
506 | EntryHi=BadVAddr&0xFFFFE000; |
507 | return get_addr_ht(0x80000000); |
508 | } |
509 | |
510 | static void clear_all_regs(signed char regmap[]) |
511 | { |
512 | int hr; |
513 | for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1; |
514 | } |
515 | |
516 | static signed char get_reg(signed char regmap[],int r) |
517 | { |
518 | int hr; |
519 | for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr; |
520 | return -1; |
521 | } |
522 | |
523 | // Find a register that is available for two consecutive cycles |
524 | static signed char get_reg2(signed char regmap1[],signed char regmap2[],int r) |
525 | { |
526 | int hr; |
527 | for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr; |
528 | return -1; |
529 | } |
530 | |
531 | static int count_free_regs(signed char regmap[]) |
532 | { |
533 | int count=0; |
534 | int hr; |
535 | for(hr=0;hr<HOST_REGS;hr++) |
536 | { |
537 | if(hr!=EXCLUDE_REG) { |
538 | if(regmap[hr]<0) count++; |
539 | } |
540 | } |
541 | return count; |
542 | } |
543 | |
544 | static void dirty_reg(struct regstat *cur,signed char reg) |
545 | { |
546 | int hr; |
547 | if(!reg) return; |
548 | for (hr=0;hr<HOST_REGS;hr++) { |
549 | if((cur->regmap[hr]&63)==reg) { |
550 | cur->dirty|=1<<hr; |
551 | } |
552 | } |
553 | } |
554 | |
555 | // If we dirty the lower half of a 64 bit register which is now being |
556 | // sign-extended, we need to dump the upper half. |
557 | // Note: Do this only after completion of the instruction, because |
558 | // some instructions may need to read the full 64-bit value even if |
559 | // overwriting it (eg SLTI, DSRA32). |
560 | static void flush_dirty_uppers(struct regstat *cur) |
561 | { |
562 | int hr,reg; |
563 | for (hr=0;hr<HOST_REGS;hr++) { |
564 | if((cur->dirty>>hr)&1) { |
565 | reg=cur->regmap[hr]; |
566 | if(reg>=64) |
567 | if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1; |
568 | } |
569 | } |
570 | } |
571 | |
572 | static void set_const(struct regstat *cur,signed char reg,uint64_t value) |
573 | { |
574 | int hr; |
575 | if(!reg) return; |
576 | for (hr=0;hr<HOST_REGS;hr++) { |
577 | if(cur->regmap[hr]==reg) { |
578 | cur->isconst|=1<<hr; |
579 | cur->constmap[hr]=value; |
580 | } |
581 | else if((cur->regmap[hr]^64)==reg) { |
582 | cur->isconst|=1<<hr; |
583 | cur->constmap[hr]=value>>32; |
584 | } |
585 | } |
586 | } |
587 | |
588 | static void clear_const(struct regstat *cur,signed char reg) |
589 | { |
590 | int hr; |
591 | if(!reg) return; |
592 | for (hr=0;hr<HOST_REGS;hr++) { |
593 | if((cur->regmap[hr]&63)==reg) { |
594 | cur->isconst&=~(1<<hr); |
595 | } |
596 | } |
597 | } |
598 | |
599 | static int is_const(struct regstat *cur,signed char reg) |
600 | { |
601 | int hr; |
602 | if(reg<0) return 0; |
603 | if(!reg) return 1; |
604 | for (hr=0;hr<HOST_REGS;hr++) { |
605 | if((cur->regmap[hr]&63)==reg) { |
606 | return (cur->isconst>>hr)&1; |
607 | } |
608 | } |
609 | return 0; |
610 | } |
611 | static uint64_t get_const(struct regstat *cur,signed char reg) |
612 | { |
613 | int hr; |
614 | if(!reg) return 0; |
615 | for (hr=0;hr<HOST_REGS;hr++) { |
616 | if(cur->regmap[hr]==reg) { |
617 | return cur->constmap[hr]; |
618 | } |
619 | } |
620 | DebugMessage(M64MSG_ERROR, "Unknown constant in r%d",reg); |
621 | exit(1); |
622 | } |
623 | |
624 | // Least soon needed registers |
625 | // Look at the next ten instructions and see which registers |
626 | // will be used. Try not to reallocate these. |
627 | static void lsn(u_char hsn[], int i, int *preferred_reg) |
628 | { |
629 | int j; |
630 | int b=-1; |
631 | for(j=0;j<9;j++) |
632 | { |
633 | if(i+j>=slen) { |
634 | j=slen-i-1; |
635 | break; |
636 | } |
637 | if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000) |
638 | { |
639 | // Don't go past an unconditonal jump |
640 | j++; |
641 | break; |
642 | } |
643 | } |
644 | for(;j>=0;j--) |
645 | { |
646 | if(rs1[i+j]) hsn[rs1[i+j]]=j; |
647 | if(rs2[i+j]) hsn[rs2[i+j]]=j; |
648 | if(rt1[i+j]) hsn[rt1[i+j]]=j; |
649 | if(rt2[i+j]) hsn[rt2[i+j]]=j; |
650 | if(itype[i+j]==STORE || itype[i+j]==STORELR) { |
651 | // Stores can allocate zero |
652 | hsn[rs1[i+j]]=j; |
653 | hsn[rs2[i+j]]=j; |
654 | } |
655 | // On some architectures stores need invc_ptr |
656 | #if defined(HOST_IMM8) |
657 | if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39) { |
658 | hsn[INVCP]=j; |
659 | } |
660 | #endif |
661 | if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP)) |
662 | { |
663 | hsn[CCREG]=j; |
664 | b=j; |
665 | } |
666 | } |
667 | if(b>=0) |
668 | { |
669 | if(ba[i+b]>=start && ba[i+b]<(start+slen*4)) |
670 | { |
671 | // Follow first branch |
672 | int t=(ba[i+b]-start)>>2; |
673 | j=7-b;if(t+j>=slen) j=slen-t-1; |
674 | for(;j>=0;j--) |
675 | { |
676 | if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2; |
677 | if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2; |
678 | //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2; |
679 | //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2; |
680 | } |
681 | } |
682 | // TODO: preferred register based on backward branch |
683 | } |
684 | // Delay slot should preferably not overwrite branch conditions or cycle count |
685 | if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) { |
686 | if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1; |
687 | if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1; |
688 | hsn[CCREG]=1; |
689 | // ...or hash tables |
690 | hsn[RHASH]=1; |
691 | hsn[RHTBL]=1; |
692 | } |
693 | // Coprocessor load/store needs FTEMP, even if not declared |
694 | if(itype[i]==C1LS) { |
695 | hsn[FTEMP]=0; |
696 | } |
697 | // Load L/R also uses FTEMP as a temporary register |
698 | if(itype[i]==LOADLR) { |
699 | hsn[FTEMP]=0; |
700 | } |
701 | // Also 64-bit SDL/SDR |
702 | if(opcode[i]==0x2c||opcode[i]==0x2d) { |
703 | hsn[FTEMP]=0; |
704 | } |
705 | // Don't remove the TLB registers either |
706 | if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS ) { |
707 | hsn[TLREG]=0; |
708 | } |
709 | // Don't remove the miniht registers |
710 | if(itype[i]==UJUMP||itype[i]==RJUMP) |
711 | { |
712 | hsn[RHASH]=0; |
713 | hsn[RHTBL]=0; |
714 | } |
715 | } |
716 | |
717 | // We only want to allocate registers if we're going to use them again soon |
718 | static int needed_again(int r, int i) |
719 | { |
720 | int j; |
721 | /*int b=-1;*/ |
722 | int rn=10; |
723 | |
724 | if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) |
725 | { |
726 | if(ba[i-1]<start || ba[i-1]>start+slen*4-4) |
727 | return 0; // Don't need any registers if exiting the block |
728 | } |
729 | for(j=0;j<9;j++) |
730 | { |
731 | if(i+j>=slen) { |
732 | j=slen-i-1; |
733 | break; |
734 | } |
735 | if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000) |
736 | { |
737 | // Don't go past an unconditonal jump |
738 | j++; |
739 | break; |
740 | } |
741 | if(itype[i+j]==SYSCALL||((source[i+j]&0xfc00003f)==0x0d)) |
742 | { |
743 | break; |
744 | } |
745 | } |
746 | for(;j>=1;j--) |
747 | { |
748 | if(rs1[i+j]==r) rn=j; |
749 | if(rs2[i+j]==r) rn=j; |
750 | if((unneeded_reg[i+j]>>r)&1) rn=10; |
751 | if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP)) |
752 | { |
753 | /*b=j;*/ |
754 | } |
755 | } |
756 | /* |
757 | if(b>=0) |
758 | { |
759 | if(ba[i+b]>=start && ba[i+b]<(start+slen*4)) |
760 | { |
761 | // Follow first branch |
762 | int o=rn; |
763 | int t=(ba[i+b]-start)>>2; |
764 | j=7-b;if(t+j>=slen) j=slen-t-1; |
765 | for(;j>=0;j--) |
766 | { |
767 | if(!((unneeded_reg[t+j]>>r)&1)) { |
768 | if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2; |
769 | if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2; |
770 | } |
771 | else rn=o; |
772 | } |
773 | } |
774 | }*/ |
775 | if(rn<10) return 1; |
776 | return 0; |
777 | } |
778 | |
779 | // Try to match register allocations at the end of a loop with those |
780 | // at the beginning |
781 | static int loop_reg(int i, int r, int hr) |
782 | { |
783 | int j,k; |
784 | for(j=0;j<9;j++) |
785 | { |
786 | if(i+j>=slen) { |
787 | j=slen-i-1; |
788 | break; |
789 | } |
790 | if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000) |
791 | { |
792 | // Don't go past an unconditonal jump |
793 | j++; |
794 | break; |
795 | } |
796 | } |
797 | k=0; |
798 | if(i>0){ |
799 | if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) |
800 | k--; |
801 | } |
802 | for(;k<j;k++) |
803 | { |
804 | if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr; |
805 | if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr; |
806 | if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP)) |
807 | { |
808 | if(ba[i+k]>=start && ba[i+k]<(start+i*4)) |
809 | { |
810 | int t=(ba[i+k]-start)>>2; |
811 | int reg=get_reg(regs[t].regmap_entry,r); |
812 | if(reg>=0) return reg; |
813 | //reg=get_reg(regs[t+1].regmap_entry,r); |
814 | //if(reg>=0) return reg; |
815 | } |
816 | } |
817 | } |
818 | return hr; |
819 | } |
820 | |
821 | |
822 | // Allocate every register, preserving source/target regs |
823 | static void alloc_all(struct regstat *cur,int i) |
824 | { |
825 | int hr; |
826 | |
827 | for(hr=0;hr<HOST_REGS;hr++) { |
828 | if(hr!=EXCLUDE_REG) { |
829 | if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&& |
830 | ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i])) |
831 | { |
832 | cur->regmap[hr]=-1; |
833 | cur->dirty&=~(1<<hr); |
834 | } |
835 | // Don't need zeros |
836 | if((cur->regmap[hr]&63)==0) |
837 | { |
838 | cur->regmap[hr]=-1; |
839 | cur->dirty&=~(1<<hr); |
840 | } |
841 | } |
842 | } |
843 | } |
844 | |
845 | |
846 | static void div64(int64_t dividend,int64_t divisor) |
847 | { |
848 | lo=dividend/divisor; |
849 | hi=dividend%divisor; |
850 | //DebugMessage(M64MSG_VERBOSE, "TRACE: ddiv %8x%8x %8x%8x" ,(int)reg[HIREG],(int)(reg[HIREG]>>32) |
851 | // ,(int)reg[LOREG],(int)(reg[LOREG]>>32)); |
852 | } |
853 | static void divu64(uint64_t dividend,uint64_t divisor) |
854 | { |
855 | lo=dividend/divisor; |
856 | hi=dividend%divisor; |
857 | //DebugMessage(M64MSG_VERBOSE, "TRACE: ddivu %8x%8x %8x%8x",(int)reg[HIREG],(int)(reg[HIREG]>>32) |
858 | // ,(int)reg[LOREG],(int)(reg[LOREG]>>32)); |
859 | } |
860 | |
ce68e3b9 |
861 | static void mult64(int64_t m1,int64_t m2) |
451ab91e |
862 | { |
863 | unsigned long long int op1, op2, op3, op4; |
864 | unsigned long long int result1, result2, result3, result4; |
865 | unsigned long long int temp1, temp2, temp3, temp4; |
866 | int sign = 0; |
867 | |
868 | if (m1 < 0) |
869 | { |
870 | op2 = -m1; |
871 | sign = 1 - sign; |
872 | } |
873 | else op2 = m1; |
874 | if (m2 < 0) |
875 | { |
876 | op4 = -m2; |
877 | sign = 1 - sign; |
878 | } |
879 | else op4 = m2; |
880 | |
881 | op1 = op2 & 0xFFFFFFFF; |
882 | op2 = (op2 >> 32) & 0xFFFFFFFF; |
883 | op3 = op4 & 0xFFFFFFFF; |
884 | op4 = (op4 >> 32) & 0xFFFFFFFF; |
885 | |
886 | temp1 = op1 * op3; |
887 | temp2 = (temp1 >> 32) + op1 * op4; |
888 | temp3 = op2 * op3; |
889 | temp4 = (temp3 >> 32) + op2 * op4; |
890 | |
891 | result1 = temp1 & 0xFFFFFFFF; |
892 | result2 = temp2 + (temp3 & 0xFFFFFFFF); |
893 | result3 = (result2 >> 32) + temp4; |
894 | result4 = (result3 >> 32); |
895 | |
896 | lo = result1 | (result2 << 32); |
897 | hi = (result3 & 0xFFFFFFFF) | (result4 << 32); |
898 | if (sign) |
899 | { |
900 | hi = ~hi; |
901 | if (!lo) hi++; |
902 | else lo = ~lo + 1; |
903 | } |
904 | } |
905 | |
906 | #if NEW_DYNAREC == NEW_DYNAREC_ARM |
907 | static void multu64(uint64_t m1,uint64_t m2) |
908 | { |
909 | unsigned long long int op1, op2, op3, op4; |
910 | unsigned long long int result1, result2, result3, result4; |
911 | unsigned long long int temp1, temp2, temp3, temp4; |
912 | |
913 | op1 = m1 & 0xFFFFFFFF; |
914 | op2 = (m1 >> 32) & 0xFFFFFFFF; |
915 | op3 = m2 & 0xFFFFFFFF; |
916 | op4 = (m2 >> 32) & 0xFFFFFFFF; |
917 | |
918 | temp1 = op1 * op3; |
919 | temp2 = (temp1 >> 32) + op1 * op4; |
920 | temp3 = op2 * op3; |
921 | temp4 = (temp3 >> 32) + op2 * op4; |
922 | |
923 | result1 = temp1 & 0xFFFFFFFF; |
924 | result2 = temp2 + (temp3 & 0xFFFFFFFF); |
925 | result3 = (result2 >> 32) + temp4; |
926 | result4 = (result3 >> 32); |
927 | |
928 | lo = result1 | (result2 << 32); |
929 | hi = (result3 & 0xFFFFFFFF) | (result4 << 32); |
930 | |
931 | //DebugMessage(M64MSG_VERBOSE, "TRACE: dmultu %8x%8x %8x%8x",(int)reg[HIREG],(int)(reg[HIREG]>>32) |
932 | // ,(int)reg[LOREG],(int)(reg[LOREG]>>32)); |
933 | } |
934 | #endif |
935 | |
936 | static uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits) |
937 | { |
938 | if(bits) { |
939 | original<<=64-bits; |
940 | original>>=64-bits; |
941 | loaded<<=bits; |
942 | original|=loaded; |
943 | } |
944 | else original=loaded; |
945 | return original; |
946 | } |
947 | static uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits) |
948 | { |
949 | if(bits^56) { |
950 | original>>=64-(bits^56); |
951 | original<<=64-(bits^56); |
952 | loaded>>=bits^56; |
953 | original|=loaded; |
954 | } |
955 | else original=loaded; |
956 | return original; |
957 | } |
958 | |
959 | #if NEW_DYNAREC == NEW_DYNAREC_X86 |
960 | #include "assem_x86.c" |
961 | #elif NEW_DYNAREC == NEW_DYNAREC_ARM |
962 | #include "assem_arm.c" |
963 | #else |
964 | #error Unsupported dynarec architecture |
965 | #endif |
966 | |
967 | // Add virtual address mapping to linked list |
968 | static void ll_add(struct ll_entry **head,int vaddr,void *addr) |
969 | { |
970 | struct ll_entry *new_entry; |
971 | new_entry=malloc(sizeof(struct ll_entry)); |
972 | assert(new_entry!=NULL); |
973 | new_entry->vaddr=vaddr; |
974 | new_entry->reg32=0; |
975 | new_entry->addr=addr; |
976 | new_entry->next=*head; |
977 | *head=new_entry; |
978 | } |
979 | |
980 | // Add virtual address mapping for 32-bit compiled block |
981 | static void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr) |
982 | { |
983 | struct ll_entry *new_entry; |
984 | new_entry=malloc(sizeof(struct ll_entry)); |
985 | assert(new_entry!=NULL); |
986 | new_entry->vaddr=vaddr; |
987 | new_entry->reg32=reg32; |
988 | new_entry->addr=addr; |
989 | new_entry->next=*head; |
990 | *head=new_entry; |
991 | } |
992 | |
993 | // Check if an address is already compiled |
994 | // but don't return addresses which are about to expire from the cache |
995 | static void *check_addr(u_int vaddr) |
996 | { |
997 | u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; |
998 | if(ht_bin[0]==vaddr) { |
999 | if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) |
1000 | if(isclean(ht_bin[1])) return (void *)ht_bin[1]; |
1001 | } |
1002 | if(ht_bin[2]==vaddr) { |
1003 | if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) |
1004 | if(isclean(ht_bin[3])) return (void *)ht_bin[3]; |
1005 | } |
1006 | u_int page=(vaddr^0x80000000)>>12; |
1007 | if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12; |
1008 | if(page>2048) page=2048+(page&2047); |
1009 | struct ll_entry *head; |
1010 | head=jump_in[page]; |
1011 | while(head!=NULL) { |
1012 | if(head->vaddr==vaddr&&head->reg32==0) { |
1013 | if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) { |
1014 | // Update existing entry with current address |
1015 | if(ht_bin[0]==vaddr) { |
1016 | ht_bin[1]=(int)head->addr; |
1017 | return head->addr; |
1018 | } |
1019 | if(ht_bin[2]==vaddr) { |
1020 | ht_bin[3]=(int)head->addr; |
1021 | return head->addr; |
1022 | } |
1023 | // Insert into hash table with low priority. |
1024 | // Don't evict existing entries, as they are probably |
1025 | // addresses that are being accessed frequently. |
1026 | if(ht_bin[0]==-1) { |
1027 | ht_bin[1]=(int)head->addr; |
1028 | ht_bin[0]=vaddr; |
1029 | }else if(ht_bin[2]==-1) { |
1030 | ht_bin[3]=(int)head->addr; |
1031 | ht_bin[2]=vaddr; |
1032 | } |
1033 | return head->addr; |
1034 | } |
1035 | } |
1036 | head=head->next; |
1037 | } |
1038 | return 0; |
1039 | } |
1040 | |
1041 | static void remove_hash(int vaddr) |
1042 | { |
1043 | //DebugMessage(M64MSG_VERBOSE, "remove hash: %x",vaddr); |
1044 | u_int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF]; |
1045 | if(ht_bin[2]==vaddr) { |
1046 | ht_bin[2]=ht_bin[3]=-1; |
1047 | } |
1048 | if(ht_bin[0]==vaddr) { |
1049 | ht_bin[0]=ht_bin[2]; |
1050 | ht_bin[1]=ht_bin[3]; |
1051 | ht_bin[2]=ht_bin[3]=-1; |
1052 | } |
1053 | } |
1054 | |
1055 | static void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift) |
1056 | { |
1057 | struct ll_entry *next; |
1058 | while(*head) { |
1059 | if(((u_int)((*head)->addr)>>shift)==(addr>>shift) || |
1060 | ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)) |
1061 | { |
1062 | inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr); |
1063 | remove_hash((*head)->vaddr); |
1064 | next=(*head)->next; |
1065 | free(*head); |
1066 | *head=next; |
1067 | } |
1068 | else |
1069 | { |
1070 | head=&((*head)->next); |
1071 | } |
1072 | } |
1073 | } |
1074 | |
1075 | // Remove all entries from linked list |
1076 | static void ll_clear(struct ll_entry **head) |
1077 | { |
1078 | struct ll_entry *cur; |
1079 | struct ll_entry *next; |
1080 | if((cur=*head)) { |
1081 | *head=0; |
1082 | while(cur) { |
1083 | next=cur->next; |
1084 | free(cur); |
1085 | cur=next; |
1086 | } |
1087 | } |
1088 | } |
1089 | |
1090 | // Dereference the pointers and remove if it matches |
1091 | static void ll_kill_pointers(struct ll_entry *head,int addr,int shift) |
1092 | { |
1093 | while(head) { |
1094 | int ptr=get_pointer(head->addr); |
1095 | inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr); |
1096 | if(((ptr>>shift)==(addr>>shift)) || |
1097 | (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))) |
1098 | { |
1099 | inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr); |
1100 | u_int host_addr=(int)kill_pointer(head->addr); |
1101 | #if NEW_DYNAREC == NEW_DYNAREC_ARM |
1102 | needs_clear_cache[(host_addr-(u_int)base_addr)>>17]|=1<<(((host_addr-(u_int)base_addr)>>12)&31); |
1103 | #endif |
1104 | } |
1105 | head=head->next; |
1106 | } |
1107 | } |
1108 | |
1109 | // This is called when we write to a compiled block (see do_invstub) |
1110 | static void invalidate_page(u_int page) |
1111 | { |
1112 | struct ll_entry *head; |
1113 | struct ll_entry *next; |
1114 | head=jump_in[page]; |
1115 | jump_in[page]=0; |
1116 | while(head!=NULL) { |
1117 | inv_debug("INVALIDATE: %x\n",head->vaddr); |
1118 | remove_hash(head->vaddr); |
1119 | next=head->next; |
1120 | free(head); |
1121 | head=next; |
1122 | } |
1123 | head=jump_out[page]; |
1124 | jump_out[page]=0; |
1125 | while(head!=NULL) { |
1126 | inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr); |
1127 | u_int host_addr=(int)kill_pointer(head->addr); |
1128 | #if NEW_DYNAREC == NEW_DYNAREC_ARM |
1129 | needs_clear_cache[(host_addr-(u_int)base_addr)>>17]|=1<<(((host_addr-(u_int)base_addr)>>12)&31); |
1130 | #endif |
1131 | next=head->next; |
1132 | free(head); |
1133 | head=next; |
1134 | } |
1135 | } |
1136 | void invalidate_block(u_int block) |
1137 | { |
1138 | u_int page,vpage; |
1139 | page=vpage=block^0x80000; |
1140 | if(page>262143&&tlb_LUT_r[block]) page=(tlb_LUT_r[block]^0x80000000)>>12; |
1141 | if(page>2048) page=2048+(page&2047); |
1142 | if(vpage>262143&&tlb_LUT_r[block]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead |
1143 | if(vpage>2048) vpage=2048+(vpage&2047); |
1144 | inv_debug("INVALIDATE: %x (%d)\n",block<<12,page); |
1145 | //inv_debug("invalid_code[block]=%d\n",invalid_code[block]); |
1146 | u_int first,last; |
1147 | first=last=page; |
1148 | struct ll_entry *head; |
1149 | head=jump_dirty[vpage]; |
1150 | //DebugMessage(M64MSG_VERBOSE, "page=%d vpage=%d",page,vpage); |
1151 | while(head!=NULL) { |
1152 | u_int start,end; |
1153 | if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision |
1154 | get_bounds((int)head->addr,&start,&end); |
1155 | //DebugMessage(M64MSG_VERBOSE, "start: %x end: %x",start,end); |
1156 | if(page<2048&&start>=0x80000000&&end<0x80800000) { |
1157 | if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) { |
1158 | if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047; |
1159 | if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047; |
1160 | } |
1161 | } |
1162 | if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) { |
1163 | if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) { |
1164 | if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047; |
1165 | if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047; |
1166 | } |
1167 | } |
1168 | } |
1169 | head=head->next; |
1170 | } |
1171 | //DebugMessage(M64MSG_VERBOSE, "first=%d last=%d",first,last); |
1172 | invalidate_page(page); |
1173 | assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages) |
1174 | assert(last<page+5); |
1175 | // Invalidate the adjacent pages if a block crosses a 4K boundary |
1176 | while(first<page) { |
1177 | invalidate_page(first); |
1178 | first++; |
1179 | } |
1180 | for(first=page+1;first<last;first++) { |
1181 | invalidate_page(first); |
1182 | } |
1183 | #if NEW_DYNAREC == NEW_DYNAREC_ARM |
1184 | do_clear_cache(); |
1185 | #endif |
1186 | |
1187 | // Don't trap writes |
1188 | invalid_code[block]=1; |
1189 | // If there is a valid TLB entry for this page, remove write protect |
1190 | if(tlb_LUT_w[block]) { |
1191 | assert(tlb_LUT_r[block]==tlb_LUT_w[block]); |
1192 | // CHECK: Is this right? |
1193 | memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2; |
1194 | u_int real_block=tlb_LUT_w[block]>>12; |
1195 | invalid_code[real_block]=1; |
1196 | if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2; |
1197 | } |
1198 | else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2; |
1199 | #ifdef USE_MINI_HT |
1200 | memset(mini_ht,-1,sizeof(mini_ht)); |
1201 | #endif |
1202 | } |
1203 | |
1204 | #if NEW_DYNAREC == NEW_DYNAREC_ARM |
1205 | static void invalidate_addr(u_int addr) |
1206 | { |
1207 | invalidate_block(addr>>12); |
1208 | } |
1209 | #endif |
1210 | |
1211 | // This is called when loading a save state. |
1212 | // Anything could have changed, so invalidate everything. |
1213 | void invalidate_all_pages() |
1214 | { |
1215 | u_int page; |
1216 | for(page=0;page<4096;page++) |
1217 | invalidate_page(page); |
1218 | for(page=0;page<1048576;page++) |
1219 | if(!invalid_code[page]) { |
1220 | restore_candidate[(page&2047)>>3]|=1<<(page&7); |
1221 | restore_candidate[((page&2047)>>3)+256]|=1<<(page&7); |
1222 | } |
1223 | #if NEW_DYNAREC == NEW_DYNAREC_ARM |
1224 | __clear_cache((void *)base_addr,(void *)base_addr+(1<<TARGET_SIZE_2)); |
1225 | //cacheflush((void *)base_addr,(void *)base_addr+(1<<TARGET_SIZE_2),0); |
1226 | #endif |
1227 | #ifdef USE_MINI_HT |
1228 | memset(mini_ht,-1,sizeof(mini_ht)); |
1229 | #endif |
1230 | // TLB |
1231 | for(page=0;page<0x100000;page++) { |
1232 | if(tlb_LUT_r[page]) { |
1233 | memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2; |
1234 | if(!tlb_LUT_w[page]||!invalid_code[page]) |
1235 | memory_map[page]|=0x40000000; // Write protect |
1236 | } |
1237 | else memory_map[page]=-1; |
1238 | if(page==0x80000) page=0xC0000; |
1239 | } |
1240 | tlb_hacks(); |
1241 | } |
1242 | |
1243 | // Add an entry to jump_out after making a link |
1244 | void add_link(u_int vaddr,void *src) |
1245 | { |
1246 | u_int page=(vaddr^0x80000000)>>12; |
1247 | if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12; |
1248 | if(page>4095) page=2048+(page&2047); |
1249 | inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page); |
1250 | ll_add(jump_out+page,vaddr,src); |
1251 | //int ptr=get_pointer(src); |
1252 | //inv_debug("add_link: Pointer is to %x\n",(int)ptr); |
1253 | } |
1254 | |
1255 | // If a code block was found to be unmodified (bit was set in |
1256 | // restore_candidate) and it remains unmodified (bit is clear |
1257 | // in invalid_code) then move the entries for that 4K page from |
1258 | // the dirty list to the clean list. |
1259 | void clean_blocks(u_int page) |
1260 | { |
1261 | struct ll_entry *head; |
1262 | inv_debug("INV: clean_blocks page=%d\n",page); |
1263 | head=jump_dirty[page]; |
1264 | while(head!=NULL) { |
1265 | if(!invalid_code[head->vaddr>>12]) { |
1266 | // Don't restore blocks which are about to expire from the cache |
1267 | if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) { |
1268 | u_int start,end; |
1269 | if(verify_dirty(head->addr)) { |
1270 | //DebugMessage(M64MSG_VERBOSE, "Possibly Restore %x (%x)",head->vaddr, (int)head->addr); |
1271 | u_int i; |
1272 | u_int inv=0; |
1273 | get_bounds((int)head->addr,&start,&end); |
1274 | if(start-(u_int)rdram<0x800000) { |
1275 | for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) { |
1276 | inv|=invalid_code[i]; |
1277 | } |
1278 | } |
1279 | if((signed int)head->vaddr>=(signed int)0xC0000000) { |
1280 | u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2)); |
1281 | //DebugMessage(M64MSG_VERBOSE, "addr=%x start=%x end=%x",addr,start,end); |
1282 | if(addr<start||addr>=end) inv=1; |
1283 | } |
1284 | else if((signed int)head->vaddr>=(signed int)0x80800000) { |
1285 | inv=1; |
1286 | } |
1287 | if(!inv) { |
1288 | void * clean_addr=(void *)get_clean_addr((int)head->addr); |
1289 | if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) { |
1290 | u_int ppage=page; |
1291 | if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12; |
1292 | inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr); |
1293 | //DebugMessage(M64MSG_VERBOSE, "page=%x, addr=%x",page,head->vaddr); |
1294 | //assert(head->vaddr>>12==(page|0x80000)); |
1295 | ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr); |
1296 | u_int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF]; |
1297 | if(!head->reg32) { |
1298 | if(ht_bin[0]==head->vaddr) { |
1299 | ht_bin[1]=(int)clean_addr; // Replace existing entry |
1300 | } |
1301 | if(ht_bin[2]==head->vaddr) { |
1302 | ht_bin[3]=(int)clean_addr; // Replace existing entry |
1303 | } |
1304 | } |
1305 | } |
1306 | } |
1307 | } |
1308 | } |
1309 | } |
1310 | head=head->next; |
1311 | } |
1312 | } |
1313 | |
1314 | |
1315 | static void mov_alloc(struct regstat *current,int i) |
1316 | { |
1317 | // Note: Don't need to actually alloc the source registers |
1318 | if((~current->is32>>rs1[i])&1) { |
1319 | //alloc_reg64(current,i,rs1[i]); |
1320 | alloc_reg64(current,i,rt1[i]); |
1321 | current->is32&=~(1LL<<rt1[i]); |
1322 | } else { |
1323 | //alloc_reg(current,i,rs1[i]); |
1324 | alloc_reg(current,i,rt1[i]); |
1325 | current->is32|=(1LL<<rt1[i]); |
1326 | } |
1327 | clear_const(current,rs1[i]); |
1328 | clear_const(current,rt1[i]); |
1329 | dirty_reg(current,rt1[i]); |
1330 | } |
1331 | |
1332 | static void shiftimm_alloc(struct regstat *current,int i) |
1333 | { |
1334 | clear_const(current,rs1[i]); |
1335 | clear_const(current,rt1[i]); |
1336 | if(opcode2[i]<=0x3) // SLL/SRL/SRA |
1337 | { |
1338 | if(rt1[i]) { |
1339 | if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); |
1340 | else lt1[i]=rs1[i]; |
1341 | alloc_reg(current,i,rt1[i]); |
1342 | current->is32|=1LL<<rt1[i]; |
1343 | dirty_reg(current,rt1[i]); |
1344 | } |
1345 | } |
1346 | if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA |
1347 | { |
1348 | if(rt1[i]) { |
1349 | if(rs1[i]) alloc_reg64(current,i,rs1[i]); |
1350 | alloc_reg64(current,i,rt1[i]); |
1351 | current->is32&=~(1LL<<rt1[i]); |
1352 | dirty_reg(current,rt1[i]); |
1353 | } |
1354 | } |
1355 | if(opcode2[i]==0x3c) // DSLL32 |
1356 | { |
1357 | if(rt1[i]) { |
1358 | if(rs1[i]) alloc_reg(current,i,rs1[i]); |
1359 | alloc_reg64(current,i,rt1[i]); |
1360 | current->is32&=~(1LL<<rt1[i]); |
1361 | dirty_reg(current,rt1[i]); |
1362 | } |
1363 | } |
1364 | if(opcode2[i]==0x3e) // DSRL32 |
1365 | { |
1366 | if(rt1[i]) { |
1367 | alloc_reg64(current,i,rs1[i]); |
1368 | if(imm[i]==32) { |
1369 | alloc_reg64(current,i,rt1[i]); |
1370 | current->is32&=~(1LL<<rt1[i]); |
1371 | } else { |
1372 | alloc_reg(current,i,rt1[i]); |
1373 | current->is32|=1LL<<rt1[i]; |
1374 | } |
1375 | dirty_reg(current,rt1[i]); |
1376 | } |
1377 | } |
1378 | if(opcode2[i]==0x3f) // DSRA32 |
1379 | { |
1380 | if(rt1[i]) { |
1381 | alloc_reg64(current,i,rs1[i]); |
1382 | alloc_reg(current,i,rt1[i]); |
1383 | current->is32|=1LL<<rt1[i]; |
1384 | dirty_reg(current,rt1[i]); |
1385 | } |
1386 | } |
1387 | } |
1388 | |
1389 | static void shift_alloc(struct regstat *current,int i) |
1390 | { |
1391 | if(rt1[i]) { |
1392 | if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV |
1393 | { |
1394 | if(rs1[i]) alloc_reg(current,i,rs1[i]); |
1395 | if(rs2[i]) alloc_reg(current,i,rs2[i]); |
1396 | alloc_reg(current,i,rt1[i]); |
1397 | if(rt1[i]==rs2[i]) { |
1398 | alloc_reg_temp(current,i,-1); |
1399 | minimum_free_regs[i]=1; |
1400 | } |
1401 | current->is32|=1LL<<rt1[i]; |
1402 | } else { // DSLLV/DSRLV/DSRAV |
1403 | if(rs1[i]) alloc_reg64(current,i,rs1[i]); |
1404 | if(rs2[i]) alloc_reg(current,i,rs2[i]); |
1405 | alloc_reg64(current,i,rt1[i]); |
1406 | current->is32&=~(1LL<<rt1[i]); |
1407 | if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register |
1408 | { |
1409 | alloc_reg_temp(current,i,-1); |
1410 | minimum_free_regs[i]=1; |
1411 | } |
1412 | } |
1413 | clear_const(current,rs1[i]); |
1414 | clear_const(current,rs2[i]); |
1415 | clear_const(current,rt1[i]); |
1416 | dirty_reg(current,rt1[i]); |
1417 | } |
1418 | } |
1419 | |
1420 | static void alu_alloc(struct regstat *current,int i) |
1421 | { |
1422 | if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU |
1423 | if(rt1[i]) { |
1424 | if(rs1[i]&&rs2[i]) { |
1425 | alloc_reg(current,i,rs1[i]); |
1426 | alloc_reg(current,i,rs2[i]); |
1427 | } |
1428 | else { |
1429 | if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); |
1430 | if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]); |
1431 | } |
1432 | alloc_reg(current,i,rt1[i]); |
1433 | } |
1434 | current->is32|=1LL<<rt1[i]; |
1435 | } |
1436 | if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU |
1437 | if(rt1[i]) { |
1438 | if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1)) |
1439 | { |
1440 | alloc_reg64(current,i,rs1[i]); |
1441 | alloc_reg64(current,i,rs2[i]); |
1442 | alloc_reg(current,i,rt1[i]); |
1443 | } else { |
1444 | alloc_reg(current,i,rs1[i]); |
1445 | alloc_reg(current,i,rs2[i]); |
1446 | alloc_reg(current,i,rt1[i]); |
1447 | } |
1448 | } |
1449 | current->is32|=1LL<<rt1[i]; |
1450 | } |
1451 | if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR |
1452 | if(rt1[i]) { |
1453 | if(rs1[i]&&rs2[i]) { |
1454 | alloc_reg(current,i,rs1[i]); |
1455 | alloc_reg(current,i,rs2[i]); |
1456 | } |
1457 | else |
1458 | { |
1459 | if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); |
1460 | if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]); |
1461 | } |
1462 | alloc_reg(current,i,rt1[i]); |
1463 | if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1)) |
1464 | { |
1465 | if(!((current->uu>>rt1[i])&1)) { |
1466 | alloc_reg64(current,i,rt1[i]); |
1467 | } |
1468 | if(get_reg(current->regmap,rt1[i]|64)>=0) { |
1469 | if(rs1[i]&&rs2[i]) { |
1470 | alloc_reg64(current,i,rs1[i]); |
1471 | alloc_reg64(current,i,rs2[i]); |
1472 | } |
1473 | else |
1474 | { |
1475 | // Is is really worth it to keep 64-bit values in registers? |
1476 | #ifdef NATIVE_64BIT |
1477 | if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]); |
1478 | if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]); |
1479 | #endif |
1480 | } |
1481 | } |
1482 | current->is32&=~(1LL<<rt1[i]); |
1483 | } else { |
1484 | current->is32|=1LL<<rt1[i]; |
1485 | } |
1486 | } |
1487 | } |
1488 | if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU |
1489 | if(rt1[i]) { |
1490 | if(rs1[i]&&rs2[i]) { |
1491 | if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) { |
1492 | alloc_reg64(current,i,rs1[i]); |
1493 | alloc_reg64(current,i,rs2[i]); |
1494 | alloc_reg64(current,i,rt1[i]); |
1495 | } else { |
1496 | alloc_reg(current,i,rs1[i]); |
1497 | alloc_reg(current,i,rs2[i]); |
1498 | alloc_reg(current,i,rt1[i]); |
1499 | } |
1500 | } |
1501 | else { |
1502 | alloc_reg(current,i,rt1[i]); |
1503 | if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) { |
1504 | // DADD used as move, or zeroing |
1505 | // If we have a 64-bit source, then make the target 64 bits too |
1506 | if(rs1[i]&&!((current->is32>>rs1[i])&1)) { |
1507 | if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]); |
1508 | alloc_reg64(current,i,rt1[i]); |
1509 | } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) { |
1510 | if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]); |
1511 | alloc_reg64(current,i,rt1[i]); |
1512 | } |
1513 | if(opcode2[i]>=0x2e&&rs2[i]) { |
1514 | // DSUB used as negation - 64-bit result |
1515 | // If we have a 32-bit register, extend it to 64 bits |
1516 | if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]); |
1517 | alloc_reg64(current,i,rt1[i]); |
1518 | } |
1519 | } |
1520 | } |
1521 | if(rs1[i]&&rs2[i]) { |
1522 | current->is32&=~(1LL<<rt1[i]); |
1523 | } else if(rs1[i]) { |
1524 | current->is32&=~(1LL<<rt1[i]); |
1525 | if((current->is32>>rs1[i])&1) |
1526 | current->is32|=1LL<<rt1[i]; |
1527 | } else if(rs2[i]) { |
1528 | current->is32&=~(1LL<<rt1[i]); |
1529 | if((current->is32>>rs2[i])&1) |
1530 | current->is32|=1LL<<rt1[i]; |
1531 | } else { |
1532 | current->is32|=1LL<<rt1[i]; |
1533 | } |
1534 | } |
1535 | } |
1536 | clear_const(current,rs1[i]); |
1537 | clear_const(current,rs2[i]); |
1538 | clear_const(current,rt1[i]); |
1539 | dirty_reg(current,rt1[i]); |
1540 | } |
1541 | |
1542 | static void imm16_alloc(struct regstat *current,int i) |
1543 | { |
1544 | if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); |
1545 | else lt1[i]=rs1[i]; |
1546 | if(rt1[i]) alloc_reg(current,i,rt1[i]); |
1547 | if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU |
1548 | current->is32&=~(1LL<<rt1[i]); |
1549 | if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) { |
1550 | // TODO: Could preserve the 32-bit flag if the immediate is zero |
1551 | alloc_reg64(current,i,rt1[i]); |
1552 | alloc_reg64(current,i,rs1[i]); |
1553 | } |
1554 | clear_const(current,rs1[i]); |
1555 | clear_const(current,rt1[i]); |
1556 | } |
1557 | else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU |
1558 | if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]); |
1559 | current->is32|=1LL<<rt1[i]; |
1560 | clear_const(current,rs1[i]); |
1561 | clear_const(current,rt1[i]); |
1562 | } |
1563 | else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI |
1564 | if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) { |
1565 | if(rs1[i]!=rt1[i]) { |
1566 | if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]); |
1567 | alloc_reg64(current,i,rt1[i]); |
1568 | current->is32&=~(1LL<<rt1[i]); |
1569 | } |
1570 | } |
1571 | else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits |
1572 | if(is_const(current,rs1[i])) { |
1573 | int v=get_const(current,rs1[i]); |
1574 | if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]); |
1575 | if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]); |
1576 | if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]); |
1577 | } |
1578 | else clear_const(current,rt1[i]); |
1579 | } |
1580 | else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU |
1581 | if(is_const(current,rs1[i])) { |
1582 | int v=get_const(current,rs1[i]); |
1583 | set_const(current,rt1[i],v+imm[i]); |
1584 | } |
1585 | else clear_const(current,rt1[i]); |
1586 | current->is32|=1LL<<rt1[i]; |
1587 | } |
1588 | else { |
1589 | set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI |
1590 | current->is32|=1LL<<rt1[i]; |
1591 | } |
1592 | dirty_reg(current,rt1[i]); |
1593 | } |
1594 | |
1595 | static void load_alloc(struct regstat *current,int i) |
1596 | { |
1597 | clear_const(current,rt1[i]); |
1598 | //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt? |
1599 | if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register |
1600 | if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); |
1601 | if(rt1[i]&&!((current->u>>rt1[i])&1)) { |
1602 | alloc_reg(current,i,rt1[i]); |
1603 | assert(get_reg(current->regmap,rt1[i])>=0); |
1604 | if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD |
1605 | { |
1606 | current->is32&=~(1LL<<rt1[i]); |
1607 | alloc_reg64(current,i,rt1[i]); |
1608 | } |
1609 | else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR |
1610 | { |
1611 | current->is32&=~(1LL<<rt1[i]); |
1612 | alloc_reg64(current,i,rt1[i]); |
1613 | alloc_all(current,i); |
1614 | alloc_reg64(current,i,FTEMP); |
1615 | minimum_free_regs[i]=HOST_REGS; |
1616 | } |
1617 | else current->is32|=1LL<<rt1[i]; |
1618 | dirty_reg(current,rt1[i]); |
1619 | // If using TLB, need a register for pointer to the mapping table |
1620 | if(using_tlb) alloc_reg(current,i,TLREG); |
1621 | // LWL/LWR need a temporary register for the old value |
1622 | if(opcode[i]==0x22||opcode[i]==0x26) |
1623 | { |
1624 | alloc_reg(current,i,FTEMP); |
1625 | alloc_reg_temp(current,i,-1); |
1626 | minimum_free_regs[i]=1; |
1627 | } |
1628 | } |
1629 | else |
1630 | { |
1631 | // Load to r0 or unneeded register (dummy load) |
1632 | // but we still need a register to calculate the address |
1633 | if(opcode[i]==0x22||opcode[i]==0x26) |
1634 | { |
1635 | alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary |
1636 | } |
1637 | // If using TLB, need a register for pointer to the mapping table |
1638 | if(using_tlb) alloc_reg(current,i,TLREG); |
1639 | alloc_reg_temp(current,i,-1); |
1640 | minimum_free_regs[i]=1; |
1641 | if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR |
1642 | { |
1643 | alloc_all(current,i); |
1644 | alloc_reg64(current,i,FTEMP); |
1645 | minimum_free_regs[i]=HOST_REGS; |
1646 | } |
1647 | } |
1648 | } |
1649 | |
1650 | static void store_alloc(struct regstat *current,int i) |
1651 | { |
1652 | clear_const(current,rs2[i]); |
1653 | if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary |
1654 | if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); |
1655 | alloc_reg(current,i,rs2[i]); |
1656 | if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD |
1657 | alloc_reg64(current,i,rs2[i]); |
1658 | if(rs2[i]) alloc_reg(current,i,FTEMP); |
1659 | } |
1660 | // If using TLB, need a register for pointer to the mapping table |
1661 | if(using_tlb) alloc_reg(current,i,TLREG); |
1662 | #if defined(HOST_IMM8) |
1663 | // On CPUs without 32-bit immediates we need a pointer to invalid_code |
1664 | else alloc_reg(current,i,INVCP); |
1665 | #endif |
1666 | if(opcode[i]==0x2c||opcode[i]==0x2d) { // 64-bit SDL/SDR |
1667 | alloc_reg(current,i,FTEMP); |
1668 | } |
1669 | // We need a temporary register for address generation |
1670 | alloc_reg_temp(current,i,-1); |
1671 | minimum_free_regs[i]=1; |
1672 | } |
1673 | |
1674 | static void c1ls_alloc(struct regstat *current,int i) |
1675 | { |
1676 | //clear_const(current,rs1[i]); // FIXME |
1677 | clear_const(current,rt1[i]); |
1678 | if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); |
1679 | alloc_reg(current,i,CSREG); // Status |
1680 | alloc_reg(current,i,FTEMP); |
1681 | if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1 |
1682 | alloc_reg64(current,i,FTEMP); |
1683 | } |
1684 | // If using TLB, need a register for pointer to the mapping table |
1685 | if(using_tlb) alloc_reg(current,i,TLREG); |
1686 | #if defined(HOST_IMM8) |
1687 | // On CPUs without 32-bit immediates we need a pointer to invalid_code |
1688 | else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1 |
1689 | alloc_reg(current,i,INVCP); |
1690 | #endif |
1691 | // We need a temporary register for address generation |
1692 | alloc_reg_temp(current,i,-1); |
1693 | minimum_free_regs[i]=1; |
1694 | } |
1695 | |
1696 | #ifndef multdiv_alloc |
1697 | void multdiv_alloc(struct regstat *current,int i) |
1698 | { |
1699 | // case 0x18: MULT |
1700 | // case 0x19: MULTU |
1701 | // case 0x1A: DIV |
1702 | // case 0x1B: DIVU |
1703 | // case 0x1C: DMULT |
1704 | // case 0x1D: DMULTU |
1705 | // case 0x1E: DDIV |
1706 | // case 0x1F: DDIVU |
1707 | clear_const(current,rs1[i]); |
1708 | clear_const(current,rs2[i]); |
1709 | if(rs1[i]&&rs2[i]) |
1710 | { |
1711 | if((opcode2[i]&4)==0) // 32-bit |
1712 | { |
1713 | current->u&=~(1LL<<HIREG); |
1714 | current->u&=~(1LL<<LOREG); |
1715 | alloc_reg(current,i,HIREG); |
1716 | alloc_reg(current,i,LOREG); |
1717 | alloc_reg(current,i,rs1[i]); |
1718 | alloc_reg(current,i,rs2[i]); |
1719 | current->is32|=1LL<<HIREG; |
1720 | current->is32|=1LL<<LOREG; |
1721 | dirty_reg(current,HIREG); |
1722 | dirty_reg(current,LOREG); |
1723 | } |
1724 | else // 64-bit |
1725 | { |
1726 | current->u&=~(1LL<<HIREG); |
1727 | current->u&=~(1LL<<LOREG); |
1728 | current->uu&=~(1LL<<HIREG); |
1729 | current->uu&=~(1LL<<LOREG); |
1730 | alloc_reg64(current,i,HIREG); |
ce68e3b9 |
1731 | //if(HOST_REGS>10) alloc_reg64(current,i,LOREG); //*SEB* Why commenting this line? uncommenting make SM64 freeze after title (before mario head and spinning stars) |
451ab91e |
1732 | alloc_reg64(current,i,rs1[i]); |
1733 | alloc_reg64(current,i,rs2[i]); |
1734 | alloc_all(current,i); |
1735 | current->is32&=~(1LL<<HIREG); |
1736 | current->is32&=~(1LL<<LOREG); |
1737 | dirty_reg(current,HIREG); |
1738 | dirty_reg(current,LOREG); |
1739 | minimum_free_regs[i]=HOST_REGS; |
1740 | } |
1741 | } |
1742 | else |
1743 | { |
1744 | // Multiply by zero is zero. |
1745 | // MIPS does not have a divide by zero exception. |
1746 | // The result is undefined, we return zero. |
ce68e3b9 |
1747 | alloc_reg(current,i,HIREG); |
1748 | alloc_reg(current,i,LOREG); |
1749 | current->is32|=1LL<<HIREG; |
1750 | current->is32|=1LL<<LOREG; |
1751 | dirty_reg(current,HIREG); |
1752 | dirty_reg(current,LOREG); |
451ab91e |
1753 | } |
1754 | } |
1755 | #endif |
1756 | |
1757 | static void cop0_alloc(struct regstat *current,int i) |
1758 | { |
1759 | if(opcode2[i]==0) // MFC0 |
1760 | { |
1761 | if(rt1[i]) { |
1762 | clear_const(current,rt1[i]); |
1763 | alloc_all(current,i); |
1764 | alloc_reg(current,i,rt1[i]); |
1765 | current->is32|=1LL<<rt1[i]; |
1766 | dirty_reg(current,rt1[i]); |
1767 | } |
1768 | } |
1769 | else if(opcode2[i]==4) // MTC0 |
1770 | { |
1771 | if(rs1[i]){ |
1772 | clear_const(current,rs1[i]); |
1773 | alloc_reg(current,i,rs1[i]); |
1774 | alloc_all(current,i); |
1775 | } |
1776 | else { |
1777 | alloc_all(current,i); // FIXME: Keep r0 |
1778 | current->u&=~1LL; |
1779 | alloc_reg(current,i,0); |
1780 | } |
1781 | } |
1782 | else |
1783 | { |
1784 | // TLBR/TLBWI/TLBWR/TLBP/ERET |
1785 | assert(opcode2[i]==0x10); |
1786 | alloc_all(current,i); |
1787 | } |
1788 | minimum_free_regs[i]=HOST_REGS; |
1789 | } |
1790 | |
1791 | static void cop1_alloc(struct regstat *current,int i) |
1792 | { |
1793 | alloc_reg(current,i,CSREG); // Load status |
1794 | if(opcode2[i]<3) // MFC1/DMFC1/CFC1 |
1795 | { |
1796 | assert(rt1[i]); |
1797 | clear_const(current,rt1[i]); |
1798 | if(opcode2[i]==1) { |
1799 | alloc_reg64(current,i,rt1[i]); // DMFC1 |
1800 | current->is32&=~(1LL<<rt1[i]); |
1801 | }else{ |
1802 | alloc_reg(current,i,rt1[i]); // MFC1/CFC1 |
1803 | current->is32|=1LL<<rt1[i]; |
1804 | } |
1805 | dirty_reg(current,rt1[i]); |
1806 | alloc_reg_temp(current,i,-1); |
1807 | } |
1808 | else if(opcode2[i]>3) // MTC1/DMTC1/CTC1 |
1809 | { |
1810 | if(rs1[i]){ |
1811 | clear_const(current,rs1[i]); |
1812 | if(opcode2[i]==5) |
1813 | alloc_reg64(current,i,rs1[i]); // DMTC1 |
1814 | else |
1815 | alloc_reg(current,i,rs1[i]); // MTC1/CTC1 |
1816 | alloc_reg_temp(current,i,-1); |
1817 | } |
1818 | else { |
1819 | current->u&=~1LL; |
1820 | alloc_reg(current,i,0); |
1821 | alloc_reg_temp(current,i,-1); |
1822 | } |
1823 | } |
1824 | minimum_free_regs[i]=1; |
1825 | } |
1826 | static void fconv_alloc(struct regstat *current,int i) |
1827 | { |
1828 | alloc_reg(current,i,CSREG); // Load status |
1829 | alloc_reg_temp(current,i,-1); |
1830 | minimum_free_regs[i]=1; |
1831 | } |
1832 | static void float_alloc(struct regstat *current,int i) |
1833 | { |
1834 | alloc_reg(current,i,CSREG); // Load status |
1835 | alloc_reg_temp(current,i,-1); |
1836 | minimum_free_regs[i]=1; |
1837 | } |
1838 | static void fcomp_alloc(struct regstat *current,int i) |
1839 | { |
1840 | alloc_reg(current,i,CSREG); // Load status |
1841 | alloc_reg(current,i,FSREG); // Load flags |
1842 | dirty_reg(current,FSREG); // Flag will be modified |
1843 | alloc_reg_temp(current,i,-1); |
1844 | minimum_free_regs[i]=1; |
1845 | } |
1846 | |
1847 | static void syscall_alloc(struct regstat *current,int i) |
1848 | { |
1849 | alloc_cc(current,i); |
1850 | dirty_reg(current,CCREG); |
1851 | alloc_all(current,i); |
1852 | minimum_free_regs[i]=HOST_REGS; |
1853 | current->isconst=0; |
1854 | } |
1855 | |
1856 | static void delayslot_alloc(struct regstat *current,int i) |
1857 | { |
1858 | switch(itype[i]) { |
1859 | case UJUMP: |
1860 | case CJUMP: |
1861 | case SJUMP: |
1862 | case RJUMP: |
1863 | case FJUMP: |
1864 | case SYSCALL: |
1865 | case SPAN: |
1866 | assem_debug("jump in the delay slot. this shouldn't happen.");//exit(1); |
1867 | DebugMessage(M64MSG_VERBOSE, "Disabled speculative precompilation"); |
1868 | stop_after_jal=1; |
1869 | break; |
1870 | case IMM16: |
1871 | imm16_alloc(current,i); |
1872 | break; |
1873 | case LOAD: |
1874 | case LOADLR: |
1875 | load_alloc(current,i); |
1876 | break; |
1877 | case STORE: |
1878 | case STORELR: |
1879 | store_alloc(current,i); |
1880 | break; |
1881 | case ALU: |
1882 | alu_alloc(current,i); |
1883 | break; |
1884 | case SHIFT: |
1885 | shift_alloc(current,i); |
1886 | break; |
1887 | case MULTDIV: |
1888 | multdiv_alloc(current,i); |
1889 | break; |
1890 | case SHIFTIMM: |
1891 | shiftimm_alloc(current,i); |
1892 | break; |
1893 | case MOV: |
1894 | mov_alloc(current,i); |
1895 | break; |
1896 | case COP0: |
1897 | cop0_alloc(current,i); |
1898 | break; |
1899 | case COP1: |
1900 | cop1_alloc(current,i); |
1901 | break; |
1902 | case C1LS: |
1903 | c1ls_alloc(current,i); |
1904 | break; |
1905 | case FCONV: |
1906 | fconv_alloc(current,i); |
1907 | break; |
1908 | case FLOAT: |
1909 | float_alloc(current,i); |
1910 | break; |
1911 | case FCOMP: |
1912 | fcomp_alloc(current,i); |
1913 | break; |
1914 | } |
1915 | } |
1916 | |
1917 | // Special case where a branch and delay slot span two pages in virtual memory |
1918 | static void pagespan_alloc(struct regstat *current,int i) |
1919 | { |
1920 | current->isconst=0; |
1921 | current->wasconst=0; |
1922 | regs[i].wasconst=0; |
1923 | minimum_free_regs[i]=HOST_REGS; |
1924 | alloc_all(current,i); |
1925 | alloc_cc(current,i); |
1926 | dirty_reg(current,CCREG); |
1927 | if(opcode[i]==3) // JAL |
1928 | { |
1929 | alloc_reg(current,i,31); |
1930 | dirty_reg(current,31); |
1931 | } |
1932 | if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR |
1933 | { |
1934 | alloc_reg(current,i,rs1[i]); |
1935 | if (rt1[i]!=0) { |
1936 | alloc_reg(current,i,rt1[i]); |
1937 | dirty_reg(current,rt1[i]); |
1938 | } |
1939 | } |
1940 | if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL |
1941 | { |
1942 | if(rs1[i]) alloc_reg(current,i,rs1[i]); |
1943 | if(rs2[i]) alloc_reg(current,i,rs2[i]); |
1944 | if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1)) |
1945 | { |
1946 | if(rs1[i]) alloc_reg64(current,i,rs1[i]); |
1947 | if(rs2[i]) alloc_reg64(current,i,rs2[i]); |
1948 | } |
1949 | } |
1950 | else |
1951 | if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL |
1952 | { |
1953 | if(rs1[i]) alloc_reg(current,i,rs1[i]); |
1954 | if(!((current->is32>>rs1[i])&1)) |
1955 | { |
1956 | if(rs1[i]) alloc_reg64(current,i,rs1[i]); |
1957 | } |
1958 | } |
1959 | else |
1960 | if(opcode[i]==0x11) // BC1 |
1961 | { |
1962 | alloc_reg(current,i,FSREG); |
1963 | alloc_reg(current,i,CSREG); |
1964 | } |
1965 | //else ... |
1966 | } |
1967 | |
1968 | static void add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e) |
1969 | { |
1970 | stubs[stubcount][0]=type; |
1971 | stubs[stubcount][1]=addr; |
1972 | stubs[stubcount][2]=retaddr; |
1973 | stubs[stubcount][3]=a; |
1974 | stubs[stubcount][4]=b; |
1975 | stubs[stubcount][5]=c; |
1976 | stubs[stubcount][6]=d; |
1977 | stubs[stubcount][7]=e; |
1978 | stubcount++; |
1979 | } |
1980 | |
1981 | // Write out a single register |
1982 | static void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32) |
1983 | { |
1984 | int hr; |
1985 | for(hr=0;hr<HOST_REGS;hr++) { |
1986 | if(hr!=EXCLUDE_REG) { |
1987 | if((regmap[hr]&63)==r) { |
1988 | if((dirty>>hr)&1) { |
1989 | if(regmap[hr]<64) { |
1990 | emit_storereg(r,hr); |
1991 | if((is32>>regmap[hr])&1) { |
1992 | emit_sarimm(hr,31,hr); |
1993 | emit_storereg(r|64,hr); |
1994 | } |
1995 | }else{ |
1996 | emit_storereg(r|64,hr); |
1997 | } |
1998 | } |
1999 | } |
2000 | } |
2001 | } |
2002 | } |
2003 | #if 0 |
2004 | static int mchecksum() |
2005 | { |
2006 | //if(!tracedebug) return 0; |
2007 | int i; |
2008 | int sum=0; |
2009 | for(i=0;i<2097152;i++) { |
2010 | unsigned int temp=sum; |
2011 | sum<<=1; |
2012 | sum|=(~temp)>>31; |
2013 | sum^=((u_int *)rdram)[i]; |
2014 | } |
2015 | return sum; |
2016 | } |
2017 | |
2018 | static int rchecksum() |
2019 | { |
2020 | int i; |
2021 | int sum=0; |
2022 | for(i=0;i<64;i++) |
2023 | sum^=((u_int *)reg)[i]; |
2024 | return sum; |
2025 | } |
2026 | |
2027 | static void rlist() |
2028 | { |
2029 | int i; |
2030 | DebugMessage(M64MSG_VERBOSE, "TRACE: "); |
2031 | for(i=0;i<32;i++) |
2032 | DebugMessage(M64MSG_VERBOSE, "r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]); |
2033 | DebugMessage(M64MSG_VERBOSE, "TRACE: "); |
2034 | for(i=0;i<32;i++) |
2035 | DebugMessage(M64MSG_VERBOSE, "f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i])); |
2036 | } |
2037 | |
2038 | static void enabletrace() |
2039 | { |
2040 | tracedebug=1; |
2041 | } |
2042 | |
2043 | |
2044 | static void memdebug(int i) |
2045 | { |
2046 | //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (checksum %x) lo=%8x%8x",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]); |
2047 | //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (rchecksum %x)",Count,next_interupt,rchecksum()); |
2048 | //rlist(); |
2049 | //if(tracedebug) { |
2050 | //if(Count>=-2084597794) { |
2051 | if((signed int)Count>=-2084597794&&(signed int)Count<0) { |
2052 | //if(0) { |
2053 | DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (checksum %x)",Count,next_interupt,mchecksum()); |
2054 | //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (checksum %x) Status=%x",Count,next_interupt,mchecksum(),Status); |
2055 | //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (checksum %x) hi=%8x%8x",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]); |
2056 | rlist(); |
2057 | #if NEW_DYNAREC == NEW_DYNAREC_X86 |
2058 | DebugMessage(M64MSG_VERBOSE, "TRACE: %x",(&i)[-1]); |
2059 | #endif |
2060 | #if NEW_DYNAREC == NEW_DYNAREC_ARM |
2061 | int j; |
2062 | DebugMessage(M64MSG_VERBOSE, "TRACE: %x ",(&j)[10]); |
2063 | DebugMessage(M64MSG_VERBOSE, "TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]); |
2064 | #endif |
2065 | //fflush(stdout); |
2066 | } |
2067 | //DebugMessage(M64MSG_VERBOSE, "TRACE: %x",(&i)[-1]); |
2068 | } |
2069 | #endif |
2070 | |
2071 | /* Debug: |
2072 | static void tlb_debug(u_int cause, u_int addr, u_int iaddr) |
2073 | { |
2074 | DebugMessage(M64MSG_VERBOSE, "TLB Exception: instruction=%x addr=%x cause=%x",iaddr, addr, cause); |
2075 | } |
2076 | end debug */ |
2077 | |
2078 | static void alu_assemble(int i,struct regstat *i_regs) |
2079 | { |
2080 | if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU |
2081 | if(rt1[i]) { |
2082 | signed char s1,s2,t; |
2083 | t=get_reg(i_regs->regmap,rt1[i]); |
2084 | if(t>=0) { |
2085 | s1=get_reg(i_regs->regmap,rs1[i]); |
2086 | s2=get_reg(i_regs->regmap,rs2[i]); |
2087 | if(rs1[i]&&rs2[i]) { |
2088 | assert(s1>=0); |
2089 | assert(s2>=0); |
2090 | if(opcode2[i]&2) emit_sub(s1,s2,t); |
2091 | else emit_add(s1,s2,t); |
2092 | } |
2093 | else if(rs1[i]) { |
2094 | if(s1>=0) emit_mov(s1,t); |
2095 | else emit_loadreg(rs1[i],t); |
2096 | } |
2097 | else if(rs2[i]) { |
2098 | if(s2>=0) { |
2099 | if(opcode2[i]&2) emit_neg(s2,t); |
2100 | else emit_mov(s2,t); |
2101 | } |
2102 | else { |
2103 | emit_loadreg(rs2[i],t); |
2104 | if(opcode2[i]&2) emit_neg(t,t); |
2105 | } |
2106 | } |
2107 | else emit_zeroreg(t); |
2108 | } |
2109 | } |
2110 | } |
2111 | if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU |
2112 | if(rt1[i]) { |
2113 | signed char s1l,s2l,s1h,s2h,tl,th; |
2114 | tl=get_reg(i_regs->regmap,rt1[i]); |
2115 | th=get_reg(i_regs->regmap,rt1[i]|64); |
2116 | if(tl>=0) { |
2117 | s1l=get_reg(i_regs->regmap,rs1[i]); |
2118 | s2l=get_reg(i_regs->regmap,rs2[i]); |
2119 | s1h=get_reg(i_regs->regmap,rs1[i]|64); |
2120 | s2h=get_reg(i_regs->regmap,rs2[i]|64); |
2121 | if(rs1[i]&&rs2[i]) { |
2122 | assert(s1l>=0); |
2123 | assert(s2l>=0); |
2124 | if(opcode2[i]&2) emit_subs(s1l,s2l,tl); |
2125 | else emit_adds(s1l,s2l,tl); |
2126 | if(th>=0) { |
2127 | #ifdef INVERTED_CARRY |
2128 | if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);} |
2129 | #else |
2130 | if(opcode2[i]&2) emit_sbc(s1h,s2h,th); |
2131 | #endif |
2132 | else emit_add(s1h,s2h,th); |
2133 | } |
2134 | } |
2135 | else if(rs1[i]) { |
2136 | if(s1l>=0) emit_mov(s1l,tl); |
2137 | else emit_loadreg(rs1[i],tl); |
2138 | if(th>=0) { |
2139 | if(s1h>=0) emit_mov(s1h,th); |
2140 | else emit_loadreg(rs1[i]|64,th); |
2141 | } |
2142 | } |
2143 | else if(rs2[i]) { |
2144 | if(s2l>=0) { |
2145 | if(opcode2[i]&2) emit_negs(s2l,tl); |
2146 | else emit_mov(s2l,tl); |
2147 | } |
2148 | else { |
2149 | emit_loadreg(rs2[i],tl); |
2150 | if(opcode2[i]&2) emit_negs(tl,tl); |
2151 | } |
2152 | if(th>=0) { |
2153 | #ifdef INVERTED_CARRY |
2154 | if(s2h>=0) emit_mov(s2h,th); |
2155 | else emit_loadreg(rs2[i]|64,th); |
2156 | if(opcode2[i]&2) { |
2157 | emit_adcimm(-1,th); // x86 has inverted carry flag |
2158 | emit_not(th,th); |
2159 | } |
2160 | #else |
2161 | if(opcode2[i]&2) { |
2162 | if(s2h>=0) emit_rscimm(s2h,0,th); |
2163 | else { |
2164 | emit_loadreg(rs2[i]|64,th); |
2165 | emit_rscimm(th,0,th); |
2166 | } |
2167 | }else{ |
2168 | if(s2h>=0) emit_mov(s2h,th); |
2169 | else emit_loadreg(rs2[i]|64,th); |
2170 | } |
2171 | #endif |
2172 | } |
2173 | } |
2174 | else { |
2175 | emit_zeroreg(tl); |
2176 | if(th>=0) emit_zeroreg(th); |
2177 | } |
2178 | } |
2179 | } |
2180 | } |
2181 | if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU |
2182 | if(rt1[i]) { |
2183 | signed char s1l,s1h,s2l,s2h,t; |
2184 | if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)) |
2185 | { |
2186 | t=get_reg(i_regs->regmap,rt1[i]); |
2187 | //assert(t>=0); |
2188 | if(t>=0) { |
2189 | s1l=get_reg(i_regs->regmap,rs1[i]); |
2190 | s1h=get_reg(i_regs->regmap,rs1[i]|64); |
2191 | s2l=get_reg(i_regs->regmap,rs2[i]); |
2192 | s2h=get_reg(i_regs->regmap,rs2[i]|64); |
2193 | if(rs2[i]==0) // rx<r0 |
2194 | { |
2195 | assert(s1h>=0); |
2196 | if(opcode2[i]==0x2a) // SLT |
2197 | emit_shrimm(s1h,31,t); |
2198 | else // SLTU (unsigned can not be less than zero) |
2199 | emit_zeroreg(t); |
2200 | } |
2201 | else if(rs1[i]==0) // r0<rx |
2202 | { |
2203 | assert(s2h>=0); |
2204 | if(opcode2[i]==0x2a) // SLT |
2205 | emit_set_gz64_32(s2h,s2l,t); |
2206 | else // SLTU (set if not zero) |
2207 | emit_set_nz64_32(s2h,s2l,t); |
2208 | } |
2209 | else { |
2210 | assert(s1l>=0);assert(s1h>=0); |
2211 | assert(s2l>=0);assert(s2h>=0); |
2212 | if(opcode2[i]==0x2a) // SLT |
2213 | emit_set_if_less64_32(s1h,s1l,s2h,s2l,t); |
2214 | else // SLTU |
2215 | emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t); |
2216 | } |
2217 | } |
2218 | } else { |
2219 | t=get_reg(i_regs->regmap,rt1[i]); |
2220 | //assert(t>=0); |
2221 | if(t>=0) { |
2222 | s1l=get_reg(i_regs->regmap,rs1[i]); |
2223 | s2l=get_reg(i_regs->regmap,rs2[i]); |
2224 | if(rs2[i]==0) // rx<r0 |
2225 | { |
2226 | assert(s1l>=0); |
2227 | if(opcode2[i]==0x2a) // SLT |
2228 | emit_shrimm(s1l,31,t); |
2229 | else // SLTU (unsigned can not be less than zero) |
2230 | emit_zeroreg(t); |
2231 | } |
2232 | else if(rs1[i]==0) // r0<rx |
2233 | { |
2234 | assert(s2l>=0); |
2235 | if(opcode2[i]==0x2a) // SLT |
2236 | emit_set_gz32(s2l,t); |
2237 | else // SLTU (set if not zero) |
2238 | emit_set_nz32(s2l,t); |
2239 | } |
2240 | else{ |
2241 | assert(s1l>=0);assert(s2l>=0); |
2242 | if(opcode2[i]==0x2a) // SLT |
2243 | emit_set_if_less32(s1l,s2l,t); |
2244 | else // SLTU |
2245 | emit_set_if_carry32(s1l,s2l,t); |
2246 | } |
2247 | } |
2248 | } |
2249 | } |
2250 | } |
2251 | if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR |
2252 | if(rt1[i]) { |
2253 | signed char s1l,s1h,s2l,s2h,th,tl; |
2254 | tl=get_reg(i_regs->regmap,rt1[i]); |
2255 | th=get_reg(i_regs->regmap,rt1[i]|64); |
2256 | if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0) |
2257 | { |
2258 | assert(tl>=0); |
2259 | if(tl>=0) { |
2260 | s1l=get_reg(i_regs->regmap,rs1[i]); |
2261 | s1h=get_reg(i_regs->regmap,rs1[i]|64); |
2262 | s2l=get_reg(i_regs->regmap,rs2[i]); |
2263 | s2h=get_reg(i_regs->regmap,rs2[i]|64); |
2264 | if(rs1[i]&&rs2[i]) { |
2265 | assert(s1l>=0);assert(s1h>=0); |
2266 | assert(s2l>=0);assert(s2h>=0); |
2267 | if(opcode2[i]==0x24) { // AND |
2268 | emit_and(s1l,s2l,tl); |
2269 | emit_and(s1h,s2h,th); |
2270 | } else |
2271 | if(opcode2[i]==0x25) { // OR |
2272 | emit_or(s1l,s2l,tl); |
2273 | emit_or(s1h,s2h,th); |
2274 | } else |
2275 | if(opcode2[i]==0x26) { // XOR |
2276 | emit_xor(s1l,s2l,tl); |
2277 | emit_xor(s1h,s2h,th); |
2278 | } else |
2279 | if(opcode2[i]==0x27) { // NOR |
2280 | emit_or(s1l,s2l,tl); |
2281 | emit_or(s1h,s2h,th); |
2282 | emit_not(tl,tl); |
2283 | emit_not(th,th); |
2284 | } |
2285 | } |
2286 | else |
2287 | { |
2288 | if(opcode2[i]==0x24) { // AND |
2289 | emit_zeroreg(tl); |
2290 | emit_zeroreg(th); |
2291 | } else |
2292 | if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR |
2293 | if(rs1[i]){ |
2294 | if(s1l>=0) emit_mov(s1l,tl); |
2295 | else emit_loadreg(rs1[i],tl); |
2296 | if(s1h>=0) emit_mov(s1h,th); |
2297 | else emit_loadreg(rs1[i]|64,th); |
2298 | } |
2299 | else |
2300 | if(rs2[i]){ |
2301 | if(s2l>=0) emit_mov(s2l,tl); |
2302 | else emit_loadreg(rs2[i],tl); |
2303 | if(s2h>=0) emit_mov(s2h,th); |
2304 | else emit_loadreg(rs2[i]|64,th); |
2305 | } |
2306 | else{ |
2307 | emit_zeroreg(tl); |
2308 | emit_zeroreg(th); |
2309 | } |
2310 | } else |
2311 | if(opcode2[i]==0x27) { // NOR |
2312 | if(rs1[i]){ |
2313 | if(s1l>=0) emit_not(s1l,tl); |
2314 | else{ |
2315 | emit_loadreg(rs1[i],tl); |
2316 | emit_not(tl,tl); |
2317 | } |
2318 | if(s1h>=0) emit_not(s1h,th); |
2319 | else{ |
2320 | emit_loadreg(rs1[i]|64,th); |
2321 | emit_not(th,th); |
2322 | } |
2323 | } |
2324 | else |
2325 | if(rs2[i]){ |
2326 | if(s2l>=0) emit_not(s2l,tl); |
2327 | else{ |
2328 | emit_loadreg(rs2[i],tl); |
2329 | emit_not(tl,tl); |
2330 | } |
2331 | if(s2h>=0) emit_not(s2h,th); |
2332 | else{ |
2333 | emit_loadreg(rs2[i]|64,th); |
2334 | emit_not(th,th); |
2335 | } |
2336 | } |
2337 | else { |
2338 | emit_movimm(-1,tl); |
2339 | emit_movimm(-1,th); |
2340 | } |
2341 | } |
2342 | } |
2343 | } |
2344 | } |
2345 | else |
2346 | { |
2347 | // 32 bit |
2348 | if(tl>=0) { |
2349 | s1l=get_reg(i_regs->regmap,rs1[i]); |
2350 | s2l=get_reg(i_regs->regmap,rs2[i]); |
2351 | if(rs1[i]&&rs2[i]) { |
2352 | assert(s1l>=0); |
2353 | assert(s2l>=0); |
2354 | if(opcode2[i]==0x24) { // AND |
2355 | emit_and(s1l,s2l,tl); |
2356 | } else |
2357 | if(opcode2[i]==0x25) { // OR |
2358 | emit_or(s1l,s2l,tl); |
2359 | } else |
2360 | if(opcode2[i]==0x26) { // XOR |
2361 | emit_xor(s1l,s2l,tl); |
2362 | } else |
2363 | if(opcode2[i]==0x27) { // NOR |
2364 | emit_or(s1l,s2l,tl); |
2365 | emit_not(tl,tl); |
2366 | } |
2367 | } |
2368 | else |
2369 | { |
2370 | if(opcode2[i]==0x24) { // AND |
2371 | emit_zeroreg(tl); |
2372 | } else |
2373 | if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR |
2374 | if(rs1[i]){ |
2375 | if(s1l>=0) emit_mov(s1l,tl); |
2376 | else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry? |
2377 | } |
2378 | else |
2379 | if(rs2[i]){ |
2380 | if(s2l>=0) emit_mov(s2l,tl); |
2381 | else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry? |
2382 | } |
2383 | else emit_zeroreg(tl); |
2384 | } else |
2385 | if(opcode2[i]==0x27) { // NOR |
2386 | if(rs1[i]){ |
2387 | if(s1l>=0) emit_not(s1l,tl); |
2388 | else { |
2389 | emit_loadreg(rs1[i],tl); |
2390 | emit_not(tl,tl); |
2391 | } |
2392 | } |
2393 | else |
2394 | if(rs2[i]){ |
2395 | if(s2l>=0) emit_not(s2l,tl); |
2396 | else { |
2397 | emit_loadreg(rs2[i],tl); |
2398 | emit_not(tl,tl); |
2399 | } |
2400 | } |
2401 | else emit_movimm(-1,tl); |
2402 | } |
2403 | } |
2404 | } |
2405 | } |
2406 | } |
2407 | } |
2408 | } |
2409 | |
2410 | static void imm16_assemble(int i,struct regstat *i_regs) |
2411 | { |
2412 | if (opcode[i]==0x0f) { // LUI |
2413 | if(rt1[i]) { |
2414 | signed char t; |
2415 | t=get_reg(i_regs->regmap,rt1[i]); |
2416 | //assert(t>=0); |
2417 | if(t>=0) { |
2418 | if(!((i_regs->isconst>>t)&1)) |
2419 | emit_movimm(imm[i]<<16,t); |
2420 | } |
2421 | } |
2422 | } |
2423 | if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU |
2424 | if(rt1[i]) { |
2425 | signed char s,t; |
2426 | t=get_reg(i_regs->regmap,rt1[i]); |
2427 | s=get_reg(i_regs->regmap,rs1[i]); |
2428 | if(rs1[i]) { |
2429 | //assert(t>=0); |
2430 | //assert(s>=0); |
2431 | if(t>=0) { |
2432 | if(!((i_regs->isconst>>t)&1)) { |
2433 | if(s<0) { |
2434 | if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t); |
2435 | emit_addimm(t,imm[i],t); |
2436 | }else{ |
2437 | if(!((i_regs->wasconst>>s)&1)) |
2438 | emit_addimm(s,imm[i],t); |
2439 | else |
2440 | emit_movimm(constmap[i][s]+imm[i],t); |
2441 | } |
2442 | } |
2443 | } |
2444 | } else { |
2445 | if(t>=0) { |
2446 | if(!((i_regs->isconst>>t)&1)) |
2447 | emit_movimm(imm[i],t); |
2448 | } |
2449 | } |
2450 | } |
2451 | } |
2452 | if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU |
2453 | if(rt1[i]) { |
2454 | signed char sh,sl,th,tl; |
2455 | th=get_reg(i_regs->regmap,rt1[i]|64); |
2456 | tl=get_reg(i_regs->regmap,rt1[i]); |
2457 | sh=get_reg(i_regs->regmap,rs1[i]|64); |
2458 | sl=get_reg(i_regs->regmap,rs1[i]); |
2459 | if(tl>=0) { |
2460 | if(rs1[i]) { |
2461 | assert(sh>=0); |
2462 | assert(sl>=0); |
2463 | if(th>=0) { |
2464 | emit_addimm64_32(sh,sl,imm[i],th,tl); |
2465 | } |
2466 | else { |
2467 | emit_addimm(sl,imm[i],tl); |
2468 | } |
2469 | } else { |
2470 | emit_movimm(imm[i],tl); |
2471 | if(th>=0) emit_movimm(((signed int)imm[i])>>31,th); |
2472 | } |
2473 | } |
2474 | } |
2475 | } |
2476 | else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU |
2477 | if(rt1[i]) { |
2478 | //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug |
2479 | signed char sh,sl,t; |
2480 | t=get_reg(i_regs->regmap,rt1[i]); |
2481 | sh=get_reg(i_regs->regmap,rs1[i]|64); |
2482 | sl=get_reg(i_regs->regmap,rs1[i]); |
2483 | //assert(t>=0); |
2484 | if(t>=0) { |
2485 | if(rs1[i]>0) { |
2486 | if(sh<0) assert((i_regs->was32>>rs1[i])&1); |
2487 | if(sh<0||((i_regs->was32>>rs1[i])&1)) { |
2488 | if(opcode[i]==0x0a) { // SLTI |
2489 | if(sl<0) { |
2490 | if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t); |
2491 | emit_slti32(t,imm[i],t); |
2492 | }else{ |
2493 | emit_slti32(sl,imm[i],t); |
2494 | } |
2495 | } |
2496 | else { // SLTIU |
2497 | if(sl<0) { |
2498 | if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t); |
2499 | emit_sltiu32(t,imm[i],t); |
2500 | }else{ |
2501 | emit_sltiu32(sl,imm[i],t); |
2502 | } |
2503 | } |
2504 | }else{ // 64-bit |
2505 | assert(sl>=0); |
2506 | if(opcode[i]==0x0a) // SLTI |
2507 | emit_slti64_32(sh,sl,imm[i],t); |
2508 | else // SLTIU |
2509 | emit_sltiu64_32(sh,sl,imm[i],t); |
2510 | } |
2511 | }else{ |
2512 | // SLTI(U) with r0 is just stupid, |
2513 | // nonetheless examples can be found |
2514 | if(opcode[i]==0x0a) // SLTI |
2515 | if(0<imm[i]) emit_movimm(1,t); |
2516 | else emit_zeroreg(t); |
2517 | else // SLTIU |
2518 | { |
2519 | if(imm[i]) emit_movimm(1,t); |
2520 | else emit_zeroreg(t); |
2521 | } |
2522 | } |
2523 | } |
2524 | } |
2525 | } |
2526 | else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI |
2527 | if(rt1[i]) { |
2528 | signed char sh,sl,th,tl; |
2529 | th=get_reg(i_regs->regmap,rt1[i]|64); |
2530 | tl=get_reg(i_regs->regmap,rt1[i]); |
2531 | sh=get_reg(i_regs->regmap,rs1[i]|64); |
2532 | sl=get_reg(i_regs->regmap,rs1[i]); |
2533 | if(tl>=0 && !((i_regs->isconst>>tl)&1)) { |
2534 | if(opcode[i]==0x0c) //ANDI |
2535 | { |
2536 | if(rs1[i]) { |
2537 | if(sl<0) { |
2538 | if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl); |
2539 | emit_andimm(tl,imm[i],tl); |
2540 | }else{ |
2541 | if(!((i_regs->wasconst>>sl)&1)) |
2542 | emit_andimm(sl,imm[i],tl); |
2543 | else |
2544 | emit_movimm(constmap[i][sl]&imm[i],tl); |
2545 | } |
2546 | } |
2547 | else |
2548 | emit_zeroreg(tl); |
2549 | if(th>=0) emit_zeroreg(th); |
2550 | } |
2551 | else |
2552 | { |
2553 | if(rs1[i]) { |
2554 | if(sl<0) { |
2555 | if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl); |
2556 | } |
2557 | if(th>=0) { |
2558 | if(sh<0) { |
2559 | emit_loadreg(rs1[i]|64,th); |
2560 | }else{ |
2561 | emit_mov(sh,th); |
2562 | } |
2563 | } |
2564 | if(opcode[i]==0x0d) { //ORI |
2565 | if(sl<0) { |
2566 | emit_orimm(tl,imm[i],tl); |
2567 | }else{ |
2568 | if(!((i_regs->wasconst>>sl)&1)) |
2569 | emit_orimm(sl,imm[i],tl); |
2570 | else |
2571 | emit_movimm(constmap[i][sl]|imm[i],tl); |
2572 | } |
2573 | } |
2574 | if(opcode[i]==0x0e) { //XORI |
2575 | if(sl<0) { |
2576 | emit_xorimm(tl,imm[i],tl); |
2577 | }else{ |
2578 | if(!((i_regs->wasconst>>sl)&1)) |
2579 | emit_xorimm(sl,imm[i],tl); |
2580 | else |
2581 | emit_movimm(constmap[i][sl]^imm[i],tl); |
2582 | } |
2583 | } |
2584 | } |
2585 | else { |
2586 | emit_movimm(imm[i],tl); |
2587 | if(th>=0) emit_zeroreg(th); |
2588 | } |
2589 | } |
2590 | } |
2591 | } |
2592 | } |
2593 | } |
2594 | |
2595 | static void shiftimm_assemble(int i,struct regstat *i_regs) |
2596 | { |
2597 | if(opcode2[i]<=0x3) // SLL/SRL/SRA |
2598 | { |
2599 | if(rt1[i]) { |
2600 | signed char s,t; |
2601 | t=get_reg(i_regs->regmap,rt1[i]); |
2602 | s=get_reg(i_regs->regmap,rs1[i]); |
2603 | //assert(t>=0); |
2604 | if(t>=0){ |
2605 | if(rs1[i]==0) |
2606 | { |
2607 | emit_zeroreg(t); |
2608 | } |
2609 | else |
2610 | { |
2611 | if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t); |
2612 | if(imm[i]) { |
2613 | if(opcode2[i]==0) // SLL |
2614 | { |
2615 | emit_shlimm(s<0?t:s,imm[i],t); |
2616 | } |
2617 | if(opcode2[i]==2) // SRL |
2618 | { |
2619 | emit_shrimm(s<0?t:s,imm[i],t); |
2620 | } |
2621 | if(opcode2[i]==3) // SRA |
2622 | { |
2623 | emit_sarimm(s<0?t:s,imm[i],t); |
2624 | } |
2625 | }else{ |
2626 | // Shift by zero |
2627 | if(s>=0 && s!=t) emit_mov(s,t); |
2628 | } |
2629 | } |
2630 | } |
2631 | //emit_storereg(rt1[i],t); //DEBUG |
2632 | } |
2633 | } |
2634 | if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA |
2635 | { |
2636 | if(rt1[i]) { |
2637 | signed char sh,sl,th,tl; |
2638 | th=get_reg(i_regs->regmap,rt1[i]|64); |
2639 | tl=get_reg(i_regs->regmap,rt1[i]); |
2640 | sh=get_reg(i_regs->regmap,rs1[i]|64); |
2641 | sl=get_reg(i_regs->regmap,rs1[i]); |
2642 | if(tl>=0) { |
2643 | if(rs1[i]==0) |
2644 | { |
2645 | emit_zeroreg(tl); |
2646 | if(th>=0) emit_zeroreg(th); |
2647 | } |
2648 | else |
2649 | { |
2650 | assert(sl>=0); |
2651 | assert(sh>=0); |
2652 | if(imm[i]) { |
2653 | if(opcode2[i]==0x38) // DSLL |
2654 | { |
2655 | if(th>=0) emit_shldimm(sh,sl,imm[i],th); |
2656 | emit_shlimm(sl,imm[i],tl); |
2657 | } |
2658 | if(opcode2[i]==0x3a) // DSRL |
2659 | { |
2660 | emit_shrdimm(sl,sh,imm[i],tl); |
2661 | if(th>=0) emit_shrimm(sh,imm[i],th); |
2662 | } |
2663 | if(opcode2[i]==0x3b) // DSRA |
2664 | { |
2665 | emit_shrdimm(sl,sh,imm[i],tl); |
2666 | if(th>=0) emit_sarimm(sh,imm[i],th); |
2667 | } |
2668 | }else{ |
2669 | // Shift by zero |
2670 | if(sl!=tl) emit_mov(sl,tl); |
2671 | if(th>=0&&sh!=th) emit_mov(sh,th); |
2672 | } |
2673 | } |
2674 | } |
2675 | } |
2676 | } |
2677 | if(opcode2[i]==0x3c) // DSLL32 |
2678 | { |
2679 | if(rt1[i]) { |
2680 | signed char sl,tl,th; |
2681 | tl=get_reg(i_regs->regmap,rt1[i]); |
2682 | th=get_reg(i_regs->regmap,rt1[i]|64); |
2683 | sl=get_reg(i_regs->regmap,rs1[i]); |
2684 | if(th>=0||tl>=0){ |
2685 | assert(tl>=0); |
2686 | assert(th>=0); |
2687 | assert(sl>=0); |
2688 | emit_mov(sl,th); |
2689 | emit_zeroreg(tl); |
2690 | if(imm[i]>32) |
2691 | { |
2692 | emit_shlimm(th,imm[i]&31,th); |
2693 | } |
2694 | } |
2695 | } |
2696 | } |
2697 | if(opcode2[i]==0x3e) // DSRL32 |
2698 | { |
2699 | if(rt1[i]) { |
2700 | signed char sh,tl,th; |
2701 | tl=get_reg(i_regs->regmap,rt1[i]); |
2702 | th=get_reg(i_regs->regmap,rt1[i]|64); |
2703 | sh=get_reg(i_regs->regmap,rs1[i]|64); |
2704 | if(tl>=0){ |
2705 | assert(sh>=0); |
2706 | emit_mov(sh,tl); |
2707 | if(th>=0) emit_zeroreg(th); |
2708 | if(imm[i]>32) |
2709 | { |
2710 | emit_shrimm(tl,imm[i]&31,tl); |
2711 | } |
2712 | } |
2713 | } |
2714 | } |
2715 | if(opcode2[i]==0x3f) // DSRA32 |
2716 | { |
2717 | if(rt1[i]) { |
2718 | signed char sh,tl; |
2719 | tl=get_reg(i_regs->regmap,rt1[i]); |
2720 | sh=get_reg(i_regs->regmap,rs1[i]|64); |
2721 | if(tl>=0){ |
2722 | assert(sh>=0); |
2723 | emit_mov(sh,tl); |
2724 | if(imm[i]>32) |
2725 | { |
2726 | emit_sarimm(tl,imm[i]&31,tl); |
2727 | } |
2728 | } |
2729 | } |
2730 | } |
2731 | } |
2732 | |
2733 | #ifndef shift_assemble |
2734 | void shift_assemble(int i,struct regstat *i_regs) |
2735 | { |
2736 | DebugMessage(M64MSG_ERROR, "Need shift_assemble for this architecture."); |
2737 | exit(1); |
2738 | } |
2739 | #endif |
2740 | |
2741 | static void load_assemble(int i,struct regstat *i_regs) |
2742 | { |
2743 | int s,th,tl,addr,map=-1,cache=-1; |
2744 | int offset; |
2745 | int jaddr=0; |
2746 | int memtarget,c=0; |
2747 | u_int hr,reglist=0; |
2748 | th=get_reg(i_regs->regmap,rt1[i]|64); |
2749 | tl=get_reg(i_regs->regmap,rt1[i]); |
2750 | s=get_reg(i_regs->regmap,rs1[i]); |
2751 | offset=imm[i]; |
2752 | for(hr=0;hr<HOST_REGS;hr++) { |
2753 | if(i_regs->regmap[hr]>=0) reglist|=1<<hr; |
2754 | } |
2755 | if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG); |
2756 | if(s>=0) { |
2757 | c=(i_regs->wasconst>>s)&1; |
2758 | memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000; |
2759 | if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1; |
2760 | } |
2761 | if(tl<0) tl=get_reg(i_regs->regmap,-1); |
2762 | if(offset||s<0||c) addr=tl; |
2763 | else addr=s; |
2764 | //DebugMessage(M64MSG_VERBOSE, "load_assemble: c=%d",c); |
2765 | //if(c) DebugMessage(M64MSG_VERBOSE, "load_assemble: const=%x",(int)constmap[i][s]+offset); |
2766 | assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O |
2767 | reglist&=~(1<<tl); |
2768 | if(th>=0) reglist&=~(1<<th); |
2769 | if(!using_tlb) { |
2770 | if(!c) { |
2771 | #ifdef RAM_OFFSET |
2772 | map=get_reg(i_regs->regmap,ROREG); |
2773 | if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG); |
2774 | #endif |
2775 | //#define R29_HACK 1 |
2776 | #ifdef R29_HACK |
2777 | // Strmnnrmn's speed hack |
2778 | if(rs1[i]!=29||start<0x80001000||start>=0x80800000) |
2779 | #endif |
2780 | { |
2781 | emit_cmpimm(addr,0x800000); |
2782 | jaddr=(int)out; |
2783 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
2784 | // Hint to branch predictor that the branch is unlikely to be taken |
2785 | if(rs1[i]>=28) |
2786 | emit_jno_unlikely(0); |
2787 | else |
2788 | #endif |
2789 | emit_jno(0); |
2790 | } |
2791 | } |
2792 | }else{ // using tlb |
2793 | int x=0; |
2794 | if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU |
2795 | if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU |
2796 | map=get_reg(i_regs->regmap,TLREG); |
2797 | cache=get_reg(i_regs->regmap,MMREG); |
2798 | assert(map>=0); |
2799 | reglist&=~(1<<map); |
2800 | map=do_tlb_r(addr,tl,map,cache,x,-1,-1,c,constmap[i][s]+offset); |
2801 | do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr); |
2802 | } |
2803 | int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg |
2804 | if (opcode[i]==0x20) { // LB |
2805 | if(!c||memtarget) { |
2806 | if(!dummy) { |
2807 | #ifdef HOST_IMM_ADDR32 |
2808 | if(c) |
2809 | emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl); |
2810 | else |
2811 | #endif |
2812 | { |
2813 | //emit_xorimm(addr,3,tl); |
2814 | //gen_tlb_addr_r(tl,map); |
2815 | //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl); |
2816 | int x=0; |
2817 | if(!c) emit_xorimm(addr,3,tl); |
2818 | else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset); |
2819 | emit_movsbl_indexed_tlb(x,tl,map,tl); |
2820 | } |
2821 | } |
2822 | if(jaddr) |
2823 | add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); |
2824 | } |
2825 | else |
2826 | inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); |
2827 | } |
2828 | if (opcode[i]==0x21) { // LH |
2829 | if(!c||memtarget) { |
2830 | if(!dummy) { |
2831 | #ifdef HOST_IMM_ADDR32 |
2832 | if(c) |
2833 | emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl); |
2834 | else |
2835 | #endif |
2836 | { |
2837 | int x=0; |
2838 | if(!c) emit_xorimm(addr,2,tl); |
2839 | else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset); |
2840 | //#ifdef |
2841 | //emit_movswl_indexed_tlb(x,tl,map,tl); |
2842 | //else |
2843 | if(map>=0) { |
2844 | gen_tlb_addr_r(tl,map); |
2845 | emit_movswl_indexed(x,tl,tl); |
2846 | }else{ |
2847 | #ifdef RAM_OFFSET |
2848 | emit_movswl_indexed(x,tl,tl); |
2849 | #else |
2850 | emit_movswl_indexed((int)rdram-0x80000000+x,tl,tl); |
2851 | #endif |
2852 | } |
2853 | } |
2854 | } |
2855 | if(jaddr) |
2856 | add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); |
2857 | } |
2858 | else |
2859 | inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); |
2860 | } |
2861 | if (opcode[i]==0x23) { // LW |
2862 | if(!c||memtarget) { |
2863 | if(!dummy) { |
2864 | //emit_readword_indexed((int)rdram-0x80000000,addr,tl); |
2865 | #ifdef HOST_IMM_ADDR32 |
2866 | if(c) |
2867 | emit_readword_tlb(constmap[i][s]+offset,map,tl); |
2868 | else |
2869 | #endif |
2870 | emit_readword_indexed_tlb(0,addr,map,tl); |
2871 | } |
2872 | if(jaddr) |
2873 | add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); |
2874 | } |
2875 | else |
2876 | inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); |
2877 | } |
2878 | if (opcode[i]==0x24) { // LBU |
2879 | if(!c||memtarget) { |
2880 | if(!dummy) { |
2881 | #ifdef HOST_IMM_ADDR32 |
2882 | if(c) |
2883 | emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl); |
2884 | else |
2885 | #endif |
2886 | { |
2887 | //emit_xorimm(addr,3,tl); |
2888 | //gen_tlb_addr_r(tl,map); |
2889 | //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl); |
2890 | int x=0; |
2891 | if(!c) emit_xorimm(addr,3,tl); |
2892 | else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset); |
2893 | emit_movzbl_indexed_tlb(x,tl,map,tl); |
2894 | } |
2895 | } |
2896 | if(jaddr) |
2897 | add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); |
2898 | } |
2899 | else |
2900 | inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); |
2901 | } |
2902 | if (opcode[i]==0x25) { // LHU |
2903 | if(!c||memtarget) { |
2904 | if(!dummy) { |
2905 | #ifdef HOST_IMM_ADDR32 |
2906 | if(c) |
2907 | emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl); |
2908 | else |
2909 | #endif |
2910 | { |
2911 | int x=0; |
2912 | if(!c) emit_xorimm(addr,2,tl); |
2913 | else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset); |
2914 | //#ifdef |
2915 | //emit_movzwl_indexed_tlb(x,tl,map,tl); |
2916 | //#else |
2917 | if(map>=0) { |
2918 | gen_tlb_addr_r(tl,map); |
2919 | emit_movzwl_indexed(x,tl,tl); |
2920 | }else{ |
2921 | #ifdef RAM_OFFSET |
2922 | emit_movzwl_indexed(x,tl,tl); |
2923 | #else |
2924 | emit_movzwl_indexed((int)rdram-0x80000000+x,tl,tl); |
2925 | #endif |
2926 | } |
2927 | } |
2928 | } |
2929 | if(jaddr) |
2930 | add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); |
2931 | } |
2932 | else |
2933 | inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); |
2934 | } |
2935 | if (opcode[i]==0x27) { // LWU |
2936 | assert(th>=0); |
2937 | if(!c||memtarget) { |
2938 | if(!dummy) { |
2939 | //emit_readword_indexed((int)rdram-0x80000000,addr,tl); |
2940 | #ifdef HOST_IMM_ADDR32 |
2941 | if(c) |
2942 | emit_readword_tlb(constmap[i][s]+offset,map,tl); |
2943 | else |
2944 | #endif |
2945 | emit_readword_indexed_tlb(0,addr,map,tl); |
2946 | } |
2947 | if(jaddr) |
2948 | add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); |
2949 | } |
2950 | else { |
2951 | inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); |
2952 | } |
2953 | emit_zeroreg(th); |
2954 | } |
2955 | if (opcode[i]==0x37) { // LD |
2956 | if(!c||memtarget) { |
2957 | if(!dummy) { |
2958 | //gen_tlb_addr_r(tl,map); |
2959 | //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th); |
2960 | //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl); |
2961 | #ifdef HOST_IMM_ADDR32 |
2962 | if(c) |
2963 | emit_readdword_tlb(constmap[i][s]+offset,map,th,tl); |
2964 | else |
2965 | #endif |
2966 | emit_readdword_indexed_tlb(0,addr,map,th,tl); |
2967 | } |
2968 | if(jaddr) |
2969 | add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); |
2970 | } |
2971 | else |
2972 | inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); |
2973 | } |
2974 | //emit_storereg(rt1[i],tl); // DEBUG |
2975 | //if(opcode[i]==0x23) |
2976 | //if(opcode[i]==0x24) |
2977 | //if(opcode[i]==0x23||opcode[i]==0x24) |
2978 | /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24) |
2979 | { |
2980 | //emit_pusha(); |
2981 | save_regs(0x100f); |
2982 | emit_readword((int)&last_count,ECX); |
2983 | #if NEW_DYNAREC == NEW_DYNAREC_X86 |
2984 | if(get_reg(i_regs->regmap,CCREG)<0) |
2985 | emit_loadreg(CCREG,HOST_CCREG); |
2986 | emit_add(HOST_CCREG,ECX,HOST_CCREG); |
2987 | emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG); |
2988 | emit_writeword(HOST_CCREG,(int)&Count); |
2989 | #endif |
2990 | #if NEW_DYNAREC == NEW_DYNAREC_ARM |
2991 | if(get_reg(i_regs->regmap,CCREG)<0) |
2992 | emit_loadreg(CCREG,0); |
2993 | else |
2994 | emit_mov(HOST_CCREG,0); |
2995 | emit_add(0,ECX,0); |
2996 | emit_addimm(0,2*ccadj[i],0); |
2997 | emit_writeword(0,(int)&Count); |
2998 | #endif |
2999 | emit_call((int)memdebug); |
3000 | //emit_popa(); |
3001 | restore_regs(0x100f); |
3002 | }*/ |
3003 | } |
3004 | |
3005 | #ifndef loadlr_assemble |
3006 | static void loadlr_assemble(int i,struct regstat *i_regs) |
3007 | { |
3008 | DebugMessage(M64MSG_ERROR, "Need loadlr_assemble for this architecture."); |
3009 | exit(1); |
3010 | } |
3011 | #endif |
3012 | |
3013 | static void store_assemble(int i,struct regstat *i_regs) |
3014 | { |
3015 | int s,th,tl,map=-1,cache=-1; |
3016 | int addr,temp; |
3017 | int offset; |
3018 | int jaddr=0,jaddr2,type; |
3019 | int memtarget,c=0; |
3020 | int agr=AGEN1+(i&1); |
3021 | u_int hr,reglist=0; |
3022 | th=get_reg(i_regs->regmap,rs2[i]|64); |
3023 | tl=get_reg(i_regs->regmap,rs2[i]); |
3024 | s=get_reg(i_regs->regmap,rs1[i]); |
3025 | temp=get_reg(i_regs->regmap,agr); |
3026 | if(temp<0) temp=get_reg(i_regs->regmap,-1); |
3027 | offset=imm[i]; |
3028 | if(s>=0) { |
3029 | c=(i_regs->wasconst>>s)&1; |
3030 | memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000; |
3031 | if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1; |
3032 | } |
3033 | assert(tl>=0); |
3034 | assert(temp>=0); |
3035 | for(hr=0;hr<HOST_REGS;hr++) { |
3036 | if(i_regs->regmap[hr]>=0) reglist|=1<<hr; |
3037 | } |
3038 | if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG); |
3039 | if(offset||s<0||c) addr=temp; |
3040 | else addr=s; |
3041 | if(!using_tlb) { |
3042 | #ifdef RAM_OFFSET |
3043 | map=get_reg(i_regs->regmap,ROREG); |
3044 | if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG); |
3045 | #endif |
3046 | if(!c) { |
3047 | #ifdef R29_HACK |
3048 | // Strmnnrmn's speed hack |
3049 | memtarget=1; |
3050 | if(rs1[i]!=29||start<0x80001000||start>=0x80800000) |
3051 | #endif |
3052 | emit_cmpimm(addr,0x800000); |
3053 | #ifdef DESTRUCTIVE_SHIFT |
3054 | if(s==addr) emit_mov(s,temp); |
3055 | #endif |
3056 | #ifdef R29_HACK |
3057 | if(rs1[i]!=29||start<0x80001000||start>=0x80800000) |
3058 | #endif |
3059 | { |
3060 | jaddr=(int)out; |
3061 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
3062 | // Hint to branch predictor that the branch is unlikely to be taken |
3063 | if(rs1[i]>=28) |
3064 | emit_jno_unlikely(0); |
3065 | else |
3066 | #endif |
3067 | emit_jno(0); |
3068 | } |
3069 | } |
3070 | }else{ // using tlb |
3071 | int x=0; |
3072 | if (opcode[i]==0x28) x=3; // SB |
3073 | if (opcode[i]==0x29) x=2; // SH |
3074 | map=get_reg(i_regs->regmap,TLREG); |
3075 | cache=get_reg(i_regs->regmap,MMREG); |
3076 | assert(map>=0); |
3077 | reglist&=~(1<<map); |
3078 | map=do_tlb_w(addr,temp,map,cache,x,c,constmap[i][s]+offset); |
3079 | do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr); |
3080 | } |
3081 | |
3082 | if (opcode[i]==0x28) { // SB |
3083 | if(!c||memtarget) { |
3084 | int x=0; |
3085 | if(!c) emit_xorimm(addr,3,temp); |
3086 | else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset); |
3087 | //gen_tlb_addr_w(temp,map); |
3088 | //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp); |
3089 | emit_writebyte_indexed_tlb(tl,x,temp,map,temp); |
3090 | } |
3091 | type=STOREB_STUB; |
3092 | } |
3093 | if (opcode[i]==0x29) { // SH |
3094 | if(!c||memtarget) { |
3095 | int x=0; |
3096 | if(!c) emit_xorimm(addr,2,temp); |
3097 | else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset); |
3098 | //#ifdef |
3099 | //emit_writehword_indexed_tlb(tl,x,temp,map,temp); |
3100 | //#else |
3101 | if(map>=0) { |
3102 | gen_tlb_addr_w(temp,map); |
3103 | emit_writehword_indexed(tl,x,temp); |
3104 | }else |
3105 | emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp); |
3106 | } |
3107 | type=STOREH_STUB; |
3108 | } |
3109 | if (opcode[i]==0x2B) { // SW |
3110 | if(!c||memtarget) |
3111 | //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr); |
3112 | emit_writeword_indexed_tlb(tl,0,addr,map,temp); |
3113 | type=STOREW_STUB; |
3114 | } |
3115 | if (opcode[i]==0x3F) { // SD |
3116 | if(!c||memtarget) { |
3117 | if(rs2[i]) { |
3118 | assert(th>=0); |
3119 | //emit_writeword_indexed(th,(int)rdram-0x80000000,addr); |
3120 | //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr); |
3121 | emit_writedword_indexed_tlb(th,tl,0,addr,map,temp); |
3122 | }else{ |
3123 | // Store zero |
3124 | //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp); |
3125 | //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp); |
3126 | emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp); |
3127 | } |
3128 | } |
3129 | type=STORED_STUB; |
3130 | } |
3131 | if(!using_tlb) { |
3132 | if(!c||memtarget) { |
3133 | #ifdef DESTRUCTIVE_SHIFT |
3134 | // The x86 shift operation is 'destructive'; it overwrites the |
3135 | // source register, so we need to make a copy first and use that. |
3136 | addr=temp; |
3137 | #endif |
3138 | #if defined(HOST_IMM8) |
3139 | int ir=get_reg(i_regs->regmap,INVCP); |
3140 | assert(ir>=0); |
3141 | emit_cmpmem_indexedsr12_reg(ir,addr,1); |
3142 | #else |
3143 | emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1); |
3144 | #endif |
3145 | #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT) |
3146 | emit_callne(invalidate_addr_reg[addr]); |
3147 | #else |
3148 | jaddr2=(int)out; |
3149 | emit_jne(0); |
3150 | add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0); |
3151 | #endif |
3152 | } |
3153 | } |
3154 | if(jaddr) { |
3155 | add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); |
3156 | } else if(c&&!memtarget) { |
3157 | inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist); |
3158 | } |
3159 | //if(opcode[i]==0x2B || opcode[i]==0x3F) |
3160 | //if(opcode[i]==0x2B || opcode[i]==0x28) |
3161 | //if(opcode[i]==0x2B || opcode[i]==0x29) |
3162 | //if(opcode[i]==0x2B) |
3163 | |
3164 | // Uncomment for extra debug output: |
3165 | /* |
3166 | if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F) |
3167 | { |
3168 | #if NEW_DYNAREC == NEW_DYNAREC_X86 |
3169 | emit_pusha(); |
3170 | #endif |
3171 | #if NEW_DYNAREC == NEW_DYNAREC_ARM |
3172 | save_regs(0x100f); |
3173 | #endif |
3174 | emit_readword((int)&last_count,ECX); |
3175 | #if NEW_DYNAREC == NEW_DYNAREC_X86 |
3176 | if(get_reg(i_regs->regmap,CCREG)<0) |
3177 | emit_loadreg(CCREG,HOST_CCREG); |
3178 | emit_add(HOST_CCREG,ECX,HOST_CCREG); |
3179 | emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG); |
3180 | emit_writeword(HOST_CCREG,(int)&Count); |
3181 | #endif |
3182 | #if NEW_DYNAREC == NEW_DYNAREC_ARM |
3183 | if(get_reg(i_regs->regmap,CCREG)<0) |
3184 | emit_loadreg(CCREG,0); |
3185 | else |
3186 | emit_mov(HOST_CCREG,0); |
3187 | emit_add(0,ECX,0); |
3188 | emit_addimm(0,2*ccadj[i],0); |
3189 | emit_writeword(0,(int)&Count); |
3190 | #endif |
3191 | emit_call((int)memdebug); |
3192 | #if NEW_DYNAREC == NEW_DYNAREC_X86 |
3193 | emit_popa(); |
3194 | #endif |
3195 | #if NEW_DYNAREC == NEW_DYNAREC_ARM |
3196 | restore_regs(0x100f); |
3197 | #endif |
3198 | } |
3199 | */ |
3200 | } |
3201 | |
3202 | static void storelr_assemble(int i,struct regstat *i_regs) |
3203 | { |
3204 | int s,th,tl; |
3205 | int temp; |
3206 | int temp2; |
3207 | int offset; |
3208 | int jaddr=0,jaddr2; |
3209 | int case1,case2,case3; |
3210 | int done0,done1,done2; |
3211 | int memtarget,c=0; |
3212 | int agr=AGEN1+(i&1); |
3213 | u_int hr,reglist=0; |
3214 | th=get_reg(i_regs->regmap,rs2[i]|64); |
3215 | tl=get_reg(i_regs->regmap,rs2[i]); |
3216 | s=get_reg(i_regs->regmap,rs1[i]); |
3217 | temp=get_reg(i_regs->regmap,agr); |
3218 | if(temp<0) temp=get_reg(i_regs->regmap,-1); |
3219 | offset=imm[i]; |
3220 | if(s>=0) { |
3221 | c=(i_regs->isconst>>s)&1; |
3222 | memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000; |
3223 | if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1; |
3224 | } |
3225 | assert(tl>=0); |
3226 | for(hr=0;hr<HOST_REGS;hr++) { |
3227 | if(i_regs->regmap[hr]>=0) reglist|=1<<hr; |
3228 | } |
3229 | assert(temp>=0); |
3230 | if(!using_tlb) { |
3231 | if(!c) { |
3232 | emit_cmpimm(s<0||offset?temp:s,0x800000); |
3233 | if(!offset&&s!=temp) emit_mov(s,temp); |
3234 | jaddr=(int)out; |
3235 | emit_jno(0); |
3236 | } |
3237 | else |
3238 | { |
3239 | if(!memtarget||!rs1[i]) { |
3240 | jaddr=(int)out; |
3241 | emit_jmp(0); |
3242 | } |
3243 | } |
3244 | #ifdef RAM_OFFSET |
3245 | int map=get_reg(i_regs->regmap,ROREG); |
3246 | if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG); |
3247 | gen_tlb_addr_w(temp,map); |
3248 | #else |
3249 | if((u_int)rdram!=0x80000000) |
3250 | emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp); |
3251 | #endif |
3252 | }else{ // using tlb |
3253 | int map=get_reg(i_regs->regmap,TLREG); |
3254 | int cache=get_reg(i_regs->regmap,MMREG); |
3255 | assert(map>=0); |
3256 | reglist&=~(1<<map); |
3257 | map=do_tlb_w(c||s<0||offset?temp:s,temp,map,cache,0,c,constmap[i][s]+offset); |
3258 | if(!c&&!offset&&s>=0) emit_mov(s,temp); |
3259 | do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr); |
3260 | if(!jaddr&&!memtarget) { |
3261 | jaddr=(int)out; |
3262 | emit_jmp(0); |
3263 | } |
3264 | gen_tlb_addr_w(temp,map); |
3265 | } |
3266 | |
3267 | if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR |
3268 | temp2=get_reg(i_regs->regmap,FTEMP); |
3269 | if(!rs2[i]) temp2=th=tl; |
3270 | } |
3271 | |
3272 | emit_testimm(temp,2); |
3273 | case2=(int)out; |
3274 | emit_jne(0); |
3275 | emit_testimm(temp,1); |
3276 | case1=(int)out; |
3277 | emit_jne(0); |
3278 | // 0 |
3279 | if (opcode[i]==0x2A) { // SWL |
3280 | emit_writeword_indexed(tl,0,temp); |
3281 | } |
3282 | if (opcode[i]==0x2E) { // SWR |
3283 | emit_writebyte_indexed(tl,3,temp); |
3284 | } |
3285 | if (opcode[i]==0x2C) { // SDL |
3286 | emit_writeword_indexed(th,0,temp); |
3287 | if(rs2[i]) emit_mov(tl,temp2); |
3288 | } |
3289 | if (opcode[i]==0x2D) { // SDR |
3290 | emit_writebyte_indexed(tl,3,temp); |
3291 | if(rs2[i]) emit_shldimm(th,tl,24,temp2); |
3292 | } |
3293 | done0=(int)out; |
3294 | emit_jmp(0); |
3295 | // 1 |
3296 | set_jump_target(case1,(int)out); |
3297 | if (opcode[i]==0x2A) { // SWL |
3298 | // Write 3 msb into three least significant bytes |
3299 | if(rs2[i]) emit_rorimm(tl,8,tl); |
3300 | emit_writehword_indexed(tl,-1,temp); |
3301 | if(rs2[i]) emit_rorimm(tl,16,tl); |
3302 | emit_writebyte_indexed(tl,1,temp); |
3303 | if(rs2[i]) emit_rorimm(tl,8,tl); |
3304 | } |
3305 | if (opcode[i]==0x2E) { // SWR |
3306 | // Write two lsb into two most significant bytes |
3307 | emit_writehword_indexed(tl,1,temp); |
3308 | } |
3309 | if (opcode[i]==0x2C) { // SDL |
3310 | if(rs2[i]) emit_shrdimm(tl,th,8,temp2); |
3311 | // Write 3 msb into three least significant bytes |
3312 | if(rs2[i]) emit_rorimm(th,8,th); |
3313 | emit_writehword_indexed(th,-1,temp); |
3314 | if(rs2[i]) emit_rorimm(th,16,th); |
3315 | emit_writebyte_indexed(th,1,temp); |
3316 | if(rs2[i]) emit_rorimm(th,8,th); |
3317 | } |
3318 | if (opcode[i]==0x2D) { // SDR |
3319 | if(rs2[i]) emit_shldimm(th,tl,16,temp2); |
3320 | // Write two lsb into two most significant bytes |
3321 | emit_writehword_indexed(tl,1,temp); |
3322 | } |
3323 | done1=(int)out; |
3324 | emit_jmp(0); |
3325 | // 2 |
3326 | set_jump_target(case2,(int)out); |
3327 | emit_testimm(temp,1); |
3328 | case3=(int)out; |
3329 | emit_jne(0); |
3330 | if (opcode[i]==0x2A) { // SWL |
3331 | // Write two msb into two least significant bytes |
3332 | if(rs2[i]) emit_rorimm(tl,16,tl); |
3333 | emit_writehword_indexed(tl,-2,temp); |
3334 | if(rs2[i]) emit_rorimm(tl,16,tl); |
3335 | } |
3336 | if (opcode[i]==0x2E) { // SWR |
3337 | // Write 3 lsb into three most significant bytes |
3338 | emit_writebyte_indexed(tl,-1,temp); |
3339 | if(rs2[i]) emit_rorimm(tl,8,tl); |
3340 | emit_writehword_indexed(tl,0,temp); |
3341 | if(rs2[i]) emit_rorimm(tl,24,tl); |
3342 | } |
3343 | if (opcode[i]==0x2C) { // SDL |
3344 | if(rs2[i]) emit_shrdimm(tl,th,16,temp2); |
3345 | // Write two msb into two least significant bytes |
3346 | if(rs2[i]) emit_rorimm(th,16,th); |
3347 | emit_writehword_indexed(th,-2,temp); |
3348 | if(rs2[i]) emit_rorimm(th,16,th); |
3349 | } |
3350 | if (opcode[i]==0x2D) { // SDR |
3351 | if(rs2[i]) emit_shldimm(th,tl,8,temp2); |
3352 | // Write 3 lsb into three most significant bytes |
3353 | emit_writebyte_indexed(tl,-1,temp); |
3354 | if(rs2[i]) emit_rorimm(tl,8,tl); |
3355 | emit_writehword_indexed(tl,0,temp); |
3356 | if(rs2[i]) emit_rorimm(tl,24,tl); |
3357 | } |
3358 | done2=(int)out; |
3359 | emit_jmp(0); |
3360 | // 3 |
3361 | set_jump_target(case3,(int)out); |
3362 | if (opcode[i]==0x2A) { // SWL |
3363 | // Write msb into least significant byte |
3364 | if(rs2[i]) emit_rorimm(tl,24,tl); |
3365 | emit_writebyte_indexed(tl,-3,temp); |
3366 | if(rs2[i]) emit_rorimm(tl,8,tl); |
3367 | } |
3368 | if (opcode[i]==0x2E) { // SWR |
3369 | // Write entire word |
3370 | emit_writeword_indexed(tl,-3,temp); |
3371 | } |
3372 | if (opcode[i]==0x2C) { // SDL |
3373 | if(rs2[i]) emit_shrdimm(tl,th,24,temp2); |
3374 | // Write msb into least significant byte |
3375 | if(rs2[i]) emit_rorimm(th,24,th); |
3376 | emit_writebyte_indexed(th,-3,temp); |
3377 | if(rs2[i]) emit_rorimm(th,8,th); |
3378 | } |
3379 | if (opcode[i]==0x2D) { // SDR |
3380 | if(rs2[i]) emit_mov(th,temp2); |
3381 | // Write entire word |
3382 | emit_writeword_indexed(tl,-3,temp); |
3383 | } |
3384 | set_jump_target(done0,(int)out); |
3385 | set_jump_target(done1,(int)out); |
3386 | set_jump_target(done2,(int)out); |
3387 | if (opcode[i]==0x2C) { // SDL |
3388 | emit_testimm(temp,4); |
3389 | done0=(int)out; |
3390 | emit_jne(0); |
3391 | emit_andimm(temp,~3,temp); |
3392 | emit_writeword_indexed(temp2,4,temp); |
3393 | set_jump_target(done0,(int)out); |
3394 | } |
3395 | if (opcode[i]==0x2D) { // SDR |
3396 | emit_testimm(temp,4); |
3397 | done0=(int)out; |
3398 | emit_jeq(0); |
3399 | emit_andimm(temp,~3,temp); |
3400 | emit_writeword_indexed(temp2,-4,temp); |
3401 | set_jump_target(done0,(int)out); |
3402 | } |
3403 | if(!c||!memtarget) |
3404 | add_stub(STORELR_STUB,jaddr,(int)out,0,(int)i_regs,rs2[i],ccadj[i],reglist); |
3405 | if(!using_tlb) { |
3406 | #ifdef RAM_OFFSET |
3407 | int map=get_reg(i_regs->regmap,ROREG); |
3408 | if(map<0) map=HOST_TEMPREG; |
3409 | gen_orig_addr_w(temp,map); |
3410 | #else |
3411 | emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp); |
3412 | #endif |
3413 | #if defined(HOST_IMM8) |
3414 | int ir=get_reg(i_regs->regmap,INVCP); |
3415 | assert(ir>=0); |
3416 | emit_cmpmem_indexedsr12_reg(ir,temp,1); |
3417 | #else |
3418 | emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1); |
3419 | #endif |
3420 | #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT) |
3421 | emit_callne(invalidate_addr_reg[temp]); |
3422 | #else |
3423 | jaddr2=(int)out; |
3424 | emit_jne(0); |
3425 | add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0); |
3426 | #endif |
3427 | } |
3428 | /* |
3429 | emit_pusha(); |
3430 | //save_regs(0x100f); |
3431 | emit_readword((int)&last_count,ECX); |
3432 | if(get_reg(i_regs->regmap,CCREG)<0) |
3433 | emit_loadreg(CCREG,HOST_CCREG); |
3434 | emit_add(HOST_CCREG,ECX,HOST_CCREG); |
3435 | emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG); |
3436 | emit_writeword(HOST_CCREG,(int)&Count); |
3437 | emit_call((int)memdebug); |
3438 | emit_popa(); |
3439 | //restore_regs(0x100f); |
3440 | */ |
3441 | } |
3442 | |
3443 | static void c1ls_assemble(int i,struct regstat *i_regs) |
3444 | { |
3445 | int s,th,tl; |
3446 | int temp,ar; |
3447 | int map=-1; |
3448 | int offset; |
3449 | int c=0; |
3450 | int jaddr,jaddr2=0,jaddr3,type; |
3451 | int agr=AGEN1+(i&1); |
3452 | u_int hr,reglist=0; |
3453 | th=get_reg(i_regs->regmap,FTEMP|64); |
3454 | tl=get_reg(i_regs->regmap,FTEMP); |
3455 | s=get_reg(i_regs->regmap,rs1[i]); |
3456 | temp=get_reg(i_regs->regmap,agr); |
3457 | if(temp<0) temp=get_reg(i_regs->regmap,-1); |
3458 | offset=imm[i]; |
3459 | assert(tl>=0); |
3460 | assert(rs1[i]>0); |
3461 | assert(temp>=0); |
3462 | for(hr=0;hr<HOST_REGS;hr++) { |
3463 | if(i_regs->regmap[hr]>=0) reglist|=1<<hr; |
3464 | } |
3465 | if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG); |
3466 | if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1 |
3467 | { |
3468 | // Loads use a temporary register which we need to save |
3469 | reglist|=1<<temp; |
3470 | } |
3471 | if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1 |
3472 | ar=temp; |
3473 | else // LWC1/LDC1 |
3474 | ar=tl; |
3475 | //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now |
3476 | //else c=(i_regs->wasconst>>s)&1; |
3477 | if(s>=0) c=(i_regs->wasconst>>s)&1; |
3478 | // Check cop1 unusable |
3479 | if(!cop1_usable) { |
3480 | signed char rs=get_reg(i_regs->regmap,CSREG); |
3481 | assert(rs>=0); |
3482 | emit_testimm(rs,0x20000000); |
3483 | jaddr=(int)out; |
3484 | emit_jeq(0); |
3485 | add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0); |
3486 | cop1_usable=1; |
3487 | } |
3488 | if (opcode[i]==0x39) { // SWC1 (get float address) |
3489 | emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],tl); |
3490 | } |
3491 | if (opcode[i]==0x3D) { // SDC1 (get double address) |
3492 | emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],tl); |
3493 | } |
3494 | // Generate address + offset |
3495 | if(!using_tlb) { |
3496 | #ifdef RAM_OFFSET |
3497 | if (!c||opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1 |
3498 | { |
3499 | map=get_reg(i_regs->regmap,ROREG); |
3500 | if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG); |
3501 | } |
3502 | #endif |
3503 | if(!c) |
3504 | emit_cmpimm(offset||c||s<0?ar:s,0x800000); |
3505 | } |
3506 | else |
3507 | { |
3508 | map=get_reg(i_regs->regmap,TLREG); |
3509 | int cache=get_reg(i_regs->regmap,MMREG); |
3510 | assert(map>=0); |
3511 | reglist&=~(1<<map); |
3512 | if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1 |
3513 | map=do_tlb_r(offset||c||s<0?ar:s,ar,map,cache,0,-1,-1,c,constmap[i][s]+offset); |
3514 | } |
3515 | if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1 |
3516 | map=do_tlb_w(offset||c||s<0?ar:s,ar,map,cache,0,c,constmap[i][s]+offset); |
3517 | } |
3518 | } |
3519 | if (opcode[i]==0x39) { // SWC1 (read float) |
3520 | emit_readword_indexed(0,tl,tl); |
3521 | } |
3522 | if (opcode[i]==0x3D) { // SDC1 (read double) |
3523 | emit_readword_indexed(4,tl,th); |
3524 | emit_readword_indexed(0,tl,tl); |
3525 | } |
3526 | if (opcode[i]==0x31) { // LWC1 (get target address) |
3527 | emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],temp); |
3528 | } |
3529 | if (opcode[i]==0x35) { // LDC1 (get target address) |
3530 | emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],temp); |
3531 | } |
3532 | if(!using_tlb) { |
3533 | if(!c) { |
3534 | jaddr2=(int)out; |
3535 | emit_jno(0); |
3536 | } |
3537 | else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80800000) { |
3538 | jaddr2=(int)out; |
3539 | emit_jmp(0); // inline_readstub/inline_writestub? Very rare case |
3540 | } |
3541 | #ifdef DESTRUCTIVE_SHIFT |
3542 | if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1 |
3543 | if(!offset&&!c&&s>=0) emit_mov(s,ar); |
3544 | } |
3545 | #endif |
3546 | }else{ |
3547 | if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1 |
3548 | do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2); |
3549 | } |
3550 | if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1 |
3551 | do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2); |
3552 | } |
3553 | } |
3554 | if (opcode[i]==0x31) { // LWC1 |
3555 | //if(s>=0&&!c&&!offset) emit_mov(s,tl); |
3556 | //gen_tlb_addr_r(ar,map); |
3557 | //emit_readword_indexed((int)rdram-0x80000000,tl,tl); |
3558 | #ifdef HOST_IMM_ADDR32 |
3559 | if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl); |
3560 | else |
3561 | #endif |
3562 | emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl); |
3563 | type=LOADW_STUB; |
3564 | } |
3565 | if (opcode[i]==0x35) { // LDC1 |
3566 | assert(th>=0); |
3567 | //if(s>=0&&!c&&!offset) emit_mov(s,tl); |
3568 | //gen_tlb_addr_r(ar,map); |
3569 | //emit_readword_indexed((int)rdram-0x80000000,tl,th); |
3570 | //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl); |
3571 | #ifdef HOST_IMM_ADDR32 |
3572 | if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl); |
3573 | else |
3574 | #endif |
3575 | emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl); |
3576 | type=LOADD_STUB; |
3577 | } |
3578 | if (opcode[i]==0x39) { // SWC1 |
3579 | //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp); |
3580 | emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp); |
3581 | type=STOREW_STUB; |
3582 | } |
3583 | if (opcode[i]==0x3D) { // SDC1 |
3584 | assert(th>=0); |
3585 | //emit_writeword_indexed(th,(int)rdram-0x80000000,temp); |
3586 | //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp); |
3587 | emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp); |
3588 | type=STORED_STUB; |
3589 | } |
3590 | if(!using_tlb) { |
3591 | if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1 |
3592 | #ifndef DESTRUCTIVE_SHIFT |
3593 | temp=offset||c||s<0?ar:s; |
3594 | #endif |
3595 | #if defined(HOST_IMM8) |
3596 | int ir=get_reg(i_regs->regmap,INVCP); |
3597 | assert(ir>=0); |
3598 | emit_cmpmem_indexedsr12_reg(ir,temp,1); |
3599 | #else |
3600 | emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1); |
3601 | #endif |
3602 | #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT) |
3603 | emit_callne(invalidate_addr_reg[temp]); |
3604 | #else |
3605 | jaddr3=(int)out; |
3606 | emit_jne(0); |
3607 | add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0); |
3608 | #endif |
3609 | } |
3610 | } |
3611 | if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist); |
3612 | if (opcode[i]==0x31) { // LWC1 (write float) |
3613 | emit_writeword_indexed(tl,0,temp); |
3614 | } |
3615 | if (opcode[i]==0x35) { // LDC1 (write double) |
3616 | emit_writeword_indexed(th,4,temp); |
3617 | emit_writeword_indexed(tl,0,temp); |
3618 | } |
3619 | //if(opcode[i]==0x39) |
3620 | /*if(opcode[i]==0x39||opcode[i]==0x31) |
3621 | { |
3622 | emit_pusha(); |
3623 | emit_readword((int)&last_count,ECX); |
3624 | if(get_reg(i_regs->regmap,CCREG)<0) |
3625 | emit_loadreg(CCREG,HOST_CCREG); |
3626 | emit_add(HOST_CCREG,ECX,HOST_CCREG); |
3627 | emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG); |
3628 | emit_writeword(HOST_CCREG,(int)&Count); |
3629 | emit_call((int)memdebug); |
3630 | emit_popa(); |
3631 | }*/ |
3632 | } |
3633 | |
3634 | #ifndef multdiv_assemble |
3635 | void multdiv_assemble(int i,struct regstat *i_regs) |
3636 | { |
3637 | DebugMessage(M64MSG_ERROR, "Need multdiv_assemble for this architecture."); |
3638 | exit(1); |
3639 | } |
3640 | #endif |
3641 | |
3642 | static void mov_assemble(int i,struct regstat *i_regs) |
3643 | { |
3644 | //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO |
3645 | //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO |
3646 | if(rt1[i]) { |
3647 | signed char sh,sl,th,tl; |
3648 | th=get_reg(i_regs->regmap,rt1[i]|64); |
3649 | tl=get_reg(i_regs->regmap,rt1[i]); |
3650 | //assert(tl>=0); |
3651 | if(tl>=0) { |
3652 | sh=get_reg(i_regs->regmap,rs1[i]|64); |
3653 | sl=get_reg(i_regs->regmap,rs1[i]); |
3654 | if(sl>=0) emit_mov(sl,tl); |
3655 | else emit_loadreg(rs1[i],tl); |
3656 | if(th>=0) { |
3657 | if(sh>=0) emit_mov(sh,th); |
3658 | else emit_loadreg(rs1[i]|64,th); |
3659 | } |
3660 | } |
3661 | } |
3662 | } |
3663 | |
3664 | #ifndef fconv_assemble |
3665 | void fconv_assemble(int i,struct regstat *i_regs) |
3666 | { |
3667 | DebugMessage(M64MSG_ERROR, "Need fconv_assemble for this architecture."); |
3668 | exit(1); |
3669 | } |
3670 | #endif |
3671 | |
3672 | #if 0 |
3673 | static void float_assemble(int i,struct regstat *i_regs) |
3674 | { |
3675 | DebugMessage(M64MSG_ERROR, "Need float_assemble for this architecture."); |
3676 | exit(1); |
3677 | } |
3678 | #endif |
3679 | |
3680 | static void syscall_assemble(int i,struct regstat *i_regs) |
3681 | { |
3682 | signed char ccreg=get_reg(i_regs->regmap,CCREG); |
3683 | assert(ccreg==HOST_CCREG); |
3684 | assert(!is_delayslot); |
3685 | emit_movimm(start+i*4,EAX); // Get PC |
3686 | emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle... |
3687 | emit_jmp((int)jump_syscall); |
3688 | } |
3689 | |
3690 | static void ds_assemble(int i,struct regstat *i_regs) |
3691 | { |
3692 | is_delayslot=1; |
3693 | switch(itype[i]) { |
3694 | case ALU: |
3695 | alu_assemble(i,i_regs);break; |
3696 | case IMM16: |
3697 | imm16_assemble(i,i_regs);break; |
3698 | case SHIFT: |
3699 | shift_assemble(i,i_regs);break; |
3700 | case SHIFTIMM: |
3701 | shiftimm_assemble(i,i_regs);break; |
3702 | case LOAD: |
3703 | load_assemble(i,i_regs);break; |
3704 | case LOADLR: |
3705 | loadlr_assemble(i,i_regs);break; |
3706 | case STORE: |
3707 | store_assemble(i,i_regs);break; |
3708 | case STORELR: |
3709 | storelr_assemble(i,i_regs);break; |
3710 | case COP0: |
3711 | cop0_assemble(i,i_regs);break; |
3712 | case COP1: |
3713 | cop1_assemble(i,i_regs);break; |
3714 | case C1LS: |
3715 | c1ls_assemble(i,i_regs);break; |
3716 | case FCONV: |
3717 | fconv_assemble(i,i_regs);break; |
3718 | case FLOAT: |
3719 | float_assemble(i,i_regs);break; |
3720 | case FCOMP: |
3721 | fcomp_assemble(i,i_regs);break; |
3722 | case MULTDIV: |
3723 | multdiv_assemble(i,i_regs);break; |
3724 | case MOV: |
3725 | mov_assemble(i,i_regs);break; |
3726 | case SYSCALL: |
3727 | case SPAN: |
3728 | case UJUMP: |
3729 | case RJUMP: |
3730 | case CJUMP: |
3731 | case SJUMP: |
3732 | case FJUMP: |
3733 | DebugMessage(M64MSG_VERBOSE, "Jump in the delay slot. This is probably a bug."); |
3734 | } |
3735 | is_delayslot=0; |
3736 | } |
3737 | |
3738 | // Is the branch target a valid internal jump? |
3739 | static int internal_branch(uint64_t i_is32,int addr) |
3740 | { |
3741 | if(addr&1) return 0; // Indirect (register) jump |
3742 | if(addr>=start && addr<start+slen*4-4) |
3743 | { |
3744 | int t=(addr-start)>>2; |
3745 | // Delay slots are not valid branch targets |
3746 | //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0; |
3747 | // 64 -> 32 bit transition requires a recompile |
3748 | /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32) |
3749 | { |
3750 | if(requires_32bit[t]&~i_is32) DebugMessage(M64MSG_VERBOSE, "optimizable: no"); |
3751 | else DebugMessage(M64MSG_VERBOSE, "optimizable: yes"); |
3752 | }*/ |
3753 | //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0; |
3754 | if(requires_32bit[t]&~i_is32) return 0; |
3755 | else return 1; |
3756 | } |
3757 | return 0; |
3758 | } |
3759 | |
3760 | #ifndef wb_invalidate |
3761 | static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32, |
3762 | uint64_t u,uint64_t uu) |
3763 | { |
3764 | int hr; |
3765 | for(hr=0;hr<HOST_REGS;hr++) { |
3766 | if(hr!=EXCLUDE_REG) { |
3767 | if(pre[hr]!=entry[hr]) { |
3768 | if(pre[hr]>=0) { |
3769 | if((dirty>>hr)&1) { |
3770 | if(get_reg(entry,pre[hr])<0) { |
3771 | if(pre[hr]<64) { |
3772 | if(!((u>>pre[hr])&1)) { |
3773 | emit_storereg(pre[hr],hr); |
3774 | if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) { |
3775 | emit_sarimm(hr,31,hr); |
3776 | emit_storereg(pre[hr]|64,hr); |
3777 | } |
3778 | } |
3779 | }else{ |
3780 | if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) { |
3781 | emit_storereg(pre[hr],hr); |
3782 | } |
3783 | } |
3784 | } |
3785 | } |
3786 | } |
3787 | } |
3788 | } |
3789 | } |
3790 | // Move from one register to another (no writeback) |
3791 | for(hr=0;hr<HOST_REGS;hr++) { |
3792 | if(hr!=EXCLUDE_REG) { |
3793 | if(pre[hr]!=entry[hr]) { |
3794 | if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) { |
3795 | int nr; |
3796 | if((nr=get_reg(entry,pre[hr]))>=0) { |
3797 | emit_mov(hr,nr); |
3798 | } |
3799 | } |
3800 | } |
3801 | } |
3802 | } |
3803 | } |
3804 | #endif |
3805 | |
3806 | // Load the specified registers |
3807 | // This only loads the registers given as arguments because |
3808 | // we don't want to load things that will be overwritten |
3809 | static void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2) |
3810 | { |
3811 | int hr; |
3812 | // Load 32-bit regs |
3813 | for(hr=0;hr<HOST_REGS;hr++) { |
3814 | if(hr!=EXCLUDE_REG&®map[hr]>=0) { |
3815 | if(entry[hr]!=regmap[hr]) { |
3816 | if(regmap[hr]==rs1||regmap[hr]==rs2) |
3817 | { |
3818 | if(regmap[hr]==0) { |
3819 | emit_zeroreg(hr); |
3820 | } |
3821 | else |
3822 | { |
3823 | emit_loadreg(regmap[hr],hr); |
3824 | } |
3825 | } |
3826 | } |
3827 | } |
3828 | } |
3829 | //Load 64-bit regs |
3830 | for(hr=0;hr<HOST_REGS;hr++) { |
3831 | if(hr!=EXCLUDE_REG&®map[hr]>=0) { |
3832 | if(entry[hr]!=regmap[hr]) { |
3833 | if(regmap[hr]-64==rs1||regmap[hr]-64==rs2) |
3834 | { |
3835 | assert(regmap[hr]!=64); |
3836 | if((is32>>(regmap[hr]&63))&1) { |
3837 | int lr=get_reg(regmap,regmap[hr]-64); |
3838 | if(lr>=0) |
3839 | emit_sarimm(lr,31,hr); |
3840 | else |
3841 | emit_loadreg(regmap[hr],hr); |
3842 | } |
3843 | else |
3844 | { |
3845 | emit_loadreg(regmap[hr],hr); |
3846 | } |
3847 | } |
3848 | } |
3849 | } |
3850 | } |
3851 | } |
3852 | |
3853 | // Load registers prior to the start of a loop |
3854 | // so that they are not loaded within the loop |
3855 | static void loop_preload(signed char pre[],signed char entry[]) |
3856 | { |
3857 | int hr; |
3858 | for(hr=0;hr<HOST_REGS;hr++) { |
3859 | if(hr!=EXCLUDE_REG) { |
3860 | if(pre[hr]!=entry[hr]) { |
3861 | if(entry[hr]>=0) { |
3862 | if(get_reg(pre,entry[hr])<0) { |
3863 | assem_debug("loop preload:"); |
3864 | //DebugMessage(M64MSG_VERBOSE, "loop preload: %d",hr); |
3865 | if(entry[hr]==0) { |
3866 | emit_zeroreg(hr); |
3867 | } |
3868 | else if(entry[hr]<TEMPREG) |
3869 | { |
3870 | emit_loadreg(entry[hr],hr); |
3871 | } |
3872 | else if(entry[hr]-64<TEMPREG) |
3873 | { |
3874 | emit_loadreg(entry[hr],hr); |
3875 | } |
3876 | } |
3877 | } |
3878 | } |
3879 | } |
3880 | } |
3881 | } |
3882 | |
3883 | // Generate address for load/store instruction |
3884 | static void address_generation(int i,struct regstat *i_regs,signed char entry[]) |
3885 | { |
3886 | if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) { |
3887 | int ra; |
3888 | int agr=AGEN1+(i&1); |
3889 | int mgr=MGEN1+(i&1); |
3890 | if(itype[i]==LOAD) { |
3891 | ra=get_reg(i_regs->regmap,rt1[i]); |
3892 | if(ra<0) ra=get_reg(i_regs->regmap,-1); |
3893 | assert(ra>=0); |
3894 | } |
3895 | if(itype[i]==LOADLR) { |
3896 | ra=get_reg(i_regs->regmap,FTEMP); |
3897 | } |
3898 | if(itype[i]==STORE||itype[i]==STORELR) { |
3899 | ra=get_reg(i_regs->regmap,agr); |
3900 | if(ra<0) ra=get_reg(i_regs->regmap,-1); |
3901 | } |
3902 | if(itype[i]==C1LS) { |
3903 | if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1 |
3904 | ra=get_reg(i_regs->regmap,FTEMP); |
3905 | else { // SWC1/SDC1 |
3906 | ra=get_reg(i_regs->regmap,agr); |
3907 | if(ra<0) ra=get_reg(i_regs->regmap,-1); |
3908 | } |
3909 | } |
3910 | int rs=get_reg(i_regs->regmap,rs1[i]); |
3911 | int rm=get_reg(i_regs->regmap,TLREG); |
3912 | if(ra>=0) { |
3913 | int offset=imm[i]; |
3914 | int c=(i_regs->wasconst>>rs)&1; |
3915 | if(rs1[i]==0) { |
3916 | // Using r0 as a base address |
3917 | /*if(rm>=0) { |
3918 | if(!entry||entry[rm]!=mgr) { |
3919 | generate_map_const(offset,rm); |
3920 | } // else did it in the previous cycle |
3921 | }*/ |
3922 | if(!entry||entry[ra]!=agr) { |
3923 | if (opcode[i]==0x22||opcode[i]==0x26) { |
3924 | emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR |
3925 | }else if (opcode[i]==0x1a||opcode[i]==0x1b) { |
3926 | emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR |
3927 | }else{ |
3928 | emit_movimm(offset,ra); |
3929 | } |
3930 | } // else did it in the previous cycle |
3931 | } |
3932 | else if(rs<0) { |
3933 | if(!entry||entry[ra]!=rs1[i]) |
3934 | emit_loadreg(rs1[i],ra); |
3935 | //if(!entry||entry[ra]!=rs1[i]) |
3936 | // DebugMessage(M64MSG_VERBOSE, "poor load scheduling!"); |
3937 | } |
3938 | else if(c) { |
3939 | if(rm>=0) { |
3940 | if(!entry||entry[rm]!=mgr) { |
3941 | if(itype[i]==STORE||itype[i]==STORELR||opcode[i]==0x39||opcode[i]==0x3D) { |
3942 | // Stores to memory go thru the mapper to detect self-modifying |
3943 | // code, loads don't. |
3944 | if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 || |
3945 | (unsigned int)(constmap[i][rs]+offset)<0x80800000 ) |
3946 | generate_map_const(constmap[i][rs]+offset,rm); |
3947 | }else{ |
3948 | if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000) |
3949 | generate_map_const(constmap[i][rs]+offset,rm); |
3950 | } |
3951 | } |
3952 | } |
3953 | if(rs1[i]!=rt1[i]||itype[i]!=LOAD) { |
3954 | if(!entry||entry[ra]!=agr) { |
3955 | if (opcode[i]==0x22||opcode[i]==0x26) { // LWL/LWR |
3956 | #ifdef RAM_OFFSET |
3957 | if((signed int)constmap[i][rs]+offset<(signed int)0x80800000) |
3958 | emit_movimm(((constmap[i][rs]+offset)&0xFFFFFFFC)+(int)rdram-0x80000000,ra); |
3959 | else |
3960 | #endif |
3961 | emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); |
3962 | }else if (opcode[i]==0x1a||opcode[i]==0x1b) { // LDL/LDR |
3963 | #ifdef RAM_OFFSET |
3964 | if((signed int)constmap[i][rs]+offset<(signed int)0x80800000) |
3965 | emit_movimm(((constmap[i][rs]+offset)&0xFFFFFFF8)+(int)rdram-0x80000000,ra); |
3966 | else |
3967 | #endif |
3968 | emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); |
3969 | }else{ |
3970 | #ifdef HOST_IMM_ADDR32 |
3971 | if((itype[i]!=LOAD&&opcode[i]!=0x31&&opcode[i]!=0x35) || |
3972 | (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000)) |
3973 | #endif |
3974 | #ifdef RAM_OFFSET |
3975 | if((itype[i]==LOAD||opcode[i]==0x31||opcode[i]==0x35)&&(signed int)constmap[i][rs]+offset<(signed int)0x80800000) |
3976 | emit_movimm(constmap[i][rs]+offset+(int)rdram-0x80000000,ra); |
3977 | else |
3978 | #endif |
3979 | emit_movimm(constmap[i][rs]+offset,ra); |
3980 | } |
3981 | } // else did it in the previous cycle |
3982 | } // else load_consts already did it |
3983 | } |
3984 | if(offset&&!c&&rs1[i]) { |
3985 | if(rs>=0) { |
3986 | emit_addimm(rs,offset,ra); |
3987 | }else{ |
3988 | emit_addimm(ra,offset,ra); |
3989 | } |
3990 | } |
3991 | } |
3992 | } |
3993 | // Preload constants for next instruction |
3994 | if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS) { |
3995 | int agr,ra; |
3996 | #ifndef HOST_IMM_ADDR32 |
3997 | // Mapper entry |
3998 | agr=MGEN1+((i+1)&1); |
3999 | ra=get_reg(i_regs->regmap,agr); |
4000 | if(ra>=0) { |
4001 | int rs=get_reg(regs[i+1].regmap,rs1[i+1]); |
4002 | int offset=imm[i+1]; |
4003 | int c=(regs[i+1].wasconst>>rs)&1; |
4004 | if(c) { |
4005 | if(itype[i+1]==STORE||itype[i+1]==STORELR||opcode[i+1]==0x39||opcode[i+1]==0x3D) { |
4006 | // Stores to memory go thru the mapper to detect self-modifying |
4007 | // code, loads don't. |
4008 | if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 || |
4009 | (unsigned int)(constmap[i+1][rs]+offset)<0x80800000 ) |
4010 | generate_map_const(constmap[i+1][rs]+offset,ra); |
4011 | }else{ |
4012 | if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000) |
4013 | generate_map_const(constmap[i+1][rs]+offset,ra); |
4014 | } |
4015 | } |
4016 | /*else if(rs1[i]==0) { |
4017 | generate_map_const(offset,ra); |
4018 | }*/ |
4019 | } |
4020 | #endif |
4021 | // Actual address |
4022 | agr=AGEN1+((i+1)&1); |
4023 | ra=get_reg(i_regs->regmap,agr); |
4024 | if(ra>=0) { |
4025 | int rs=get_reg(regs[i+1].regmap,rs1[i+1]); |
4026 | int offset=imm[i+1]; |
4027 | int c=(regs[i+1].wasconst>>rs)&1; |
4028 | if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) { |
4029 | if (opcode[i+1]==0x22||opcode[i+1]==0x26) { // LWL/LWR |
4030 | #ifdef RAM_OFFSET |
4031 | if((signed int)constmap[i+1][rs]+offset<(signed int)0x80800000) |
4032 | emit_movimm(((constmap[i+1][rs]+offset)&0xFFFFFFFC)+(int)rdram-0x80000000,ra); |
4033 | else |
4034 | #endif |
4035 | emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); |
4036 | }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) { // LDL/LDR |
4037 | #ifdef RAM_OFFSET |
4038 | if((signed int)constmap[i+1][rs]+offset<(signed int)0x80800000) |
4039 | emit_movimm(((constmap[i+1][rs]+offset)&0xFFFFFFF8)+(int)rdram-0x80000000,ra); |
4040 | else |
4041 | #endif |
4042 | emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); |
4043 | }else{ |
4044 | #ifdef HOST_IMM_ADDR32 |
4045 | if((itype[i+1]!=LOAD&&opcode[i+1]!=0x31&&opcode[i+1]!=0x35) || |
4046 | (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000)) |
4047 | #endif |
4048 | #ifdef RAM_OFFSET |
4049 | if((itype[i+1]==LOAD||opcode[i+1]==0x31||opcode[i+1]==0x35)&&(signed int)constmap[i+1][rs]+offset<(signed int)0x80800000) |
4050 | emit_movimm(constmap[i+1][rs]+offset+(int)rdram-0x80000000,ra); |
4051 | else |
4052 | #endif |
4053 | emit_movimm(constmap[i+1][rs]+offset,ra); |
4054 | } |
4055 | } |
4056 | else if(rs1[i+1]==0) { |
4057 | // Using r0 as a base address |
4058 | if (opcode[i+1]==0x22||opcode[i+1]==0x26) { |
4059 | emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR |
4060 | }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) { |
4061 | emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR |
4062 | }else{ |
4063 | emit_movimm(offset,ra); |
4064 | } |
4065 | } |
4066 | } |
4067 | } |
4068 | } |
4069 | |
4070 | static int get_final_value(int hr, int i, int *value) |
4071 | { |
4072 | int reg=regs[i].regmap[hr]; |
4073 | while(i<slen-1) { |
4074 | if(regs[i+1].regmap[hr]!=reg) break; |
4075 | if(!((regs[i+1].isconst>>hr)&1)) break; |
4076 | if(bt[i+1]) break; |
4077 | i++; |
4078 | } |
4079 | if(i<slen-1) { |
4080 | if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) { |
4081 | *value=constmap[i][hr]; |
4082 | return 1; |
4083 | } |
4084 | if(!bt[i+1]) { |
4085 | if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) { |
4086 | // Load in delay slot, out-of-order execution |
4087 | if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1)) |
4088 | { |
4089 | #ifdef HOST_IMM_ADDR32 |
4090 | if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0; |
4091 | #endif |
4092 | #ifdef RAM_OFFSET |
4093 | if((signed int)constmap[i][hr]+imm[i+2]<(signed int)0x80800000) |
4094 | *value=constmap[i][hr]+imm[i+2]+(int)rdram-0x80000000; |
4095 | else |
4096 | #endif |
4097 | // Precompute load address |
4098 | *value=constmap[i][hr]+imm[i+2]; |
4099 | return 1; |
4100 | } |
4101 | } |
4102 | if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg) |
4103 | { |
4104 | #ifdef HOST_IMM_ADDR32 |
4105 | if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0; |
4106 | #endif |
4107 | #ifdef RAM_OFFSET |
4108 | if((signed int)constmap[i][hr]+imm[i+1]<(signed int)0x80800000) |
4109 | *value=constmap[i][hr]+imm[i+1]+(int)rdram-0x80000000; |
4110 | else |
4111 | #endif |
4112 | // Precompute load address |
4113 | *value=constmap[i][hr]+imm[i+1]; |
4114 | //DebugMessage(M64MSG_VERBOSE, "c=%x imm=%x",(int)constmap[i][hr],imm[i+1]); |
4115 | return 1; |
4116 | } |
4117 | } |
4118 | } |
4119 | *value=constmap[i][hr]; |
4120 | //DebugMessage(M64MSG_VERBOSE, "c=%x",(int)constmap[i][hr]); |
4121 | if(i==slen-1) return 1; |
4122 | if(reg<64) { |
4123 | return !((unneeded_reg[i+1]>>reg)&1); |
4124 | }else{ |
4125 | return !((unneeded_reg_upper[i+1]>>reg)&1); |
4126 | } |
4127 | } |
4128 | |
4129 | // Load registers with known constants |
4130 | static void load_consts(signed char pre[],signed char regmap[],int is32,int i) |
4131 | { |
4132 | int hr; |
4133 | // Load 32-bit regs |
4134 | for(hr=0;hr<HOST_REGS;hr++) { |
4135 | if(hr!=EXCLUDE_REG&®map[hr]>=0) { |
4136 | //if(entry[hr]!=regmap[hr]) { |
4137 | if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) { |
4138 | if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) { |
4139 | int value; |
4140 | if(get_final_value(hr,i,&value)) { |
4141 | if(value==0) { |
4142 | emit_zeroreg(hr); |
4143 | } |
4144 | else { |
4145 | emit_movimm(value,hr); |
4146 | } |
4147 | } |
4148 | } |
4149 | } |
4150 | } |
4151 | } |
4152 | // Load 64-bit regs |
4153 | for(hr=0;hr<HOST_REGS;hr++) { |
4154 | if(hr!=EXCLUDE_REG&®map[hr]>=0) { |
4155 | //if(entry[hr]!=regmap[hr]) { |
4156 | if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) { |
4157 | if(((regs[i].isconst>>hr)&1)&®map[hr]>64) { |
4158 | if((is32>>(regmap[hr]&63))&1) { |
4159 | int lr=get_reg(regmap,regmap[hr]-64); |
4160 | assert(lr>=0); |
4161 | emit_sarimm(lr,31,hr); |
4162 | } |
4163 | else |
4164 | { |
4165 | int value; |
4166 | if(get_final_value(hr,i,&value)) { |
4167 | if(value==0) { |
4168 | emit_zeroreg(hr); |
4169 | } |
4170 | else { |
4171 | emit_movimm(value,hr); |
4172 | } |
4173 | } |
4174 | } |
4175 | } |
4176 | } |
4177 | } |
4178 | } |
4179 | } |
4180 | static void load_all_consts(signed char regmap[],int is32,u_int dirty,int i) |
4181 | { |
4182 | int hr; |
4183 | // Load 32-bit regs |
4184 | for(hr=0;hr<HOST_REGS;hr++) { |
4185 | if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) { |
4186 | if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) { |
4187 | int value=constmap[i][hr]; |
4188 | if(value==0) { |
4189 | emit_zeroreg(hr); |
4190 | } |
4191 | else { |
4192 | emit_movimm(value,hr); |
4193 | } |
4194 | } |
4195 | } |
4196 | } |
4197 | // Load 64-bit regs |
4198 | for(hr=0;hr<HOST_REGS;hr++) { |
4199 | if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) { |
4200 | if(((regs[i].isconst>>hr)&1)&®map[hr]>64) { |
4201 | if((is32>>(regmap[hr]&63))&1) { |
4202 | int lr=get_reg(regmap,regmap[hr]-64); |
4203 | assert(lr>=0); |
4204 | emit_sarimm(lr,31,hr); |
4205 | } |
4206 | else |
4207 | { |
4208 | int value=constmap[i][hr]; |
4209 | if(value==0) { |
4210 | emit_zeroreg(hr); |
4211 | } |
4212 | else { |
4213 | emit_movimm(value,hr); |
4214 | } |
4215 | } |
4216 | } |
4217 | } |
4218 | } |
4219 | } |
4220 | |
4221 | // Write out all dirty registers (except cycle count) |
4222 | static void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty) |
4223 | { |
4224 | int hr; |
4225 | for(hr=0;hr<HOST_REGS;hr++) { |
4226 | if(hr!=EXCLUDE_REG) { |
4227 | if(i_regmap[hr]>0) { |
4228 | if(i_regmap[hr]!=CCREG) { |
4229 | if((i_dirty>>hr)&1) { |
4230 | if(i_regmap[hr]<64) { |
4231 | emit_storereg(i_regmap[hr],hr); |
4232 | if( ((i_is32>>i_regmap[hr])&1) ) { |
4233 | #ifdef DESTRUCTIVE_WRITEBACK |
4234 | emit_sarimm(hr,31,hr); |
4235 | emit_storereg(i_regmap[hr]|64,hr); |
4236 | #else |
4237 | emit_sarimm(hr,31,HOST_TEMPREG); |
4238 | emit_storereg(i_regmap[hr]|64,HOST_TEMPREG); |
4239 | #endif |
4240 | } |
4241 | }else{ |
4242 | if( !((i_is32>>(i_regmap[hr]&63))&1) ) { |
4243 | emit_storereg(i_regmap[hr],hr); |
4244 | } |
4245 | } |
4246 | } |
4247 | } |
4248 | } |
4249 | } |
4250 | } |
4251 | } |
4252 | // Write out dirty registers that we need to reload (pair with load_needed_regs) |
4253 | // This writes the registers not written by store_regs_bt |
4254 | static void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr) |
4255 | { |
4256 | int hr; |
4257 | int t=(addr-start)>>2; |
4258 | for(hr=0;hr<HOST_REGS;hr++) { |
4259 | if(hr!=EXCLUDE_REG) { |
4260 | if(i_regmap[hr]>0) { |
4261 | if(i_regmap[hr]!=CCREG) { |
4262 | if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) { |
4263 | if((i_dirty>>hr)&1) { |
4264 | if(i_regmap[hr]<64) { |
4265 | emit_storereg(i_regmap[hr],hr); |
4266 | if( ((i_is32>>i_regmap[hr])&1) ) { |
4267 | #ifdef DESTRUCTIVE_WRITEBACK |
4268 | emit_sarimm(hr,31,hr); |
4269 | emit_storereg(i_regmap[hr]|64,hr); |
4270 | #else |
4271 | emit_sarimm(hr,31,HOST_TEMPREG); |
4272 | emit_storereg(i_regmap[hr]|64,HOST_TEMPREG); |
4273 | #endif |
4274 | } |
4275 | }else{ |
4276 | if( !((i_is32>>(i_regmap[hr]&63))&1) ) { |
4277 | emit_storereg(i_regmap[hr],hr); |
4278 | } |
4279 | } |
4280 | } |
4281 | } |
4282 | } |
4283 | } |
4284 | } |
4285 | } |
4286 | } |
4287 | |
4288 | // Load all registers (except cycle count) |
4289 | static void load_all_regs(signed char i_regmap[]) |
4290 | { |
4291 | int hr; |
4292 | for(hr=0;hr<HOST_REGS;hr++) { |
4293 | if(hr!=EXCLUDE_REG) { |
4294 | if(i_regmap[hr]==0) { |
4295 | emit_zeroreg(hr); |
4296 | } |
4297 | else |
4298 | if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG) |
4299 | { |
4300 | emit_loadreg(i_regmap[hr],hr); |
4301 | } |
4302 | } |
4303 | } |
4304 | } |
4305 | |
4306 | // Load all current registers also needed by next instruction |
4307 | static void load_needed_regs(signed char i_regmap[],signed char next_regmap[]) |
4308 | { |
4309 | int hr; |
4310 | for(hr=0;hr<HOST_REGS;hr++) { |
4311 | if(hr!=EXCLUDE_REG) { |
4312 | if(get_reg(next_regmap,i_regmap[hr])>=0) { |
4313 | if(i_regmap[hr]==0) { |
4314 | emit_zeroreg(hr); |
4315 | } |
4316 | else |
4317 | if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG) |
4318 | { |
4319 | emit_loadreg(i_regmap[hr],hr); |
4320 | } |
4321 | } |
4322 | } |
4323 | } |
4324 | } |
4325 | |
4326 | // Load all regs, storing cycle count if necessary |
4327 | static void load_regs_entry(int t) |
4328 | { |
4329 | int hr; |
4330 | if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG); |
4331 | else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG); |
4332 | if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) { |
4333 | emit_storereg(CCREG,HOST_CCREG); |
4334 | } |
4335 | // Load 32-bit regs |
4336 | for(hr=0;hr<HOST_REGS;hr++) { |
4337 | if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) { |
4338 | if(regs[t].regmap_entry[hr]==0) { |
4339 | emit_zeroreg(hr); |
4340 | } |
4341 | else if(regs[t].regmap_entry[hr]!=CCREG) |
4342 | { |
4343 | emit_loadreg(regs[t].regmap_entry[hr],hr); |
4344 | } |
4345 | } |
4346 | } |
4347 | // Load 64-bit regs |
4348 | for(hr=0;hr<HOST_REGS;hr++) { |
4349 | if(regs[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) { |
4350 | assert(regs[t].regmap_entry[hr]!=64); |
4351 | if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) { |
4352 | int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64); |
4353 | if(lr<0) { |
4354 | emit_loadreg(regs[t].regmap_entry[hr],hr); |
4355 | } |
4356 | else |
4357 | { |
4358 | emit_sarimm(lr,31,hr); |
4359 | } |
4360 | } |
4361 | else |
4362 | { |
4363 | emit_loadreg(regs[t].regmap_entry[hr],hr); |
4364 | } |
4365 | } |
4366 | } |
4367 | } |
4368 | |
4369 | // Store dirty registers prior to branch |
4370 | static void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr) |
4371 | { |
4372 | if(internal_branch(i_is32,addr)) |
4373 | { |
4374 | int t=(addr-start)>>2; |
4375 | int hr; |
4376 | for(hr=0;hr<HOST_REGS;hr++) { |
4377 | if(hr!=EXCLUDE_REG) { |
4378 | if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) { |
4379 | if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) { |
4380 | if((i_dirty>>hr)&1) { |
4381 | if(i_regmap[hr]<64) { |
4382 | if(!((unneeded_reg[t]>>i_regmap[hr])&1)) { |
4383 | emit_storereg(i_regmap[hr],hr); |
4384 | if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) { |
4385 | #ifdef DESTRUCTIVE_WRITEBACK |
4386 | emit_sarimm(hr,31,hr); |
4387 | emit_storereg(i_regmap[hr]|64,hr); |
4388 | #else |
4389 | emit_sarimm(hr,31,HOST_TEMPREG); |
4390 | emit_storereg(i_regmap[hr]|64,HOST_TEMPREG); |
4391 | #endif |
4392 | } |
4393 | } |
4394 | }else{ |
4395 | if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) { |
4396 | emit_storereg(i_regmap[hr],hr); |
4397 | } |
4398 | } |
4399 | } |
4400 | } |
4401 | } |
4402 | } |
4403 | } |
4404 | } |
4405 | else |
4406 | { |
4407 | // Branch out of this block, write out all dirty regs |
4408 | wb_dirtys(i_regmap,i_is32,i_dirty); |
4409 | } |
4410 | } |
4411 | |
4412 | // Load all needed registers for branch target |
4413 | static void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr) |
4414 | { |
4415 | //if(addr>=start && addr<(start+slen*4)) |
4416 | if(internal_branch(i_is32,addr)) |
4417 | { |
4418 | int t=(addr-start)>>2; |
4419 | int hr; |
4420 | // Store the cycle count before loading something else |
4421 | if(i_regmap[HOST_CCREG]!=CCREG) { |
4422 | assert(i_regmap[HOST_CCREG]==-1); |
4423 | } |
4424 | if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) { |
4425 | emit_storereg(CCREG,HOST_CCREG); |
4426 | } |
4427 | // Load 32-bit regs |
4428 | for(hr=0;hr<HOST_REGS;hr++) { |
4429 | if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) { |
4430 | #ifdef DESTRUCTIVE_WRITEBACK |
4431 | if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) { |
4432 | #else |
4433 | if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) { |
4434 | #endif |
4435 | if(regs[t].regmap_entry[hr]==0) { |
4436 | emit_zeroreg(hr); |
4437 | } |
4438 | else if(regs[t].regmap_entry[hr]!=CCREG) |
4439 | { |
4440 | emit_loadreg(regs[t].regmap_entry[hr],hr); |
4441 | } |
4442 | } |
4443 | } |
4444 | } |
4445 | //Load 64-bit regs |
4446 | for(hr=0;hr<HOST_REGS;hr++) { |
4447 | if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) { |
4448 | if(i_regmap[hr]!=regs[t].regmap_entry[hr]) { |
4449 | assert(regs[t].regmap_entry[hr]!=64); |
4450 | if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) { |
4451 | int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64); |
4452 | if(lr<0) { |
4453 | emit_loadreg(regs[t].regmap_entry[hr],hr); |
4454 | } |
4455 | else |
4456 | { |
4457 | emit_sarimm(lr,31,hr); |
4458 | } |
4459 | } |
4460 | else |
4461 | { |
4462 | emit_loadreg(regs[t].regmap_entry[hr],hr); |
4463 | } |
4464 | } |
4465 | else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) { |
4466 | int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64); |
4467 | assert(lr>=0); |
4468 | emit_sarimm(lr,31,hr); |
4469 | } |
4470 | } |
4471 | } |
4472 | } |
4473 | } |
4474 | |
4475 | static int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr) |
4476 | { |
4477 | if(addr>=start && addr<start+slen*4-4) |
4478 | { |
4479 | int t=(addr-start)>>2; |
4480 | int hr; |
4481 | if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0; |
4482 | for(hr=0;hr<HOST_REGS;hr++) |
4483 | { |
4484 | if(hr!=EXCLUDE_REG) |
4485 | { |
4486 | if(i_regmap[hr]!=regs[t].regmap_entry[hr]) |
4487 | { |
4488 | if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64) |
4489 | { |
4490 | return 0; |
4491 | } |
4492 | else |
4493 | if((i_dirty>>hr)&1) |
4494 | { |
4495 | if(i_regmap[hr]<TEMPREG) |
4496 | { |
4497 | if(!((unneeded_reg[t]>>i_regmap[hr])&1)) |
4498 | return 0; |
4499 | } |
4500 | else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64) |
4501 | { |
4502 | if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1)) |
4503 | return 0; |
4504 | } |
4505 | } |
4506 | } |
4507 | else // Same register but is it 32-bit or dirty? |
4508 | if(i_regmap[hr]>=0) |
4509 | { |
4510 | if(!((regs[t].dirty>>hr)&1)) |
4511 | { |
4512 | if((i_dirty>>hr)&1) |
4513 | { |
4514 | if(!((unneeded_reg[t]>>i_regmap[hr])&1)) |
4515 | { |
4516 | //DebugMessage(M64MSG_VERBOSE, "%x: dirty no match",addr); |
4517 | return 0; |
4518 | } |
4519 | } |
4520 | } |
4521 | if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1) |
4522 | { |
4523 | //DebugMessage(M64MSG_VERBOSE, "%x: is32 no match",addr); |
4524 | return 0; |
4525 | } |
4526 | } |
4527 | } |
4528 | } |
4529 | //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0; |
4530 | if(requires_32bit[t]&~i_is32) return 0; |
4531 | // Delay slots are not valid branch targets |
4532 | //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0; |
4533 | // Delay slots require additional processing, so do not match |
4534 | if(is_ds[t]) return 0; |
4535 | } |
4536 | else |
4537 | { |
4538 | int hr; |
4539 | for(hr=0;hr<HOST_REGS;hr++) |
4540 | { |
4541 | if(hr!=EXCLUDE_REG) |
4542 | { |
4543 | if(i_regmap[hr]>=0) |
4544 | { |
4545 | if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG) |
4546 | { |
4547 | if((i_dirty>>hr)&1) |
4548 | { |
4549 | return 0; |
4550 | } |
4551 | } |
4552 | } |
4553 | } |
4554 | } |
4555 | } |
4556 | return 1; |
4557 | } |
4558 | |
4559 | // Used when a branch jumps into the delay slot of another branch |
4560 | static void ds_assemble_entry(int i) |
4561 | { |
4562 | int t=(ba[i]-start)>>2; |
4563 | if(!instr_addr[t]) instr_addr[t]=(u_int)out; |
4564 | assem_debug("Assemble delay slot at %x",ba[i]); |
4565 | assem_debug("<->"); |
4566 | if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG) |
4567 | wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32); |
4568 | load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]); |
4569 | address_generation(t,®s[t],regs[t].regmap_entry); |
4570 | if(itype[t]==LOAD||itype[t]==LOADLR||itype[t]==STORE||itype[t]==STORELR||itype[t]==C1LS) |
4571 | load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,MMREG,ROREG); |
4572 | if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39) |
4573 | load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP); |
4574 | cop1_usable=0; |
4575 | is_delayslot=0; |
4576 | switch(itype[t]) { |
4577 | case ALU: |
4578 | alu_assemble(t,®s[t]);break; |
4579 | case IMM16: |
4580 | imm16_assemble(t,®s[t]);break; |
4581 | case SHIFT: |
4582 | shift_assemble(t,®s[t]);break; |
4583 | case SHIFTIMM: |
4584 | shiftimm_assemble(t,®s[t]);break; |
4585 | case LOAD: |
4586 | load_assemble(t,®s[t]);break; |
4587 | case LOADLR: |
4588 | loadlr_assemble(t,®s[t]);break; |
4589 | case STORE: |
4590 | store_assemble(t,®s[t]);break; |
4591 | case STORELR: |
4592 | storelr_assemble(t,®s[t]);break; |
4593 | case COP0: |
4594 | cop0_assemble(t,®s[t]);break; |
4595 | case COP1: |
4596 | cop1_assemble(t,®s[t]);break; |
4597 | case C1LS: |
4598 | c1ls_assemble(t,®s[t]);break; |
4599 | case FCONV: |
4600 | fconv_assemble(t,®s[t]);break; |
4601 | case FLOAT: |
4602 | float_assemble(t,®s[t]);break; |
4603 | case FCOMP: |
4604 | fcomp_assemble(t,®s[t]);break; |
4605 | case MULTDIV: |
4606 | multdiv_assemble(t,®s[t]);break; |
4607 | case MOV: |
4608 | mov_assemble(t,®s[t]);break; |
4609 | case SYSCALL: |
4610 | case SPAN: |
4611 | case UJUMP: |
4612 | case RJUMP: |
4613 | case CJUMP: |
4614 | case SJUMP: |
4615 | case FJUMP: |
4616 | DebugMessage(M64MSG_VERBOSE, "Jump in the delay slot. This is probably a bug."); |
4617 | } |
4618 | store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4); |
4619 | load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4); |
4620 | if(internal_branch(regs[t].is32,ba[i]+4)) |
4621 | assem_debug("branch: internal"); |
4622 | else |
4623 | assem_debug("branch: external"); |
4624 | assert(internal_branch(regs[t].is32,ba[i]+4)); |
4625 | add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4)); |
4626 | emit_jmp(0); |
4627 | } |
4628 | |
4629 | static void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert) |
4630 | { |
4631 | int count; |
4632 | int jaddr; |
4633 | int idle=0; |
4634 | if(itype[i]==RJUMP) |
4635 | { |
4636 | *adj=0; |
4637 | } |
4638 | //if(ba[i]>=start && ba[i]<(start+slen*4)) |
4639 | if(internal_branch(branch_regs[i].is32,ba[i])) |
4640 | { |
4641 | int t=(ba[i]-start)>>2; |
4642 | if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle |
4643 | else *adj=ccadj[t]; |
4644 | } |
4645 | else |
4646 | { |
4647 | *adj=0; |
4648 | } |
4649 | count=ccadj[i]; |
4650 | if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) { |
4651 | // Idle loop |
4652 | if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG); |
4653 | idle=(int)out; |
4654 | //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles |
4655 | emit_andimm(HOST_CCREG,3,HOST_CCREG); |
4656 | jaddr=(int)out; |
4657 | emit_jmp(0); |
4658 | } |
4659 | else if(*adj==0||invert) { |
4660 | emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG); |
4661 | jaddr=(int)out; |
4662 | emit_jns(0); |
4663 | } |
4664 | else |
4665 | { |
4666 | emit_cmpimm(HOST_CCREG,-CLOCK_DIVIDER*(count+2)); |
4667 | jaddr=(int)out; |
4668 | emit_jns(0); |
4669 | } |
4670 | add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0); |
4671 | } |
4672 | |
4673 | static void do_ccstub(int n) |
4674 | { |
4675 | literal_pool(256); |
4676 | assem_debug("do_ccstub %x",start+stubs[n][4]*4); |
4677 | set_jump_target(stubs[n][1],(int)out); |
4678 | int i=stubs[n][4]; |
4679 | if(stubs[n][6]==NULLDS) { |
4680 | // Delay slot instruction is nullified ("likely" branch) |
4681 | wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty); |
4682 | } |
4683 | else if(stubs[n][6]!=TAKEN) { |
4684 | wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty); |
4685 | } |
4686 | else { |
4687 | if(internal_branch(branch_regs[i].is32,ba[i])) |
4688 | wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); |
4689 | } |
4690 | if(stubs[n][5]!=-1) |
4691 | { |
4692 | // Save PC as return address |
4693 | emit_movimm(stubs[n][5],EAX); |
4694 | emit_writeword(EAX,(int)&pcaddr); |
4695 | } |
4696 | else |
4697 | { |
4698 | // Return address depends on which way the branch goes |
4699 | if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) |
4700 | { |
4701 | int s1l=get_reg(branch_regs[i].regmap,rs1[i]); |
4702 | int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64); |
4703 | int s2l=get_reg(branch_regs[i].regmap,rs2[i]); |
4704 | int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64); |
4705 | if(rs1[i]==0) |
4706 | { |
4707 | s1l=s2l;s1h=s2h; |
4708 | s2l=s2h=-1; |
4709 | } |
4710 | else if(rs2[i]==0) |
4711 | { |
4712 | s2l=s2h=-1; |
4713 | } |
4714 | if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) { |
4715 | s1h=s2h=-1; |
4716 | } |
4717 | assert(s1l>=0); |
4718 | #ifdef DESTRUCTIVE_WRITEBACK |
4719 | if(rs1[i]) { |
4720 | if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1) |
4721 | emit_loadreg(rs1[i],s1l); |
4722 | } |
4723 | else { |
4724 | if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1) |
4725 | emit_loadreg(rs2[i],s1l); |
4726 | } |
4727 | if(s2l>=0) |
4728 | if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1) |
4729 | emit_loadreg(rs2[i],s2l); |
4730 | #endif |
4731 | int hr=0; |
4732 | int addr,alt,ntaddr; |
4733 | while(hr<HOST_REGS) |
4734 | { |
4735 | if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && |
4736 | (branch_regs[i].regmap[hr]&63)!=rs1[i] && |
4737 | (branch_regs[i].regmap[hr]&63)!=rs2[i] ) |
4738 | { |
4739 | addr=hr++;break; |
4740 | } |
4741 | hr++; |
4742 | } |
4743 | while(hr<HOST_REGS) |
4744 | { |
4745 | if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && |
4746 | (branch_regs[i].regmap[hr]&63)!=rs1[i] && |
4747 | (branch_regs[i].regmap[hr]&63)!=rs2[i] ) |
4748 | { |
4749 | alt=hr++;break; |
4750 | } |
4751 | hr++; |
4752 | } |
4753 | if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register |
4754 | { |
4755 | while(hr<HOST_REGS) |
4756 | { |
4757 | if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && |
4758 | (branch_regs[i].regmap[hr]&63)!=rs1[i] && |
4759 | (branch_regs[i].regmap[hr]&63)!=rs2[i] ) |
4760 | { |
4761 | ntaddr=hr;break; |
4762 | } |
4763 | hr++; |
4764 | } |
4765 | assert(hr<HOST_REGS); |
4766 | } |
4767 | if((opcode[i]&0x2f)==4) // BEQ |
4768 | { |
4769 | #ifdef HAVE_CMOV_IMM |
4770 | if(s1h<0) { |
4771 | if(s2l>=0) emit_cmp(s1l,s2l); |
4772 | else emit_test(s1l,s1l); |
4773 | emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr); |
4774 | } |
4775 | else |
4776 | #endif |
4777 | { |
4778 | emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt); |
4779 | if(s1h>=0) { |
4780 | if(s2h>=0) emit_cmp(s1h,s2h); |
4781 | else emit_test(s1h,s1h); |
4782 | emit_cmovne_reg(alt,addr); |
4783 | } |
4784 | if(s2l>=0) emit_cmp(s1l,s2l); |
4785 | else emit_test(s1l,s1l); |
4786 | emit_cmovne_reg(alt,addr); |
4787 | } |
4788 | } |
4789 | if((opcode[i]&0x2f)==5) // BNE |
4790 | { |
4791 | #ifdef HAVE_CMOV_IMM |
4792 | if(s1h<0) { |
4793 | if(s2l>=0) emit_cmp(s1l,s2l); |
4794 | else emit_test(s1l,s1l); |
4795 | emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr); |
4796 | } |
4797 | else |
4798 | #endif |
4799 | { |
4800 | emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt); |
4801 | if(s1h>=0) { |
4802 | if(s2h>=0) emit_cmp(s1h,s2h); |
4803 | else emit_test(s1h,s1h); |
4804 | emit_cmovne_reg(alt,addr); |
4805 | } |
4806 | if(s2l>=0) emit_cmp(s1l,s2l); |
4807 | else emit_test(s1l,s1l); |
4808 | emit_cmovne_reg(alt,addr); |
4809 | } |
4810 | } |
4811 | if((opcode[i]&0x2f)==6) // BLEZ |
4812 | { |
4813 | //emit_movimm(ba[i],alt); |
4814 | //emit_movimm(start+i*4+8,addr); |
4815 | emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr); |
4816 | emit_cmpimm(s1l,1); |
4817 | if(s1h>=0) emit_mov(addr,ntaddr); |
4818 | emit_cmovl_reg(alt,addr); |
4819 | if(s1h>=0) { |
4820 | emit_test(s1h,s1h); |
4821 | emit_cmovne_reg(ntaddr,addr); |
4822 | emit_cmovs_reg(alt,addr); |
4823 | } |
4824 | } |
4825 | if((opcode[i]&0x2f)==7) // BGTZ |
4826 | { |
4827 | //emit_movimm(ba[i],addr); |
4828 | //emit_movimm(start+i*4+8,ntaddr); |
4829 | emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr); |
4830 | emit_cmpimm(s1l,1); |
4831 | if(s1h>=0) emit_mov(addr,alt); |
4832 | emit_cmovl_reg(ntaddr,addr); |
4833 | if(s1h>=0) { |
4834 | emit_test(s1h,s1h); |
4835 | emit_cmovne_reg(alt,addr); |
4836 | emit_cmovs_reg(ntaddr,addr); |
4837 | } |
4838 | } |
4839 | if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ |
4840 | { |
4841 | //emit_movimm(ba[i],alt); |
4842 | //emit_movimm(start+i*4+8,addr); |
4843 | emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr); |
4844 | if(s1h>=0) emit_test(s1h,s1h); |
4845 | else emit_test(s1l,s1l); |
4846 | emit_cmovs_reg(alt,addr); |
4847 | } |
4848 | if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ |
4849 | { |
4850 | //emit_movimm(ba[i],addr); |
4851 | //emit_movimm(start+i*4+8,alt); |
4852 | emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt); |
4853 | if(s1h>=0) emit_test(s1h,s1h); |
4854 | else emit_test(s1l,s1l); |
4855 | emit_cmovs_reg(alt,addr); |
4856 | } |
4857 | if(opcode[i]==0x11 && opcode2[i]==0x08 ) { |
4858 | if(source[i]&0x10000) // BC1T |
4859 | { |
4860 | //emit_movimm(ba[i],alt); |
4861 | //emit_movimm(start+i*4+8,addr); |
4862 | emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr); |
4863 | emit_testimm(s1l,0x800000); |
4864 | emit_cmovne_reg(alt,addr); |
4865 | } |
4866 | else // BC1F |
4867 | { |
4868 | //emit_movimm(ba[i],addr); |
4869 | //emit_movimm(start+i*4+8,alt); |
4870 | emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt); |
4871 | emit_testimm(s1l,0x800000); |
4872 | emit_cmovne_reg(alt,addr); |
4873 | } |
4874 | } |
4875 | emit_writeword(addr,(int)&pcaddr); |
4876 | } |
4877 | else |
4878 | if(itype[i]==RJUMP) |
4879 | { |
4880 | int r=get_reg(branch_regs[i].regmap,rs1[i]); |
4881 | if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) { |
4882 | r=get_reg(branch_regs[i].regmap,RTEMP); |
4883 | } |
4884 | emit_writeword(r,(int)&pcaddr); |
4885 | } |
4886 | else {DebugMessage(M64MSG_ERROR, "Unknown branch type in do_ccstub");exit(1);} |
4887 | } |
4888 | // Update cycle count |
4889 | assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1); |
4890 | if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG); |
4891 | emit_call((int)cc_interrupt); |
4892 | if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG); |
4893 | if(stubs[n][6]==TAKEN) { |
4894 | if(internal_branch(branch_regs[i].is32,ba[i])) |
4895 | load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry); |
4896 | else if(itype[i]==RJUMP) { |
4897 | if(get_reg(branch_regs[i].regmap,RTEMP)>=0) |
4898 | emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP)); |
4899 | else |
4900 | emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i])); |
4901 | } |
4902 | }else if(stubs[n][6]==NOTTAKEN) { |
4903 | if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]); |
4904 | else load_all_regs(branch_regs[i].regmap); |
4905 | }else if(stubs[n][6]==NULLDS) { |
4906 | // Delay slot instruction is nullified ("likely" branch) |
4907 | if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]); |
4908 | else load_all_regs(regs[i].regmap); |
4909 | }else{ |
4910 | load_all_regs(branch_regs[i].regmap); |
4911 | } |
4912 | emit_jmp(stubs[n][2]); // return address |
4913 | |
4914 | /* This works but uses a lot of memory... |
4915 | emit_readword((int)&last_count,ECX); |
4916 | emit_add(HOST_CCREG,ECX,EAX); |
4917 | emit_writeword(EAX,(int)&Count); |
4918 | emit_call((int)gen_interupt); |
4919 | emit_readword((int)&Count,HOST_CCREG); |
4920 | emit_readword((int)&next_interupt,EAX); |
4921 | emit_readword((int)&pending_exception,EBX); |
4922 | emit_writeword(EAX,(int)&last_count); |
4923 | emit_sub(HOST_CCREG,EAX,HOST_CCREG); |
4924 | emit_test(EBX,EBX); |
4925 | int jne_instr=(int)out; |
4926 | emit_jne(0); |
4927 | if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG); |
4928 | load_all_regs(branch_regs[i].regmap); |
4929 | emit_jmp(stubs[n][2]); // return address |
4930 | set_jump_target(jne_instr,(int)out); |
4931 | emit_readword((int)&pcaddr,EAX); |
4932 | // Call get_addr_ht instead of doing the hash table here. |
4933 | // This code is executed infrequently and takes up a lot of space |
4934 | // so smaller is better. |
4935 | emit_storereg(CCREG,HOST_CCREG); |
4936 | emit_pushreg(EAX); |
4937 | emit_call((int)get_addr_ht); |
4938 | emit_loadreg(CCREG,HOST_CCREG); |
4939 | emit_addimm(ESP,4,ESP); |
4940 | emit_jmpreg(EAX);*/ |
4941 | } |
4942 | |
4943 | static void add_to_linker(int addr,int target,int ext) |
4944 | { |
4945 | link_addr[linkcount][0]=addr; |
4946 | link_addr[linkcount][1]=target; |
4947 | link_addr[linkcount][2]=ext; |
4948 | linkcount++; |
4949 | } |
4950 | |
4951 | static void ujump_assemble(int i,struct regstat *i_regs) |
4952 | { |
4953 | #ifdef REG_PREFETCH |
4954 | signed char *i_regmap=i_regs->regmap; |
4955 | #endif |
4956 | if(i==(ba[i]-start)>>2) assem_debug("idle loop"); |
4957 | address_generation(i+1,i_regs,regs[i].regmap_entry); |
4958 | #ifdef REG_PREFETCH |
4959 | int temp=get_reg(branch_regs[i].regmap,PTEMP); |
4960 | if(rt1[i]==31&&temp>=0) |
4961 | { |
4962 | int return_address=start+i*4+8; |
4963 | if(get_reg(branch_regs[i].regmap,31)>0) |
4964 | if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp); |
4965 | } |
4966 | #endif |
4967 | ds_assemble(i+1,i_regs); |
4968 | uint64_t bc_unneeded=branch_regs[i].u; |
4969 | uint64_t bc_unneeded_upper=branch_regs[i].uu; |
4970 | bc_unneeded|=1|(1LL<<rt1[i]); |
4971 | bc_unneeded_upper|=1|(1LL<<rt1[i]); |
4972 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32, |
4973 | bc_unneeded,bc_unneeded_upper); |
4974 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG); |
4975 | if(rt1[i]==31) { |
4976 | int rt; |
4977 | unsigned int return_address; |
4978 | assert(rt1[i+1]!=31); |
4979 | assert(rt2[i+1]!=31); |
4980 | rt=get_reg(branch_regs[i].regmap,31); |
4981 | assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); |
4982 | //assert(rt>=0); |
4983 | return_address=start+i*4+8; |
4984 | if(rt>=0) { |
4985 | #ifdef USE_MINI_HT |
4986 | if(internal_branch(branch_regs[i].is32,return_address)) { |
4987 | int temp=rt+1; |
4988 | if(temp==EXCLUDE_REG||temp>=HOST_REGS|| |
4989 | branch_regs[i].regmap[temp]>=0) |
4990 | { |
4991 | temp=get_reg(branch_regs[i].regmap,-1); |
4992 | } |
4993 | #ifdef HOST_TEMPREG |
4994 | if(temp<0) temp=HOST_TEMPREG; |
4995 | #endif |
4996 | if(temp>=0) do_miniht_insert(return_address,rt,temp); |
4997 | else emit_movimm(return_address,rt); |
4998 | } |
4999 | else |
5000 | #endif |
5001 | { |
5002 | #ifdef REG_PREFETCH |
5003 | if(temp>=0) |
5004 | { |
5005 | if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp); |
5006 | } |
5007 | #endif |
5008 | emit_movimm(return_address,rt); // PC into link register |
5009 | #ifdef IMM_PREFETCH |
5010 | emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]); |
5011 | #endif |
5012 | } |
5013 | } |
5014 | } |
5015 | int cc,adj; |
5016 | cc=get_reg(branch_regs[i].regmap,CCREG); |
5017 | assert(cc==HOST_CCREG); |
5018 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); |
5019 | #ifdef REG_PREFETCH |
5020 | if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp); |
5021 | #endif |
5022 | do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0); |
5023 | if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc); |
5024 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); |
5025 | if(internal_branch(branch_regs[i].is32,ba[i])) |
5026 | assem_debug("branch: internal"); |
5027 | else |
5028 | assem_debug("branch: external"); |
5029 | if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) { |
5030 | ds_assemble_entry(i); |
5031 | } |
5032 | else { |
5033 | add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i])); |
5034 | emit_jmp(0); |
5035 | } |
5036 | } |
5037 | |
5038 | static void rjump_assemble(int i,struct regstat *i_regs) |
5039 | { |
5040 | #ifdef REG_PREFETCH |
5041 | signed char *i_regmap=i_regs->regmap; |
5042 | #endif |
5043 | int temp; |
5044 | int rs,cc; |
5045 | rs=get_reg(branch_regs[i].regmap,rs1[i]); |
5046 | assert(rs>=0); |
5047 | if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) { |
5048 | // Delay slot abuse, make a copy of the branch address register |
5049 | temp=get_reg(branch_regs[i].regmap,RTEMP); |
5050 | assert(temp>=0); |
5051 | assert(regs[i].regmap[temp]==RTEMP); |
5052 | emit_mov(rs,temp); |
5053 | rs=temp; |
5054 | } |
5055 | address_generation(i+1,i_regs,regs[i].regmap_entry); |
5056 | #ifdef REG_PREFETCH |
5057 | if(rt1[i]==31) |
5058 | { |
5059 | if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) { |
5060 | int return_address=start+i*4+8; |
5061 | if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp); |
5062 | } |
5063 | } |
5064 | #endif |
5065 | #ifdef USE_MINI_HT |
5066 | if(rs1[i]==31) { |
5067 | int rh=get_reg(regs[i].regmap,RHASH); |
5068 | if(rh>=0) do_preload_rhash(rh); |
5069 | } |
5070 | #endif |
5071 | ds_assemble(i+1,i_regs); |
5072 | uint64_t bc_unneeded=branch_regs[i].u; |
5073 | uint64_t bc_unneeded_upper=branch_regs[i].uu; |
5074 | bc_unneeded|=1|(1LL<<rt1[i]); |
5075 | bc_unneeded_upper|=1|(1LL<<rt1[i]); |
5076 | bc_unneeded&=~(1LL<<rs1[i]); |
5077 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32, |
5078 | bc_unneeded,bc_unneeded_upper); |
5079 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG); |
5080 | if(rt1[i]!=0) { |
5081 | int rt,return_address; |
5082 | assert(rt1[i+1]!=rt1[i]); |
5083 | assert(rt2[i+1]!=rt1[i]); |
5084 | rt=get_reg(branch_regs[i].regmap,rt1[i]); |
5085 | assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); |
5086 | assert(rt>=0); |
5087 | return_address=start+i*4+8; |
5088 | #ifdef REG_PREFETCH |
5089 | if(temp>=0) |
5090 | { |
5091 | if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp); |
5092 | } |
5093 | #endif |
5094 | emit_movimm(return_address,rt); // PC into link register |
5095 | #ifdef IMM_PREFETCH |
5096 | emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]); |
5097 | #endif |
5098 | } |
5099 | cc=get_reg(branch_regs[i].regmap,CCREG); |
5100 | assert(cc==HOST_CCREG); |
5101 | #ifdef USE_MINI_HT |
5102 | int rh=get_reg(branch_regs[i].regmap,RHASH); |
5103 | int ht=get_reg(branch_regs[i].regmap,RHTBL); |
5104 | if(rs1[i]==31) { |
5105 | if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh); |
5106 | do_preload_rhtbl(ht); |
5107 | do_rhash(rs,rh); |
5108 | } |
5109 | #endif |
5110 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1); |
5111 | #ifdef DESTRUCTIVE_WRITEBACK |
5112 | if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) { |
5113 | if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) { |
5114 | emit_loadreg(rs1[i],rs); |
5115 | } |
5116 | } |
5117 | #endif |
5118 | #ifdef REG_PREFETCH |
5119 | if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp); |
5120 | #endif |
5121 | #ifdef USE_MINI_HT |
5122 | if(rs1[i]==31) { |
5123 | do_miniht_load(ht,rh); |
5124 | } |
5125 | #endif |
5126 | //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN); |
5127 | //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen |
5128 | //assert(adj==0); |
5129 | emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG); |
5130 | add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0); |
5131 | emit_jns(0); |
5132 | //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1); |
5133 | #ifdef USE_MINI_HT |
5134 | if(rs1[i]==31) { |
5135 | do_miniht_jump(rs,rh,ht); |
5136 | } |
5137 | else |
5138 | #endif |
5139 | { |
5140 | //if(rs!=EAX) emit_mov(rs,EAX); |
5141 | //emit_jmp((int)jump_vaddr_eax); |
5142 | emit_jmp(jump_vaddr_reg[rs]); |
5143 | } |
5144 | /* Check hash table |
5145 | temp=!rs; |
5146 | emit_mov(rs,temp); |
5147 | emit_shrimm(rs,16,rs); |
5148 | emit_xor(temp,rs,rs); |
5149 | emit_movzwl_reg(rs,rs); |
5150 | emit_shlimm(rs,4,rs); |
5151 | emit_cmpmem_indexed((int)hash_table,rs,temp); |
5152 | emit_jne((int)out+14); |
5153 | emit_readword_indexed((int)hash_table+4,rs,rs); |
5154 | emit_jmpreg(rs); |
5155 | emit_cmpmem_indexed((int)hash_table+8,rs,temp); |
5156 | emit_addimm_no_flags(8,rs); |
5157 | emit_jeq((int)out-17); |
5158 | // No hit on hash table, call compiler |
5159 | emit_pushreg(temp); |
5160 | //DEBUG > |
5161 | #ifdef DEBUG_CYCLE_COUNT |
5162 | emit_readword((int)&last_count,ECX); |
5163 | emit_add(HOST_CCREG,ECX,HOST_CCREG); |
5164 | emit_readword((int)&next_interupt,ECX); |
5165 | emit_writeword(HOST_CCREG,(int)&Count); |
5166 | emit_sub(HOST_CCREG,ECX,HOST_CCREG); |
5167 | emit_writeword(ECX,(int)&last_count); |
5168 | #endif |
5169 | //DEBUG < |
5170 | emit_storereg(CCREG,HOST_CCREG); |
5171 | emit_call((int)get_addr); |
5172 | emit_loadreg(CCREG,HOST_CCREG); |
5173 | emit_addimm(ESP,4,ESP); |
5174 | emit_jmpreg(EAX);*/ |
5175 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
5176 | if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13); |
5177 | #endif |
5178 | } |
5179 | |
5180 | static void cjump_assemble(int i,struct regstat *i_regs) |
5181 | { |
5182 | signed char *i_regmap=i_regs->regmap; |
5183 | int cc; |
5184 | int match; |
5185 | match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); |
5186 | assem_debug("match=%d",match); |
5187 | int s1h,s1l,s2h,s2l; |
5188 | int prev_cop1_usable=cop1_usable; |
5189 | int unconditional=0,nop=0; |
5190 | int only32=0; |
5191 | int invert=0; |
5192 | int internal=internal_branch(branch_regs[i].is32,ba[i]); |
5193 | if(i==(ba[i]-start)>>2) assem_debug("idle loop"); |
5194 | if(!match) invert=1; |
5195 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
5196 | if(i>(ba[i]-start)>>2) invert=1; |
5197 | #endif |
5198 | |
5199 | if(ooo[i]) { |
5200 | s1l=get_reg(branch_regs[i].regmap,rs1[i]); |
5201 | s1h=get_reg(branch_regs[i].regmap,rs1[i]|64); |
5202 | s2l=get_reg(branch_regs[i].regmap,rs2[i]); |
5203 | s2h=get_reg(branch_regs[i].regmap,rs2[i]|64); |
5204 | } |
5205 | else { |
5206 | s1l=get_reg(i_regmap,rs1[i]); |
5207 | s1h=get_reg(i_regmap,rs1[i]|64); |
5208 | s2l=get_reg(i_regmap,rs2[i]); |
5209 | s2h=get_reg(i_regmap,rs2[i]|64); |
5210 | } |
5211 | if(rs1[i]==0&&rs2[i]==0) |
5212 | { |
5213 | if(opcode[i]&1) nop=1; |
5214 | else unconditional=1; |
5215 | //assert(opcode[i]!=5); |
5216 | //assert(opcode[i]!=7); |
5217 | //assert(opcode[i]!=0x15); |
5218 | //assert(opcode[i]!=0x17); |
5219 | } |
5220 | else if(rs1[i]==0) |
5221 | { |
5222 | s1l=s2l;s1h=s2h; |
5223 | s2l=s2h=-1; |
5224 | only32=(regs[i].was32>>rs2[i])&1; |
5225 | } |
5226 | else if(rs2[i]==0) |
5227 | { |
5228 | s2l=s2h=-1; |
5229 | only32=(regs[i].was32>>rs1[i])&1; |
5230 | } |
5231 | else { |
5232 | only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1; |
5233 | } |
5234 | |
5235 | if(ooo[i]) { |
5236 | // Out of order execution (delay slot first) |
5237 | //DebugMessage(M64MSG_VERBOSE, "OOOE"); |
5238 | address_generation(i+1,i_regs,regs[i].regmap_entry); |
5239 | ds_assemble(i+1,i_regs); |
5240 | int adj; |
5241 | uint64_t bc_unneeded=branch_regs[i].u; |
5242 | uint64_t bc_unneeded_upper=branch_regs[i].uu; |
5243 | bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i])); |
5244 | bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i])); |
5245 | bc_unneeded|=1; |
5246 | bc_unneeded_upper|=1; |
5247 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32, |
5248 | bc_unneeded,bc_unneeded_upper); |
5249 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]); |
5250 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG); |
5251 | cc=get_reg(branch_regs[i].regmap,CCREG); |
5252 | assert(cc==HOST_CCREG); |
5253 | if(unconditional) |
5254 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); |
5255 | //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional); |
5256 | //assem_debug("cycle count (adj)"); |
5257 | if(unconditional) { |
5258 | do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0); |
5259 | if(i!=(ba[i]-start)>>2 || source[i+1]!=0) { |
5260 | if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc); |
5261 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); |
5262 | if(internal) |
5263 | assem_debug("branch: internal"); |
5264 | else |
5265 | assem_debug("branch: external"); |
5266 | if(internal&&is_ds[(ba[i]-start)>>2]) { |
5267 | ds_assemble_entry(i); |
5268 | } |
5269 | else { |
5270 | add_to_linker((int)out,ba[i],internal); |
5271 | emit_jmp(0); |
5272 | } |
5273 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
5274 | if(((u_int)out)&7) emit_addnop(0); |
5275 | #endif |
5276 | } |
5277 | } |
5278 | else if(nop) { |
5279 | emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc); |
5280 | int jaddr=(int)out; |
5281 | emit_jns(0); |
5282 | add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0); |
5283 | } |
5284 | else { |
5285 | int taken=0,nottaken=0,nottaken1=0; |
5286 | do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert); |
5287 | if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc); |
5288 | if(!only32) |
5289 | { |
5290 | assert(s1h>=0); |
5291 | if(opcode[i]==4) // BEQ |
5292 | { |
5293 | if(s2h>=0) emit_cmp(s1h,s2h); |
5294 | else emit_test(s1h,s1h); |
5295 | nottaken1=(int)out; |
5296 | emit_jne(1); |
5297 | } |
5298 | if(opcode[i]==5) // BNE |
5299 | { |
5300 | if(s2h>=0) emit_cmp(s1h,s2h); |
5301 | else emit_test(s1h,s1h); |
5302 | if(invert) taken=(int)out; |
5303 | else add_to_linker((int)out,ba[i],internal); |
5304 | emit_jne(0); |
5305 | } |
5306 | if(opcode[i]==6) // BLEZ |
5307 | { |
5308 | emit_test(s1h,s1h); |
ce68e3b9 |
5309 | // emit_testimm(s1h,0); |
451ab91e |
5310 | if(invert) taken=(int)out; |
5311 | else add_to_linker((int)out,ba[i],internal); |
5312 | emit_js(0); |
5313 | nottaken1=(int)out; |
5314 | emit_jne(1); |
5315 | } |
5316 | if(opcode[i]==7) // BGTZ |
5317 | { |
5318 | emit_test(s1h,s1h); |
ce68e3b9 |
5319 | // emit_testimm(s1h,0); |
451ab91e |
5320 | nottaken1=(int)out; |
5321 | emit_js(1); |
5322 | if(invert) taken=(int)out; |
5323 | else add_to_linker((int)out,ba[i],internal); |
5324 | emit_jne(0); |
5325 | } |
5326 | } // if(!only32) |
5327 | |
5328 | //DebugMessage(M64MSG_VERBOSE, "branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); |
5329 | assert(s1l>=0); |
5330 | if(opcode[i]==4) // BEQ |
5331 | { |
5332 | if(s2l>=0) emit_cmp(s1l,s2l); |
5333 | else emit_test(s1l,s1l); |
5334 | if(invert){ |
5335 | nottaken=(int)out; |
5336 | emit_jne(1); |
5337 | }else{ |
5338 | add_to_linker((int)out,ba[i],internal); |
5339 | emit_jeq(0); |
5340 | } |
5341 | } |
5342 | if(opcode[i]==5) // BNE |
5343 | { |
5344 | if(s2l>=0) emit_cmp(s1l,s2l); |
5345 | else emit_test(s1l,s1l); |
5346 | if(invert){ |
5347 | nottaken=(int)out; |
5348 | emit_jeq(1); |
5349 | }else{ |
5350 | add_to_linker((int)out,ba[i],internal); |
5351 | emit_jne(0); |
5352 | } |
5353 | } |
5354 | if(opcode[i]==6) // BLEZ |
5355 | { |
5356 | emit_cmpimm(s1l,1); |
5357 | if(invert){ |
5358 | nottaken=(int)out; |
5359 | emit_jge(1); |
5360 | }else{ |
5361 | add_to_linker((int)out,ba[i],internal); |
5362 | emit_jl(0); |
5363 | } |
5364 | } |
5365 | if(opcode[i]==7) // BGTZ |
5366 | { |
5367 | emit_cmpimm(s1l,1); |
5368 | if(invert){ |
5369 | nottaken=(int)out; |
5370 | emit_jl(1); |
5371 | }else{ |
5372 | add_to_linker((int)out,ba[i],internal); |
5373 | emit_jge(0); |
5374 | } |
5375 | } |
5376 | if(invert) { |
5377 | if(taken) set_jump_target(taken,(int)out); |
5378 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
5379 | if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) { |
5380 | if(adj) { |
5381 | emit_addimm(cc,-CLOCK_DIVIDER*adj,cc); |
5382 | add_to_linker((int)out,ba[i],internal); |
5383 | }else{ |
5384 | emit_addnop(13); |
5385 | add_to_linker((int)out,ba[i],internal*2); |
5386 | } |
5387 | emit_jmp(0); |
5388 | }else |
5389 | #endif |
5390 | { |
5391 | if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc); |
5392 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); |
5393 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); |
5394 | if(internal) |
5395 | assem_debug("branch: internal"); |
5396 | else |
5397 | assem_debug("branch: external"); |
5398 | if(internal&&is_ds[(ba[i]-start)>>2]) { |
5399 | ds_assemble_entry(i); |
5400 | } |
5401 | else { |
5402 | add_to_linker((int)out,ba[i],internal); |
5403 | emit_jmp(0); |
5404 | } |
5405 | } |
5406 | set_jump_target(nottaken,(int)out); |
5407 | } |
5408 | |
5409 | if(nottaken1) set_jump_target(nottaken1,(int)out); |
5410 | if(adj) { |
5411 | if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc); |
5412 | } |
5413 | } // (!unconditional) |
5414 | } // if(ooo) |
5415 | else |
5416 | { |
5417 | // In-order execution (branch first) |
5418 | //if(likely[i]) DebugMessage(M64MSG_VERBOSE, "IOL"); |
5419 | //else |
5420 | //DebugMessage(M64MSG_VERBOSE, "IOE"); |
5421 | int taken=0,nottaken=0,nottaken1=0; |
5422 | if(!unconditional&&!nop) { |
5423 | if(!only32) |
5424 | { |
5425 | assert(s1h>=0); |
5426 | if((opcode[i]&0x2f)==4) // BEQ |
5427 | { |
5428 | if(s2h>=0) emit_cmp(s1h,s2h); |
5429 | else emit_test(s1h,s1h); |
5430 | nottaken1=(int)out; |
5431 | emit_jne(2); |
5432 | } |
5433 | if((opcode[i]&0x2f)==5) // BNE |
5434 | { |
5435 | if(s2h>=0) emit_cmp(s1h,s2h); |
5436 | else emit_test(s1h,s1h); |
5437 | taken=(int)out; |
5438 | emit_jne(1); |
5439 | } |
5440 | if((opcode[i]&0x2f)==6) // BLEZ |
5441 | { |
5442 | emit_test(s1h,s1h); |
5443 | taken=(int)out; |
5444 | emit_js(1); |
5445 | nottaken1=(int)out; |
5446 | emit_jne(2); |
5447 | } |
5448 | if((opcode[i]&0x2f)==7) // BGTZ |
5449 | { |
5450 | emit_test(s1h,s1h); |
5451 | nottaken1=(int)out; |
5452 | emit_js(2); |
5453 | taken=(int)out; |
5454 | emit_jne(1); |
5455 | } |
5456 | } // if(!only32) |
5457 | |
5458 | //DebugMessage(M64MSG_VERBOSE, "branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); |
5459 | assert(s1l>=0); |
5460 | if((opcode[i]&0x2f)==4) // BEQ |
5461 | { |
5462 | if(s2l>=0) emit_cmp(s1l,s2l); |
5463 | else emit_test(s1l,s1l); |
5464 | nottaken=(int)out; |
5465 | emit_jne(2); |
5466 | } |
5467 | if((opcode[i]&0x2f)==5) // BNE |
5468 | { |
5469 | if(s2l>=0) emit_cmp(s1l,s2l); |
5470 | else emit_test(s1l,s1l); |
5471 | nottaken=(int)out; |
5472 | emit_jeq(2); |
5473 | } |
5474 | if((opcode[i]&0x2f)==6) // BLEZ |
5475 | { |
5476 | emit_cmpimm(s1l,1); |
5477 | nottaken=(int)out; |
5478 | emit_jge(2); |
5479 | } |
5480 | if((opcode[i]&0x2f)==7) // BGTZ |
5481 | { |
5482 | emit_cmpimm(s1l,1); |
5483 | nottaken=(int)out; |
5484 | emit_jl(2); |
5485 | } |
5486 | } // if(!unconditional) |
5487 | int adj; |
5488 | uint64_t ds_unneeded=branch_regs[i].u; |
5489 | uint64_t ds_unneeded_upper=branch_regs[i].uu; |
5490 | ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1])); |
5491 | ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1])); |
5492 | if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1])); |
5493 | ds_unneeded|=1; |
5494 | ds_unneeded_upper|=1; |
5495 | // branch taken |
5496 | if(!nop) { |
5497 | if(taken) set_jump_target(taken,(int)out); |
5498 | assem_debug("1:"); |
5499 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32, |
5500 | ds_unneeded,ds_unneeded_upper); |
5501 | // load regs |
5502 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]); |
5503 | address_generation(i+1,&branch_regs[i],0); |
5504 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP); |
5505 | ds_assemble(i+1,&branch_regs[i]); |
5506 | cc=get_reg(branch_regs[i].regmap,CCREG); |
5507 | if(cc==-1) { |
5508 | emit_loadreg(CCREG,cc=HOST_CCREG); |
5509 | // CHECK: Is the following instruction (fall thru) allocated ok? |
5510 | } |
5511 | assert(cc==HOST_CCREG); |
5512 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); |
5513 | do_cc(i,i_regmap,&adj,ba[i],TAKEN,0); |
5514 | assem_debug("cycle count (adj)"); |
5515 | if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc); |
5516 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); |
5517 | if(internal) |
5518 | assem_debug("branch: internal"); |
5519 | else |
5520 | assem_debug("branch: external"); |
5521 | if(internal&&is_ds[(ba[i]-start)>>2]) { |
5522 | ds_assemble_entry(i); |
5523 | } |
5524 | else { |
5525 | add_to_linker((int)out,ba[i],internal); |
5526 | emit_jmp(0); |
5527 | } |
5528 | } |
5529 | // branch not taken |
5530 | cop1_usable=prev_cop1_usable; |
5531 | if(!unconditional) { |
5532 | if(nottaken1) set_jump_target(nottaken1,(int)out); |
5533 | set_jump_target(nottaken,(int)out); |
5534 | assem_debug("2:"); |
5535 | if(!likely[i]) { |
5536 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32, |
5537 | ds_unneeded,ds_unneeded_upper); |
5538 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]); |
5539 | address_generation(i+1,&branch_regs[i],0); |
5540 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG); |
5541 | ds_assemble(i+1,&branch_regs[i]); |
5542 | } |
5543 | cc=get_reg(branch_regs[i].regmap,CCREG); |
5544 | if(cc==-1&&!likely[i]) { |
5545 | // Cycle count isn't in a register, temporarily load it then write it out |
5546 | emit_loadreg(CCREG,HOST_CCREG); |
5547 | emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG); |
5548 | int jaddr=(int)out; |
5549 | emit_jns(0); |
5550 | add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0); |
5551 | emit_storereg(CCREG,HOST_CCREG); |
5552 | } |
5553 | else{ |
5554 | cc=get_reg(i_regmap,CCREG); |
5555 | assert(cc==HOST_CCREG); |
5556 | emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc); |
5557 | int jaddr=(int)out; |
5558 | emit_jns(0); |
5559 | add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0); |
5560 | } |
5561 | } |
5562 | } |
5563 | } |
5564 | |
5565 | static void sjump_assemble(int i,struct regstat *i_regs) |
5566 | { |
5567 | signed char *i_regmap=i_regs->regmap; |
5568 | int cc; |
5569 | int match; |
5570 | match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); |
5571 | assem_debug("smatch=%d",match); |
5572 | int s1h,s1l; |
5573 | int prev_cop1_usable=cop1_usable; |
5574 | int unconditional=0,nevertaken=0; |
5575 | int only32=0; |
5576 | int invert=0; |
5577 | int internal=internal_branch(branch_regs[i].is32,ba[i]); |
5578 | if(i==(ba[i]-start)>>2) assem_debug("idle loop"); |
5579 | if(!match) invert=1; |
5580 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
5581 | if(i>(ba[i]-start)>>2) invert=1; |
5582 | #endif |
5583 | |
5584 | //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL) |
5585 | assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL) |
5586 | |
5587 | if(ooo[i]) { |
5588 | s1l=get_reg(branch_regs[i].regmap,rs1[i]); |
5589 | s1h=get_reg(branch_regs[i].regmap,rs1[i]|64); |
5590 | } |
5591 | else { |
5592 | s1l=get_reg(i_regmap,rs1[i]); |
5593 | s1h=get_reg(i_regmap,rs1[i]|64); |
5594 | } |
5595 | if(rs1[i]==0) |
5596 | { |
5597 | if(opcode2[i]&1) unconditional=1; |
5598 | else nevertaken=1; |
5599 | // These are never taken (r0 is never less than zero) |
5600 | //assert(opcode2[i]!=0); |
5601 | //assert(opcode2[i]!=2); |
5602 | //assert(opcode2[i]!=0x10); |
5603 | //assert(opcode2[i]!=0x12); |
5604 | } |
5605 | else { |
5606 | only32=(regs[i].was32>>rs1[i])&1; |
5607 | } |
5608 | |
5609 | if(ooo[i]) { |
5610 | // Out of order execution (delay slot first) |
5611 | //DebugMessage(M64MSG_VERBOSE, "OOOE"); |
5612 | address_generation(i+1,i_regs,regs[i].regmap_entry); |
5613 | ds_assemble(i+1,i_regs); |
5614 | int adj; |
5615 | uint64_t bc_unneeded=branch_regs[i].u; |
5616 | uint64_t bc_unneeded_upper=branch_regs[i].uu; |
5617 | bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i])); |
5618 | bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i])); |
5619 | bc_unneeded|=1; |
5620 | bc_unneeded_upper|=1; |
5621 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32, |
5622 | bc_unneeded,bc_unneeded_upper); |
5623 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]); |
5624 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG); |
5625 | if(rt1[i]==31) { |
5626 | int rt,return_address; |
5627 | assert(rt1[i+1]!=31); |
5628 | assert(rt2[i+1]!=31); |
5629 | rt=get_reg(branch_regs[i].regmap,31); |
5630 | assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); |
5631 | if(rt>=0) { |
5632 | // Save the PC even if the branch is not taken |
5633 | return_address=start+i*4+8; |
5634 | emit_movimm(return_address,rt); // PC into link register |
5635 | #ifdef IMM_PREFETCH |
5636 | if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]); |
5637 | #endif |
5638 | } |
5639 | } |
5640 | cc=get_reg(branch_regs[i].regmap,CCREG); |
5641 | assert(cc==HOST_CCREG); |
5642 | if(unconditional) |
5643 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); |
5644 | //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional); |
5645 | assem_debug("cycle count (adj)"); |
5646 | if(unconditional) { |
5647 | do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0); |
5648 | if(i!=(ba[i]-start)>>2 || source[i+1]!=0) { |
5649 | if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc); |
5650 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); |
5651 | if(internal) |
5652 | assem_debug("branch: internal"); |
5653 | else |
5654 | assem_debug("branch: external"); |
5655 | if(internal&&is_ds[(ba[i]-start)>>2]) { |
5656 | ds_assemble_entry(i); |
5657 | } |
5658 | else { |
5659 | add_to_linker((int)out,ba[i],internal); |
5660 | emit_jmp(0); |
5661 | } |
5662 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
5663 | if(((u_int)out)&7) emit_addnop(0); |
5664 | #endif |
5665 | } |
5666 | } |
5667 | else if(nevertaken) { |
5668 | emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc); |
5669 | int jaddr=(int)out; |
5670 | emit_jns(0); |
5671 | add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0); |
5672 | } |
5673 | else { |
5674 | int nottaken=0; |
5675 | do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert); |
5676 | if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc); |
5677 | if(!only32) |
5678 | { |
5679 | assert(s1h>=0); |
5680 | if(opcode2[i]==0) // BLTZ |
5681 | { |
5682 | emit_test(s1h,s1h); |
5683 | if(invert){ |
5684 | nottaken=(int)out; |
5685 | emit_jns(1); |
5686 | }else{ |
5687 | add_to_linker((int)out,ba[i],internal); |
5688 | emit_js(0); |
5689 | } |
5690 | } |
5691 | if(opcode2[i]==1) // BGEZ |
5692 | { |
5693 | emit_test(s1h,s1h); |
5694 | if(invert){ |
5695 | nottaken=(int)out; |
5696 | emit_js(1); |
5697 | }else{ |
5698 | add_to_linker((int)out,ba[i],internal); |
5699 | emit_jns(0); |
5700 | } |
5701 | } |
5702 | } // if(!only32) |
5703 | else |
5704 | { |
5705 | assert(s1l>=0); |
5706 | if(opcode2[i]==0) // BLTZ |
5707 | { |
5708 | emit_test(s1l,s1l); |
5709 | if(invert){ |
5710 | nottaken=(int)out; |
5711 | emit_jns(1); |
5712 | }else{ |
5713 | add_to_linker((int)out,ba[i],internal); |
5714 | emit_js(0); |
5715 | } |
5716 | } |
5717 | if(opcode2[i]==1) // BGEZ |
5718 | { |
5719 | emit_test(s1l,s1l); |
5720 | if(invert){ |
5721 | nottaken=(int)out; |
5722 | emit_js(1); |
5723 | }else{ |
5724 | add_to_linker((int)out,ba[i],internal); |
5725 | emit_jns(0); |
5726 | } |
5727 | } |
5728 | } // if(!only32) |
5729 | |
5730 | if(invert) { |
5731 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
5732 | if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) { |
5733 | if(adj) { |
5734 | emit_addimm(cc,-CLOCK_DIVIDER*adj,cc); |
5735 | add_to_linker((int)out,ba[i],internal); |
5736 | }else{ |
5737 | emit_addnop(13); |
5738 | add_to_linker((int)out,ba[i],internal*2); |
5739 | } |
5740 | emit_jmp(0); |
5741 | }else |
5742 | #endif |
5743 | { |
5744 | if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc); |
5745 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); |
5746 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); |
5747 | if(internal) |
5748 | assem_debug("branch: internal"); |
5749 | else |
5750 | assem_debug("branch: external"); |
5751 | if(internal&&is_ds[(ba[i]-start)>>2]) { |
5752 | ds_assemble_entry(i); |
5753 | } |
5754 | else { |
5755 | add_to_linker((int)out,ba[i],internal); |
5756 | emit_jmp(0); |
5757 | } |
5758 | } |
5759 | set_jump_target(nottaken,(int)out); |
5760 | } |
5761 | |
5762 | if(adj) { |
5763 | if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc); |
5764 | } |
5765 | } // (!unconditional) |
5766 | } // if(ooo) |
5767 | else |
5768 | { |
5769 | // In-order execution (branch first) |
5770 | //DebugMessage(M64MSG_VERBOSE, "IOE"); |
5771 | int nottaken=0; |
5772 | if(!unconditional) { |
5773 | //DebugMessage(M64MSG_VERBOSE, "branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); |
5774 | if(!only32) |
5775 | { |
5776 | assert(s1h>=0); |
5777 | if((opcode2[i]&0x1d)==0) // BLTZ/BLTZL |
5778 | { |
5779 | emit_test(s1h,s1h); |
5780 | nottaken=(int)out; |
5781 | emit_jns(1); |
5782 | } |
5783 | if((opcode2[i]&0x1d)==1) // BGEZ/BGEZL |
5784 | { |
5785 | emit_test(s1h,s1h); |
5786 | nottaken=(int)out; |
5787 | emit_js(1); |
5788 | } |
5789 | } // if(!only32) |
5790 | else |
5791 | { |
5792 | assert(s1l>=0); |
5793 | if((opcode2[i]&0x1d)==0) // BLTZ/BLTZL |
5794 | { |
5795 | emit_test(s1l,s1l); |
5796 | nottaken=(int)out; |
5797 | emit_jns(1); |
5798 | } |
5799 | if((opcode2[i]&0x1d)==1) // BGEZ/BGEZL |
5800 | { |
5801 | emit_test(s1l,s1l); |
5802 | nottaken=(int)out; |
5803 | emit_js(1); |
5804 | } |
5805 | } |
5806 | } // if(!unconditional) |
5807 | int adj; |
5808 | uint64_t ds_unneeded=branch_regs[i].u; |
5809 | uint64_t ds_unneeded_upper=branch_regs[i].uu; |
5810 | ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1])); |
5811 | ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1])); |
5812 | if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1])); |
5813 | ds_unneeded|=1; |
5814 | ds_unneeded_upper|=1; |
5815 | // branch taken |
5816 | if(!nevertaken) { |
5817 | //assem_debug("1:"); |
5818 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32, |
5819 | ds_unneeded,ds_unneeded_upper); |
5820 | // load regs |
5821 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]); |
5822 | address_generation(i+1,&branch_regs[i],0); |
5823 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP); |
5824 | ds_assemble(i+1,&branch_regs[i]); |
5825 | cc=get_reg(branch_regs[i].regmap,CCREG); |
5826 | if(cc==-1) { |
5827 | emit_loadreg(CCREG,cc=HOST_CCREG); |
5828 | // CHECK: Is the following instruction (fall thru) allocated ok? |
5829 | } |
5830 | assert(cc==HOST_CCREG); |
5831 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); |
5832 | do_cc(i,i_regmap,&adj,ba[i],TAKEN,0); |
5833 | assem_debug("cycle count (adj)"); |
5834 | if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc); |
5835 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); |
5836 | if(internal) |
5837 | assem_debug("branch: internal"); |
5838 | else |
5839 | assem_debug("branch: external"); |
5840 | if(internal&&is_ds[(ba[i]-start)>>2]) { |
5841 | ds_assemble_entry(i); |
5842 | } |
5843 | else { |
5844 | add_to_linker((int)out,ba[i],internal); |
5845 | emit_jmp(0); |
5846 | } |
5847 | } |
5848 | // branch not taken |
5849 | cop1_usable=prev_cop1_usable; |
5850 | if(!unconditional) { |
5851 | set_jump_target(nottaken,(int)out); |
5852 | assem_debug("1:"); |
5853 | if(!likely[i]) { |
5854 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32, |
5855 | ds_unneeded,ds_unneeded_upper); |
5856 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]); |
5857 | address_generation(i+1,&branch_regs[i],0); |
5858 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG); |
5859 | ds_assemble(i+1,&branch_regs[i]); |
5860 | } |
5861 | cc=get_reg(branch_regs[i].regmap,CCREG); |
5862 | if(cc==-1&&!likely[i]) { |
5863 | // Cycle count isn't in a register, temporarily load it then write it out |
5864 | emit_loadreg(CCREG,HOST_CCREG); |
5865 | emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG); |
5866 | int jaddr=(int)out; |
5867 | emit_jns(0); |
5868 | add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0); |
5869 | emit_storereg(CCREG,HOST_CCREG); |
5870 | } |
5871 | else{ |
5872 | cc=get_reg(i_regmap,CCREG); |
5873 | assert(cc==HOST_CCREG); |
5874 | emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc); |
5875 | int jaddr=(int)out; |
5876 | emit_jns(0); |
5877 | add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0); |
5878 | } |
5879 | } |
5880 | } |
5881 | } |
5882 | |
5883 | static void fjump_assemble(int i,struct regstat *i_regs) |
5884 | { |
5885 | signed char *i_regmap=i_regs->regmap; |
5886 | int cc; |
5887 | int match; |
5888 | match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); |
5889 | assem_debug("fmatch=%d",match); |
5890 | int fs,cs; |
5891 | int eaddr; |
5892 | int invert=0; |
5893 | int internal=internal_branch(branch_regs[i].is32,ba[i]); |
5894 | if(i==(ba[i]-start)>>2) assem_debug("idle loop"); |
5895 | if(!match) invert=1; |
5896 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
5897 | if(i>(ba[i]-start)>>2) invert=1; |
5898 | #endif |
5899 | |
5900 | if(ooo[i]) { |
5901 | fs=get_reg(branch_regs[i].regmap,FSREG); |
5902 | address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay? |
5903 | } |
5904 | else { |
5905 | fs=get_reg(i_regmap,FSREG); |
5906 | } |
5907 | |
5908 | // Check cop1 unusable |
5909 | if(!cop1_usable) { |
5910 | cs=get_reg(i_regmap,CSREG); |
5911 | assert(cs>=0); |
5912 | emit_testimm(cs,0x20000000); |
5913 | eaddr=(int)out; |
5914 | emit_jeq(0); |
5915 | add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0); |
5916 | cop1_usable=1; |
5917 | } |
5918 | |
5919 | if(ooo[i]) { |
5920 | // Out of order execution (delay slot first) |
5921 | //DebugMessage(M64MSG_VERBOSE, "OOOE"); |
5922 | ds_assemble(i+1,i_regs); |
5923 | int adj; |
5924 | uint64_t bc_unneeded=branch_regs[i].u; |
5925 | uint64_t bc_unneeded_upper=branch_regs[i].uu; |
5926 | bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i])); |
5927 | bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i])); |
5928 | bc_unneeded|=1; |
5929 | bc_unneeded_upper|=1; |
5930 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32, |
5931 | bc_unneeded,bc_unneeded_upper); |
5932 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]); |
5933 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG); |
5934 | cc=get_reg(branch_regs[i].regmap,CCREG); |
5935 | assert(cc==HOST_CCREG); |
5936 | do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert); |
5937 | assem_debug("cycle count (adj)"); |
5938 | if(1) { |
5939 | int nottaken=0; |
5940 | if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc); |
5941 | if(1) { |
5942 | assert(fs>=0); |
5943 | emit_testimm(fs,0x800000); |
5944 | if(source[i]&0x10000) // BC1T |
5945 | { |
5946 | if(invert){ |
5947 | nottaken=(int)out; |
5948 | emit_jeq(1); |
5949 | }else{ |
5950 | add_to_linker((int)out,ba[i],internal); |
5951 | emit_jne(0); |
5952 | } |
5953 | } |
5954 | else // BC1F |
5955 | if(invert){ |
5956 | nottaken=(int)out; |
5957 | emit_jne(1); |
5958 | }else{ |
5959 | add_to_linker((int)out,ba[i],internal); |
5960 | emit_jeq(0); |
5961 | } |
5962 | { |
5963 | } |
5964 | } // if(!only32) |
5965 | |
5966 | if(invert) { |
5967 | if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc); |
5968 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
5969 | else if(match) emit_addnop(13); |
5970 | #endif |
5971 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); |
5972 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); |
5973 | if(internal) |
5974 | assem_debug("branch: internal"); |
5975 | else |
5976 | assem_debug("branch: external"); |
5977 | if(internal&&is_ds[(ba[i]-start)>>2]) { |
5978 | ds_assemble_entry(i); |
5979 | } |
5980 | else { |
5981 | add_to_linker((int)out,ba[i],internal); |
5982 | emit_jmp(0); |
5983 | } |
5984 | set_jump_target(nottaken,(int)out); |
5985 | } |
5986 | |
5987 | if(adj) { |
5988 | if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc); |
5989 | } |
5990 | } // (!unconditional) |
5991 | } // if(ooo) |
5992 | else |
5993 | { |
5994 | // In-order execution (branch first) |
5995 | //DebugMessage(M64MSG_VERBOSE, "IOE"); |
5996 | int nottaken=0; |
5997 | if(1) { |
5998 | //DebugMessage(M64MSG_VERBOSE, "branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); |
5999 | if(1) { |
6000 | assert(fs>=0); |
6001 | emit_testimm(fs,0x800000); |
6002 | if(source[i]&0x10000) // BC1T |
6003 | { |
6004 | nottaken=(int)out; |
6005 | emit_jeq(1); |
6006 | } |
6007 | else // BC1F |
6008 | { |
6009 | nottaken=(int)out; |
6010 | emit_jne(1); |
6011 | } |
6012 | } |
6013 | } // if(!unconditional) |
6014 | int adj; |
6015 | uint64_t ds_unneeded=branch_regs[i].u; |
6016 | uint64_t ds_unneeded_upper=branch_regs[i].uu; |
6017 | ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1])); |
6018 | ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1])); |
6019 | if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1])); |
6020 | ds_unneeded|=1; |
6021 | ds_unneeded_upper|=1; |
6022 | // branch taken |
6023 | //assem_debug("1:"); |
6024 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32, |
6025 | ds_unneeded,ds_unneeded_upper); |
6026 | // load regs |
6027 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]); |
6028 | address_generation(i+1,&branch_regs[i],0); |
6029 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP); |
6030 | ds_assemble(i+1,&branch_regs[i]); |
6031 | cc=get_reg(branch_regs[i].regmap,CCREG); |
6032 | if(cc==-1) { |
6033 | emit_loadreg(CCREG,cc=HOST_CCREG); |
6034 | // CHECK: Is the following instruction (fall thru) allocated ok? |
6035 | } |
6036 | assert(cc==HOST_CCREG); |
6037 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); |
6038 | do_cc(i,i_regmap,&adj,ba[i],TAKEN,0); |
6039 | assem_debug("cycle count (adj)"); |
6040 | if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc); |
6041 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); |
6042 | if(internal) |
6043 | assem_debug("branch: internal"); |
6044 | else |
6045 | assem_debug("branch: external"); |
6046 | if(internal&&is_ds[(ba[i]-start)>>2]) { |
6047 | ds_assemble_entry(i); |
6048 | } |
6049 | else { |
6050 | add_to_linker((int)out,ba[i],internal); |
6051 | emit_jmp(0); |
6052 | } |
6053 | |
6054 | // branch not taken |
6055 | if(1) { // <- FIXME (don't need this) |
6056 | set_jump_target(nottaken,(int)out); |
6057 | assem_debug("1:"); |
6058 | if(!likely[i]) { |
6059 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32, |
6060 | ds_unneeded,ds_unneeded_upper); |
6061 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]); |
6062 | address_generation(i+1,&branch_regs[i],0); |
6063 | load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG); |
6064 | ds_assemble(i+1,&branch_regs[i]); |
6065 | } |
6066 | cc=get_reg(branch_regs[i].regmap,CCREG); |
6067 | if(cc==-1&&!likely[i]) { |
6068 | // Cycle count isn't in a register, temporarily load it then write it out |
6069 | emit_loadreg(CCREG,HOST_CCREG); |
6070 | emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG); |
6071 | int jaddr=(int)out; |
6072 | emit_jns(0); |
6073 | add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0); |
6074 | emit_storereg(CCREG,HOST_CCREG); |
6075 | } |
6076 | else{ |
6077 | cc=get_reg(i_regmap,CCREG); |
6078 | assert(cc==HOST_CCREG); |
6079 | emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc); |
6080 | int jaddr=(int)out; |
6081 | emit_jns(0); |
6082 | add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0); |
6083 | } |
6084 | } |
6085 | } |
6086 | } |
6087 | |
6088 | static void pagespan_assemble(int i,struct regstat *i_regs) |
6089 | { |
6090 | int s1l=get_reg(i_regs->regmap,rs1[i]); |
6091 | int s1h=get_reg(i_regs->regmap,rs1[i]|64); |
6092 | int s2l=get_reg(i_regs->regmap,rs2[i]); |
6093 | int s2h=get_reg(i_regs->regmap,rs2[i]|64); |
6094 | int taken=0; |
6095 | int nottaken=0; |
6096 | int unconditional=0; |
6097 | if(rs1[i]==0) |
6098 | { |
6099 | s1l=s2l;s1h=s2h; |
6100 | s2l=s2h=-1; |
6101 | } |
6102 | else if(rs2[i]==0) |
6103 | { |
6104 | s2l=s2h=-1; |
6105 | } |
6106 | if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) { |
6107 | s1h=s2h=-1; |
6108 | } |
6109 | int hr=0; |
6110 | int addr,alt,ntaddr; |
6111 | if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;} |
6112 | else { |
6113 | while(hr<HOST_REGS) |
6114 | { |
6115 | if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && |
6116 | (i_regs->regmap[hr]&63)!=rs1[i] && |
6117 | (i_regs->regmap[hr]&63)!=rs2[i] ) |
6118 | { |
6119 | addr=hr++;break; |
6120 | } |
6121 | hr++; |
6122 | } |
6123 | } |
6124 | while(hr<HOST_REGS) |
6125 | { |
6126 | if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG && |
6127 | (i_regs->regmap[hr]&63)!=rs1[i] && |
6128 | (i_regs->regmap[hr]&63)!=rs2[i] ) |
6129 | { |
6130 | alt=hr++;break; |
6131 | } |
6132 | hr++; |
6133 | } |
6134 | if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register |
6135 | { |
6136 | while(hr<HOST_REGS) |
6137 | { |
6138 | if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG && |
6139 | (i_regs->regmap[hr]&63)!=rs1[i] && |
6140 | (i_regs->regmap[hr]&63)!=rs2[i] ) |
6141 | { |
6142 | ntaddr=hr;break; |
6143 | } |
6144 | hr++; |
6145 | } |
6146 | } |
6147 | assert(hr<HOST_REGS); |
6148 | if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1 |
6149 | load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG); |
6150 | } |
6151 | emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG); |
6152 | if(opcode[i]==2) // J |
6153 | { |
6154 | unconditional=1; |
6155 | } |
6156 | if(opcode[i]==3) // JAL |
6157 | { |
6158 | // TODO: mini_ht |
6159 | int rt=get_reg(i_regs->regmap,31); |
6160 | emit_movimm(start+i*4+8,rt); |
6161 | unconditional=1; |
6162 | } |
6163 | if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR |
6164 | { |
6165 | emit_mov(s1l,addr); |
6166 | if(opcode2[i]==9) // JALR |
6167 | { |
6168 | int rt=get_reg(i_regs->regmap,rt1[i]); |
6169 | emit_movimm(start+i*4+8,rt); |
6170 | } |
6171 | } |
6172 | if((opcode[i]&0x3f)==4) // BEQ |
6173 | { |
6174 | if(rs1[i]==rs2[i]) |
6175 | { |
6176 | unconditional=1; |
6177 | } |
6178 | else |
6179 | #ifdef HAVE_CMOV_IMM |
6180 | if(s1h<0) { |
6181 | if(s2l>=0) emit_cmp(s1l,s2l); |
6182 | else emit_test(s1l,s1l); |
6183 | emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr); |
6184 | } |
6185 | else |
6186 | #endif |
6187 | { |
6188 | assert(s1l>=0); |
6189 | emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt); |
6190 | if(s1h>=0) { |
6191 | if(s2h>=0) emit_cmp(s1h,s2h); |
6192 | else emit_test(s1h,s1h); |
6193 | emit_cmovne_reg(alt,addr); |
6194 | } |
6195 | if(s2l>=0) emit_cmp(s1l,s2l); |
6196 | else emit_test(s1l,s1l); |
6197 | emit_cmovne_reg(alt,addr); |
6198 | } |
6199 | } |
6200 | if((opcode[i]&0x3f)==5) // BNE |
6201 | { |
6202 | #ifdef HAVE_CMOV_IMM |
6203 | if(s1h<0) { |
6204 | if(s2l>=0) emit_cmp(s1l,s2l); |
6205 | else emit_test(s1l,s1l); |
6206 | emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr); |
6207 | } |
6208 | else |
6209 | #endif |
6210 | { |
6211 | assert(s1l>=0); |
6212 | emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt); |
6213 | if(s1h>=0) { |
6214 | if(s2h>=0) emit_cmp(s1h,s2h); |
6215 | else emit_test(s1h,s1h); |
6216 | emit_cmovne_reg(alt,addr); |
6217 | } |
6218 | if(s2l>=0) emit_cmp(s1l,s2l); |
6219 | else emit_test(s1l,s1l); |
6220 | emit_cmovne_reg(alt,addr); |
6221 | } |
6222 | } |
6223 | if((opcode[i]&0x3f)==0x14) // BEQL |
6224 | { |
6225 | if(s1h>=0) { |
6226 | if(s2h>=0) emit_cmp(s1h,s2h); |
6227 | else emit_test(s1h,s1h); |
6228 | nottaken=(int)out; |
6229 | emit_jne(0); |
6230 | } |
6231 | if(s2l>=0) emit_cmp(s1l,s2l); |
6232 | else emit_test(s1l,s1l); |
6233 | if(nottaken) set_jump_target(nottaken,(int)out); |
6234 | nottaken=(int)out; |
6235 | emit_jne(0); |
6236 | } |
6237 | if((opcode[i]&0x3f)==0x15) // BNEL |
6238 | { |
6239 | if(s1h>=0) { |
6240 | if(s2h>=0) emit_cmp(s1h,s2h); |
6241 | else emit_test(s1h,s1h); |
6242 | taken=(int)out; |
6243 | emit_jne(0); |
6244 | } |
6245 | if(s2l>=0) emit_cmp(s1l,s2l); |
6246 | else emit_test(s1l,s1l); |
6247 | nottaken=(int)out; |
6248 | emit_jeq(0); |
6249 | if(taken) set_jump_target(taken,(int)out); |
6250 | } |
6251 | if((opcode[i]&0x3f)==6) // BLEZ |
6252 | { |
6253 | emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr); |
6254 | emit_cmpimm(s1l,1); |
6255 | if(s1h>=0) emit_mov(addr,ntaddr); |
6256 | emit_cmovl_reg(alt,addr); |
6257 | if(s1h>=0) { |
6258 | emit_test(s1h,s1h); |
6259 | emit_cmovne_reg(ntaddr,addr); |
6260 | emit_cmovs_reg(alt,addr); |
6261 | } |
6262 | } |
6263 | if((opcode[i]&0x3f)==7) // BGTZ |
6264 | { |
6265 | emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr); |
6266 | emit_cmpimm(s1l,1); |
6267 | if(s1h>=0) emit_mov(addr,alt); |
6268 | emit_cmovl_reg(ntaddr,addr); |
6269 | if(s1h>=0) { |
6270 | emit_test(s1h,s1h); |
6271 | emit_cmovne_reg(alt,addr); |
6272 | emit_cmovs_reg(ntaddr,addr); |
6273 | } |
6274 | } |
6275 | if((opcode[i]&0x3f)==0x16) // BLEZL |
6276 | { |
6277 | assert((opcode[i]&0x3f)!=0x16); |
6278 | } |
6279 | if((opcode[i]&0x3f)==0x17) // BGTZL |
6280 | { |
6281 | assert((opcode[i]&0x3f)!=0x17); |
6282 | } |
6283 | assert(opcode[i]!=1); // BLTZ/BGEZ |
6284 | |
6285 | //FIXME: Check CSREG |
6286 | if(opcode[i]==0x11 && opcode2[i]==0x08 ) { |
6287 | if((source[i]&0x30000)==0) // BC1F |
6288 | { |
6289 | emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt); |
6290 | emit_testimm(s1l,0x800000); |
6291 | emit_cmovne_reg(alt,addr); |
6292 | } |
6293 | if((source[i]&0x30000)==0x10000) // BC1T |
6294 | { |
6295 | emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr); |
6296 | emit_testimm(s1l,0x800000); |
6297 | emit_cmovne_reg(alt,addr); |
6298 | } |
6299 | if((source[i]&0x30000)==0x20000) // BC1FL |
6300 | { |
6301 | emit_testimm(s1l,0x800000); |
6302 | nottaken=(int)out; |
6303 | emit_jne(0); |
6304 | } |
6305 | if((source[i]&0x30000)==0x30000) // BC1TL |
6306 | { |
6307 | emit_testimm(s1l,0x800000); |
6308 | nottaken=(int)out; |
6309 | emit_jeq(0); |
6310 | } |
6311 | } |
6312 | |
6313 | assert(i_regs->regmap[HOST_CCREG]==CCREG); |
6314 | wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty); |
6315 | if(likely[i]||unconditional) |
6316 | { |
6317 | emit_movimm(ba[i],HOST_BTREG); |
6318 | } |
6319 | else if(addr!=HOST_BTREG) |
6320 | { |
6321 | emit_mov(addr,HOST_BTREG); |
6322 | } |
6323 | void *branch_addr=out; |
6324 | emit_jmp(0); |
6325 | int target_addr=start+i*4+5; |
6326 | void *stub=out; |
6327 | void *compiled_target_addr=check_addr(target_addr); |
6328 | emit_extjump_ds((int)branch_addr,target_addr); |
6329 | if(compiled_target_addr) { |
6330 | set_jump_target((int)branch_addr,(int)compiled_target_addr); |
6331 | add_link(target_addr,stub); |
6332 | } |
6333 | else set_jump_target((int)branch_addr,(int)stub); |
6334 | if(likely[i]) { |
6335 | // Not-taken path |
6336 | set_jump_target((int)nottaken,(int)out); |
6337 | wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty); |
6338 | void *branch_addr=out; |
6339 | emit_jmp(0); |
6340 | int target_addr=start+i*4+8; |
6341 | void *stub=out; |
6342 | void *compiled_target_addr=check_addr(target_addr); |
6343 | emit_extjump_ds((int)branch_addr,target_addr); |
6344 | if(compiled_target_addr) { |
6345 | set_jump_target((int)branch_addr,(int)compiled_target_addr); |
6346 | add_link(target_addr,stub); |
6347 | } |
6348 | else set_jump_target((int)branch_addr,(int)stub); |
6349 | } |
6350 | } |
6351 | |
6352 | // Assemble the delay slot for the above |
6353 | static void pagespan_ds() |
6354 | { |
6355 | assem_debug("initial delay slot:"); |
6356 | u_int vaddr=start+1; |
6357 | u_int page=(0x80000000^vaddr)>>12; |
6358 | u_int vpage=page; |
6359 | if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[page^0x80000]^0x80000000)>>12; |
6360 | if(page>2048) page=2048+(page&2047); |
6361 | if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead |
6362 | if(vpage>2048) vpage=2048+(vpage&2047); |
6363 | ll_add(jump_dirty+vpage,vaddr,(void *)out); |
6364 | do_dirty_stub_ds(); |
6365 | ll_add(jump_in+page,vaddr,(void *)out); |
6366 | assert(regs[0].regmap_entry[HOST_CCREG]==CCREG); |
6367 | if(regs[0].regmap[HOST_CCREG]!=CCREG) |
6368 | wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32); |
6369 | if(regs[0].regmap[HOST_BTREG]!=BTREG) |
6370 | emit_writeword(HOST_BTREG,(int)&branch_target); |
6371 | load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]); |
6372 | address_generation(0,®s[0],regs[0].regmap_entry); |
6373 | if(itype[0]==LOAD||itype[0]==LOADLR||itype[0]==STORE||itype[0]==STORELR||itype[0]==C1LS) |
6374 | load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,MMREG,ROREG); |
6375 | if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39) |
6376 | load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP); |
6377 | cop1_usable=0; |
6378 | is_delayslot=0; |
6379 | switch(itype[0]) { |
6380 | case ALU: |
6381 | alu_assemble(0,®s[0]);break; |
6382 | case IMM16: |
6383 | imm16_assemble(0,®s[0]);break; |
6384 | case SHIFT: |
6385 | shift_assemble(0,®s[0]);break; |
6386 | case SHIFTIMM: |
6387 | shiftimm_assemble(0,®s[0]);break; |
6388 | case LOAD: |
6389 | load_assemble(0,®s[0]);break; |
6390 | case LOADLR: |
6391 | loadlr_assemble(0,®s[0]);break; |
6392 | case STORE: |
6393 | store_assemble(0,®s[0]);break; |
6394 | case STORELR: |
6395 | storelr_assemble(0,®s[0]);break; |
6396 | case COP0: |
6397 | cop0_assemble(0,®s[0]);break; |
6398 | case COP1: |
6399 | cop1_assemble(0,®s[0]);break; |
6400 | case C1LS: |
6401 | c1ls_assemble(0,®s[0]);break; |
6402 | case FCONV: |
6403 | fconv_assemble(0,®s[0]);break; |
6404 | case FLOAT: |
6405 | float_assemble(0,®s[0]);break; |
6406 | case FCOMP: |
6407 | fcomp_assemble(0,®s[0]);break; |
6408 | case MULTDIV: |
6409 | multdiv_assemble(0,®s[0]);break; |
6410 | case MOV: |
6411 | mov_assemble(0,®s[0]);break; |
6412 | case SYSCALL: |
6413 | case SPAN: |
6414 | case UJUMP: |
6415 | case RJUMP: |
6416 | case CJUMP: |
6417 | case SJUMP: |
6418 | case FJUMP: |
6419 | DebugMessage(M64MSG_VERBOSE, "Jump in the delay slot. This is probably a bug."); |
6420 | } |
6421 | int btaddr=get_reg(regs[0].regmap,BTREG); |
6422 | if(btaddr<0) { |
6423 | btaddr=get_reg(regs[0].regmap,-1); |
6424 | emit_readword((int)&branch_target,btaddr); |
6425 | } |
6426 | assert(btaddr!=HOST_CCREG); |
6427 | if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG); |
6428 | #ifdef HOST_IMM8 |
6429 | emit_movimm(start+4,HOST_TEMPREG); |
6430 | emit_cmp(btaddr,HOST_TEMPREG); |
6431 | #else |
6432 | emit_cmpimm(btaddr,start+4); |
6433 | #endif |
6434 | int branch=(int)out; |
6435 | emit_jeq(0); |
6436 | store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1); |
6437 | emit_jmp(jump_vaddr_reg[btaddr]); |
6438 | set_jump_target(branch,(int)out); |
6439 | store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4); |
6440 | load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4); |
6441 | } |
6442 | |
6443 | // Basic liveness analysis for MIPS registers |
6444 | static void unneeded_registers(int istart,int iend,int r) |
6445 | { |
6446 | int i; |
6447 | uint64_t u,uu,b,bu; |
6448 | uint64_t temp_u,temp_uu; |
6449 | uint64_t tdep; |
6450 | if(iend==slen-1) { |
6451 | u=1;uu=1; |
6452 | }else{ |
6453 | u=unneeded_reg[iend+1]; |
6454 | uu=unneeded_reg_upper[iend+1]; |
6455 | u=1;uu=1; |
6456 | } |
6457 | for (i=iend;i>=istart;i--) |
6458 | { |
6459 | //DebugMessage(M64MSG_VERBOSE, "unneeded registers i=%d (%d,%d) r=%d",i,istart,iend,r); |
6460 | if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) |
6461 | { |
6462 | // If subroutine call, flag return address as a possible branch target |
6463 | if(rt1[i]==31 && i<slen-2) bt[i+2]=1; |
6464 | |
6465 | if(ba[i]<start || ba[i]>=(start+slen*4)) |
6466 | { |
6467 | // Branch out of this block, flush all regs |
6468 | u=1; |
6469 | uu=1; |
6470 | /* Hexagon hack |
6471 | if(itype[i]==UJUMP&&rt1[i]==31) |
6472 | { |
6473 | uu=u=0x300C00F; // Discard at, v0-v1, t6-t9 |
6474 | } |
6475 | if(itype[i]==RJUMP&&rs1[i]==31) |
6476 | { |
6477 | uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9 |
6478 | } |
6479 | if(start>0x80000400&&start<0x80800000) { |
6480 | if(itype[i]==UJUMP&&rt1[i]==31) |
6481 | { |
6482 | //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi |
6483 | uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9 |
6484 | } |
6485 | if(itype[i]==RJUMP&&rs1[i]==31) |
6486 | { |
6487 | //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi |
6488 | uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9 |
6489 | } |
6490 | }*/ |
6491 | branch_unneeded_reg[i]=u; |
6492 | branch_unneeded_reg_upper[i]=uu; |
6493 | // Merge in delay slot |
6494 | tdep=(~uu>>rt1[i+1])&1; |
6495 | u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]); |
6496 | uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]); |
6497 | u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1])); |
6498 | uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1])); |
6499 | uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1])); |
6500 | u|=1;uu|=1; |
6501 | // If branch is "likely" (and conditional) |
6502 | // then we skip the delay slot on the fall-thru path |
6503 | if(likely[i]) { |
6504 | if(i<slen-1) { |
6505 | u&=unneeded_reg[i+2]; |
6506 | uu&=unneeded_reg_upper[i+2]; |
6507 | } |
6508 | else |
6509 | { |
6510 | u=1; |
6511 | uu=1; |
6512 | } |
6513 | } |
6514 | } |
6515 | else |
6516 | { |
6517 | // Internal branch, flag target |
6518 | bt[(ba[i]-start)>>2]=1; |
6519 | if(ba[i]<=start+i*4) { |
6520 | // Backward branch |
6521 | if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000) |
6522 | { |
6523 | // Unconditional branch |
6524 | temp_u=1;temp_uu=1; |
6525 | } else { |
6526 | // Conditional branch (not taken case) |
6527 | temp_u=unneeded_reg[i+2]; |
6528 | temp_uu=unneeded_reg_upper[i+2]; |
6529 | } |
6530 | // Merge in delay slot |
6531 | tdep=(~temp_uu>>rt1[i+1])&1; |
6532 | temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]); |
6533 | temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]); |
6534 | temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1])); |
6535 | temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1])); |
6536 | temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1])); |
6537 | temp_u|=1;temp_uu|=1; |
6538 | // If branch is "likely" (and conditional) |
6539 | // then we skip the delay slot on the fall-thru path |
6540 | if(likely[i]) { |
6541 | if(i<slen-1) { |
6542 | temp_u&=unneeded_reg[i+2]; |
6543 | temp_uu&=unneeded_reg_upper[i+2]; |
6544 | } |
6545 | else |
6546 | { |
6547 | temp_u=1; |
6548 | temp_uu=1; |
6549 | } |
6550 | } |
6551 | tdep=(~temp_uu>>rt1[i])&1; |
6552 | temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]); |
6553 | temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]); |
6554 | temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i])); |
6555 | temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i])); |
6556 | temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i])); |
6557 | temp_u|=1;temp_uu|=1; |
6558 | unneeded_reg[i]=temp_u; |
6559 | unneeded_reg_upper[i]=temp_uu; |
6560 | // Only go three levels deep. This recursion can take an |
6561 | // excessive amount of time if there are a lot of nested loops. |
6562 | if(r<2) { |
6563 | unneeded_registers((ba[i]-start)>>2,i-1,r+1); |
6564 | }else{ |
6565 | unneeded_reg[(ba[i]-start)>>2]=1; |
6566 | unneeded_reg_upper[(ba[i]-start)>>2]=1; |
6567 | } |
6568 | } /*else*/ if(1) { |
6569 | if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000) |
6570 | { |
6571 | // Unconditional branch |
6572 | u=unneeded_reg[(ba[i]-start)>>2]; |
6573 | uu=unneeded_reg_upper[(ba[i]-start)>>2]; |
6574 | branch_unneeded_reg[i]=u; |
6575 | branch_unneeded_reg_upper[i]=uu; |
6576 | //u=1; |
6577 | //uu=1; |
6578 | //branch_unneeded_reg[i]=u; |
6579 | //branch_unneeded_reg_upper[i]=uu; |
6580 | // Merge in delay slot |
6581 | tdep=(~uu>>rt1[i+1])&1; |
6582 | u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]); |
6583 | uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]); |
6584 | u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1])); |
6585 | uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1])); |
6586 | uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1])); |
6587 | u|=1;uu|=1; |
6588 | } else { |
6589 | // Conditional branch |
6590 | b=unneeded_reg[(ba[i]-start)>>2]; |
6591 | bu=unneeded_reg_upper[(ba[i]-start)>>2]; |
6592 | branch_unneeded_reg[i]=b; |
6593 | branch_unneeded_reg_upper[i]=bu; |
6594 | //b=1; |
6595 | //bu=1; |
6596 | //branch_unneeded_reg[i]=b; |
6597 | //branch_unneeded_reg_upper[i]=bu; |
6598 | // Branch delay slot |
6599 | tdep=(~uu>>rt1[i+1])&1; |
6600 | b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]); |
6601 | bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]); |
6602 | b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1])); |
6603 | bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1])); |
6604 | bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1])); |
6605 | b|=1;bu|=1; |
6606 | // If branch is "likely" then we skip the |
6607 | // delay slot on the fall-thru path |
6608 | if(likely[i]) { |
6609 | u=b; |
6610 | uu=bu; |
6611 | if(i<slen-1) { |
6612 | u&=unneeded_reg[i+2]; |
6613 | uu&=unneeded_reg_upper[i+2]; |
6614 | //u=1; |
6615 | //uu=1; |
6616 | } |
6617 | } else { |
6618 | u&=b; |
6619 | uu&=bu; |
6620 | //u=1; |
6621 | //uu=1; |
6622 | } |
6623 | if(i<slen-1) { |
6624 | branch_unneeded_reg[i]&=unneeded_reg[i+2]; |
6625 | branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2]; |
6626 | //branch_unneeded_reg[i]=1; |
6627 | //branch_unneeded_reg_upper[i]=1; |
6628 | } else { |
6629 | branch_unneeded_reg[i]=1; |
6630 | branch_unneeded_reg_upper[i]=1; |
6631 | } |
6632 | } |
6633 | } |
6634 | } |
6635 | } |
6636 | else if(itype[i]==SYSCALL) |
6637 | { |
6638 | // SYSCALL instruction (software interrupt) |
6639 | u=1; |
6640 | uu=1; |
6641 | } |
6642 | else if(itype[i]==COP0 && (source[i]&0x3f)==0x18) |
6643 | { |
6644 | // ERET instruction (return from interrupt) |
6645 | u=1; |
6646 | uu=1; |
6647 | } |
6648 | //u=uu=1; // DEBUG |
6649 | tdep=(~uu>>rt1[i])&1; |
6650 | // Written registers are unneeded |
6651 | u|=1LL<<rt1[i]; |
6652 | u|=1LL<<rt2[i]; |
6653 | uu|=1LL<<rt1[i]; |
6654 | uu|=1LL<<rt2[i]; |
6655 | // Accessed registers are needed |
6656 | u&=~(1LL<<rs1[i]); |
6657 | u&=~(1LL<<rs2[i]); |
6658 | uu&=~(1LL<<us1[i]); |
6659 | uu&=~(1LL<<us2[i]); |
6660 | // Source-target dependencies |
6661 | uu&=~(tdep<<dep1[i]); |
6662 | uu&=~(tdep<<dep2[i]); |
6663 | // R0 is always unneeded |
6664 | u|=1;uu|=1; |
6665 | // Save it |
6666 | unneeded_reg[i]=u; |
6667 | unneeded_reg_upper[i]=uu; |
6668 | /* |
6669 | DebugMessage(M64MSG_VERBOSE, "ur (%d,%d) %x: ",istart,iend,start+i*4); |
6670 | DebugMessage(M64MSG_VERBOSE, "U:"); |
6671 | int r; |
6672 | for(r=1;r<=CCREG;r++) { |
6673 | if((unneeded_reg[i]>>r)&1) { |
6674 | if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI"); |
6675 | else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO"); |
6676 | else DebugMessage(M64MSG_VERBOSE, " r%d",r); |
6677 | } |
6678 | } |
6679 | DebugMessage(M64MSG_VERBOSE, " UU:"); |
6680 | for(r=1;r<=CCREG;r++) { |
6681 | if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) { |
6682 | if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI"); |
6683 | else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO"); |
6684 | else DebugMessage(M64MSG_VERBOSE, " r%d",r); |
6685 | } |
6686 | }*/ |
6687 | } |
6688 | } |
6689 | |
6690 | // Identify registers which are likely to contain 32-bit values |
6691 | // This is used to predict whether any branches will jump to a |
6692 | // location with 64-bit values in registers. |
6693 | static void provisional_32bit() |
6694 | { |
6695 | int i,j; |
6696 | uint64_t is32=1; |
6697 | uint64_t lastbranch=1; |
6698 | |
6699 | for(i=0;i<slen;i++) |
6700 | { |
6701 | if(i>0) { |
6702 | if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) { |
6703 | if(i>1) is32=lastbranch; |
6704 | else is32=1; |
6705 | } |
6706 | } |
6707 | if(i>1) |
6708 | { |
6709 | if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) { |
6710 | if(likely[i-2]) { |
6711 | if(i>2) is32=lastbranch; |
6712 | else is32=1; |
6713 | } |
6714 | } |
6715 | if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL |
6716 | { |
6717 | if(rs1[i-2]==0||rs2[i-2]==0) |
6718 | { |
6719 | if(rs1[i-2]) { |
6720 | is32|=1LL<<rs1[i-2]; |
6721 | } |
6722 | if(rs2[i-2]) { |
6723 | is32|=1LL<<rs2[i-2]; |
6724 | } |
6725 | } |
6726 | } |
6727 | } |
6728 | // If something jumps here with 64-bit values |
6729 | // then promote those registers to 64 bits |
6730 | if(bt[i]) |
6731 | { |
6732 | uint64_t temp_is32=is32; |
6733 | for(j=i-1;j>=0;j--) |
6734 | { |
6735 | if(ba[j]==start+i*4) |
6736 | //temp_is32&=branch_regs[j].is32; |
6737 | temp_is32&=p32[j]; |
6738 | } |
6739 | for(j=i;j<slen;j++) |
6740 | { |
6741 | if(ba[j]==start+i*4) |
6742 | temp_is32=1; |
6743 | } |
6744 | is32=temp_is32; |
6745 | } |
6746 | int type=itype[i]; |
6747 | int op=opcode[i]; |
6748 | int op2=opcode2[i]; |
6749 | int rt=rt1[i]; |
6750 | int s1=rs1[i]; |
6751 | int s2=rs2[i]; |
6752 | if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) { |
6753 | // Branches don't write registers, consider the delay slot instead. |
6754 | type=itype[i+1]; |
6755 | op=opcode[i+1]; |
6756 | op2=opcode2[i+1]; |
6757 | rt=rt1[i+1]; |
6758 | s1=rs1[i+1]; |
6759 | s2=rs2[i+1]; |
6760 | lastbranch=is32; |
6761 | } |
6762 | switch(type) { |
6763 | case LOAD: |
6764 | if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD |
6765 | opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR |
6766 | is32&=~(1LL<<rt); |
6767 | else |
6768 | is32|=1LL<<rt; |
6769 | break; |
6770 | case STORE: |
6771 | case STORELR: |
6772 | break; |
6773 | case LOADLR: |
6774 | if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL |
6775 | if(op==0x22) is32|=1LL<<rt; // LWL |
6776 | break; |
6777 | case IMM16: |
6778 | if (op==0x08||op==0x09|| // ADDI/ADDIU |
6779 | op==0x0a||op==0x0b|| // SLTI/SLTIU |
6780 | op==0x0c|| // ANDI |
6781 | op==0x0f) // LUI |
6782 | { |
6783 | is32|=1LL<<rt; |
6784 | } |
6785 | if(op==0x18||op==0x19) { // DADDI/DADDIU |
6786 | is32&=~(1LL<<rt); |
6787 | //if(imm[i]==0) |
6788 | // is32|=((is32>>s1)&1LL)<<rt; |
6789 | } |
6790 | if(op==0x0d||op==0x0e) { // ORI/XORI |
6791 | uint64_t sr=((is32>>s1)&1LL); |
6792 | is32&=~(1LL<<rt); |
6793 | is32|=sr<<rt; |
6794 | } |
6795 | break; |
6796 | case UJUMP: |
6797 | break; |
6798 | case RJUMP: |
6799 | break; |
6800 | case CJUMP: |
6801 | break; |
6802 | case SJUMP: |
6803 | break; |
6804 | case FJUMP: |
6805 | break; |
6806 | case ALU: |
6807 | if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU |
6808 | is32|=1LL<<rt; |
6809 | } |
6810 | if(op2==0x2a||op2==0x2b) { // SLT/SLTU |
6811 | is32|=1LL<<rt; |
6812 | } |
6813 | else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR |
6814 | uint64_t sr=((is32>>s1)&(is32>>s2)&1LL); |
6815 | is32&=~(1LL<<rt); |
6816 | is32|=sr<<rt; |
6817 | } |
6818 | else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU |
6819 | if(s1==0&&s2==0) { |
6820 | is32|=1LL<<rt; |
6821 | } |
6822 | else if(s2==0) { |
6823 | uint64_t sr=((is32>>s1)&1LL); |
6824 | is32&=~(1LL<<rt); |
6825 | is32|=sr<<rt; |
6826 | } |
6827 | else if(s1==0) { |
6828 | uint64_t sr=((is32>>s2)&1LL); |
6829 | is32&=~(1LL<<rt); |
6830 | is32|=sr<<rt; |
6831 | } |
6832 | else { |
6833 | is32&=~(1LL<<rt); |
6834 | } |
6835 | } |
6836 | else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU |
6837 | if(s1==0&&s2==0) { |
6838 | is32|=1LL<<rt; |
6839 | } |
6840 | else if(s2==0) { |
6841 | uint64_t sr=((is32>>s1)&1LL); |
6842 | is32&=~(1LL<<rt); |
6843 | is32|=sr<<rt; |
6844 | } |
6845 | else { |
6846 | is32&=~(1LL<<rt); |
6847 | } |
6848 | } |
6849 | break; |
6850 | case MULTDIV: |
6851 | if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU |
6852 | is32&=~((1LL<<HIREG)|(1LL<<LOREG)); |
6853 | } |
6854 | else { |
6855 | is32|=(1LL<<HIREG)|(1LL<<LOREG); |
6856 | } |
6857 | break; |
6858 | case MOV: |
6859 | { |
6860 | uint64_t sr=((is32>>s1)&1LL); |
6861 | is32&=~(1LL<<rt); |
6862 | is32|=sr<<rt; |
6863 | } |
6864 | break; |
6865 | case SHIFT: |
6866 | if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV |
6867 | else is32|=1LL<<rt; // SLLV/SRLV/SRAV |
6868 | break; |
6869 | case SHIFTIMM: |
6870 | is32|=1LL<<rt; |
6871 | // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result |
6872 | if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt); |
6873 | break; |
6874 | case COP0: |
6875 | if(op2==0) is32|=1LL<<rt; // MFC0 |
6876 | break; |
6877 | case COP1: |
6878 | if(op2==0) is32|=1LL<<rt; // MFC1 |
6879 | if(op2==1) is32&=~(1LL<<rt); // DMFC1 |
6880 | if(op2==2) is32|=1LL<<rt; // CFC1 |
6881 | break; |
6882 | case C1LS: |
6883 | break; |
6884 | case FLOAT: |
6885 | case FCONV: |
6886 | break; |
6887 | case FCOMP: |
6888 | break; |
6889 | case SYSCALL: |
6890 | break; |
6891 | default: |
6892 | break; |
6893 | } |
6894 | is32|=1; |
6895 | p32[i]=is32; |
6896 | |
6897 | if(i>0) |
6898 | { |
6899 | if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000) |
6900 | { |
6901 | if(rt1[i-1]==31) // JAL/JALR |
6902 | { |
6903 | // Subroutine call will return here, don't alloc any registers |
6904 | is32=1; |
6905 | } |
6906 | else if(i+1<slen) |
6907 | { |
6908 | // Internal branch will jump here, match registers to caller |
6909 | is32=0x3FFFFFFFFLL; |
6910 | } |
6911 | } |
6912 | } |
6913 | } |
6914 | } |
6915 | |
6916 | // Identify registers which may be assumed to contain 32-bit values |
6917 | // and where optimizations will rely on this. |
6918 | // This is used to determine whether backward branches can safely |
6919 | // jump to a location with 64-bit values in registers. |
6920 | static void provisional_r32() |
6921 | { |
6922 | u_int r32=0; |
6923 | int i; |
6924 | |
6925 | for (i=slen-1;i>=0;i--) |
6926 | { |
6927 | int hr; |
6928 | if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) |
6929 | { |
6930 | if(ba[i]<start || ba[i]>=(start+slen*4)) |
6931 | { |
6932 | // Branch out of this block, don't need anything |
6933 | r32=0; |
6934 | } |
6935 | else |
6936 | { |
6937 | // Internal branch |
6938 | // Need whatever matches the target |
6939 | // (and doesn't get overwritten by the delay slot instruction) |
6940 | r32=0; |
6941 | int t=(ba[i]-start)>>2; |
6942 | if(ba[i]>start+i*4) { |
6943 | // Forward branch |
6944 | //if(!(requires_32bit[t]&~regs[i].was32)) |
6945 | // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1])); |
6946 | if(!(pr32[t]&~regs[i].was32)) |
6947 | r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1])); |
6948 | }else{ |
6949 | // Backward branch |
6950 | if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32)) |
6951 | r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1])); |
6952 | } |
6953 | } |
6954 | // Conditional branch may need registers for following instructions |
6955 | if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) |
6956 | { |
6957 | if(i<slen-2) { |
6958 | //r32|=requires_32bit[i+2]; |
6959 | r32|=pr32[i+2]; |
6960 | r32&=regs[i].was32; |
6961 | // Mark this address as a branch target since it may be called |
6962 | // upon return from interrupt |
6963 | //bt[i+2]=1; |
6964 | } |
6965 | } |
6966 | // Merge in delay slot |
6967 | if(!likely[i]) { |
6968 | // These are overwritten unless the branch is "likely" |
6969 | // and the delay slot is nullified if not taken |
6970 | r32&=~(1LL<<rt1[i+1]); |
6971 | r32&=~(1LL<<rt2[i+1]); |
6972 | } |
6973 | // Assume these are needed (delay slot) |
6974 | if(us1[i+1]>0) |
6975 | { |
6976 | if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1]; |
6977 | } |
6978 | if(us2[i+1]>0) |
6979 | { |
6980 | if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1]; |
6981 | } |
6982 | if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) |
6983 | { |
6984 | if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1]; |
6985 | } |
6986 | if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) |
6987 | { |
6988 | if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1]; |
6989 | } |
6990 | } |
6991 | else if(itype[i]==SYSCALL) |
6992 | { |
6993 | // SYSCALL instruction (software interrupt) |
6994 | r32=0; |
6995 | } |
6996 | else if(itype[i]==COP0 && (source[i]&0x3f)==0x18) |
6997 | { |
6998 | // ERET instruction (return from interrupt) |
6999 | r32=0; |
7000 | } |
7001 | // Check 32 bits |
7002 | r32&=~(1LL<<rt1[i]); |
7003 | r32&=~(1LL<<rt2[i]); |
7004 | if(us1[i]>0) |
7005 | { |
7006 | if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i]; |
7007 | } |
7008 | if(us2[i]>0) |
7009 | { |
7010 | if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i]; |
7011 | } |
7012 | if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) |
7013 | { |
7014 | if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i]; |
7015 | } |
7016 | if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) |
7017 | { |
7018 | if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i]; |
7019 | } |
7020 | //requires_32bit[i]=r32; |
7021 | pr32[i]=r32; |
7022 | |
7023 | // Dirty registers which are 32-bit, require 32-bit input |
7024 | // as they will be written as 32-bit values |
7025 | for(hr=0;hr<HOST_REGS;hr++) |
7026 | { |
7027 | if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) { |
7028 | if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) { |
7029 | if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1)) |
7030 | pr32[i]|=1LL<<regs[i].regmap_entry[hr]; |
7031 | //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr]; |
7032 | } |
7033 | } |
7034 | } |
7035 | } |
7036 | } |
7037 | |
7038 | // Write back dirty registers as soon as we will no longer modify them, |
7039 | // so that we don't end up with lots of writes at the branches. |
7040 | static void clean_registers(int istart,int iend,int wr) |
7041 | { |
7042 | int i; |
7043 | int r; |
7044 | u_int will_dirty_i,will_dirty_next,temp_will_dirty; |
7045 | u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty; |
7046 | if(iend==slen-1) { |
7047 | will_dirty_i=will_dirty_next=0; |
7048 | wont_dirty_i=wont_dirty_next=0; |
7049 | }else{ |
7050 | will_dirty_i=will_dirty_next=will_dirty[iend+1]; |
7051 | wont_dirty_i=wont_dirty_next=wont_dirty[iend+1]; |
7052 | } |
7053 | for (i=iend;i>=istart;i--) |
7054 | { |
7055 | if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) |
7056 | { |
7057 | if(ba[i]<start || ba[i]>=(start+slen*4)) |
7058 | { |
7059 | // Branch out of this block, flush all regs |
7060 | if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000) |
7061 | { |
7062 | // Unconditional branch |
7063 | will_dirty_i=0; |
7064 | wont_dirty_i=0; |
7065 | // Merge in delay slot (will dirty) |
7066 | for(r=0;r<HOST_REGS;r++) { |
7067 | if(r!=EXCLUDE_REG) { |
7068 | if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r; |
7069 | if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r; |
7070 | if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r; |
7071 | if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r; |
7072 | if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r); |
7073 | if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r); |
7074 | if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r; |
7075 | if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r; |
7076 | if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r; |
7077 | if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r; |
7078 | if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r; |
7079 | if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r); |
7080 | if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r); |
7081 | if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r; |
7082 | } |
7083 | } |
7084 | } |
7085 | else |
7086 | { |
7087 | // Conditional branch |
7088 | will_dirty_i=0; |
7089 | wont_dirty_i=wont_dirty_next; |
7090 | // Merge in delay slot (will dirty) |
7091 | for(r=0;r<HOST_REGS;r++) { |
7092 | if(r!=EXCLUDE_REG) { |
7093 | if(!likely[i]) { |
7094 | // Might not dirty if likely branch is not taken |
7095 | if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r; |
7096 | if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r; |
7097 | if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r; |
7098 | if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r; |
7099 | if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r); |
7100 | if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r); |
7101 | if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r; |
7102 | //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r; |
7103 | //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r; |
7104 | if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r; |
7105 | if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r; |
7106 | if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r); |
7107 | if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r); |
7108 | if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r; |
7109 | } |
7110 | } |
7111 | } |
7112 | } |
7113 | // Merge in delay slot (wont dirty) |
7114 | for(r=0;r<HOST_REGS;r++) { |
7115 | if(r!=EXCLUDE_REG) { |
7116 | if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r; |
7117 | if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r; |
7118 | if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r; |
7119 | if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r; |
7120 | if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r; |
7121 | if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r; |
7122 | if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r; |
7123 | if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r; |
7124 | if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r; |
7125 | if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r; |
7126 | } |
7127 | } |
7128 | if(wr) { |
7129 | #ifndef DESTRUCTIVE_WRITEBACK |
7130 | branch_regs[i].dirty&=wont_dirty_i; |
7131 | #endif |
7132 | branch_regs[i].dirty|=will_dirty_i; |
7133 | } |
7134 | } |
7135 | else |
7136 | { |
7137 | // Internal branch |
7138 | if(ba[i]<=start+i*4) { |
7139 | // Backward branch |
7140 | if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000) |
7141 | { |
7142 | // Unconditional branch |
7143 | temp_will_dirty=0; |
7144 | temp_wont_dirty=0; |
7145 | // Merge in delay slot (will dirty) |
7146 | for(r=0;r<HOST_REGS;r++) { |
7147 | if(r!=EXCLUDE_REG) { |
7148 | if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r; |
7149 | if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r; |
7150 | if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r; |
7151 | if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r; |
7152 | if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r); |
7153 | if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r); |
7154 | if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r; |
7155 | if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r; |
7156 | if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r; |
7157 | if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r; |
7158 | if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r; |
7159 | if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r); |
7160 | if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r); |
7161 | if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r; |
7162 | } |
7163 | } |
7164 | } else { |
7165 | // Conditional branch (not taken case) |
7166 | temp_will_dirty=will_dirty_next; |
7167 | temp_wont_dirty=wont_dirty_next; |
7168 | // Merge in delay slot (will dirty) |
7169 | for(r=0;r<HOST_REGS;r++) { |
7170 | if(r!=EXCLUDE_REG) { |
7171 | if(!likely[i]) { |
7172 | // Will not dirty if likely branch is not taken |
7173 | if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r; |
7174 | if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r; |
7175 | if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r; |
7176 | if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r; |
7177 | if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r); |
7178 | if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r); |
7179 | if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r; |
7180 | //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r; |
7181 | //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r; |
7182 | if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r; |
7183 | if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r; |
7184 | if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r); |
7185 | if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r); |
7186 | if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r; |
7187 | } |
7188 | } |
7189 | } |
7190 | } |
7191 | // Merge in delay slot (wont dirty) |
7192 | for(r=0;r<HOST_REGS;r++) { |
7193 | if(r!=EXCLUDE_REG) { |
7194 | if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r; |
7195 | if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r; |
7196 | if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r; |
7197 | if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r; |
7198 | if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r; |
7199 | if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r; |
7200 | if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r; |
7201 | if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r; |
7202 | if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r; |
7203 | if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r; |
7204 | } |
7205 | } |
7206 | // Deal with changed mappings |
7207 | if(i<iend) { |
7208 | for(r=0;r<HOST_REGS;r++) { |
7209 | if(r!=EXCLUDE_REG) { |
7210 | if(regs[i].regmap[r]!=regmap_pre[i][r]) { |
7211 | temp_will_dirty&=~(1<<r); |
7212 | temp_wont_dirty&=~(1<<r); |
7213 | if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) { |
7214 | temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r; |
7215 | temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r; |
7216 | } else { |
7217 | temp_will_dirty|=1<<r; |
7218 | temp_wont_dirty|=1<<r; |
7219 | } |
7220 | } |
7221 | } |
7222 | } |
7223 | } |
7224 | if(wr) { |
7225 | will_dirty[i]=temp_will_dirty; |
7226 | wont_dirty[i]=temp_wont_dirty; |
7227 | clean_registers((ba[i]-start)>>2,i-1,0); |
7228 | }else{ |
7229 | // Limit recursion. It can take an excessive amount |
7230 | // of time if there are a lot of nested loops. |
7231 | will_dirty[(ba[i]-start)>>2]=0; |
7232 | wont_dirty[(ba[i]-start)>>2]=-1; |
7233 | } |
7234 | } |
7235 | /*else*/ if(1) |
7236 | { |
7237 | if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000) |
7238 | { |
7239 | // Unconditional branch |
7240 | will_dirty_i=0; |
7241 | wont_dirty_i=0; |
7242 | //if(ba[i]>start+i*4) { // Disable recursion (for debugging) |
7243 | for(r=0;r<HOST_REGS;r++) { |
7244 | if(r!=EXCLUDE_REG) { |
7245 | if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) { |
7246 | will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r); |
7247 | wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r); |
7248 | } |
7249 | if(branch_regs[i].regmap[r]>=0) { |
7250 | will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r; |
7251 | wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r; |
7252 | } |
7253 | } |
7254 | } |
7255 | //} |
7256 | // Merge in delay slot |
7257 | for(r=0;r<HOST_REGS;r++) { |
7258 | if(r!=EXCLUDE_REG) { |
7259 | if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r; |
7260 | if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r; |
7261 | if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r; |
7262 | if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r; |
7263 | if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r); |
7264 | if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r); |
7265 | if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r; |
7266 | if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r; |
7267 | if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r; |
7268 | if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r; |
7269 | if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r; |
7270 | if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r); |
7271 | if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r); |
7272 | if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r; |
7273 | } |
7274 | } |
7275 | } else { |
7276 | // Conditional branch |
7277 | will_dirty_i=will_dirty_next; |
7278 | wont_dirty_i=wont_dirty_next; |
7279 | //if(ba[i]>start+i*4) { // Disable recursion (for debugging) |
7280 | for(r=0;r<HOST_REGS;r++) { |
7281 | if(r!=EXCLUDE_REG) { |
7282 | signed char target_reg=branch_regs[i].regmap[r]; |
7283 | if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) { |
7284 | will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r); |
7285 | wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r); |
7286 | } |
7287 | else if(target_reg>=0) { |
7288 | will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r; |
7289 | wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r; |
7290 | } |
7291 | // Treat delay slot as part of branch too |
7292 | /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) { |
7293 | will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r); |
7294 | wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r); |
7295 | } |
7296 | else |
7297 | { |
7298 | will_dirty[i+1]&=~(1<<r); |
7299 | }*/ |
7300 | } |
7301 | } |
7302 | //} |
7303 | // Merge in delay slot |
7304 | for(r=0;r<HOST_REGS;r++) { |
7305 | if(r!=EXCLUDE_REG) { |
7306 | if(!likely[i]) { |
7307 | // Might not dirty if likely branch is not taken |
7308 | if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r; |
7309 | if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r; |
7310 | if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r; |
7311 | if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r; |
7312 | if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r); |
7313 | if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r); |
7314 | if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r; |
7315 | //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r; |
7316 | //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r; |
7317 | if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r; |
7318 | if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r; |
7319 | if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r); |
7320 | if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r); |
7321 | if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r; |
7322 | } |
7323 | } |
7324 | } |
7325 | } |
7326 | // Merge in delay slot (won't dirty) |
7327 | for(r=0;r<HOST_REGS;r++) { |
7328 | if(r!=EXCLUDE_REG) { |
7329 | if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r; |
7330 | if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r; |
7331 | if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r; |
7332 | if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r; |
7333 | if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r; |
7334 | if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r; |
7335 | if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r; |
7336 | if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r; |
7337 | if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r; |
7338 | if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r; |
7339 | } |
7340 | } |
7341 | if(wr) { |
7342 | #ifndef DESTRUCTIVE_WRITEBACK |
7343 | branch_regs[i].dirty&=wont_dirty_i; |
7344 | #endif |
7345 | branch_regs[i].dirty|=will_dirty_i; |
7346 | } |
7347 | } |
7348 | } |
7349 | } |
7350 | else if(itype[i]==SYSCALL) |
7351 | { |
7352 | // SYSCALL instruction (software interrupt) |
7353 | will_dirty_i=0; |
7354 | wont_dirty_i=0; |
7355 | } |
7356 | else if(itype[i]==COP0 && (source[i]&0x3f)==0x18) |
7357 | { |
7358 | // ERET instruction (return from interrupt) |
7359 | will_dirty_i=0; |
7360 | wont_dirty_i=0; |
7361 | } |
7362 | will_dirty_next=will_dirty_i; |
7363 | wont_dirty_next=wont_dirty_i; |
7364 | for(r=0;r<HOST_REGS;r++) { |
7365 | if(r!=EXCLUDE_REG) { |
7366 | if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r; |
7367 | if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r; |
7368 | if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r); |
7369 | if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r); |
7370 | if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r; |
7371 | if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r; |
7372 | if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r; |
7373 | if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r; |
7374 | if(i>istart) { |
7375 | if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP) |
7376 | { |
7377 | // Don't store a register immediately after writing it, |
7378 | // may prevent dual-issue. |
7379 | if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r; |
7380 | if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r; |
7381 | } |
7382 | } |
7383 | } |
7384 | } |
7385 | // Save it |
7386 | will_dirty[i]=will_dirty_i; |
7387 | wont_dirty[i]=wont_dirty_i; |
7388 | // Mark registers that won't be dirtied as not dirty |
7389 | if(wr) { |
7390 | /*DebugMessage(M64MSG_VERBOSE, "wr (%d,%d) %x will:",istart,iend,start+i*4); |
7391 | for(r=0;r<HOST_REGS;r++) { |
7392 | if((will_dirty_i>>r)&1) { |
7393 | DebugMessage(M64MSG_VERBOSE, " r%d",r); |
7394 | } |
7395 | }*/ |
7396 | |
7397 | //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) { |
7398 | regs[i].dirty|=will_dirty_i; |
7399 | #ifndef DESTRUCTIVE_WRITEBACK |
7400 | regs[i].dirty&=wont_dirty_i; |
7401 | if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) |
7402 | { |
7403 | if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) { |
7404 | for(r=0;r<HOST_REGS;r++) { |
7405 | if(r!=EXCLUDE_REG) { |
7406 | if(regs[i].regmap[r]==regmap_pre[i+2][r]) { |
7407 | regs[i+2].wasdirty&=wont_dirty_i|~(1<<r); |
7408 | }else {/*DebugMessage(M64MSG_VERBOSE, "i: %x (%d) mismatch(+2): %d",start+i*4,i,r); / *assert(!((wont_dirty_i>>r)&1));*/} |
7409 | } |
7410 | } |
7411 | } |
7412 | } |
7413 | else |
7414 | { |
7415 | if(i<iend) { |
7416 | for(r=0;r<HOST_REGS;r++) { |
7417 | if(r!=EXCLUDE_REG) { |
7418 | if(regs[i].regmap[r]==regmap_pre[i+1][r]) { |
7419 | regs[i+1].wasdirty&=wont_dirty_i|~(1<<r); |
7420 | }else {/*DebugMessage(M64MSG_VERBOSE, "i: %x (%d) mismatch(+1): %d",start+i*4,i,r);/ *assert(!((wont_dirty_i>>r)&1));*/} |
7421 | } |
7422 | } |
7423 | } |
7424 | } |
7425 | #endif |
7426 | //} |
7427 | } |
7428 | // Deal with changed mappings |
7429 | temp_will_dirty=will_dirty_i; |
7430 | temp_wont_dirty=wont_dirty_i; |
7431 | for(r=0;r<HOST_REGS;r++) { |
7432 | if(r!=EXCLUDE_REG) { |
7433 | int nr; |
7434 | if(regs[i].regmap[r]==regmap_pre[i][r]) { |
7435 | if(wr) { |
7436 | #ifndef DESTRUCTIVE_WRITEBACK |
7437 | regs[i].wasdirty&=wont_dirty_i|~(1<<r); |
7438 | #endif |
7439 | regs[i].wasdirty|=will_dirty_i&(1<<r); |
7440 | } |
7441 | } |
7442 | else if((nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) { |
7443 | // Register moved to a different register |
7444 | will_dirty_i&=~(1<<r); |
7445 | wont_dirty_i&=~(1<<r); |
7446 | will_dirty_i|=((temp_will_dirty>>nr)&1)<<r; |
7447 | wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r; |
7448 | if(wr) { |
7449 | #ifndef DESTRUCTIVE_WRITEBACK |
7450 | regs[i].wasdirty&=wont_dirty_i|~(1<<r); |
7451 | #endif |
7452 | regs[i].wasdirty|=will_dirty_i&(1<<r); |
7453 | } |
7454 | } |
7455 | else { |
7456 | will_dirty_i&=~(1<<r); |
7457 | wont_dirty_i&=~(1<<r); |
7458 | if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) { |
7459 | will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r; |
7460 | wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r; |
7461 | } else { |
7462 | wont_dirty_i|=1<<r; |
7463 | /*DebugMessage(M64MSG_VERBOSE, "i: %x (%d) mismatch: %d",start+i*4,i,r);/ *assert(!((will_dirty>>r)&1));*/ |
7464 | } |
7465 | } |
7466 | } |
7467 | } |
7468 | } |
7469 | } |
7470 | |
7471 | #ifdef ASSEM_DEBUG |
7472 | /* disassembly */ |
7473 | static void disassemble_inst(int i) |
7474 | { |
7475 | if (bt[i]) DebugMessage(M64MSG_VERBOSE, "*"); else DebugMessage(M64MSG_VERBOSE, " "); |
7476 | switch(itype[i]) { |
7477 | case UJUMP: |
7478 | printf (" %x: %s %8x",start+i*4,insn[i],ba[i]);break; |
7479 | case CJUMP: |
7480 | printf (" %x: %s r%d,r%d,%8x",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break; |
7481 | case SJUMP: |
7482 | printf (" %x: %s r%d,%8x",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break; |
7483 | case FJUMP: |
7484 | printf (" %x: %s %8x",start+i*4,insn[i],ba[i]);break; |
7485 | case RJUMP: |
7486 | if ((opcode2[i]&1)&&rt1[i]!=31) |
7487 | printf (" %x: %s r%d,r%d",start+i*4,insn[i],rt1[i],rs1[i]); |
7488 | else |
7489 | printf (" %x: %s r%d",start+i*4,insn[i],rs1[i]); |
7490 | break; |
7491 | case SPAN: |
7492 | printf (" %x: %s (pagespan) r%d,r%d,%8x",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break; |
7493 | case IMM16: |
7494 | if(opcode[i]==0xf) //LUI |
7495 | printf (" %x: %s r%d,%4x0000",start+i*4,insn[i],rt1[i],imm[i]&0xffff); |
7496 | else |
7497 | printf (" %x: %s r%d,r%d,%d",start+i*4,insn[i],rt1[i],rs1[i],imm[i]); |
7498 | break; |
7499 | case LOAD: |
7500 | case LOADLR: |
7501 | printf (" %x: %s r%d,r%d+%x",start+i*4,insn[i],rt1[i],rs1[i],imm[i]); |
7502 | break; |
7503 | case STORE: |
7504 | case STORELR: |
7505 | printf (" %x: %s r%d,r%d+%x",start+i*4,insn[i],rs2[i],rs1[i],imm[i]); |
7506 | break; |
7507 | case ALU: |
7508 | case SHIFT: |
7509 | printf (" %x: %s r%d,r%d,r%d",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]); |
7510 | break; |
7511 | case MULTDIV: |
7512 | printf (" %x: %s r%d,r%d",start+i*4,insn[i],rs1[i],rs2[i]); |
7513 | break; |
7514 | case SHIFTIMM: |
7515 | printf (" %x: %s r%d,r%d,%d",start+i*4,insn[i],rt1[i],rs1[i],imm[i]); |
7516 | break; |
7517 | case MOV: |
7518 | if((opcode2[i]&0x1d)==0x10) |
7519 | printf (" %x: %s r%d",start+i*4,insn[i],rt1[i]); |
7520 | else if((opcode2[i]&0x1d)==0x11) |
7521 | printf (" %x: %s r%d",start+i*4,insn[i],rs1[i]); |
7522 | else |
7523 | printf (" %x: %s",start+i*4,insn[i]); |
7524 | break; |
7525 | case COP0: |
7526 | if(opcode2[i]==0) |
7527 | printf (" %x: %s r%d,cpr0[%d]",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0 |
7528 | else if(opcode2[i]==4) |
7529 | printf (" %x: %s r%d,cpr0[%d]",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0 |
7530 | else printf (" %x: %s",start+i*4,insn[i]); |
7531 | break; |
7532 | case COP1: |
7533 | if(opcode2[i]<3) |
7534 | printf (" %x: %s r%d,cpr1[%d]",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1 |
7535 | else if(opcode2[i]>3) |
7536 | printf (" %x: %s r%d,cpr1[%d]",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1 |
7537 | else printf (" %x: %s",start+i*4,insn[i]); |
7538 | break; |
7539 | case C1LS: |
7540 | printf (" %x: %s cpr1[%d],r%d+%x",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]); |
7541 | break; |
7542 | default: |
7543 | //printf (" %s %8x",insn[i],source[i]); |
7544 | printf (" %x: %s",start+i*4,insn[i]); |
7545 | } |
7546 | } |
7547 | #endif |
7548 | |
7549 | void new_dynarec_init() |
7550 | { |
7551 | DebugMessage(M64MSG_INFO, "Init new dynarec"); |
7552 | |
7553 | #if NEW_DYNAREC == NEW_DYNAREC_ARM |
7554 | if ((base_addr = mmap ((u_char *)BASE_ADDR, 1<<TARGET_SIZE_2, |
7555 | PROT_READ | PROT_WRITE | PROT_EXEC, |
7556 | MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS, |
7557 | -1, 0)) <= 0) {DebugMessage(M64MSG_ERROR, "mmap() failed");} |
7558 | #else |
7559 | if ((base_addr = mmap (NULL, 1<<TARGET_SIZE_2, |
7560 | PROT_READ | PROT_WRITE | PROT_EXEC, |
7561 | MAP_PRIVATE | MAP_ANONYMOUS, |
7562 | -1, 0)) <= 0) {DebugMessage(M64MSG_ERROR, "mmap() failed");} |
7563 | #endif |
7564 | out=(u_char *)base_addr; |
7565 | |
7566 | rdword=&readmem_dword; |
7567 | fake_pc.f.r.rs=(long long int *)&readmem_dword; |
7568 | fake_pc.f.r.rt=(long long int *)&readmem_dword; |
7569 | fake_pc.f.r.rd=(long long int *)&readmem_dword; |
7570 | int n; |
7571 | for(n=0x80000;n<0x80800;n++) |
7572 | invalid_code[n]=1; |
7573 | for(n=0;n<65536;n++) |
7574 | hash_table[n][0]=hash_table[n][2]=-1; |
7575 | memset(mini_ht,-1,sizeof(mini_ht)); |
7576 | memset(restore_candidate,0,sizeof(restore_candidate)); |
7577 | copy=shadow; |
7578 | expirep=16384; // Expiry pointer, +2 blocks |
7579 | pending_exception=0; |
7580 | literalcount=0; |
7581 | #ifdef HOST_IMM8 |
7582 | // Copy this into local area so we don't have to put it in every literal pool |
7583 | invc_ptr=invalid_code; |
7584 | #endif |
7585 | stop_after_jal=0; |
7586 | // TLB |
7587 | using_tlb=0; |
7588 | for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF |
7589 | memory_map[n]=-1; |
7590 | for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF |
7591 | memory_map[n]=((u_int)rdram-0x80000000)>>2; |
7592 | for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF |
7593 | memory_map[n]=-1; |
7594 | for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF |
7595 | writemem[n] = write_nomem_new; |
7596 | writememb[n] = write_nomemb_new; |
7597 | writememh[n] = write_nomemh_new; |
7598 | writememd[n] = write_nomemd_new; |
7599 | readmem[n] = read_nomem_new; |
7600 | readmemb[n] = read_nomemb_new; |
7601 | readmemh[n] = read_nomemh_new; |
7602 | readmemd[n] = read_nomemd_new; |
7603 | } |
7604 | for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF |
7605 | writemem[n] = write_rdram_new; |
7606 | writememb[n] = write_rdramb_new; |
7607 | writememh[n] = write_rdramh_new; |
7608 | writememd[n] = write_rdramd_new; |
7609 | } |
7610 | for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF |
7611 | writemem[n] = write_nomem_new; |
7612 | writememb[n] = write_nomemb_new; |
7613 | writememh[n] = write_nomemh_new; |
7614 | writememd[n] = write_nomemd_new; |
7615 | readmem[n] = read_nomem_new; |
7616 | readmemb[n] = read_nomemb_new; |
7617 | readmemh[n] = read_nomemh_new; |
7618 | readmemd[n] = read_nomemd_new; |
7619 | } |
7620 | tlb_hacks(); |
7621 | arch_init(); |
7622 | } |
7623 | |
7624 | void new_dynarec_cleanup() |
7625 | { |
7626 | int n; |
7627 | if (munmap (base_addr, 1<<TARGET_SIZE_2) < 0) {DebugMessage(M64MSG_ERROR, "munmap() failed");} |
7628 | for(n=0;n<4096;n++) ll_clear(jump_in+n); |
7629 | for(n=0;n<4096;n++) ll_clear(jump_out+n); |
7630 | for(n=0;n<4096;n++) ll_clear(jump_dirty+n); |
7631 | #ifdef ROM_COPY |
7632 | if (munmap (ROM_COPY, 67108864) < 0) {DebugMessage(M64MSG_ERROR, "munmap() failed");} |
7633 | #endif |
7634 | } |
7635 | |
7636 | int new_recompile_block(int addr) |
7637 | { |
7638 | /* |
7639 | if(addr==0x800cd050) { |
7640 | int block; |
7641 | for(block=0x80000;block<0x80800;block++) invalidate_block(block); |
7642 | int n; |
7643 | for(n=0;n<=2048;n++) ll_clear(jump_dirty+n); |
7644 | } |
7645 | */ |
7646 | //if(Count==365117028) tracedebug=1; |
7647 | assem_debug("NOTCOMPILED: addr = %x -> %x", (int)addr, (int)out); |
7648 | #if defined (COUNT_NOTCOMPILEDS ) |
7649 | notcompiledCount++; |
7650 | log_message( "notcompiledCount=%i", notcompiledCount ); |
7651 | #endif |
7652 | //DebugMessage(M64MSG_VERBOSE, "NOTCOMPILED: addr = %x -> %x", (int)addr, (int)out); |
7653 | //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (compile %x)",Count,next_interupt,addr); |
7654 | //if(debug) |
7655 | //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (checksum %x)",Count,next_interupt,mchecksum()); |
7656 | //DebugMessage(M64MSG_VERBOSE, "fpu mapping=%x enabled=%x",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29); |
7657 | /*if(Count>=312978186) { |
7658 | rlist(); |
7659 | }*/ |
7660 | //rlist(); |
7661 | start = (u_int)addr&~3; |
7662 | //assert(((u_int)addr&1)==0); |
7663 | if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) { |
7664 | source = (u_int *)((u_int)SP_DMEM+start-0xa4000000); |
7665 | pagelimit = 0xa4001000; |
7666 | } |
7667 | else if ((int)addr >= 0x80000000 && (int)addr < 0x80800000) { |
7668 | source = (u_int *)((u_int)rdram+start-0x80000000); |
7669 | pagelimit = 0x80800000; |
7670 | } |
7671 | else if ((signed int)addr >= (signed int)0xC0000000) { |
7672 | //DebugMessage(M64MSG_VERBOSE, "addr=%x mm=%x",(u_int)addr,(memory_map[start>>12]<<2)); |
7673 | //if(tlb_LUT_r[start>>12]) |
7674 | //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000); |
7675 | if((signed int)memory_map[start>>12]>=0) { |
7676 | source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2))); |
7677 | pagelimit=(start+4096)&0xFFFFF000; |
7678 | int map=memory_map[start>>12]; |
7679 | int i; |
7680 | for(i=0;i<5;i++) { |
7681 | //DebugMessage(M64MSG_VERBOSE, "start: %x next: %x",map,memory_map[pagelimit>>12]); |
7682 | if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096; |
7683 | } |
7684 | assem_debug("pagelimit=%x",pagelimit); |
7685 | assem_debug("mapping=%x (%x)",memory_map[start>>12],(memory_map[start>>12]<<2)+start); |
7686 | } |
7687 | else { |
7688 | assem_debug("Compile at unmapped memory address: %x ", (int)addr); |
7689 | //assem_debug("start: %x next: %x",memory_map[start>>12],memory_map[(start+4096)>>12]); |
7690 | return 1; // Caller will invoke exception handler |
7691 | } |
7692 | //DebugMessage(M64MSG_VERBOSE, "source= %x",(int)source); |
7693 | } |
7694 | else { |
7695 | //DebugMessage(M64MSG_VERBOSE, "Compile at bogus memory address: %x ", (int)addr); |
7696 | log_message("Compile at bogus memory address: %x", (int)addr); |
7697 | exit(1); |
7698 | } |
7699 | |
7700 | /* Pass 1: disassemble */ |
7701 | /* Pass 2: register dependencies, branch targets */ |
7702 | /* Pass 3: register allocation */ |
7703 | /* Pass 4: branch dependencies */ |
7704 | /* Pass 5: pre-alloc */ |
7705 | /* Pass 6: optimize clean/dirty state */ |
7706 | /* Pass 7: flag 32-bit registers */ |
7707 | /* Pass 8: assembly */ |
7708 | /* Pass 9: linker */ |
7709 | /* Pass 10: garbage collection / free memory */ |
7710 | |
7711 | int i,j; |
7712 | int done=0; |
7713 | unsigned int type,op,op2; |
7714 | |
7715 | //DebugMessage(M64MSG_VERBOSE, "addr = %x source = %x %x", addr,source,source[0]); |
7716 | |
7717 | /* Pass 1 disassembly */ |
7718 | |
7719 | for(i=0;!done;i++) { |
7720 | bt[i]=0;likely[i]=0;ooo[i]=0;op2=0; |
7721 | minimum_free_regs[i]=0; |
7722 | opcode[i]=op=source[i]>>26; |
7723 | switch(op) |
7724 | { |
7725 | case 0x00: strcpy(insn[i],"special"); type=NI; |
7726 | op2=source[i]&0x3f; |
7727 | switch(op2) |
7728 | { |
7729 | case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break; |
7730 | case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break; |
7731 | case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break; |
7732 | case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break; |
7733 | case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break; |
7734 | case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break; |
7735 | case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break; |
7736 | case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break; |
7737 | case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break; |
7738 | case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break; |
7739 | case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break; |
7740 | case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break; |
7741 | case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break; |
7742 | case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break; |
7743 | case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break; |
7744 | case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break; |
7745 | case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break; |
7746 | case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break; |
7747 | case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break; |
7748 | case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break; |
7749 | case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break; |
7750 | case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break; |
7751 | case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break; |
7752 | case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break; |
7753 | case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break; |
7754 | case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break; |
7755 | case 0x20: strcpy(insn[i],"ADD"); type=ALU; break; |
7756 | case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break; |
7757 | case 0x22: strcpy(insn[i],"SUB"); type=ALU; break; |
7758 | case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break; |
7759 | case 0x24: strcpy(insn[i],"AND"); type=ALU; break; |
7760 | case 0x25: strcpy(insn[i],"OR"); type=ALU; break; |
7761 | case 0x26: strcpy(insn[i],"XOR"); type=ALU; break; |
7762 | case 0x27: strcpy(insn[i],"NOR"); type=ALU; break; |
7763 | case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break; |
7764 | case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break; |
7765 | case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break; |
7766 | case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break; |
7767 | case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break; |
7768 | case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break; |
7769 | case 0x30: strcpy(insn[i],"TGE"); type=NI; break; |
7770 | case 0x31: strcpy(insn[i],"TGEU"); type=NI; break; |
7771 | case 0x32: strcpy(insn[i],"TLT"); type=NI; break; |
7772 | case 0x33: strcpy(insn[i],"TLTU"); type=NI; break; |
7773 | case 0x34: strcpy(insn[i],"TEQ"); type=NI; break; |
7774 | case 0x36: strcpy(insn[i],"TNE"); type=NI; break; |
7775 | case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break; |
7776 | case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break; |
7777 | case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break; |
7778 | case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break; |
7779 | case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break; |
7780 | case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break; |
7781 | } |
7782 | break; |
7783 | case 0x01: strcpy(insn[i],"regimm"); type=NI; |
7784 | op2=(source[i]>>16)&0x1f; |
7785 | switch(op2) |
7786 | { |
7787 | case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break; |
7788 | case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break; |
7789 | case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break; |
7790 | case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break; |
7791 | case 0x08: strcpy(insn[i],"TGEI"); type=NI; break; |
7792 | case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break; |
7793 | case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break; |
7794 | case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break; |
7795 | case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break; |
7796 | case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break; |
7797 | case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break; |
7798 | case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break; |
7799 | case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break; |
7800 | case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break; |
7801 | } |
7802 | break; |
7803 | case 0x02: strcpy(insn[i],"J"); type=UJUMP; break; |
7804 | case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break; |
7805 | case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break; |
7806 | case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break; |
7807 | case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break; |
7808 | case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break; |
7809 | case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break; |
7810 | case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break; |
7811 | case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break; |
7812 | case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break; |
7813 | case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break; |
7814 | case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break; |
7815 | case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break; |
7816 | case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break; |
7817 | case 0x10: strcpy(insn[i],"cop0"); type=NI; |
7818 | op2=(source[i]>>21)&0x1f; |
7819 | switch(op2) |
7820 | { |
7821 | case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break; |
7822 | case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break; |
7823 | case 0x10: strcpy(insn[i],"tlb"); type=NI; |
7824 | switch(source[i]&0x3f) |
7825 | { |
7826 | case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break; |
7827 | case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break; |
7828 | case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break; |
7829 | case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break; |
7830 | case 0x18: strcpy(insn[i],"ERET"); type=COP0; break; |
7831 | } |
7832 | } |
7833 | break; |
7834 | case 0x11: strcpy(insn[i],"cop1"); type=NI; |
7835 | op2=(source[i]>>21)&0x1f; |
7836 | switch(op2) |
7837 | { |
7838 | case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break; |
7839 | case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break; |
7840 | case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break; |
7841 | case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break; |
7842 | case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break; |
7843 | case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break; |
7844 | case 0x08: strcpy(insn[i],"BC1"); type=FJUMP; |
7845 | switch((source[i]>>16)&0x3) |
7846 | { |
7847 | case 0x00: strcpy(insn[i],"BC1F"); break; |
7848 | case 0x01: strcpy(insn[i],"BC1T"); break; |
7849 | case 0x02: strcpy(insn[i],"BC1FL"); break; |
7850 | case 0x03: strcpy(insn[i],"BC1TL"); break; |
7851 | } |
7852 | break; |
7853 | case 0x10: strcpy(insn[i],"C1.S"); type=NI; |
7854 | switch(source[i]&0x3f) |
7855 | { |
7856 | case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break; |
7857 | case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break; |
7858 | case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break; |
7859 | case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break; |
7860 | case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break; |
7861 | case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break; |
7862 | case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break; |
7863 | case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break; |
7864 | case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break; |
7865 | case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break; |
7866 | case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break; |
7867 | case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break; |
7868 | case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break; |
7869 | case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break; |
7870 | case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break; |
7871 | case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break; |
7872 | case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break; |
7873 | case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break; |
7874 | case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break; |
7875 | case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break; |
7876 | case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break; |
7877 | case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break; |
7878 | case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break; |
7879 | case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break; |
7880 | case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break; |
7881 | case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break; |
7882 | case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break; |
7883 | case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break; |
7884 | case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break; |
7885 | case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break; |
7886 | case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break; |
7887 | case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break; |
7888 | case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break; |
7889 | case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break; |
7890 | case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break; |
7891 | } |
7892 | break; |
7893 | case 0x11: strcpy(insn[i],"C1.D"); type=NI; |
7894 | switch(source[i]&0x3f) |
7895 | { |
7896 | case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break; |
7897 | case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break; |
7898 | case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break; |
7899 | case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break; |
7900 | case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break; |
7901 | case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break; |
7902 | case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break; |
7903 | case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break; |
7904 | case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break; |
7905 | case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break; |
7906 | case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break; |
7907 | case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break; |
7908 | case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break; |
7909 | case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break; |
7910 | case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break; |
7911 | case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break; |
7912 | case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break; |
7913 | case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break; |
7914 | case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break; |
7915 | case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break; |
7916 | case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break; |
7917 | case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break; |
7918 | case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break; |
7919 | case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break; |
7920 | case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break; |
7921 | case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break; |
7922 | case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break; |
7923 | case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break; |
7924 | case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break; |
7925 | case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break; |
7926 | case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break; |
7927 | case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break; |
7928 | case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break; |
7929 | case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break; |
7930 | case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break; |
7931 | } |
7932 | break; |
7933 | case 0x14: strcpy(insn[i],"C1.W"); type=NI; |
7934 | switch(source[i]&0x3f) |
7935 | { |
7936 | case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break; |
7937 | case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break; |
7938 | } |
7939 | break; |
7940 | case 0x15: strcpy(insn[i],"C1.L"); type=NI; |
7941 | switch(source[i]&0x3f) |
7942 | { |
7943 | case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break; |
7944 | case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break; |
7945 | } |
7946 | break; |
7947 | } |
7948 | break; |
7949 | case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break; |
7950 | case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break; |
7951 | case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break; |
7952 | case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break; |
7953 | case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break; |
7954 | case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break; |
7955 | case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break; |
7956 | case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break; |
7957 | case 0x20: strcpy(insn[i],"LB"); type=LOAD; break; |
7958 | case 0x21: strcpy(insn[i],"LH"); type=LOAD; break; |
7959 | case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break; |
7960 | case 0x23: strcpy(insn[i],"LW"); type=LOAD; break; |
7961 | case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break; |
7962 | case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break; |
7963 | case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break; |
7964 | case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break; |
7965 | case 0x28: strcpy(insn[i],"SB"); type=STORE; break; |
7966 | case 0x29: strcpy(insn[i],"SH"); type=STORE; break; |
7967 | case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break; |
7968 | case 0x2B: strcpy(insn[i],"SW"); type=STORE; break; |
7969 | case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break; |
7970 | case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break; |
7971 | case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break; |
7972 | case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break; |
7973 | case 0x30: strcpy(insn[i],"LL"); type=NI; break; |
7974 | case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break; |
7975 | case 0x34: strcpy(insn[i],"LLD"); type=NI; break; |
7976 | case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break; |
7977 | case 0x37: strcpy(insn[i],"LD"); type=LOAD; break; |
7978 | case 0x38: strcpy(insn[i],"SC"); type=NI; break; |
7979 | case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break; |
7980 | case 0x3C: strcpy(insn[i],"SCD"); type=NI; break; |
7981 | case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break; |
7982 | case 0x3F: strcpy(insn[i],"SD"); type=STORE; break; |
7983 | default: strcpy(insn[i],"???"); type=NI; break; |
7984 | } |
7985 | itype[i]=type; |
7986 | opcode2[i]=op2; |
7987 | /* Get registers/immediates */ |
7988 | lt1[i]=0; |
7989 | us1[i]=0; |
7990 | us2[i]=0; |
7991 | dep1[i]=0; |
7992 | dep2[i]=0; |
7993 | switch(type) { |
7994 | case LOAD: |
7995 | rs1[i]=(source[i]>>21)&0x1f; |
7996 | rs2[i]=0; |
7997 | rt1[i]=(source[i]>>16)&0x1f; |
7998 | rt2[i]=0; |
7999 | imm[i]=(short)source[i]; |
8000 | break; |
8001 | case STORE: |
8002 | case STORELR: |
8003 | rs1[i]=(source[i]>>21)&0x1f; |
8004 | rs2[i]=(source[i]>>16)&0x1f; |
8005 | rt1[i]=0; |
8006 | rt2[i]=0; |
8007 | imm[i]=(short)source[i]; |
8008 | if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD |
8009 | break; |
8010 | case LOADLR: |
8011 | // LWL/LWR only load part of the register, |
8012 | // therefore the target register must be treated as a source too |
8013 | rs1[i]=(source[i]>>21)&0x1f; |
8014 | rs2[i]=(source[i]>>16)&0x1f; |
8015 | rt1[i]=(source[i]>>16)&0x1f; |
8016 | rt2[i]=0; |
8017 | imm[i]=(short)source[i]; |
8018 | if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL |
8019 | if(op==0x26) dep1[i]=rt1[i]; // LWR |
8020 | break; |
8021 | case IMM16: |
8022 | if (op==0x0f) rs1[i]=0; // LUI instruction has no source register |
8023 | else rs1[i]=(source[i]>>21)&0x1f; |
8024 | rs2[i]=0; |
8025 | rt1[i]=(source[i]>>16)&0x1f; |
8026 | rt2[i]=0; |
8027 | if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI |
8028 | imm[i]=(unsigned short)source[i]; |
8029 | }else{ |
8030 | imm[i]=(short)source[i]; |
8031 | } |
8032 | if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU |
8033 | if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU |
8034 | if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI |
8035 | break; |
8036 | case UJUMP: |
8037 | rs1[i]=0; |
8038 | rs2[i]=0; |
8039 | rt1[i]=0; |
8040 | rt2[i]=0; |
8041 | // The JAL instruction writes to r31. |
8042 | if (op&1) { |
8043 | rt1[i]=31; |
8044 | } |
8045 | rs2[i]=CCREG; |
8046 | break; |
8047 | case RJUMP: |
8048 | rs1[i]=(source[i]>>21)&0x1f; |
8049 | rs2[i]=0; |
8050 | rt1[i]=0; |
8051 | rt2[i]=0; |
8052 | // The JALR instruction writes to rd. |
8053 | if (op2&1) { |
8054 | rt1[i]=(source[i]>>11)&0x1f; |
8055 | } |
8056 | rs2[i]=CCREG; |
8057 | break; |
8058 | case CJUMP: |
8059 | rs1[i]=(source[i]>>21)&0x1f; |
8060 | rs2[i]=(source[i]>>16)&0x1f; |
8061 | rt1[i]=0; |
8062 | rt2[i]=0; |
8063 | if(op&2) { // BGTZ/BLEZ |
8064 | rs2[i]=0; |
8065 | } |
8066 | us1[i]=rs1[i]; |
8067 | us2[i]=rs2[i]; |
8068 | likely[i]=op>>4; |
8069 | break; |
8070 | case SJUMP: |
8071 | rs1[i]=(source[i]>>21)&0x1f; |
8072 | rs2[i]=CCREG; |
8073 | rt1[i]=0; |
8074 | rt2[i]=0; |
8075 | us1[i]=rs1[i]; |
8076 | if(op2&0x10) { // BxxAL |
8077 | rt1[i]=31; |
8078 | // NOTE: If the branch is not taken, r31 is still overwritten |
8079 | } |
8080 | likely[i]=(op2&2)>>1; |
8081 | break; |
8082 | case FJUMP: |
8083 | rs1[i]=FSREG; |
8084 | rs2[i]=CSREG; |
8085 | rt1[i]=0; |
8086 | rt2[i]=0; |
8087 | likely[i]=((source[i])>>17)&1; |
8088 | break; |
8089 | case ALU: |
8090 | rs1[i]=(source[i]>>21)&0x1f; // source |
8091 | rs2[i]=(source[i]>>16)&0x1f; // subtract amount |
8092 | rt1[i]=(source[i]>>11)&0x1f; // destination |
8093 | rt2[i]=0; |
8094 | if(op2==0x2a||op2==0x2b) { // SLT/SLTU |
8095 | us1[i]=rs1[i];us2[i]=rs2[i]; |
8096 | } |
8097 | else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR |
8098 | dep1[i]=rs1[i];dep2[i]=rs2[i]; |
8099 | } |
8100 | else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB |
8101 | dep1[i]=rs1[i];dep2[i]=rs2[i]; |
8102 | } |
8103 | break; |
8104 | case MULTDIV: |
8105 | rs1[i]=(source[i]>>21)&0x1f; // source |
8106 | rs2[i]=(source[i]>>16)&0x1f; // divisor |
8107 | rt1[i]=HIREG; |
8108 | rt2[i]=LOREG; |
8109 | if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU |
8110 | us1[i]=rs1[i];us2[i]=rs2[i]; |
8111 | } |
8112 | break; |
8113 | case MOV: |
8114 | rs1[i]=0; |
8115 | rs2[i]=0; |
8116 | rt1[i]=0; |
8117 | rt2[i]=0; |
8118 | if(op2==0x10) rs1[i]=HIREG; // MFHI |
8119 | if(op2==0x11) rt1[i]=HIREG; // MTHI |
8120 | if(op2==0x12) rs1[i]=LOREG; // MFLO |
8121 | if(op2==0x13) rt1[i]=LOREG; // MTLO |
8122 | if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx |
8123 | if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx |
8124 | dep1[i]=rs1[i]; |
8125 | break; |
8126 | case SHIFT: |
8127 | rs1[i]=(source[i]>>16)&0x1f; // target of shift |
8128 | rs2[i]=(source[i]>>21)&0x1f; // shift amount |
8129 | rt1[i]=(source[i]>>11)&0x1f; // destination |
8130 | rt2[i]=0; |
8131 | // DSLLV/DSRLV/DSRAV are 64-bit |
8132 | if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i]; |
8133 | break; |
8134 | case SHIFTIMM: |
8135 | rs1[i]=(source[i]>>16)&0x1f; |
8136 | rs2[i]=0; |
8137 | rt1[i]=(source[i]>>11)&0x1f; |
8138 | rt2[i]=0; |
8139 | imm[i]=(source[i]>>6)&0x1f; |
8140 | // DSxx32 instructions |
8141 | if(op2>=0x3c) imm[i]|=0x20; |
8142 | // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source |
8143 | if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i]; |
8144 | break; |
8145 | case COP0: |
8146 | rs1[i]=0; |
8147 | rs2[i]=0; |
8148 | rt1[i]=0; |
8149 | rt2[i]=0; |
8150 | if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0 |
8151 | if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0 |
8152 | if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status |
8153 | if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET |
8154 | break; |
8155 | case COP1: |
8156 | rs1[i]=0; |
8157 | rs2[i]=0; |
8158 | rt1[i]=0; |
8159 | rt2[i]=0; |
8160 | if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1 |
8161 | if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1 |
8162 | if(op2==5) us1[i]=rs1[i]; // DMTC1 |
8163 | rs2[i]=CSREG; |
8164 | break; |
8165 | case C1LS: |
8166 | rs1[i]=(source[i]>>21)&0x1F; |
8167 | rs2[i]=CSREG; |
8168 | rt1[i]=0; |
8169 | rt2[i]=0; |
8170 | imm[i]=(short)source[i]; |
8171 | break; |
8172 | case FLOAT: |
8173 | case FCONV: |
8174 | rs1[i]=0; |
8175 | rs2[i]=CSREG; |
8176 | rt1[i]=0; |
8177 | rt2[i]=0; |
8178 | break; |
8179 | case FCOMP: |
8180 | rs1[i]=FSREG; |
8181 | rs2[i]=CSREG; |
8182 | rt1[i]=FSREG; |
8183 | rt2[i]=0; |
8184 | break; |
8185 | case SYSCALL: |
8186 | rs1[i]=CCREG; |
8187 | rs2[i]=0; |
8188 | rt1[i]=0; |
8189 | rt2[i]=0; |
8190 | break; |
8191 | default: |
8192 | rs1[i]=0; |
8193 | rs2[i]=0; |
8194 | rt1[i]=0; |
8195 | rt2[i]=0; |
8196 | } |
8197 | /* Calculate branch target addresses */ |
8198 | if(type==UJUMP) |
8199 | ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4); |
8200 | else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1)) |
8201 | ba[i]=start+i*4+8; // Ignore never taken branch |
8202 | else if(type==SJUMP&&rs1[i]==0&&!(op2&1)) |
8203 | ba[i]=start+i*4+8; // Ignore never taken branch |
8204 | else if(type==CJUMP||type==SJUMP||type==FJUMP) |
8205 | ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14); |
8206 | else ba[i]=-1; |
8207 | /* Is this the end of the block? */ |
8208 | if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) { |
8209 | if(rt1[i-1]==0) { // Continue past subroutine call (JAL) |
8210 | done=1; |
8211 | // Does the block continue due to a branch? |
8212 | for(j=i-1;j>=0;j--) |
8213 | { |
8214 | if(ba[j]==start+i*4) done=j=0; // Branch into delay slot |
8215 | if(ba[j]==start+i*4+4) done=j=0; |
8216 | if(ba[j]==start+i*4+8) done=j=0; |
8217 | } |
8218 | } |
8219 | else { |
8220 | if(stop_after_jal) done=1; |
8221 | // Stop on BREAK |
8222 | if((source[i+1]&0xfc00003f)==0x0d) done=1; |
8223 | } |
8224 | // Don't recompile stuff that's already compiled |
8225 | if(check_addr(start+i*4+4)) done=1; |
8226 | // Don't get too close to the limit |
8227 | if(i>MAXBLOCK/2) done=1; |
8228 | } |
8229 | if(i>0&&itype[i-1]==SYSCALL&&stop_after_jal) done=1; |
8230 | assert(i<MAXBLOCK-1); |
8231 | if(start+i*4==pagelimit-4) done=1; |
8232 | assert(start+i*4<pagelimit); |
8233 | if (i==MAXBLOCK-1) done=1; |
8234 | // Stop if we're compiling junk |
8235 | if(itype[i]==NI&&opcode[i]==0x11) { |
8236 | done=stop_after_jal=1; |
8237 | DebugMessage(M64MSG_VERBOSE, "Disabled speculative precompilation"); |
8238 | } |
8239 | } |
8240 | slen=i; |
8241 | if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) { |
8242 | if(start+i*4==pagelimit) { |
8243 | itype[i-1]=SPAN; |
8244 | } |
8245 | } |
8246 | assert(slen>0); |
8247 | |
8248 | /* Pass 2 - Register dependencies and branch targets */ |
8249 | |
8250 | unneeded_registers(0,slen-1,0); |
8251 | |
8252 | /* Pass 3 - Register allocation */ |
8253 | |
8254 | struct regstat current; // Current register allocations/status |
8255 | current.is32=1; |
8256 | current.dirty=0; |
8257 | current.u=unneeded_reg[0]; |
8258 | current.uu=unneeded_reg_upper[0]; |
8259 | clear_all_regs(current.regmap); |
8260 | alloc_reg(¤t,0,CCREG); |
8261 | dirty_reg(¤t,CCREG); |
8262 | current.isconst=0; |
8263 | current.wasconst=0; |
8264 | int ds=0; |
8265 | int cc=0; |
8266 | int hr; |
8267 | |
8268 | provisional_32bit(); |
8269 | |
8270 | if((u_int)addr&1) { |
8271 | // First instruction is delay slot |
8272 | cc=-1; |
8273 | bt[1]=1; |
8274 | ds=1; |
8275 | unneeded_reg[0]=1; |
8276 | unneeded_reg_upper[0]=1; |
8277 | current.regmap[HOST_BTREG]=BTREG; |
8278 | } |
8279 | |
8280 | for(i=0;i<slen;i++) |
8281 | { |
8282 | if(bt[i]) |
8283 | { |
8284 | int hr; |
8285 | for(hr=0;hr<HOST_REGS;hr++) |
8286 | { |
8287 | // Is this really necessary? |
8288 | if(current.regmap[hr]==0) current.regmap[hr]=-1; |
8289 | } |
8290 | current.isconst=0; |
8291 | } |
8292 | if(i>1) |
8293 | { |
8294 | if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL |
8295 | { |
8296 | if(rs1[i-2]==0||rs2[i-2]==0) |
8297 | { |
8298 | if(rs1[i-2]) { |
8299 | current.is32|=1LL<<rs1[i-2]; |
8300 | int hr=get_reg(current.regmap,rs1[i-2]|64); |
8301 | if(hr>=0) current.regmap[hr]=-1; |
8302 | } |
8303 | if(rs2[i-2]) { |
8304 | current.is32|=1LL<<rs2[i-2]; |
8305 | int hr=get_reg(current.regmap,rs2[i-2]|64); |
8306 | if(hr>=0) current.regmap[hr]=-1; |
8307 | } |
8308 | } |
8309 | } |
8310 | } |
8311 | // If something jumps here with 64-bit values |
8312 | // then promote those registers to 64 bits |
8313 | if(bt[i]) |
8314 | { |
8315 | uint64_t temp_is32=current.is32; |
8316 | for(j=i-1;j>=0;j--) |
8317 | { |
8318 | if(ba[j]==start+i*4) |
8319 | temp_is32&=branch_regs[j].is32; |
8320 | } |
8321 | for(j=i;j<slen;j++) |
8322 | { |
8323 | if(ba[j]==start+i*4) |
8324 | //temp_is32=1; |
8325 | temp_is32&=p32[j]; |
8326 | } |
8327 | if(temp_is32!=current.is32) { |
8328 | //DebugMessage(M64MSG_VERBOSE, "dumping 32-bit regs (%x)",start+i*4); |
8329 | #ifndef DESTRUCTIVE_WRITEBACK |
8330 | if(ds) |
8331 | #endif |
8332 | for(hr=0;hr<HOST_REGS;hr++) |
8333 | { |
8334 | int r=current.regmap[hr]; |
8335 | if(r>0&&r<64) |
8336 | { |
8337 | if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) { |
8338 | temp_is32|=1LL<<r; |
8339 | //DebugMessage(M64MSG_VERBOSE, "restore %d",r); |
8340 | } |
8341 | } |
8342 | } |
8343 | current.is32=temp_is32; |
8344 | } |
8345 | } |
8346 | memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap)); |
8347 | regs[i].wasconst=current.isconst; |
8348 | regs[i].was32=current.is32; |
8349 | regs[i].wasdirty=current.dirty; |
8350 | #ifdef DESTRUCTIVE_WRITEBACK |
8351 | // To change a dirty register from 32 to 64 bits, we must write |
8352 | // it out during the previous cycle (for branches, 2 cycles) |
8353 | if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP) |
8354 | { |
8355 | uint64_t temp_is32=current.is32; |
8356 | for(j=i-1;j>=0;j--) |
8357 | { |
8358 | if(ba[j]==start+i*4+4) |
8359 | temp_is32&=branch_regs[j].is32; |
8360 | } |
8361 | for(j=i;j<slen;j++) |
8362 | { |
8363 | if(ba[j]==start+i*4+4) |
8364 | //temp_is32=1; |
8365 | temp_is32&=p32[j]; |
8366 | } |
8367 | if(temp_is32!=current.is32) { |
8368 | //DebugMessage(M64MSG_VERBOSE, "pre-dumping 32-bit regs (%x)",start+i*4); |
8369 | for(hr=0;hr<HOST_REGS;hr++) |
8370 | { |
8371 | int r=current.regmap[hr]; |
8372 | if(r>0) |
8373 | { |
8374 | if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) { |
8375 | if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) |
8376 | { |
8377 | if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)) |
8378 | { |
8379 | //DebugMessage(M64MSG_VERBOSE, "dump %d/r%d",hr,r); |
8380 | current.regmap[hr]=-1; |
8381 | if(get_reg(current.regmap,r|64)>=0) |
8382 | current.regmap[get_reg(current.regmap,r|64)]=-1; |
8383 | } |
8384 | } |
8385 | } |
8386 | } |
8387 | } |
8388 | } |
8389 | } |
8390 | else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)) |
8391 | { |
8392 | uint64_t temp_is32=current.is32; |
8393 | for(j=i-1;j>=0;j--) |
8394 | { |
8395 | if(ba[j]==start+i*4+8) |
8396 | temp_is32&=branch_regs[j].is32; |
8397 | } |
8398 | for(j=i;j<slen;j++) |
8399 | { |
8400 | if(ba[j]==start+i*4+8) |
8401 | //temp_is32=1; |
8402 | temp_is32&=p32[j]; |
8403 | } |
8404 | if(temp_is32!=current.is32) { |
8405 | //DebugMessage(M64MSG_VERBOSE, "pre-dumping 32-bit regs (%x)",start+i*4); |
8406 | for(hr=0;hr<HOST_REGS;hr++) |
8407 | { |
8408 | int r=current.regmap[hr]; |
8409 | if(r>0) |
8410 | { |
8411 | if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) { |
8412 | if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63)) |
8413 | { |
8414 | //DebugMessage(M64MSG_VERBOSE, "dump %d/r%d",hr,r); |
8415 | current.regmap[hr]=-1; |
8416 | if(get_reg(current.regmap,r|64)>=0) |
8417 | current.regmap[get_reg(current.regmap,r|64)]=-1; |
8418 | } |
8419 | } |
8420 | } |
8421 | } |
8422 | } |
8423 | } |
8424 | #endif |
8425 | if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) { |
8426 | if(i+1<slen) { |
8427 | current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i])); |
8428 | current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i])); |
8429 | if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i])); |
8430 | current.u|=1; |
8431 | current.uu|=1; |
8432 | } else { |
8433 | current.u=1; |
8434 | current.uu=1; |
8435 | } |
8436 | } else { |
8437 | if(i+1<slen) { |
8438 | current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1])); |
8439 | current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1])); |
8440 | if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1])); |
8441 | current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i])); |
8442 | current.uu&=~((1LL<<us1[i])|(1LL<<us2[i])); |
8443 | current.u|=1; |
8444 | current.uu|=1; |
8445 | } else { DebugMessage(M64MSG_ERROR, "oops, branch at end of block with no delay slot");exit(1); } |
8446 | } |
8447 | is_ds[i]=ds; |
8448 | if(ds) { |
8449 | ds=0; // Skip delay slot, already allocated as part of branch |
8450 | // ...but we need to alloc it in case something jumps here |
8451 | if(i+1<slen) { |
8452 | current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1]; |
8453 | current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1]; |
8454 | }else{ |
8455 | current.u=branch_unneeded_reg[i-1]; |
8456 | current.uu=branch_unneeded_reg_upper[i-1]; |
8457 | } |
8458 | current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i])); |
8459 | current.uu&=~((1LL<<us1[i])|(1LL<<us2[i])); |
8460 | if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i])); |
8461 | current.u|=1; |
8462 | current.uu|=1; |
8463 | struct regstat temp; |
8464 | memcpy(&temp,¤t,sizeof(current)); |
8465 | temp.wasdirty=temp.dirty; |
8466 | temp.was32=temp.is32; |
8467 | // TODO: Take into account unconditional branches, as below |
8468 | delayslot_alloc(&temp,i); |
8469 | memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap)); |
8470 | regs[i].wasdirty=temp.wasdirty; |
8471 | regs[i].was32=temp.was32; |
8472 | regs[i].dirty=temp.dirty; |
8473 | regs[i].is32=temp.is32; |
8474 | regs[i].isconst=0; |
8475 | regs[i].wasconst=0; |
8476 | current.isconst=0; |
8477 | // Create entry (branch target) regmap |
8478 | for(hr=0;hr<HOST_REGS;hr++) |
8479 | { |
8480 | int r=temp.regmap[hr]; |
8481 | if(r>=0) { |
8482 | if(r!=regmap_pre[i][hr]) { |
8483 | regs[i].regmap_entry[hr]=-1; |
8484 | } |
8485 | else |
8486 | { |
8487 | if(r<64){ |
8488 | if((current.u>>r)&1) { |
8489 | regs[i].regmap_entry[hr]=-1; |
8490 | regs[i].regmap[hr]=-1; |
8491 | //Don't clear regs in the delay slot as the branch might need them |
8492 | //current.regmap[hr]=-1; |
8493 | }else |
8494 | regs[i].regmap_entry[hr]=r; |
8495 | } |
8496 | else { |
8497 | if((current.uu>>(r&63))&1) { |
8498 | regs[i].regmap_entry[hr]=-1; |
8499 | regs[i].regmap[hr]=-1; |
8500 | //Don't clear regs in the delay slot as the branch might need them |
8501 | //current.regmap[hr]=-1; |
8502 | }else |
8503 | regs[i].regmap_entry[hr]=r; |
8504 | } |
8505 | } |
8506 | } else { |
8507 | // First instruction expects CCREG to be allocated |
8508 | if(i==0&&hr==HOST_CCREG) |
8509 | regs[i].regmap_entry[hr]=CCREG; |
8510 | else |
8511 | regs[i].regmap_entry[hr]=-1; |
8512 | } |
8513 | } |
8514 | } |
8515 | else { // Not delay slot |
8516 | switch(itype[i]) { |
8517 | case UJUMP: |
8518 | //current.isconst=0; // DEBUG |
8519 | //current.wasconst=0; // DEBUG |
8520 | //regs[i].wasconst=0; // DEBUG |
8521 | clear_const(¤t,rt1[i]); |
8522 | alloc_cc(¤t,i); |
8523 | dirty_reg(¤t,CCREG); |
8524 | if (rt1[i]==31) { |
8525 | alloc_reg(¤t,i,31); |
8526 | dirty_reg(¤t,31); |
8527 | assert(rs1[i+1]!=31&&rs2[i+1]!=31); |
8528 | #ifdef REG_PREFETCH |
8529 | alloc_reg(¤t,i,PTEMP); |
8530 | #endif |
8531 | //current.is32|=1LL<<rt1[i]; |
8532 | } |
8533 | ooo[i]=1; |
8534 | delayslot_alloc(¤t,i+1); |
8535 | //current.isconst=0; // DEBUG |
8536 | ds=1; |
8537 | //DebugMessage(M64MSG_VERBOSE, "i=%d, isconst=%x",i,current.isconst); |
8538 | break; |
8539 | case RJUMP: |
8540 | //current.isconst=0; |
8541 | //current.wasconst=0; |
8542 | //regs[i].wasconst=0; |
8543 | clear_const(¤t,rs1[i]); |
8544 | clear_const(¤t,rt1[i]); |
8545 | alloc_cc(¤t,i); |
8546 | dirty_reg(¤t,CCREG); |
8547 | if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) { |
8548 | alloc_reg(¤t,i,rs1[i]); |
8549 | if (rt1[i]!=0) { |
8550 | alloc_reg(¤t,i,rt1[i]); |
8551 | dirty_reg(¤t,rt1[i]); |
8552 | assert(rs1[i+1]!=31&&rs2[i+1]!=31); |
8553 | #ifdef REG_PREFETCH |
8554 | alloc_reg(¤t,i,PTEMP); |
8555 | #endif |
8556 | } |
8557 | #ifdef USE_MINI_HT |
8558 | if(rs1[i]==31) { // JALR |
8559 | alloc_reg(¤t,i,RHASH); |
8560 | #ifndef HOST_IMM_ADDR32 |
8561 | alloc_reg(¤t,i,RHTBL); |
8562 | #endif |
8563 | } |
8564 | #endif |
8565 | delayslot_alloc(¤t,i+1); |
8566 | } else { |
8567 | // The delay slot overwrites our source register, |
8568 | // allocate a temporary register to hold the old value. |
8569 | current.isconst=0; |
8570 | current.wasconst=0; |
8571 | regs[i].wasconst=0; |
8572 | delayslot_alloc(¤t,i+1); |
8573 | current.isconst=0; |
8574 | alloc_reg(¤t,i,RTEMP); |
8575 | } |
8576 | //current.isconst=0; // DEBUG |
8577 | ooo[i]=1; |
8578 | ds=1; |
8579 | break; |
8580 | case CJUMP: |
8581 | //current.isconst=0; |
8582 | //current.wasconst=0; |
8583 | //regs[i].wasconst=0; |
8584 | clear_const(¤t,rs1[i]); |
8585 | clear_const(¤t,rs2[i]); |
8586 | if((opcode[i]&0x3E)==4) // BEQ/BNE |
8587 | { |
8588 | alloc_cc(¤t,i); |
8589 | dirty_reg(¤t,CCREG); |
8590 | if(rs1[i]) alloc_reg(¤t,i,rs1[i]); |
8591 | if(rs2[i]) alloc_reg(¤t,i,rs2[i]); |
8592 | if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1)) |
8593 | { |
8594 | if(rs1[i]) alloc_reg64(¤t,i,rs1[i]); |
8595 | if(rs2[i]) alloc_reg64(¤t,i,rs2[i]); |
8596 | } |
8597 | if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))|| |
8598 | (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) { |
8599 | // The delay slot overwrites one of our conditions. |
8600 | // Allocate the branch condition registers instead. |
8601 | current.isconst=0; |
8602 | current.wasconst=0; |
8603 | regs[i].wasconst=0; |
8604 | if(rs1[i]) alloc_reg(¤t,i,rs1[i]); |
8605 | if(rs2[i]) alloc_reg(¤t,i,rs2[i]); |
8606 | if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1)) |
8607 | { |
8608 | if(rs1[i]) alloc_reg64(¤t,i,rs1[i]); |
8609 | if(rs2[i]) alloc_reg64(¤t,i,rs2[i]); |
8610 | } |
8611 | } |
8612 | else |
8613 | { |
8614 | ooo[i]=1; |
8615 | delayslot_alloc(¤t,i+1); |
8616 | } |
8617 | } |
8618 | else |
8619 | if((opcode[i]&0x3E)==6) // BLEZ/BGTZ |
8620 | { |
8621 | alloc_cc(¤t,i); |
8622 | dirty_reg(¤t,CCREG); |
8623 | alloc_reg(¤t,i,rs1[i]); |
8624 | if(!(current.is32>>rs1[i]&1)) |
8625 | { |
8626 | alloc_reg64(¤t,i,rs1[i]); |
8627 | } |
8628 | if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) { |
8629 | // The delay slot overwrites one of our conditions. |
8630 | // Allocate the branch condition registers instead. |
8631 | current.isconst=0; |
8632 | current.wasconst=0; |
8633 | regs[i].wasconst=0; |
8634 | if(rs1[i]) alloc_reg(¤t,i,rs1[i]); |
8635 | if(!((current.is32>>rs1[i])&1)) |
8636 | { |
8637 | if(rs1[i]) alloc_reg64(¤t,i,rs1[i]); |
8638 | } |
8639 | } |
8640 | else |
8641 | { |
8642 | ooo[i]=1; |
8643 | delayslot_alloc(¤t,i+1); |
8644 | } |
8645 | } |
8646 | else |
8647 | // Don't alloc the delay slot yet because we might not execute it |
8648 | if((opcode[i]&0x3E)==0x14) // BEQL/BNEL |
8649 | { |
8650 | current.isconst=0; |
8651 | current.wasconst=0; |
8652 | regs[i].wasconst=0; |
8653 | alloc_cc(¤t,i); |
8654 | dirty_reg(¤t,CCREG); |
8655 | alloc_reg(¤t,i,rs1[i]); |
8656 | alloc_reg(¤t,i,rs2[i]); |
8657 | if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1)) |
8658 | { |
8659 | alloc_reg64(¤t,i,rs1[i]); |
8660 | alloc_reg64(¤t,i,rs2[i]); |
8661 | } |
8662 | } |
8663 | else |
8664 | if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL |
8665 | { |
8666 | current.isconst=0; |
8667 | current.wasconst=0; |
8668 | regs[i].wasconst=0; |
8669 | alloc_cc(¤t,i); |
8670 | dirty_reg(¤t,CCREG); |
8671 | alloc_reg(¤t,i,rs1[i]); |
8672 | if(!(current.is32>>rs1[i]&1)) |
8673 | { |
8674 | alloc_reg64(¤t,i,rs1[i]); |
8675 | } |
8676 | } |
8677 | ds=1; |
8678 | //current.isconst=0; |
8679 | break; |
8680 | case SJUMP: |
8681 | //current.isconst=0; |
8682 | //current.wasconst=0; |
8683 | //regs[i].wasconst=0; |
8684 | clear_const(¤t,rs1[i]); |
8685 | clear_const(¤t,rt1[i]); |
8686 | //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ |
8687 | if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ |
8688 | { |
8689 | alloc_cc(¤t,i); |
8690 | dirty_reg(¤t,CCREG); |
8691 | alloc_reg(¤t,i,rs1[i]); |
8692 | if(!(current.is32>>rs1[i]&1)) |
8693 | { |
8694 | alloc_reg64(¤t,i,rs1[i]); |
8695 | } |
8696 | if (rt1[i]==31) { // BLTZAL/BGEZAL |
8697 | alloc_reg(¤t,i,31); |
8698 | dirty_reg(¤t,31); |
8699 | assert(rs1[i+1]!=31&&rs2[i+1]!=31); |
8700 | //#ifdef REG_PREFETCH |
8701 | //alloc_reg(¤t,i,PTEMP); |
8702 | //#endif |
8703 | //current.is32|=1LL<<rt1[i]; |
8704 | } |
8705 | if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) { |
8706 | // The delay slot overwrites the branch condition. |
8707 | // Allocate the branch condition registers instead. |
8708 | current.isconst=0; |
8709 | current.wasconst=0; |
8710 | regs[i].wasconst=0; |
8711 | if(rs1[i]) alloc_reg(¤t,i,rs1[i]); |
8712 | if(!((current.is32>>rs1[i])&1)) |
8713 | { |
8714 | if(rs1[i]) alloc_reg64(¤t,i,rs1[i]); |
8715 | } |
8716 | } |
8717 | else |
8718 | { |
8719 | ooo[i]=1; |
8720 | delayslot_alloc(¤t,i+1); |
8721 | } |
8722 | } |
8723 | else |
8724 | // Don't alloc the delay slot yet because we might not execute it |
8725 | if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL |
8726 | { |
8727 | current.isconst=0; |
8728 | current.wasconst=0; |
8729 | regs[i].wasconst=0; |
8730 | alloc_cc(¤t,i); |
8731 | dirty_reg(¤t,CCREG); |
8732 | alloc_reg(¤t,i,rs1[i]); |
8733 | if(!(current.is32>>rs1[i]&1)) |
8734 | { |
8735 | alloc_reg64(¤t,i,rs1[i]); |
8736 | } |
8737 | } |
8738 | ds=1; |
8739 | //current.isconst=0; |
8740 | break; |
8741 | case FJUMP: |
8742 | current.isconst=0; |
8743 | current.wasconst=0; |
8744 | regs[i].wasconst=0; |
8745 | if(likely[i]==0) // BC1F/BC1T |
8746 | { |
8747 | // TODO: Theoretically we can run out of registers here on x86. |
8748 | // The delay slot can allocate up to six, and we need to check |
8749 | // CSREG before executing the delay slot. Possibly we can drop |
8750 | // the cycle count and then reload it after checking that the |
8751 | // FPU is in a usable state, or don't do out-of-order execution. |
8752 | alloc_cc(¤t,i); |
8753 | dirty_reg(¤t,CCREG); |
8754 | alloc_reg(¤t,i,FSREG); |
8755 | alloc_reg(¤t,i,CSREG); |
8756 | if(itype[i+1]==FCOMP) { |
8757 | // The delay slot overwrites the branch condition. |
8758 | // Allocate the branch condition registers instead. |
8759 | alloc_cc(¤t,i); |
8760 | dirty_reg(¤t,CCREG); |
8761 | alloc_reg(¤t,i,CSREG); |
8762 | alloc_reg(¤t,i,FSREG); |
8763 | } |
8764 | else { |
8765 | ooo[i]=1; |
8766 | delayslot_alloc(¤t,i+1); |
8767 | alloc_reg(¤t,i+1,CSREG); |
8768 | } |
8769 | } |
8770 | else |
8771 | // Don't alloc the delay slot yet because we might not execute it |
8772 | if(likely[i]) // BC1FL/BC1TL |
8773 | { |
8774 | alloc_cc(¤t,i); |
8775 | dirty_reg(¤t,CCREG); |
8776 | alloc_reg(¤t,i,CSREG); |
8777 | alloc_reg(¤t,i,FSREG); |
8778 | } |
8779 | ds=1; |
8780 | current.isconst=0; |
8781 | break; |
8782 | case IMM16: |
8783 | imm16_alloc(¤t,i); |
8784 | break; |
8785 | case LOAD: |
8786 | case LOADLR: |
8787 | load_alloc(¤t,i); |
8788 | break; |
8789 | case STORE: |
8790 | case STORELR: |
8791 | store_alloc(¤t,i); |
8792 | break; |
8793 | case ALU: |
8794 | alu_alloc(¤t,i); |
8795 | break; |
8796 | case SHIFT: |
8797 | shift_alloc(¤t,i); |
8798 | break; |
8799 | case MULTDIV: |
8800 | multdiv_alloc(¤t,i); |
8801 | break; |
8802 | case SHIFTIMM: |
8803 | shiftimm_alloc(¤t,i); |
8804 | break; |
8805 | case MOV: |
8806 | mov_alloc(¤t,i); |
8807 | break; |
8808 | case COP0: |
8809 | cop0_alloc(¤t,i); |
8810 | break; |
8811 | case COP1: |
8812 | cop1_alloc(¤t,i); |
8813 | break; |
8814 | case C1LS: |
8815 | c1ls_alloc(¤t,i); |
8816 | break; |
8817 | case FCONV: |
8818 | fconv_alloc(¤t,i); |
8819 | break; |
8820 | case FLOAT: |
8821 | float_alloc(¤t,i); |
8822 | break; |
8823 | case FCOMP: |
8824 | fcomp_alloc(¤t,i); |
8825 | break; |
8826 | case SYSCALL: |
8827 | syscall_alloc(¤t,i); |
8828 | break; |
8829 | case SPAN: |
8830 | pagespan_alloc(¤t,i); |
8831 | break; |
8832 | } |
8833 | |
8834 | // Drop the upper half of registers that have become 32-bit |
8835 | current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i])); |
8836 | if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) { |
8837 | current.uu&=~((1LL<<us1[i])|(1LL<<us2[i])); |
8838 | if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i])); |
8839 | current.uu|=1; |
8840 | } else { |
8841 | current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1])); |
8842 | current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1])); |
8843 | if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1])); |
8844 | current.uu&=~((1LL<<us1[i])|(1LL<<us2[i])); |
8845 | current.uu|=1; |
8846 | } |
8847 | |
8848 | // Create entry (branch target) regmap |
8849 | for(hr=0;hr<HOST_REGS;hr++) |
8850 | { |
8851 | int r,or; |
8852 | r=current.regmap[hr]; |
8853 | if(r>=0) { |
8854 | if(r!=regmap_pre[i][hr]) { |
8855 | // TODO: delay slot (?) |
8856 | or=get_reg(regmap_pre[i],r); // Get old mapping for this register |
8857 | if(or<0||(r&63)>=TEMPREG){ |
8858 | regs[i].regmap_entry[hr]=-1; |
8859 | } |
8860 | else |
8861 | { |
8862 | // Just move it to a different register |
8863 | regs[i].regmap_entry[hr]=r; |
8864 | // If it was dirty before, it's still dirty |
8865 | if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63); |
8866 | } |
8867 | } |
8868 | else |
8869 | { |
8870 | // Unneeded |
8871 | if(r==0){ |
8872 | regs[i].regmap_entry[hr]=0; |
8873 | } |
8874 | else |
8875 | if(r<64){ |
8876 | if((current.u>>r)&1) { |
8877 | regs[i].regmap_entry[hr]=-1; |
8878 | //regs[i].regmap[hr]=-1; |
8879 | current.regmap[hr]=-1; |
8880 | }else |
8881 | regs[i].regmap_entry[hr]=r; |
8882 | } |
8883 | else { |
8884 | if((current.uu>>(r&63))&1) { |
8885 | regs[i].regmap_entry[hr]=-1; |
8886 | //regs[i].regmap[hr]=-1; |
8887 | current.regmap[hr]=-1; |
8888 | }else |
8889 | regs[i].regmap_entry[hr]=r; |
8890 | } |
8891 | } |
8892 | } else { |
8893 | // Branches expect CCREG to be allocated at the target |
8894 | if(regmap_pre[i][hr]==CCREG) |
8895 | regs[i].regmap_entry[hr]=CCREG; |
8896 | else |
8897 | regs[i].regmap_entry[hr]=-1; |
8898 | } |
8899 | } |
8900 | memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap)); |
8901 | } |
8902 | /* Branch post-alloc */ |
8903 | if(i>0) |
8904 | { |
8905 | current.was32=current.is32; |
8906 | current.wasdirty=current.dirty; |
8907 | switch(itype[i-1]) { |
8908 | case UJUMP: |
8909 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); |
8910 | branch_regs[i-1].isconst=0; |
8911 | branch_regs[i-1].wasconst=0; |
8912 | branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1])); |
8913 | branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1])); |
8914 | alloc_cc(&branch_regs[i-1],i-1); |
8915 | dirty_reg(&branch_regs[i-1],CCREG); |
8916 | if(rt1[i-1]==31) { // JAL |
8917 | alloc_reg(&branch_regs[i-1],i-1,31); |
8918 | dirty_reg(&branch_regs[i-1],31); |
8919 | branch_regs[i-1].is32|=1LL<<31; |
8920 | } |
8921 | memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap)); |
8922 | memcpy(constmap[i],constmap[i-1],sizeof(current.constmap)); |
8923 | break; |
8924 | case RJUMP: |
8925 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); |
8926 | branch_regs[i-1].isconst=0; |
8927 | branch_regs[i-1].wasconst=0; |
8928 | branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1])); |
8929 | branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1])); |
8930 | alloc_cc(&branch_regs[i-1],i-1); |
8931 | dirty_reg(&branch_regs[i-1],CCREG); |
8932 | alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]); |
8933 | if(rt1[i-1]!=0) { // JALR |
8934 | alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]); |
8935 | dirty_reg(&branch_regs[i-1],rt1[i-1]); |
8936 | branch_regs[i-1].is32|=1LL<<rt1[i-1]; |
8937 | } |
8938 | #ifdef USE_MINI_HT |
8939 | if(rs1[i-1]==31) { // JALR |
8940 | alloc_reg(&branch_regs[i-1],i-1,RHASH); |
8941 | #ifndef HOST_IMM_ADDR32 |
8942 | alloc_reg(&branch_regs[i-1],i-1,RHTBL); |
8943 | #endif |
8944 | } |
8945 | #endif |
8946 | memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap)); |
8947 | memcpy(constmap[i],constmap[i-1],sizeof(current.constmap)); |
8948 | break; |
8949 | case CJUMP: |
8950 | if((opcode[i-1]&0x3E)==4) // BEQ/BNE |
8951 | { |
8952 | alloc_cc(¤t,i-1); |
8953 | dirty_reg(¤t,CCREG); |
8954 | if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))|| |
8955 | (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) { |
8956 | // The delay slot overwrote one of our conditions |
8957 | // Delay slot goes after the test (in order) |
8958 | current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])); |
8959 | current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])); |
8960 | if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i])); |
8961 | current.u|=1; |
8962 | current.uu|=1; |
8963 | delayslot_alloc(¤t,i); |
8964 | current.isconst=0; |
8965 | } |
8966 | else |
8967 | { |
8968 | current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1])); |
8969 | current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1])); |
8970 | // Alloc the branch condition registers |
8971 | if(rs1[i-1]) alloc_reg(¤t,i-1,rs1[i-1]); |
8972 | if(rs2[i-1]) alloc_reg(¤t,i-1,rs2[i-1]); |
8973 | if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1)) |
8974 | { |
8975 | if(rs1[i-1]) alloc_reg64(¤t,i-1,rs1[i-1]); |
8976 | if(rs2[i-1]) alloc_reg64(¤t,i-1,rs2[i-1]); |
8977 | } |
8978 | } |
8979 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); |
8980 | branch_regs[i-1].isconst=0; |
8981 | branch_regs[i-1].wasconst=0; |
8982 | memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap)); |
8983 | memcpy(constmap[i],constmap[i-1],sizeof(current.constmap)); |
8984 | } |
8985 | else |
8986 | if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ |
8987 | { |
8988 | alloc_cc(¤t,i-1); |
8989 | dirty_reg(¤t,CCREG); |
8990 | if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) { |
8991 | // The delay slot overwrote the branch condition |
8992 | // Delay slot goes after the test (in order) |
8993 | current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])); |
8994 | current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])); |
8995 | if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i])); |
8996 | current.u|=1; |
8997 | current.uu|=1; |
8998 | delayslot_alloc(¤t,i); |
8999 | current.isconst=0; |
9000 | } |
9001 | else |
9002 | { |
9003 | current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]); |
9004 | current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]); |
9005 | // Alloc the branch condition register |
9006 | alloc_reg(¤t,i-1,rs1[i-1]); |
9007 | if(!(current.is32>>rs1[i-1]&1)) |
9008 | { |
9009 | alloc_reg64(¤t,i-1,rs1[i-1]); |
9010 | } |
9011 | } |
9012 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); |
9013 | branch_regs[i-1].isconst=0; |
9014 | branch_regs[i-1].wasconst=0; |
9015 | memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap)); |
9016 | memcpy(constmap[i],constmap[i-1],sizeof(current.constmap)); |
9017 | } |
9018 | else |
9019 | // Alloc the delay slot in case the branch is taken |
9020 | if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL |
9021 | { |
9022 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); |
9023 | branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1; |
9024 | branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1; |
9025 | if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1; |
9026 | alloc_cc(&branch_regs[i-1],i); |
9027 | dirty_reg(&branch_regs[i-1],CCREG); |
9028 | delayslot_alloc(&branch_regs[i-1],i); |
9029 | branch_regs[i-1].isconst=0; |
9030 | alloc_reg(¤t,i,CCREG); // Not taken path |
9031 | dirty_reg(¤t,CCREG); |
9032 | memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap)); |
9033 | } |
9034 | else |
9035 | if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL |
9036 | { |
9037 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); |
9038 | branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1; |
9039 | branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1; |
9040 | if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1; |
9041 | alloc_cc(&branch_regs[i-1],i); |
9042 | dirty_reg(&branch_regs[i-1],CCREG); |
9043 | delayslot_alloc(&branch_regs[i-1],i); |
9044 | branch_regs[i-1].isconst=0; |
9045 | alloc_reg(¤t,i,CCREG); // Not taken path |
9046 | dirty_reg(¤t,CCREG); |
9047 | memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap)); |
9048 | } |
9049 | break; |
9050 | case SJUMP: |
9051 | //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ |
9052 | if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ |
9053 | { |
9054 | alloc_cc(¤t,i-1); |
9055 | dirty_reg(¤t,CCREG); |
9056 | if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) { |
9057 | // The delay slot overwrote the branch condition |
9058 | // Delay slot goes after the test (in order) |
9059 | current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])); |
9060 | current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])); |
9061 | if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i])); |
9062 | current.u|=1; |
9063 | current.uu|=1; |
9064 | delayslot_alloc(¤t,i); |
9065 | current.isconst=0; |
9066 | } |
9067 | else |
9068 | { |
9069 | current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]); |
9070 | current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]); |
9071 | // Alloc the branch condition register |
9072 | alloc_reg(¤t,i-1,rs1[i-1]); |
9073 | if(!(current.is32>>rs1[i-1]&1)) |
9074 | { |
9075 | alloc_reg64(¤t,i-1,rs1[i-1]); |
9076 | } |
9077 | } |
9078 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); |
9079 | branch_regs[i-1].isconst=0; |
9080 | branch_regs[i-1].wasconst=0; |
9081 | memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap)); |
9082 | memcpy(constmap[i],constmap[i-1],sizeof(current.constmap)); |
9083 | } |
9084 | else |
9085 | // Alloc the delay slot in case the branch is taken |
9086 | if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL |
9087 | { |
9088 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); |
9089 | branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1; |
9090 | branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1; |
9091 | if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1; |
9092 | alloc_cc(&branch_regs[i-1],i); |
9093 | dirty_reg(&branch_regs[i-1],CCREG); |
9094 | delayslot_alloc(&branch_regs[i-1],i); |
9095 | branch_regs[i-1].isconst=0; |
9096 | alloc_reg(¤t,i,CCREG); // Not taken path |
9097 | dirty_reg(¤t,CCREG); |
9098 | memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap)); |
9099 | } |
9100 | // FIXME: BLTZAL/BGEZAL |
9101 | if(opcode2[i-1]&0x10) { // BxxZAL |
9102 | alloc_reg(&branch_regs[i-1],i-1,31); |
9103 | dirty_reg(&branch_regs[i-1],31); |
9104 | branch_regs[i-1].is32|=1LL<<31; |
9105 | } |
9106 | break; |
9107 | case FJUMP: |
9108 | if(likely[i-1]==0) // BC1F/BC1T |
9109 | { |
9110 | alloc_cc(¤t,i-1); |
9111 | dirty_reg(¤t,CCREG); |
9112 | if(itype[i]==FCOMP) { |
9113 | // The delay slot overwrote the branch condition |
9114 | // Delay slot goes after the test (in order) |
9115 | delayslot_alloc(¤t,i); |
9116 | current.isconst=0; |
9117 | } |
9118 | else |
9119 | { |
9120 | current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]); |
9121 | current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]); |
9122 | // Alloc the branch condition register |
9123 | alloc_reg(¤t,i-1,FSREG); |
9124 | } |
9125 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); |
9126 | memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap)); |
9127 | } |
9128 | else // BC1FL/BC1TL |
9129 | { |
9130 | // Alloc the delay slot in case the branch is taken |
9131 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); |
9132 | branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1; |
9133 | branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1; |
9134 | if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1; |
9135 | alloc_cc(&branch_regs[i-1],i); |
9136 | dirty_reg(&branch_regs[i-1],CCREG); |
9137 | delayslot_alloc(&branch_regs[i-1],i); |
9138 | branch_regs[i-1].isconst=0; |
9139 | alloc_reg(¤t,i,CCREG); // Not taken path |
9140 | dirty_reg(¤t,CCREG); |
9141 | memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap)); |
9142 | } |
9143 | break; |
9144 | } |
9145 | |
9146 | if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000) |
9147 | { |
9148 | if(rt1[i-1]==31) // JAL/JALR |
9149 | { |
9150 | // Subroutine call will return here, don't alloc any registers |
9151 | current.is32=1; |
9152 | current.dirty=0; |
9153 | clear_all_regs(current.regmap); |
9154 | alloc_reg(¤t,i,CCREG); |
9155 | dirty_reg(¤t,CCREG); |
9156 | } |
9157 | else if(i+1<slen) |
9158 | { |
9159 | // Internal branch will jump here, match registers to caller |
9160 | current.is32=0x3FFFFFFFFLL; |
9161 | current.dirty=0; |
9162 | clear_all_regs(current.regmap); |
9163 | alloc_reg(¤t,i,CCREG); |
9164 | dirty_reg(¤t,CCREG); |
9165 | for(j=i-1;j>=0;j--) |
9166 | { |
9167 | if(ba[j]==start+i*4+4) { |
9168 | memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap)); |
9169 | current.is32=branch_regs[j].is32; |
9170 | current.dirty=branch_regs[j].dirty; |
9171 | break; |
9172 | } |
9173 | } |
9174 | while(j>=0) { |
9175 | if(ba[j]==start+i*4+4) { |
9176 | for(hr=0;hr<HOST_REGS;hr++) { |
9177 | if(current.regmap[hr]!=branch_regs[j].regmap[hr]) { |
9178 | current.regmap[hr]=-1; |
9179 | } |
9180 | current.is32&=branch_regs[j].is32; |
9181 | current.dirty&=branch_regs[j].dirty; |
9182 | } |
9183 | } |
9184 | j--; |
9185 | } |
9186 | } |
9187 | } |
9188 | } |
9189 | |
9190 | // Count cycles in between branches |
9191 | ccadj[i]=cc; |
9192 | if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL)) |
9193 | { |
9194 | cc=0; |
9195 | } |
9196 | else |
9197 | { |
9198 | cc++; |
9199 | } |
9200 | |
9201 | flush_dirty_uppers(¤t); |
9202 | if(!is_ds[i]) { |
9203 | regs[i].is32=current.is32; |
9204 | regs[i].dirty=current.dirty; |
9205 | regs[i].isconst=current.isconst; |
9206 | memcpy(constmap[i],current.constmap,sizeof(current.constmap)); |
9207 | } |
9208 | for(hr=0;hr<HOST_REGS;hr++) { |
9209 | if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) { |
9210 | if(regmap_pre[i][hr]!=regs[i].regmap[hr]) { |
9211 | regs[i].wasconst&=~(1<<hr); |
9212 | } |
9213 | } |
9214 | } |
9215 | if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1; |
9216 | } |
9217 | |
9218 | /* Pass 4 - Cull unused host registers */ |
9219 | |
9220 | uint64_t nr=0; |
9221 | |
9222 | for (i=slen-1;i>=0;i--) |
9223 | { |
9224 | int hr; |
9225 | if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) |
9226 | { |
9227 | if(ba[i]<start || ba[i]>=(start+slen*4)) |
9228 | { |
9229 | // Branch out of this block, don't need anything |
9230 | nr=0; |
9231 | } |
9232 | else |
9233 | { |
9234 | // Internal branch |
9235 | // Need whatever matches the target |
9236 | nr=0; |
9237 | int t=(ba[i]-start)>>2; |
9238 | for(hr=0;hr<HOST_REGS;hr++) |
9239 | { |
9240 | if(regs[i].regmap_entry[hr]>=0) { |
9241 | if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr; |
9242 | } |
9243 | } |
9244 | } |
9245 | // Conditional branch may need registers for following instructions |
9246 | if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) |
9247 | { |
9248 | if(i<slen-2) { |
9249 | nr|=needed_reg[i+2]; |
9250 | for(hr=0;hr<HOST_REGS;hr++) |
9251 | { |
9252 | if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr); |
9253 | //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) DebugMessage(M64MSG_VERBOSE, "%x-bogus(%d=%d)",start+i*4,hr,regmap_entry[i+2][hr]); |
9254 | } |
9255 | } |
9256 | } |
9257 | // Don't need stuff which is overwritten |
9258 | if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr); |
ce68e3b9 |
9259 | if(regs[i].regmap[hr]<0) nr&=~(1<<hr); //moved... |
451ab91e |
9260 | // Merge in delay slot |
9261 | for(hr=0;hr<HOST_REGS;hr++) |
9262 | { |
ce68e3b9 |
9263 | // Don't need stuff which is overwritten |
9264 | /* if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr); //*SEB* Moved here |
9265 | if(regs[i].regmap[hr]<0) nr&=~(1<<hr);*/ |
9266 | |
451ab91e |
9267 | if(!likely[i]) { |
9268 | // These are overwritten unless the branch is "likely" |
9269 | // and the delay slot is nullified if not taken |
9270 | if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr); |
9271 | if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr); |
9272 | } |
9273 | if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr; |
9274 | if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr; |
9275 | if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr; |
9276 | if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr; |
9277 | if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr; |
9278 | if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr; |
9279 | if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr; |
9280 | if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr; |
9281 | if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) { |
9282 | if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr; |
9283 | if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr; |
9284 | } |
9285 | if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) { |
9286 | if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr; |
9287 | if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr; |
9288 | } |
9289 | if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39) { |
9290 | if(regmap_pre[i][hr]==INVCP) nr|=1<<hr; |
9291 | if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr; |
9292 | } |
9293 | } |
9294 | } |
9295 | else if(itype[i]==SYSCALL) |
9296 | { |
9297 | // SYSCALL instruction (software interrupt) |
9298 | nr=0; |
9299 | } |
9300 | else if(itype[i]==COP0 && (source[i]&0x3f)==0x18) |
9301 | { |
9302 | // ERET instruction (return from interrupt) |
9303 | nr=0; |
9304 | } |
9305 | else // Non-branch |
9306 | { |
9307 | if(i<slen-1) { |
9308 | for(hr=0;hr<HOST_REGS;hr++) { |
9309 | if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr); |
9310 | if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr); |
9311 | if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr); |
9312 | if(regs[i].regmap[hr]<0) nr&=~(1<<hr); |
9313 | } |
9314 | } |
9315 | } |
9316 | for(hr=0;hr<HOST_REGS;hr++) |
9317 | { |
9318 | // Overwritten registers are not needed |
9319 | if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr); |
9320 | if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr); |
9321 | if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr); |
9322 | // Source registers are needed |
9323 | if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr; |
9324 | if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr; |
9325 | if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr; |
9326 | if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr; |
9327 | if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr; |
9328 | if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr; |
9329 | if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr; |
9330 | if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr; |
9331 | if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) { |
9332 | if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr; |
9333 | if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr; |
9334 | } |
9335 | if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) { |
9336 | if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr; |
9337 | if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr; |
9338 | } |
9339 | if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39) { |
9340 | if(regmap_pre[i][hr]==INVCP) nr|=1<<hr; |
9341 | if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr; |
9342 | } |
9343 | // Don't store a register immediately after writing it, |
9344 | // may prevent dual-issue. |
9345 | // But do so if this is a branch target, otherwise we |
9346 | // might have to load the register before the branch. |
9347 | if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) { |
9348 | if((regmap_pre[i][hr]>0&®map_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) || |
9349 | (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) { |
9350 | if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr; |
9351 | if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr; |
9352 | } |
9353 | if((regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) || |
9354 | (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) { |
9355 | if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr; |
9356 | if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr; |
9357 | } |
9358 | } |
9359 | } |
9360 | // Cycle count is needed at branches. Assume it is needed at the target too. |
9361 | if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) { |
9362 | if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG; |
9363 | if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG; |
9364 | } |
9365 | // Save it |
9366 | needed_reg[i]=nr; |
9367 | |
9368 | // Deallocate unneeded registers |
9369 | for(hr=0;hr<HOST_REGS;hr++) |
9370 | { |
9371 | if(!((nr>>hr)&1)) { |
9372 | if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1; |
9373 | if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] && |
9374 | (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] && |
9375 | (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG) |
9376 | { |
9377 | if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) |
9378 | { |
9379 | if(likely[i]) { |
9380 | regs[i].regmap[hr]=-1; |
9381 | regs[i].isconst&=~(1<<hr); |
9382 | if(i<slen-2) { |
9383 | regmap_pre[i+2][hr]=-1; |
9384 | regs[i+2].wasconst&=~(1<<hr); |
9385 | } |
9386 | } |
9387 | } |
9388 | } |
9389 | if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) |
9390 | { |
9391 | int d1=0,d2=0,map=0,temp=0; |
9392 | if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0) |
9393 | { |
9394 | d1=dep1[i+1]; |
9395 | d2=dep2[i+1]; |
9396 | } |
9397 | if(using_tlb) { |
9398 | if(itype[i+1]==LOAD || itype[i+1]==LOADLR || |
9399 | itype[i+1]==STORE || itype[i+1]==STORELR || |
9400 | itype[i+1]==C1LS ) |
9401 | map=TLREG; |
9402 | } else |
9403 | if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39) { |
9404 | map=INVCP; |
9405 | } |
9406 | if(itype[i+1]==LOADLR || itype[i+1]==STORELR || |
9407 | itype[i+1]==C1LS ) |
9408 | temp=FTEMP; |
9409 | if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] && |
9410 | (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] && |
9411 | (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] && |
9412 | (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] && |
9413 | (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 && |
9414 | regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] && |
9415 | (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP && |
9416 | regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL && |
9417 | regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG && |
9418 | regs[i].regmap[hr]!=map ) |
9419 | { |
9420 | regs[i].regmap[hr]=-1; |
9421 | regs[i].isconst&=~(1<<hr); |
9422 | if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] && |
9423 | (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] && |
9424 | (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] && |
9425 | (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] && |
9426 | (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 && |
9427 | branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] && |
9428 | (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP && |
9429 | branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL && |
9430 | branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG && |
9431 | branch_regs[i].regmap[hr]!=map) |
9432 | { |
9433 | branch_regs[i].regmap[hr]=-1; |
9434 | branch_regs[i].regmap_entry[hr]=-1; |
9435 | if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) |
9436 | { |
9437 | if(!likely[i]&&i<slen-2) { |
9438 | regmap_pre[i+2][hr]=-1; |
9439 | regs[i+2].wasconst&=~(1<<hr); |
9440 | } |
9441 | } |
9442 | } |
9443 | } |
9444 | } |
9445 | else |
9446 | { |
9447 | // Non-branch |
9448 | if(i>0) |
9449 | { |
9450 | int d1=0,d2=0,map=-1,temp=-1; |
9451 | if(get_reg(regs[i].regmap,rt1[i]|64)>=0) |
9452 | { |
9453 | d1=dep1[i]; |
9454 | d2=dep2[i]; |
9455 | } |
9456 | if(using_tlb) { |
9457 | if(itype[i]==LOAD || itype[i]==LOADLR || |
9458 | itype[i]==STORE || itype[i]==STORELR || |
9459 | itype[i]==C1LS ) |
9460 | map=TLREG; |
9461 | } else if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39) { |
9462 | map=INVCP; |
9463 | } |
9464 | if(itype[i]==LOADLR || itype[i]==STORELR || |
9465 | itype[i]==C1LS ) |
9466 | temp=FTEMP; |
9467 | if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] && |
9468 | (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] && |
9469 | (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 && |
9470 | regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] && |
9471 | (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map && |
9472 | (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG)) |
9473 | { |
9474 | if(i<slen-1&&!is_ds[i]) { |
9475 | if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1) |
9476 | if(regmap_pre[i+1][hr]!=regs[i].regmap[hr]) |
9477 | if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1)) |
9478 | { |
9479 | DebugMessage(M64MSG_VERBOSE, "fail: %x (%d %d!=%d)",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]); |
9480 | assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]); |
9481 | } |
9482 | regmap_pre[i+1][hr]=-1; |
9483 | if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1; |
9484 | regs[i+1].wasconst&=~(1<<hr); |
9485 | } |
9486 | regs[i].regmap[hr]=-1; |
9487 | regs[i].isconst&=~(1<<hr); |
9488 | } |
9489 | } |
9490 | } |
9491 | } |
9492 | } |
9493 | } |
9494 | |
9495 | /* Pass 5 - Pre-allocate registers */ |
9496 | |
9497 | // If a register is allocated during a loop, try to allocate it for the |
9498 | // entire loop, if possible. This avoids loading/storing registers |
9499 | // inside of the loop. |
9500 | |
9501 | signed char f_regmap[HOST_REGS]; |
9502 | clear_all_regs(f_regmap); |
9503 | for(i=0;i<slen-1;i++) |
9504 | { |
9505 | if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) |
9506 | { |
9507 | if(ba[i]>=start && ba[i]<(start+i*4)) |
9508 | if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU |
9509 | ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD |
9510 | ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS |
9511 | ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT |
9512 | ||itype[i+1]==FCOMP||itype[i+1]==FCONV) |
9513 | { |
9514 | int t=(ba[i]-start)>>2; |
9515 | if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots |
9516 | if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated |
9517 | for(hr=0;hr<HOST_REGS;hr++) |
9518 | { |
9519 | if(regs[i].regmap[hr]>64) { |
9520 | if(!((regs[i].dirty>>hr)&1)) |
9521 | f_regmap[hr]=regs[i].regmap[hr]; |
9522 | else f_regmap[hr]=-1; |
9523 | } |
9524 | else if(regs[i].regmap[hr]>=0) { |
9525 | if(f_regmap[hr]!=regs[i].regmap[hr]) { |
9526 | // dealloc old register |
9527 | int n; |
9528 | for(n=0;n<HOST_REGS;n++) |
9529 | { |
9530 | if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;} |
9531 | } |
9532 | // and alloc new one |
9533 | f_regmap[hr]=regs[i].regmap[hr]; |
9534 | } |
9535 | } |
9536 | if(branch_regs[i].regmap[hr]>64) { |
9537 | if(!((branch_regs[i].dirty>>hr)&1)) |
9538 | f_regmap[hr]=branch_regs[i].regmap[hr]; |
9539 | else f_regmap[hr]=-1; |
9540 | } |
9541 | else if(branch_regs[i].regmap[hr]>=0) { |
9542 | if(f_regmap[hr]!=branch_regs[i].regmap[hr]) { |
9543 | // dealloc old register |
9544 | int n; |
9545 | for(n=0;n<HOST_REGS;n++) |
9546 | { |
9547 | if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;} |
9548 | } |
9549 | // and alloc new one |
9550 | f_regmap[hr]=branch_regs[i].regmap[hr]; |
9551 | } |
9552 | } |
9553 | if(ooo[i]) { |
9554 | if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) |
9555 | f_regmap[hr]=branch_regs[i].regmap[hr]; |
9556 | }else{ |
9557 | if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) |
9558 | f_regmap[hr]=branch_regs[i].regmap[hr]; |
9559 | } |
9560 | // Avoid dirty->clean transition |
9561 | #ifdef DESTRUCTIVE_WRITEBACK |
9562 | if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1; |
9563 | #endif |
9564 | // This check is only strictly required in the DESTRUCTIVE_WRITEBACK |
9565 | // case above, however it's always a good idea. We can't hoist the |
9566 | // load if the register was already allocated, so there's no point |
9567 | // wasting time analyzing most of these cases. It only "succeeds" |
9568 | // when the mapping was different and the load can be replaced with |
9569 | // a mov, which is of negligible benefit. So such cases are |
9570 | // skipped below. |
9571 | if(f_regmap[hr]>0) { |
9572 | if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) { |
9573 | int r=f_regmap[hr]; |
9574 | for(j=t;j<=i;j++) |
9575 | { |
9576 | //DebugMessage(M64MSG_VERBOSE, "Test %x -> %x, %x %d/%d",start+i*4,ba[i],start+j*4,hr,r); |
9577 | if(r<34&&((unneeded_reg[j]>>r)&1)) break; |
9578 | if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break; |
9579 | if(r>63) { |
9580 | // NB This can exclude the case where the upper-half |
9581 | // register is lower numbered than the lower-half |
9582 | // register. Not sure if it's worth fixing... |
9583 | if(get_reg(regs[j].regmap,r&63)<0) break; |
9584 | if(get_reg(regs[j].regmap_entry,r&63)<0) break; |
9585 | if(regs[j].is32&(1LL<<(r&63))) break; |
9586 | } |
9587 | if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) { |
9588 | //DebugMessage(M64MSG_VERBOSE, "Hit %x -> %x, %x %d/%d",start+i*4,ba[i],start+j*4,hr,r); |
9589 | int k; |
9590 | if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) { |
9591 | if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break; |
9592 | if(r>63) { |
9593 | if(get_reg(regs[i].regmap,r&63)<0) break; |
9594 | if(get_reg(branch_regs[i].regmap,r&63)<0) break; |
9595 | } |
9596 | k=i; |
9597 | while(k>1&®s[k-1].regmap[hr]==-1) { |
9598 | if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) { |
9599 | //DebugMessage(M64MSG_VERBOSE, "no free regs for store %x",start+(k-1)*4); |
9600 | break; |
9601 | } |
9602 | if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) { |
9603 | //DebugMessage(M64MSG_VERBOSE, "no-match due to different register"); |
9604 | break; |
9605 | } |
9606 | if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) { |
9607 | //DebugMessage(M64MSG_VERBOSE, "no-match due to branch"); |
9608 | break; |
9609 | } |
9610 | // call/ret fast path assumes no registers allocated |
9611 | if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) { |
9612 | break; |
9613 | } |
9614 | if(r>63) { |
9615 | // NB This can exclude the case where the upper-half |
9616 | // register is lower numbered than the lower-half |
9617 | // register. Not sure if it's worth fixing... |
9618 | if(get_reg(regs[k-1].regmap,r&63)<0) break; |
9619 | if(regs[k-1].is32&(1LL<<(r&63))) break; |
9620 | } |
9621 | k--; |
9622 | } |
9623 | if(i<slen-1) { |
9624 | if((regs[k].is32&(1LL<<f_regmap[hr]))!= |
9625 | (regs[i+2].was32&(1LL<<f_regmap[hr]))) { |
9626 | //DebugMessage(M64MSG_VERBOSE, "bad match after branch"); |
9627 | break; |
9628 | } |
9629 | } |
9630 | if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) { |
9631 | //DebugMessage(M64MSG_VERBOSE, "Extend r%d, %x ->",hr,start+k*4); |
9632 | while(k<i) { |
9633 | regs[k].regmap_entry[hr]=f_regmap[hr]; |
9634 | regs[k].regmap[hr]=f_regmap[hr]; |
9635 | regmap_pre[k+1][hr]=f_regmap[hr]; |
9636 | regs[k].wasdirty&=~(1<<hr); |
9637 | regs[k].dirty&=~(1<<hr); |
9638 | regs[k].wasdirty|=(1<<hr)®s[k-1].dirty; |
9639 | regs[k].dirty|=(1<<hr)®s[k].wasdirty; |
9640 | regs[k].wasconst&=~(1<<hr); |
9641 | regs[k].isconst&=~(1<<hr); |
9642 | k++; |
9643 | } |
9644 | } |
9645 | else { |
9646 | //DebugMessage(M64MSG_VERBOSE, "Fail Extend r%d, %x ->",hr,start+k*4); |
9647 | break; |
9648 | } |
9649 | assert(regs[i-1].regmap[hr]==f_regmap[hr]); |
9650 | if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) { |
9651 | //DebugMessage(M64MSG_VERBOSE, "OK fill %x (r%d)",start+i*4,hr); |
9652 | regs[i].regmap_entry[hr]=f_regmap[hr]; |
9653 | regs[i].regmap[hr]=f_regmap[hr]; |
9654 | regs[i].wasdirty&=~(1<<hr); |
9655 | regs[i].dirty&=~(1<<hr); |
9656 | regs[i].wasdirty|=(1<<hr)®s[i-1].dirty; |
9657 | regs[i].dirty|=(1<<hr)®s[i-1].dirty; |
9658 | regs[i].wasconst&=~(1<<hr); |
9659 | regs[i].isconst&=~(1<<hr); |
9660 | branch_regs[i].regmap_entry[hr]=f_regmap[hr]; |
9661 | branch_regs[i].wasdirty&=~(1<<hr); |
9662 | branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty; |
9663 | branch_regs[i].regmap[hr]=f_regmap[hr]; |
9664 | branch_regs[i].dirty&=~(1<<hr); |
9665 | branch_regs[i].dirty|=(1<<hr)®s[i].dirty; |
9666 | branch_regs[i].wasconst&=~(1<<hr); |
9667 | branch_regs[i].isconst&=~(1<<hr); |
9668 | if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) { |
9669 | regmap_pre[i+2][hr]=f_regmap[hr]; |
9670 | regs[i+2].wasdirty&=~(1<<hr); |
9671 | regs[i+2].wasdirty|=(1<<hr)®s[i].dirty; |
9672 | assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))== |
9673 | (regs[i+2].was32&(1LL<<f_regmap[hr]))); |
9674 | } |
9675 | } |
9676 | } |
9677 | for(k=t;k<j;k++) { |
9678 | // Alloc register clean at beginning of loop, |
9679 | // but may dirty it in pass 6 |
9680 | regs[k].regmap_entry[hr]=f_regmap[hr]; |
9681 | regs[k].regmap[hr]=f_regmap[hr]; |
9682 | regs[k].dirty&=~(1<<hr); |
9683 | regs[k].wasconst&=~(1<<hr); |
9684 | regs[k].isconst&=~(1<<hr); |
9685 | if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) { |
9686 | branch_regs[k].regmap_entry[hr]=f_regmap[hr]; |
9687 | branch_regs[k].regmap[hr]=f_regmap[hr]; |
9688 | branch_regs[k].dirty&=~(1<<hr); |
9689 | branch_regs[k].wasconst&=~(1<<hr); |
9690 | branch_regs[k].isconst&=~(1<<hr); |
9691 | if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) { |
9692 | regmap_pre[k+2][hr]=f_regmap[hr]; |
9693 | regs[k+2].wasdirty&=~(1<<hr); |
9694 | assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))== |
9695 | (regs[k+2].was32&(1LL<<f_regmap[hr]))); |
9696 | } |
9697 | } |
9698 | else |
9699 | { |
9700 | regmap_pre[k+1][hr]=f_regmap[hr]; |
9701 | regs[k+1].wasdirty&=~(1<<hr); |
9702 | } |
9703 | } |
9704 | if(regs[j].regmap[hr]==f_regmap[hr]) |
9705 | regs[j].regmap_entry[hr]=f_regmap[hr]; |
9706 | break; |
9707 | } |
9708 | if(j==i) break; |
9709 | if(regs[j].regmap[hr]>=0) |
9710 | break; |
9711 | if(get_reg(regs[j].regmap,f_regmap[hr])>=0) { |
9712 | //DebugMessage(M64MSG_VERBOSE, "no-match due to different register"); |
9713 | break; |
9714 | } |
9715 | if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) { |
9716 | //DebugMessage(M64MSG_VERBOSE, "32/64 mismatch %x %d",start+j*4,hr); |
9717 | break; |
9718 | } |
9719 | if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000) |
9720 | { |
9721 | // Stop on unconditional branch |
9722 | break; |
9723 | } |
9724 | if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) |
9725 | { |
9726 | if(ooo[j]) { |
9727 | if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) |
9728 | break; |
9729 | }else{ |
9730 | if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) |
9731 | break; |
9732 | } |
9733 | if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) { |
9734 | //DebugMessage(M64MSG_VERBOSE, "no-match due to different register (branch)"); |
9735 | break; |
9736 | } |
9737 | } |
9738 | if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) { |
9739 | //DebugMessage(M64MSG_VERBOSE, "No free regs for store %x",start+j*4); |
9740 | break; |
9741 | } |
9742 | if(f_regmap[hr]>=64) { |
9743 | if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) { |
9744 | break; |
9745 | } |
9746 | else |
9747 | { |
9748 | if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) { |
9749 | break; |
9750 | } |
9751 | } |
9752 | } |
9753 | } |
9754 | } |
9755 | } |
9756 | } |
9757 | } |
9758 | }else{ |
9759 | // Non branch or undetermined branch target |
9760 | for(hr=0;hr<HOST_REGS;hr++) |
9761 | { |
9762 | if(hr!=EXCLUDE_REG) { |
9763 | if(regs[i].regmap[hr]>64) { |
9764 | if(!((regs[i].dirty>>hr)&1)) |
9765 | f_regmap[hr]=regs[i].regmap[hr]; |
9766 | } |
9767 | else if(regs[i].regmap[hr]>=0) { |
9768 | if(f_regmap[hr]!=regs[i].regmap[hr]) { |
9769 | // dealloc old register |
9770 | int n; |
9771 | for(n=0;n<HOST_REGS;n++) |
9772 | { |
9773 | if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;} |
9774 | } |
9775 | // and alloc new one |
9776 | f_regmap[hr]=regs[i].regmap[hr]; |
9777 | } |
9778 | } |
9779 | } |
9780 | } |
9781 | // Try to restore cycle count at branch targets |
9782 | if(bt[i]) { |
9783 | for(j=i;j<slen-1;j++) { |
9784 | if(regs[j].regmap[HOST_CCREG]!=-1) break; |
9785 | if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) { |
9786 | //DebugMessage(M64MSG_VERBOSE, "no free regs for store %x",start+j*4); |
9787 | break; |
9788 | } |
9789 | } |
9790 | if(regs[j].regmap[HOST_CCREG]==CCREG) { |
9791 | int k=i; |
9792 | //DebugMessage(M64MSG_VERBOSE, "Extend CC, %x -> %x",start+k*4,start+j*4); |
9793 | while(k<j) { |
9794 | regs[k].regmap_entry[HOST_CCREG]=CCREG; |
9795 | regs[k].regmap[HOST_CCREG]=CCREG; |
9796 | regmap_pre[k+1][HOST_CCREG]=CCREG; |
9797 | regs[k+1].wasdirty|=1<<HOST_CCREG; |
9798 | regs[k].dirty|=1<<HOST_CCREG; |
9799 | regs[k].wasconst&=~(1<<HOST_CCREG); |
9800 | regs[k].isconst&=~(1<<HOST_CCREG); |
9801 | k++; |
9802 | } |
9803 | regs[j].regmap_entry[HOST_CCREG]=CCREG; |
9804 | } |
9805 | // Work backwards from the branch target |
9806 | if(j>i&&f_regmap[HOST_CCREG]==CCREG) |
9807 | { |
9808 | //DebugMessage(M64MSG_VERBOSE, "Extend backwards"); |
9809 | int k; |
9810 | k=i; |
9811 | while(regs[k-1].regmap[HOST_CCREG]==-1) { |
9812 | if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) { |
9813 | //DebugMessage(M64MSG_VERBOSE, "no free regs for store %x",start+(k-1)*4); |
9814 | break; |
9815 | } |
9816 | k--; |
9817 | } |
9818 | if(regs[k-1].regmap[HOST_CCREG]==CCREG) { |
9819 | //DebugMessage(M64MSG_VERBOSE, "Extend CC, %x ->",start+k*4); |
9820 | while(k<=i) { |
9821 | regs[k].regmap_entry[HOST_CCREG]=CCREG; |
9822 | regs[k].regmap[HOST_CCREG]=CCREG; |
9823 | regmap_pre[k+1][HOST_CCREG]=CCREG; |
9824 | regs[k+1].wasdirty|=1<<HOST_CCREG; |
9825 | regs[k].dirty|=1<<HOST_CCREG; |
9826 | regs[k].wasconst&=~(1<<HOST_CCREG); |
9827 | regs[k].isconst&=~(1<<HOST_CCREG); |
9828 | k++; |
9829 | } |
9830 | } |
9831 | else { |
9832 | //DebugMessage(M64MSG_VERBOSE, "Fail Extend CC, %x ->",start+k*4); |
9833 | } |
9834 | } |
9835 | } |
9836 | if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&& |
9837 | itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&& |
9838 | itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&& |
9839 | itype[i]!=FCONV&&itype[i]!=FCOMP) |
9840 | { |
9841 | memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap)); |
9842 | } |
9843 | } |
9844 | } |
9845 | |
9846 | // Cache memory offset or tlb map pointer if a register is available |
9847 | #ifndef HOST_IMM_ADDR32 |
9848 | #ifndef RAM_OFFSET |
9849 | if(using_tlb) |
9850 | #endif |
9851 | { |
9852 | int earliest_available[HOST_REGS]; |
9853 | int loop_start[HOST_REGS]; |
9854 | int score[HOST_REGS]; |
9855 | int end[HOST_REGS]; |
9856 | int reg=using_tlb?MMREG:ROREG; |
9857 | |
9858 | // Init |
9859 | for(hr=0;hr<HOST_REGS;hr++) { |
9860 | score[hr]=0;earliest_available[hr]=0; |
9861 | loop_start[hr]=MAXBLOCK; |
9862 | } |
9863 | for(i=0;i<slen-1;i++) |
9864 | { |
9865 | // Can't do anything if no registers are available |
9866 | if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) { |
9867 | for(hr=0;hr<HOST_REGS;hr++) { |
9868 | score[hr]=0;earliest_available[hr]=i+1; |
9869 | loop_start[hr]=MAXBLOCK; |
9870 | } |
9871 | } |
9872 | if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) { |
9873 | if(!ooo[i]) { |
9874 | if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) { |
9875 | for(hr=0;hr<HOST_REGS;hr++) { |
9876 | score[hr]=0;earliest_available[hr]=i+1; |
9877 | loop_start[hr]=MAXBLOCK; |
9878 | } |
9879 | } |
9880 | }else{ |
9881 | if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) { |
9882 | for(hr=0;hr<HOST_REGS;hr++) { |
9883 | score[hr]=0;earliest_available[hr]=i+1; |
9884 | loop_start[hr]=MAXBLOCK; |
9885 | } |
9886 | } |
9887 | } |
9888 | } |
9889 | // Mark unavailable registers |
9890 | for(hr=0;hr<HOST_REGS;hr++) { |
9891 | if(regs[i].regmap[hr]>=0) { |
9892 | score[hr]=0;earliest_available[hr]=i+1; |
9893 | loop_start[hr]=MAXBLOCK; |
9894 | } |
9895 | if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) { |
9896 | if(branch_regs[i].regmap[hr]>=0) { |
9897 | score[hr]=0;earliest_available[hr]=i+2; |
9898 | loop_start[hr]=MAXBLOCK; |
9899 | } |
9900 | } |
9901 | } |
9902 | // No register allocations after unconditional jumps |
9903 | if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000) |
9904 | { |
9905 | for(hr=0;hr<HOST_REGS;hr++) { |
9906 | score[hr]=0;earliest_available[hr]=i+2; |
9907 | loop_start[hr]=MAXBLOCK; |
9908 | } |
9909 | i++; // Skip delay slot too |
9910 | //DebugMessage(M64MSG_VERBOSE, "skip delay slot: %x",start+i*4); |
9911 | } |
9912 | else |
9913 | // Possible match |
9914 | if(itype[i]==LOAD||itype[i]==LOADLR|| |
9915 | itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) { |
9916 | for(hr=0;hr<HOST_REGS;hr++) { |
9917 | if(hr!=EXCLUDE_REG) { |
9918 | end[hr]=i-1; |
9919 | for(j=i;j<slen-1;j++) { |
9920 | if(regs[j].regmap[hr]>=0) break; |
9921 | if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) { |
9922 | if(branch_regs[j].regmap[hr]>=0) break; |
9923 | if(ooo[j]) { |
9924 | if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break; |
9925 | }else{ |
9926 | if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break; |
9927 | } |
9928 | } |
9929 | else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break; |
9930 | if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) { |
9931 | int t=(ba[j]-start)>>2; |
9932 | if(t<j&&t>=earliest_available[hr]) { |
9933 | if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated |
9934 | // Score a point for hoisting loop invariant |
9935 | if(t<loop_start[hr]) loop_start[hr]=t; |
9936 | //DebugMessage(M64MSG_VERBOSE, "set loop_start: i=%x j=%x (%x)",start+i*4,start+j*4,start+t*4); |
9937 | score[hr]++; |
9938 | end[hr]=j; |
9939 | } |
9940 | } |
9941 | else if(t<j) { |
9942 | if(regs[t].regmap[hr]==reg) { |
9943 | // Score a point if the branch target matches this register |
9944 | score[hr]++; |
9945 | end[hr]=j; |
9946 | } |
9947 | } |
9948 | if(itype[j+1]==LOAD||itype[j+1]==LOADLR|| |
9949 | itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) { |
9950 | score[hr]++; |
9951 | end[hr]=j; |
9952 | } |
9953 | } |
9954 | if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000) |
9955 | { |
9956 | // Stop on unconditional branch |
9957 | break; |
9958 | } |
9959 | else |
9960 | if(itype[j]==LOAD||itype[j]==LOADLR|| |
9961 | itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) { |
9962 | score[hr]++; |
9963 | end[hr]=j; |
9964 | } |
9965 | } |
9966 | } |
9967 | } |
9968 | // Find highest score and allocate that register |
9969 | int maxscore=0; |
9970 | for(hr=0;hr<HOST_REGS;hr++) { |
9971 | if(hr!=EXCLUDE_REG) { |
9972 | if(score[hr]>score[maxscore]) { |
9973 | maxscore=hr; |
9974 | //DebugMessage(M64MSG_VERBOSE, "highest score: %d %d (%x->%x)",score[hr],hr,start+i*4,start+end[hr]*4); |
9975 | } |
9976 | } |
9977 | } |
9978 | if(score[maxscore]>1) |
9979 | { |
9980 | if(i<loop_start[maxscore]) loop_start[maxscore]=i; |
9981 | for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) { |
9982 | //if(regs[j].regmap[maxscore]>=0) {DebugMessage(M64MSG_ERROR, "oops: %x %x was %d=%d",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);} |
9983 | assert(regs[j].regmap[maxscore]<0); |
9984 | if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg; |
9985 | regs[j].regmap[maxscore]=reg; |
9986 | regs[j].dirty&=~(1<<maxscore); |
9987 | regs[j].wasconst&=~(1<<maxscore); |
9988 | regs[j].isconst&=~(1<<maxscore); |
9989 | if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) { |
9990 | branch_regs[j].regmap[maxscore]=reg; |
9991 | branch_regs[j].wasdirty&=~(1<<maxscore); |
9992 | branch_regs[j].dirty&=~(1<<maxscore); |
9993 | branch_regs[j].wasconst&=~(1<<maxscore); |
9994 | branch_regs[j].isconst&=~(1<<maxscore); |
9995 | if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) { |
9996 | regmap_pre[j+2][maxscore]=reg; |
9997 | regs[j+2].wasdirty&=~(1<<maxscore); |
9998 | } |
9999 | // loop optimization (loop_preload) |
10000 | int t=(ba[j]-start)>>2; |
10001 | if(t==loop_start[maxscore]) { |
10002 | if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated |
10003 | regs[t].regmap_entry[maxscore]=reg; |
10004 | } |
10005 | } |
10006 | else |
10007 | { |
10008 | if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) { |
10009 | regmap_pre[j+1][maxscore]=reg; |
10010 | regs[j+1].wasdirty&=~(1<<maxscore); |
10011 | } |
10012 | } |
10013 | } |
10014 | i=j-1; |
10015 | if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot |
10016 | for(hr=0;hr<HOST_REGS;hr++) { |
10017 | score[hr]=0;earliest_available[hr]=i+i; |
10018 | loop_start[hr]=MAXBLOCK; |
10019 | } |
10020 | } |
10021 | } |
10022 | } |
10023 | } |
10024 | #endif |
10025 | |
10026 | // This allocates registers (if possible) one instruction prior |
10027 | // to use, which can avoid a load-use penalty on certain CPUs. |
10028 | for(i=0;i<slen-1;i++) |
10029 | { |
10030 | if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)) |
10031 | { |
10032 | if(!bt[i+1]) |
10033 | { |
10034 | if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16||(itype[i]==COP1&&opcode2[i]<3)) |
10035 | { |
10036 | if(rs1[i+1]) { |
10037 | if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0) |
10038 | { |
10039 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) |
10040 | { |
10041 | regs[i].regmap[hr]=regs[i+1].regmap[hr]; |
10042 | regmap_pre[i+1][hr]=regs[i+1].regmap[hr]; |
10043 | regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr]; |
10044 | regs[i].isconst&=~(1<<hr); |
10045 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); |
10046 | constmap[i][hr]=constmap[i+1][hr]; |
10047 | regs[i+1].wasdirty&=~(1<<hr); |
10048 | regs[i].dirty&=~(1<<hr); |
10049 | } |
10050 | } |
10051 | } |
10052 | if(rs2[i+1]) { |
10053 | if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0) |
10054 | { |
10055 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) |
10056 | { |
10057 | regs[i].regmap[hr]=regs[i+1].regmap[hr]; |
10058 | regmap_pre[i+1][hr]=regs[i+1].regmap[hr]; |
10059 | regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr]; |
10060 | regs[i].isconst&=~(1<<hr); |
10061 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); |
10062 | constmap[i][hr]=constmap[i+1][hr]; |
10063 | regs[i+1].wasdirty&=~(1<<hr); |
10064 | regs[i].dirty&=~(1<<hr); |
10065 | } |
10066 | } |
10067 | } |
10068 | // Preload target address for load instruction (non-constant) |
10069 | if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) { |
10070 | if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0) |
10071 | { |
10072 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) |
10073 | { |
10074 | regs[i].regmap[hr]=rs1[i+1]; |
10075 | regmap_pre[i+1][hr]=rs1[i+1]; |
10076 | regs[i+1].regmap_entry[hr]=rs1[i+1]; |
10077 | regs[i].isconst&=~(1<<hr); |
10078 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); |
10079 | constmap[i][hr]=constmap[i+1][hr]; |
10080 | regs[i+1].wasdirty&=~(1<<hr); |
10081 | regs[i].dirty&=~(1<<hr); |
10082 | } |
10083 | } |
10084 | } |
10085 | // Load source into target register |
10086 | if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) { |
10087 | if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0) |
10088 | { |
10089 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) |
10090 | { |
10091 | regs[i].regmap[hr]=rs1[i+1]; |
10092 | regmap_pre[i+1][hr]=rs1[i+1]; |
10093 | regs[i+1].regmap_entry[hr]=rs1[i+1]; |
10094 | regs[i].isconst&=~(1<<hr); |
10095 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); |
10096 | constmap[i][hr]=constmap[i+1][hr]; |
10097 | regs[i+1].wasdirty&=~(1<<hr); |
10098 | regs[i].dirty&=~(1<<hr); |
10099 | } |
10100 | } |
10101 | } |
10102 | // Preload map address |
10103 | #ifndef HOST_IMM_ADDR32 |
10104 | if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS) { |
10105 | hr=get_reg(regs[i+1].regmap,TLREG); |
10106 | if(hr>=0) { |
10107 | int sr=get_reg(regs[i+1].regmap,rs1[i+1]); |
10108 | if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) { |
10109 | int nr; |
10110 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) |
10111 | { |
10112 | regs[i].regmap[hr]=MGEN1+((i+1)&1); |
10113 | regmap_pre[i+1][hr]=MGEN1+((i+1)&1); |
10114 | regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1); |
10115 | regs[i].isconst&=~(1<<hr); |
10116 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); |
10117 | constmap[i][hr]=constmap[i+1][hr]; |
10118 | regs[i+1].wasdirty&=~(1<<hr); |
10119 | regs[i].dirty&=~(1<<hr); |
10120 | } |
10121 | else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0) |
10122 | { |
10123 | // move it to another register |
10124 | regs[i+1].regmap[hr]=-1; |
10125 | regmap_pre[i+2][hr]=-1; |
10126 | regs[i+1].regmap[nr]=TLREG; |
10127 | regmap_pre[i+2][nr]=TLREG; |
10128 | regs[i].regmap[nr]=MGEN1+((i+1)&1); |
10129 | regmap_pre[i+1][nr]=MGEN1+((i+1)&1); |
10130 | regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1); |
10131 | regs[i].isconst&=~(1<<nr); |
10132 | regs[i+1].isconst&=~(1<<nr); |
10133 | regs[i].dirty&=~(1<<nr); |
10134 | regs[i+1].wasdirty&=~(1<<nr); |
10135 | regs[i+1].dirty&=~(1<<nr); |
10136 | regs[i+2].wasdirty&=~(1<<nr); |
10137 | } |
10138 | } |
10139 | } |
10140 | } |
10141 | #endif |
10142 | // Address for store instruction (non-constant) |
10143 | if(itype[i+1]==STORE||itype[i+1]==STORELR||opcode[i+1]==0x39||opcode[i+1]==0x3D) { // SB/SH/SW/SD/SWC1/SDC1 |
10144 | if(get_reg(regs[i+1].regmap,rs1[i+1])<0) { |
10145 | hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1); |
10146 | if(hr<0) hr=get_reg(regs[i+1].regmap,-1); |
10147 | else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);} |
10148 | assert(hr>=0); |
10149 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) |
10150 | { |
10151 | regs[i].regmap[hr]=rs1[i+1]; |
10152 | regmap_pre[i+1][hr]=rs1[i+1]; |
10153 | regs[i+1].regmap_entry[hr]=rs1[i+1]; |
10154 | regs[i].isconst&=~(1<<hr); |
10155 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); |
10156 | constmap[i][hr]=constmap[i+1][hr]; |
10157 | regs[i+1].wasdirty&=~(1<<hr); |
10158 | regs[i].dirty&=~(1<<hr); |
10159 | } |
10160 | } |
10161 | } |
10162 | if(itype[i+1]==LOADLR||opcode[i+1]==0x31||opcode[i+1]==0x35) { // LWC1/LDC1 |
10163 | if(get_reg(regs[i+1].regmap,rs1[i+1])<0) { |
10164 | int nr; |
10165 | hr=get_reg(regs[i+1].regmap,FTEMP); |
10166 | assert(hr>=0); |
10167 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) |
10168 | { |
10169 | regs[i].regmap[hr]=rs1[i+1]; |
10170 | regmap_pre[i+1][hr]=rs1[i+1]; |
10171 | regs[i+1].regmap_entry[hr]=rs1[i+1]; |
10172 | regs[i].isconst&=~(1<<hr); |
10173 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); |
10174 | constmap[i][hr]=constmap[i+1][hr]; |
10175 | regs[i+1].wasdirty&=~(1<<hr); |
10176 | regs[i].dirty&=~(1<<hr); |
10177 | } |
10178 | else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0) |
10179 | { |
10180 | // move it to another register |
10181 | regs[i+1].regmap[hr]=-1; |
10182 | regmap_pre[i+2][hr]=-1; |
10183 | regs[i+1].regmap[nr]=FTEMP; |
10184 | regmap_pre[i+2][nr]=FTEMP; |
10185 | regs[i].regmap[nr]=rs1[i+1]; |
10186 | regmap_pre[i+1][nr]=rs1[i+1]; |
10187 | regs[i+1].regmap_entry[nr]=rs1[i+1]; |
10188 | regs[i].isconst&=~(1<<nr); |
10189 | regs[i+1].isconst&=~(1<<nr); |
10190 | regs[i].dirty&=~(1<<nr); |
10191 | regs[i+1].wasdirty&=~(1<<nr); |
10192 | regs[i+1].dirty&=~(1<<nr); |
10193 | regs[i+2].wasdirty&=~(1<<nr); |
10194 | } |
10195 | } |
10196 | } |
10197 | if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS*/) { |
10198 | if(itype[i+1]==LOAD) |
10199 | hr=get_reg(regs[i+1].regmap,rt1[i+1]); |
10200 | if(itype[i+1]==LOADLR||opcode[i+1]==0x31||opcode[i+1]==0x35) // LWC1/LDC1 |
10201 | hr=get_reg(regs[i+1].regmap,FTEMP); |
10202 | if(itype[i+1]==STORE||itype[i+1]==STORELR||opcode[i+1]==0x39||opcode[i+1]==0x3D) { // SWC1/SDC1 |
10203 | hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1)); |
10204 | if(hr<0) hr=get_reg(regs[i+1].regmap,-1); |
10205 | } |
10206 | if(hr>=0&®s[i].regmap[hr]<0) { |
10207 | int rs=get_reg(regs[i+1].regmap,rs1[i+1]); |
10208 | if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) { |
10209 | regs[i].regmap[hr]=AGEN1+((i+1)&1); |
10210 | regmap_pre[i+1][hr]=AGEN1+((i+1)&1); |
10211 | regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1); |
10212 | regs[i].isconst&=~(1<<hr); |
10213 | regs[i+1].wasdirty&=~(1<<hr); |
10214 | regs[i].dirty&=~(1<<hr); |
10215 | } |
10216 | } |
10217 | } |
10218 | } |
10219 | } |
10220 | } |
10221 | } |
10222 | |
10223 | /* Pass 6 - Optimize clean/dirty state */ |
10224 | clean_registers(0,slen-1,1); |
10225 | |
10226 | /* Pass 7 - Identify 32-bit registers */ |
10227 | |
10228 | provisional_r32(); |
10229 | |
10230 | u_int r32=0; |
10231 | |
10232 | for (i=slen-1;i>=0;i--) |
10233 | { |
10234 | int hr; |
10235 | if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) |
10236 | { |
10237 | if(ba[i]<start || ba[i]>=(start+slen*4)) |
10238 | { |
10239 | // Branch out of this block, don't need anything |
10240 | r32=0; |
10241 | } |
10242 | else |
10243 | { |
10244 | // Internal branch |
10245 | // Need whatever matches the target |
10246 | // (and doesn't get overwritten by the delay slot instruction) |
10247 | r32=0; |
10248 | int t=(ba[i]-start)>>2; |
10249 | if(ba[i]>start+i*4) { |
10250 | // Forward branch |
10251 | if(!(requires_32bit[t]&~regs[i].was32)) |
10252 | r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1])); |
10253 | }else{ |
10254 | // Backward branch |
10255 | //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32)) |
10256 | // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1])); |
10257 | if(!(pr32[t]&~regs[i].was32)) |
10258 | r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1])); |
10259 | } |
10260 | } |
10261 | // Conditional branch may need registers for following instructions |
10262 | if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) |
10263 | { |
10264 | if(i<slen-2) { |
10265 | r32|=requires_32bit[i+2]; |
10266 | r32&=regs[i].was32; |
10267 | // Mark this address as a branch target since it may be called |
10268 | // upon return from interrupt |
10269 | bt[i+2]=1; |
10270 | } |
10271 | } |
10272 | // Merge in delay slot |
10273 | if(!likely[i]) { |
10274 | // These are overwritten unless the branch is "likely" |
10275 | // and the delay slot is nullified if not taken |
10276 | r32&=~(1LL<<rt1[i+1]); |
10277 | r32&=~(1LL<<rt2[i+1]); |
10278 | } |
10279 | // Assume these are needed (delay slot) |
10280 | if(us1[i+1]>0) |
10281 | { |
10282 | if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1]; |
10283 | } |
10284 | if(us2[i+1]>0) |
10285 | { |
10286 | if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1]; |
10287 | } |
10288 | if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) |
10289 | { |
10290 | if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1]; |
10291 | } |
10292 | if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) |
10293 | { |
10294 | if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1]; |
10295 | } |
10296 | } |
10297 | else if(itype[i]==SYSCALL) |
10298 | { |
10299 | // SYSCALL instruction (software interrupt) |
10300 | r32=0; |
10301 | } |
10302 | else if(itype[i]==COP0 && (source[i]&0x3f)==0x18) |
10303 | { |
10304 | // ERET instruction (return from interrupt) |
10305 | r32=0; |
10306 | } |
10307 | // Check 32 bits |
10308 | r32&=~(1LL<<rt1[i]); |
10309 | r32&=~(1LL<<rt2[i]); |
10310 | if(us1[i]>0) |
10311 | { |
10312 | if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i]; |
10313 | } |
10314 | if(us2[i]>0) |
10315 | { |
10316 | if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i]; |
10317 | } |
10318 | if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) |
10319 | { |
10320 | if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i]; |
10321 | } |
10322 | if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) |
10323 | { |
10324 | if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i]; |
10325 | } |
10326 | requires_32bit[i]=r32; |
10327 | |
10328 | // Dirty registers which are 32-bit, require 32-bit input |
10329 | // as they will be written as 32-bit values |
10330 | for(hr=0;hr<HOST_REGS;hr++) |
10331 | { |
10332 | if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) { |
10333 | if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) { |
10334 | if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1)) |
10335 | requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr]; |
10336 | } |
10337 | } |
10338 | } |
10339 | //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG |
10340 | } |
10341 | |
10342 | if(itype[slen-1]==SPAN) { |
10343 | bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception |
10344 | } |
10345 | |
10346 | /* Debug/disassembly */ |
10347 | // if((void*)assem_debug==(void*)printf) |
10348 | #if defined( ASSEM_DEBUG ) |
10349 | for(i=0;i<slen;i++) |
10350 | { |
10351 | DebugMessage(M64MSG_VERBOSE, "U:"); |
10352 | int r; |
10353 | for(r=1;r<=CCREG;r++) { |
10354 | if((unneeded_reg[i]>>r)&1) { |
10355 | if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI"); |
10356 | else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO"); |
10357 | else DebugMessage(M64MSG_VERBOSE, " r%d",r); |
10358 | } |
10359 | } |
10360 | DebugMessage(M64MSG_VERBOSE, " UU:"); |
10361 | for(r=1;r<=CCREG;r++) { |
10362 | if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) { |
10363 | if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI"); |
10364 | else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO"); |
10365 | else DebugMessage(M64MSG_VERBOSE, " r%d",r); |
10366 | } |
10367 | } |
10368 | DebugMessage(M64MSG_VERBOSE, " 32:"); |
10369 | for(r=0;r<=CCREG;r++) { |
10370 | //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) { |
10371 | if((regs[i].was32>>r)&1) { |
10372 | if(r==CCREG) DebugMessage(M64MSG_VERBOSE, " CC"); |
10373 | else if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI"); |
10374 | else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO"); |
10375 | else DebugMessage(M64MSG_VERBOSE, " r%d",r); |
10376 | } |
10377 | } |
10378 | #if NEW_DYNAREC == NEW_DYNAREC_X86 |
10379 | DebugMessage(M64MSG_VERBOSE, "pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]); |
10380 | #endif |
10381 | #if NEW_DYNAREC == NEW_DYNAREC_ARM |
10382 | DebugMessage(M64MSG_VERBOSE, "pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]); |
10383 | #endif |
10384 | DebugMessage(M64MSG_VERBOSE, "needs: "); |
10385 | if(needed_reg[i]&1) DebugMessage(M64MSG_VERBOSE, "eax "); |
10386 | if((needed_reg[i]>>1)&1) DebugMessage(M64MSG_VERBOSE, "ecx "); |
10387 | if((needed_reg[i]>>2)&1) DebugMessage(M64MSG_VERBOSE, "edx "); |
10388 | if((needed_reg[i]>>3)&1) DebugMessage(M64MSG_VERBOSE, "ebx "); |
10389 | if((needed_reg[i]>>5)&1) DebugMessage(M64MSG_VERBOSE, "ebp "); |
10390 | if((needed_reg[i]>>6)&1) DebugMessage(M64MSG_VERBOSE, "esi "); |
10391 | if((needed_reg[i]>>7)&1) DebugMessage(M64MSG_VERBOSE, "edi "); |
10392 | DebugMessage(M64MSG_VERBOSE, "r:"); |
10393 | for(r=0;r<=CCREG;r++) { |
10394 | //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) { |
10395 | if((requires_32bit[i]>>r)&1) { |
10396 | if(r==CCREG) DebugMessage(M64MSG_VERBOSE, " CC"); |
10397 | else if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI"); |
10398 | else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO"); |
10399 | else DebugMessage(M64MSG_VERBOSE, " r%d",r); |
10400 | } |
10401 | } |
10402 | /*DebugMessage(M64MSG_VERBOSE, "pr:"); |
10403 | for(r=0;r<=CCREG;r++) { |
10404 | //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) { |
10405 | if((pr32[i]>>r)&1) { |
10406 | if(r==CCREG) DebugMessage(M64MSG_VERBOSE, " CC"); |
10407 | else if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI"); |
10408 | else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO"); |
10409 | else DebugMessage(M64MSG_VERBOSE, " r%d",r); |
10410 | } |
10411 | } |
10412 | if(pr32[i]!=requires_32bit[i]) DebugMessage(M64MSG_ERROR, " OOPS");*/ |
10413 | #if NEW_DYNAREC == NEW_DYNAREC_X86 |
10414 | DebugMessage(M64MSG_VERBOSE, "entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]); |
10415 | DebugMessage(M64MSG_VERBOSE, "dirty: "); |
10416 | if(regs[i].wasdirty&1) DebugMessage(M64MSG_VERBOSE, "eax "); |
10417 | if((regs[i].wasdirty>>1)&1) DebugMessage(M64MSG_VERBOSE, "ecx "); |
10418 | if((regs[i].wasdirty>>2)&1) DebugMessage(M64MSG_VERBOSE, "edx "); |
10419 | if((regs[i].wasdirty>>3)&1) DebugMessage(M64MSG_VERBOSE, "ebx "); |
10420 | if((regs[i].wasdirty>>5)&1) DebugMessage(M64MSG_VERBOSE, "ebp "); |
10421 | if((regs[i].wasdirty>>6)&1) DebugMessage(M64MSG_VERBOSE, "esi "); |
10422 | if((regs[i].wasdirty>>7)&1) DebugMessage(M64MSG_VERBOSE, "edi "); |
10423 | #endif |
10424 | #if NEW_DYNAREC == NEW_DYNAREC_ARM |
10425 | DebugMessage(M64MSG_VERBOSE, "entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]); |
10426 | DebugMessage(M64MSG_VERBOSE, "dirty: "); |
10427 | if(regs[i].wasdirty&1) DebugMessage(M64MSG_VERBOSE, "r0 "); |
10428 | if((regs[i].wasdirty>>1)&1) DebugMessage(M64MSG_VERBOSE, "r1 "); |
10429 | if((regs[i].wasdirty>>2)&1) DebugMessage(M64MSG_VERBOSE, "r2 "); |
10430 | if((regs[i].wasdirty>>3)&1) DebugMessage(M64MSG_VERBOSE, "r3 "); |
10431 | if((regs[i].wasdirty>>4)&1) DebugMessage(M64MSG_VERBOSE, "r4 "); |
10432 | if((regs[i].wasdirty>>5)&1) DebugMessage(M64MSG_VERBOSE, "r5 "); |
10433 | if((regs[i].wasdirty>>6)&1) DebugMessage(M64MSG_VERBOSE, "r6 "); |
10434 | if((regs[i].wasdirty>>7)&1) DebugMessage(M64MSG_VERBOSE, "r7 "); |
10435 | if((regs[i].wasdirty>>8)&1) DebugMessage(M64MSG_VERBOSE, "r8 "); |
10436 | if((regs[i].wasdirty>>9)&1) DebugMessage(M64MSG_VERBOSE, "r9 "); |
10437 | if((regs[i].wasdirty>>10)&1) DebugMessage(M64MSG_VERBOSE, "r10 "); |
10438 | if((regs[i].wasdirty>>12)&1) DebugMessage(M64MSG_VERBOSE, "r12 "); |
10439 | #endif |
10440 | disassemble_inst(i); |
10441 | //printf ("ccadj[%d] = %d",i,ccadj[i]); |
10442 | #if NEW_DYNAREC == NEW_DYNAREC_X86 |
10443 | DebugMessage(M64MSG_VERBOSE, "eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]); |
10444 | if(regs[i].dirty&1) DebugMessage(M64MSG_VERBOSE, "eax "); |
10445 | if((regs[i].dirty>>1)&1) DebugMessage(M64MSG_VERBOSE, "ecx "); |
10446 | if((regs[i].dirty>>2)&1) DebugMessage(M64MSG_VERBOSE, "edx "); |
10447 | if((regs[i].dirty>>3)&1) DebugMessage(M64MSG_VERBOSE, "ebx "); |
10448 | if((regs[i].dirty>>5)&1) DebugMessage(M64MSG_VERBOSE, "ebp "); |
10449 | if((regs[i].dirty>>6)&1) DebugMessage(M64MSG_VERBOSE, "esi "); |
10450 | if((regs[i].dirty>>7)&1) DebugMessage(M64MSG_VERBOSE, "edi "); |
10451 | #endif |
10452 | #if NEW_DYNAREC == NEW_DYNAREC_ARM |
10453 | DebugMessage(M64MSG_VERBOSE, "r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]); |
10454 | if(regs[i].dirty&1) DebugMessage(M64MSG_VERBOSE, "r0 "); |
10455 | if((regs[i].dirty>>1)&1) DebugMessage(M64MSG_VERBOSE, "r1 "); |
10456 | if((regs[i].dirty>>2)&1) DebugMessage(M64MSG_VERBOSE, "r2 "); |
10457 | if((regs[i].dirty>>3)&1) DebugMessage(M64MSG_VERBOSE, "r3 "); |
10458 | if((regs[i].dirty>>4)&1) DebugMessage(M64MSG_VERBOSE, "r4 "); |
10459 | if((regs[i].dirty>>5)&1) DebugMessage(M64MSG_VERBOSE, "r5 "); |
10460 | if((regs[i].dirty>>6)&1) DebugMessage(M64MSG_VERBOSE, "r6 "); |
10461 | if((regs[i].dirty>>7)&1) DebugMessage(M64MSG_VERBOSE, "r7 "); |
10462 | if((regs[i].dirty>>8)&1) DebugMessage(M64MSG_VERBOSE, "r8 "); |
10463 | if((regs[i].dirty>>9)&1) DebugMessage(M64MSG_VERBOSE, "r9 "); |
10464 | if((regs[i].dirty>>10)&1) DebugMessage(M64MSG_VERBOSE, "r10 "); |
10465 | if((regs[i].dirty>>12)&1) DebugMessage(M64MSG_VERBOSE, "r12 "); |
10466 | #endif |
10467 | if(regs[i].isconst) { |
10468 | DebugMessage(M64MSG_VERBOSE, "constants: "); |
10469 | #if NEW_DYNAREC == NEW_DYNAREC_X86 |
10470 | if(regs[i].isconst&1) DebugMessage(M64MSG_VERBOSE, "eax=%x ",(int)constmap[i][0]); |
10471 | if((regs[i].isconst>>1)&1) DebugMessage(M64MSG_VERBOSE, "ecx=%x ",(int)constmap[i][1]); |
10472 | if((regs[i].isconst>>2)&1) DebugMessage(M64MSG_VERBOSE, "edx=%x ",(int)constmap[i][2]); |
10473 | if((regs[i].isconst>>3)&1) DebugMessage(M64MSG_VERBOSE, "ebx=%x ",(int)constmap[i][3]); |
10474 | if((regs[i].isconst>>5)&1) DebugMessage(M64MSG_VERBOSE, "ebp=%x ",(int)constmap[i][5]); |
10475 | if((regs[i].isconst>>6)&1) DebugMessage(M64MSG_VERBOSE, "esi=%x ",(int)constmap[i][6]); |
10476 | if((regs[i].isconst>>7)&1) DebugMessage(M64MSG_VERBOSE, "edi=%x ",(int)constmap[i][7]); |
10477 | #endif |
10478 | #if NEW_DYNAREC == NEW_DYNAREC_ARM |
10479 | if(regs[i].isconst&1) DebugMessage(M64MSG_VERBOSE, "r0=%x ",(int)constmap[i][0]); |
10480 | if((regs[i].isconst>>1)&1) DebugMessage(M64MSG_VERBOSE, "r1=%x ",(int)constmap[i][1]); |
10481 | if((regs[i].isconst>>2)&1) DebugMessage(M64MSG_VERBOSE, "r2=%x ",(int)constmap[i][2]); |
10482 | if((regs[i].isconst>>3)&1) DebugMessage(M64MSG_VERBOSE, "r3=%x ",(int)constmap[i][3]); |
10483 | if((regs[i].isconst>>4)&1) DebugMessage(M64MSG_VERBOSE, "r4=%x ",(int)constmap[i][4]); |
10484 | if((regs[i].isconst>>5)&1) DebugMessage(M64MSG_VERBOSE, "r5=%x ",(int)constmap[i][5]); |
10485 | if((regs[i].isconst>>6)&1) DebugMessage(M64MSG_VERBOSE, "r6=%x ",(int)constmap[i][6]); |
10486 | if((regs[i].isconst>>7)&1) DebugMessage(M64MSG_VERBOSE, "r7=%x ",(int)constmap[i][7]); |
10487 | if((regs[i].isconst>>8)&1) DebugMessage(M64MSG_VERBOSE, "r8=%x ",(int)constmap[i][8]); |
10488 | if((regs[i].isconst>>9)&1) DebugMessage(M64MSG_VERBOSE, "r9=%x ",(int)constmap[i][9]); |
10489 | if((regs[i].isconst>>10)&1) DebugMessage(M64MSG_VERBOSE, "r10=%x ",(int)constmap[i][10]); |
10490 | if((regs[i].isconst>>12)&1) DebugMessage(M64MSG_VERBOSE, "r12=%x ",(int)constmap[i][12]); |
10491 | #endif |
10492 | } |
10493 | DebugMessage(M64MSG_VERBOSE, " 32:"); |
10494 | for(r=0;r<=CCREG;r++) { |
10495 | if((regs[i].is32>>r)&1) { |
10496 | if(r==CCREG) DebugMessage(M64MSG_VERBOSE, " CC"); |
10497 | else if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI"); |
10498 | else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO"); |
10499 | else DebugMessage(M64MSG_VERBOSE, " r%d",r); |
10500 | } |
10501 | } |
10502 | /*DebugMessage(M64MSG_VERBOSE, " p32:"); |
10503 | for(r=0;r<=CCREG;r++) { |
10504 | if((p32[i]>>r)&1) { |
10505 | if(r==CCREG) DebugMessage(M64MSG_VERBOSE, " CC"); |
10506 | else if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI"); |
10507 | else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO"); |
10508 | else DebugMessage(M64MSG_VERBOSE, " r%d",r); |
10509 | } |
10510 | } |
10511 | if(p32[i]!=regs[i].is32) DebugMessage(M64MSG_VERBOSE, " NO MATCH");*/ |
10512 | if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) { |
10513 | #if NEW_DYNAREC == NEW_DYNAREC_X86 |
10514 | DebugMessage(M64MSG_VERBOSE, "branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); |
10515 | if(branch_regs[i].dirty&1) DebugMessage(M64MSG_VERBOSE, "eax "); |
10516 | if((branch_regs[i].dirty>>1)&1) DebugMessage(M64MSG_VERBOSE, "ecx "); |
10517 | if((branch_regs[i].dirty>>2)&1) DebugMessage(M64MSG_VERBOSE, "edx "); |
10518 | if((branch_regs[i].dirty>>3)&1) DebugMessage(M64MSG_VERBOSE, "ebx "); |
10519 | if((branch_regs[i].dirty>>5)&1) DebugMessage(M64MSG_VERBOSE, "ebp "); |
10520 | if((branch_regs[i].dirty>>6)&1) DebugMessage(M64MSG_VERBOSE, "esi "); |
10521 | if((branch_regs[i].dirty>>7)&1) DebugMessage(M64MSG_VERBOSE, "edi "); |
10522 | #endif |
10523 | #if NEW_DYNAREC == NEW_DYNAREC_ARM |
10524 | DebugMessage(M64MSG_VERBOSE, "branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]); |
10525 | if(branch_regs[i].dirty&1) DebugMessage(M64MSG_VERBOSE, "r0 "); |
10526 | if((branch_regs[i].dirty>>1)&1) DebugMessage(M64MSG_VERBOSE, "r1 "); |
10527 | if((branch_regs[i].dirty>>2)&1) DebugMessage(M64MSG_VERBOSE, "r2 "); |
10528 | if((branch_regs[i].dirty>>3)&1) DebugMessage(M64MSG_VERBOSE, "r3 "); |
10529 | if((branch_regs[i].dirty>>4)&1) DebugMessage(M64MSG_VERBOSE, "r4 "); |
10530 | if((branch_regs[i].dirty>>5)&1) DebugMessage(M64MSG_VERBOSE, "r5 "); |
10531 | if((branch_regs[i].dirty>>6)&1) DebugMessage(M64MSG_VERBOSE, "r6 "); |
10532 | if((branch_regs[i].dirty>>7)&1) DebugMessage(M64MSG_VERBOSE, "r7 "); |
10533 | if((branch_regs[i].dirty>>8)&1) DebugMessage(M64MSG_VERBOSE, "r8 "); |
10534 | if((branch_regs[i].dirty>>9)&1) DebugMessage(M64MSG_VERBOSE, "r9 "); |
10535 | if((branch_regs[i].dirty>>10)&1) DebugMessage(M64MSG_VERBOSE, "r10 "); |
10536 | if((branch_regs[i].dirty>>12)&1) DebugMessage(M64MSG_VERBOSE, "r12 "); |
10537 | #endif |
10538 | DebugMessage(M64MSG_VERBOSE, " 32:"); |
10539 | for(r=0;r<=CCREG;r++) { |
10540 | if((branch_regs[i].is32>>r)&1) { |
10541 | if(r==CCREG) DebugMessage(M64MSG_VERBOSE, " CC"); |
10542 | else if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI"); |
10543 | else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO"); |
10544 | else DebugMessage(M64MSG_VERBOSE, " r%d",r); |
10545 | } |
10546 | } |
10547 | } |
10548 | } |
10549 | #endif |
10550 | |
10551 | /* Pass 8 - Assembly */ |
10552 | linkcount=0;stubcount=0; |
10553 | ds=0;is_delayslot=0; |
10554 | cop1_usable=0; |
10555 | #ifndef DESTRUCTIVE_WRITEBACK |
10556 | uint64_t is32_pre=0; |
10557 | u_int dirty_pre=0; |
10558 | #endif |
10559 | u_int beginning=(u_int)out; |
10560 | if((u_int)addr&1) { |
10561 | ds=1; |
10562 | pagespan_ds(); |
10563 | } |
10564 | for(i=0;i<slen;i++) |
10565 | { |
10566 | //if(ds) DebugMessage(M64MSG_VERBOSE, "ds: "); |
10567 | // if((void*)assem_debug==(void*)printf) disassemble_inst(i); |
10568 | #if defined( ASSEM_DEBUG ) |
10569 | disassemble_inst(i); |
10570 | #endif |
10571 | if(ds) { |
10572 | ds=0; // Skip delay slot |
10573 | if(bt[i]) assem_debug("OOPS - branch into delay slot"); |
10574 | instr_addr[i]=0; |
10575 | } else { |
10576 | #ifndef DESTRUCTIVE_WRITEBACK |
10577 | if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000)) |
10578 | { |
10579 | wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32, |
10580 | unneeded_reg[i],unneeded_reg_upper[i]); |
10581 | wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre, |
10582 | unneeded_reg[i],unneeded_reg_upper[i]); |
10583 | } |
10584 | is32_pre=regs[i].is32; |
10585 | dirty_pre=regs[i].dirty; |
10586 | #endif |
10587 | // write back |
10588 | if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000)) |
10589 | { |
10590 | wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32, |
10591 | unneeded_reg[i],unneeded_reg_upper[i]); |
10592 | loop_preload(regmap_pre[i],regs[i].regmap_entry); |
10593 | } |
10594 | // branch target entry point |
10595 | instr_addr[i]=(u_int)out; |
10596 | assem_debug("<->"); |
10597 | // load regs |
10598 | if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG) |
10599 | wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32); |
10600 | load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]); |
10601 | address_generation(i,®s[i],regs[i].regmap_entry); |
10602 | load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i); |
10603 | if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) |
10604 | { |
10605 | // Load the delay slot registers if necessary |
10606 | if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]) |
10607 | load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]); |
10608 | if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]) |
10609 | load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]); |
10610 | if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39) |
10611 | load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP); |
10612 | } |
10613 | else if(i+1<slen) |
10614 | { |
10615 | // Preload registers for following instruction |
10616 | if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]) |
10617 | if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i]) |
10618 | load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]); |
10619 | if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]) |
10620 | if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i]) |
10621 | load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]); |
10622 | } |
10623 | // TODO: if(is_ooo(i)) address_generation(i+1); |
10624 | if(itype[i]==CJUMP||itype[i]==FJUMP) |
10625 | load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG); |
10626 | if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) |
10627 | load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,MMREG,ROREG); |
10628 | if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39) |
10629 | load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP); |
10630 | if(bt[i]) cop1_usable=0; |
10631 | // assemble |
10632 | switch(itype[i]) { |
10633 | case ALU: |
10634 | alu_assemble(i,®s[i]);break; |
10635 | case IMM16: |
10636 | imm16_assemble(i,®s[i]);break; |
10637 | case SHIFT: |
10638 | shift_assemble(i,®s[i]);break; |
10639 | case SHIFTIMM: |
10640 | shiftimm_assemble(i,®s[i]);break; |
10641 | case LOAD: |
10642 | load_assemble(i,®s[i]);break; |
10643 | case LOADLR: |
10644 | loadlr_assemble(i,®s[i]);break; |
10645 | case STORE: |
10646 | store_assemble(i,®s[i]);break; |
10647 | case STORELR: |
10648 | storelr_assemble(i,®s[i]);break; |
10649 | case COP0: |
10650 | cop0_assemble(i,®s[i]);break; |
10651 | case COP1: |
10652 | cop1_assemble(i,®s[i]);break; |
10653 | case C1LS: |
10654 | c1ls_assemble(i,®s[i]);break; |
10655 | case FCONV: |
10656 | fconv_assemble(i,®s[i]);break; |
10657 | case FLOAT: |
10658 | float_assemble(i,®s[i]);break; |
10659 | case FCOMP: |
10660 | fcomp_assemble(i,®s[i]);break; |
10661 | case MULTDIV: |
10662 | multdiv_assemble(i,®s[i]);break; |
10663 | case MOV: |
10664 | mov_assemble(i,®s[i]);break; |
10665 | case SYSCALL: |
10666 | syscall_assemble(i,®s[i]);break; |
10667 | case UJUMP: |
10668 | ujump_assemble(i,®s[i]);ds=1;break; |
10669 | case RJUMP: |
10670 | rjump_assemble(i,®s[i]);ds=1;break; |
10671 | case CJUMP: |
10672 | cjump_assemble(i,®s[i]);ds=1;break; |
10673 | case SJUMP: |
10674 | sjump_assemble(i,®s[i]);ds=1;break; |
10675 | case FJUMP: |
10676 | fjump_assemble(i,®s[i]);ds=1;break; |
10677 | case SPAN: |
10678 | pagespan_assemble(i,®s[i]);break; |
10679 | } |
10680 | if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000) |
10681 | literal_pool(1024); |
10682 | else |
10683 | literal_pool_jumpover(256); |
10684 | } |
10685 | } |
10686 | //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000); |
10687 | // If the block did not end with an unconditional branch, |
10688 | // add a jump to the next instruction. |
10689 | if(i>1) { |
10690 | if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) { |
10691 | assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP); |
10692 | assert(i==slen); |
10693 | if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) { |
10694 | store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4); |
10695 | if(regs[i-1].regmap[HOST_CCREG]!=CCREG) |
10696 | emit_loadreg(CCREG,HOST_CCREG); |
10697 | emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG); |
10698 | } |
10699 | else if(!likely[i-2]) |
10700 | { |
10701 | store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4); |
10702 | assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG); |
10703 | } |
10704 | else |
10705 | { |
10706 | store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4); |
10707 | assert(regs[i-2].regmap[HOST_CCREG]==CCREG); |
10708 | } |
10709 | add_to_linker((int)out,start+i*4,0); |
10710 | emit_jmp(0); |
10711 | } |
10712 | } |
10713 | else |
10714 | { |
10715 | assert(i>0); |
10716 | assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP); |
10717 | store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4); |
10718 | if(regs[i-1].regmap[HOST_CCREG]!=CCREG) |
10719 | emit_loadreg(CCREG,HOST_CCREG); |
10720 | emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG); |
10721 | add_to_linker((int)out,start+i*4,0); |
10722 | emit_jmp(0); |
10723 | } |
10724 | |
10725 | // TODO: delay slot stubs? |
10726 | // Stubs |
10727 | for(i=0;i<stubcount;i++) |
10728 | { |
10729 | switch(stubs[i][0]) |
10730 | { |
10731 | case LOADB_STUB: |
10732 | case LOADH_STUB: |
10733 | case LOADW_STUB: |
10734 | case LOADD_STUB: |
10735 | case LOADBU_STUB: |
10736 | case LOADHU_STUB: |
10737 | do_readstub(i);break; |
10738 | case STOREB_STUB: |
10739 | case STOREH_STUB: |
10740 | case STOREW_STUB: |
10741 | case STORED_STUB: |
10742 | do_writestub(i);break; |
10743 | case CC_STUB: |
10744 | do_ccstub(i);break; |
10745 | case INVCODE_STUB: |
10746 | do_invstub(i);break; |
10747 | case FP_STUB: |
10748 | do_cop1stub(i);break; |
10749 | case STORELR_STUB: |
10750 | do_unalignedwritestub(i);break; |
10751 | } |
10752 | } |
10753 | |
10754 | /* Pass 9 - Linker */ |
10755 | for(i=0;i<linkcount;i++) |
10756 | { |
10757 | assem_debug("%8x -> %8x",link_addr[i][0],link_addr[i][1]); |
10758 | literal_pool(64); |
10759 | if(!link_addr[i][2]) |
10760 | { |
10761 | void *stub=out; |
10762 | void *addr=check_addr(link_addr[i][1]); |
10763 | emit_extjump(link_addr[i][0],link_addr[i][1]); |
10764 | if(addr) { |
10765 | set_jump_target(link_addr[i][0],(int)addr); |
10766 | add_link(link_addr[i][1],stub); |
10767 | } |
10768 | else set_jump_target(link_addr[i][0],(int)stub); |
10769 | } |
10770 | else |
10771 | { |
10772 | // Internal branch |
10773 | int target=(link_addr[i][1]-start)>>2; |
10774 | assert(target>=0&&target<slen); |
10775 | assert(instr_addr[target]); |
10776 | //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
10777 | //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1); |
10778 | //#else |
10779 | set_jump_target(link_addr[i][0],instr_addr[target]); |
10780 | //#endif |
10781 | } |
10782 | } |
10783 | // External Branch Targets (jump_in) |
10784 | if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow; |
10785 | for(i=0;i<slen;i++) |
10786 | { |
10787 | if(bt[i]||i==0) |
10788 | { |
10789 | if(instr_addr[i]) // TODO - delay slots (=null) |
10790 | { |
10791 | u_int vaddr=start+i*4; |
10792 | u_int page=(0x80000000^vaddr)>>12; |
10793 | u_int vpage=page; |
10794 | if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[page^0x80000]^0x80000000)>>12; |
10795 | if(page>2048) page=2048+(page&2047); |
10796 | if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead |
10797 | if(vpage>2048) vpage=2048+(vpage&2047); |
10798 | literal_pool(256); |
10799 | //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG))) |
10800 | if(!requires_32bit[i]) |
10801 | { |
10802 | assem_debug("%8x (%d) <- %8x",instr_addr[i],i,start+i*4); |
10803 | assem_debug("jump_in: %x",start+i*4); |
10804 | ll_add(jump_dirty+vpage,vaddr,(void *)out); |
10805 | int entry_point=do_dirty_stub(i); |
10806 | ll_add(jump_in+page,vaddr,(void *)entry_point); |
10807 | // If there was an existing entry in the hash table, |
10808 | // replace it with the new address. |
10809 | // Don't add new entries. We'll insert the |
10810 | // ones that actually get used in check_addr(). |
10811 | u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; |
10812 | if(ht_bin[0]==vaddr) { |
10813 | ht_bin[1]=entry_point; |
10814 | } |
10815 | if(ht_bin[2]==vaddr) { |
10816 | ht_bin[3]=entry_point; |
10817 | } |
10818 | } |
10819 | else |
10820 | { |
10821 | u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32); |
10822 | assem_debug("%8x (%d) <- %8x",instr_addr[i],i,start+i*4); |
10823 | assem_debug("jump_in: %x (restricted - %x)",start+i*4,r); |
10824 | //int entry_point=(int)out; |
10825 | ////assem_debug("entry_point: %x",entry_point); |
10826 | //load_regs_entry(i); |
10827 | //if(entry_point==(int)out) |
10828 | // entry_point=instr_addr[i]; |
10829 | //else |
10830 | // emit_jmp(instr_addr[i]); |
10831 | //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point); |
10832 | ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out); |
10833 | int entry_point=do_dirty_stub(i); |
10834 | ll_add_32(jump_in+page,vaddr,r,(void *)entry_point); |
10835 | } |
10836 | } |
10837 | } |
10838 | } |
10839 | // Write out the literal pool if necessary |
10840 | literal_pool(0); |
10841 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
10842 | // Align code |
10843 | if(((u_int)out)&7) emit_addnop(13); |
10844 | #endif |
10845 | assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE); |
10846 | //DebugMessage(M64MSG_VERBOSE, "shadow buffer: %x-%x",(int)copy,(int)copy+slen*4); |
10847 | memcpy(copy,source,slen*4); |
10848 | copy+=slen*4; |
10849 | |
10850 | #if NEW_DYNAREC == NEW_DYNAREC_ARM |
10851 | __clear_cache((void *)beginning,out); |
10852 | //cacheflush((void *)beginning,out,0); |
10853 | #endif |
10854 | |
10855 | // If we're within 256K of the end of the buffer, |
10856 | // start over from the beginning. (Is 256K enough?) |
10857 | if(out > (u_char *)(base_addr+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE-JUMP_TABLE_SIZE)) |
10858 | out=(u_char *)base_addr; |
10859 | |
10860 | // Trap writes to any of the pages we compiled |
10861 | for(i=start>>12;i<=(start+slen*4)>>12;i++) { |
10862 | invalid_code[i]=0; |
10863 | memory_map[i]|=0x40000000; |
10864 | if((signed int)start>=(signed int)0xC0000000) { |
10865 | assert(using_tlb); |
10866 | j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12; |
10867 | invalid_code[j]=0; |
10868 | memory_map[j]|=0x40000000; |
10869 | //DebugMessage(M64MSG_VERBOSE, "write protect physical page: %x (virtual %x)",j<<12,start); |
10870 | } |
10871 | } |
10872 | |
10873 | /* Pass 10 - Free memory by expiring oldest blocks */ |
10874 | |
10875 | int end=((((intptr_t)out-(intptr_t)base_addr)>>(TARGET_SIZE_2-16))+16384)&65535; |
10876 | while(expirep!=end) |
10877 | { |
10878 | int shift=TARGET_SIZE_2-3; // Divide into 8 blocks |
10879 | int base=(int)base_addr+((expirep>>13)<<shift); // Base address of this block |
10880 | inv_debug("EXP: Phase %d\n",expirep); |
10881 | switch((expirep>>11)&3) |
10882 | { |
10883 | case 0: |
10884 | // Clear jump_in and jump_dirty |
10885 | ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift); |
10886 | ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift); |
10887 | ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift); |
10888 | ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift); |
10889 | break; |
10890 | case 1: |
10891 | // Clear pointers |
10892 | ll_kill_pointers(jump_out[expirep&2047],base,shift); |
10893 | ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift); |
10894 | break; |
10895 | case 2: |
10896 | // Clear hash table |
10897 | for(i=0;i<32;i++) { |
10898 | u_int *ht_bin=hash_table[((expirep&2047)<<5)+i]; |
10899 | if((ht_bin[3]>>shift)==(base>>shift) || |
10900 | ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) { |
10901 | inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]); |
10902 | ht_bin[2]=ht_bin[3]=-1; |
10903 | } |
10904 | if((ht_bin[1]>>shift)==(base>>shift) || |
10905 | ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) { |
10906 | inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]); |
10907 | ht_bin[0]=ht_bin[2]; |
10908 | ht_bin[1]=ht_bin[3]; |
10909 | ht_bin[2]=ht_bin[3]=-1; |
10910 | } |
10911 | } |
10912 | break; |
10913 | case 3: |
10914 | // Clear jump_out |
10915 | #if NEW_DYNAREC == NEW_DYNAREC_ARM |
10916 | if((expirep&2047)==0) |
10917 | do_clear_cache(); |
10918 | #endif |
10919 | ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift); |
10920 | ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift); |
10921 | break; |
10922 | } |
10923 | expirep=(expirep+1)&65535; |
10924 | } |
10925 | return 0; |
10926 | } |
10927 | |
10928 | void TLBWI_new(void) |
10929 | { |
10930 | unsigned int i; |
10931 | /* Remove old entries */ |
10932 | unsigned int old_start_even=tlb_e[Index&0x3F].start_even; |
10933 | unsigned int old_end_even=tlb_e[Index&0x3F].end_even; |
10934 | unsigned int old_start_odd=tlb_e[Index&0x3F].start_odd; |
10935 | unsigned int old_end_odd=tlb_e[Index&0x3F].end_odd; |
10936 | for (i=old_start_even>>12; i<=old_end_even>>12; i++) |
10937 | { |
10938 | if(i<0x80000||i>0xBFFFF) |
10939 | { |
10940 | invalidate_block(i); |
10941 | memory_map[i]=-1; |
10942 | } |
10943 | } |
10944 | for (i=old_start_odd>>12; i<=old_end_odd>>12; i++) |
10945 | { |
10946 | if(i<0x80000||i>0xBFFFF) |
10947 | { |
10948 | invalidate_block(i); |
10949 | memory_map[i]=-1; |
10950 | } |
10951 | } |
10952 | cached_interpreter_table.TLBWI(); |
10953 | //DebugMessage(M64MSG_VERBOSE, "TLBWI: index=%d",Index); |
10954 | //DebugMessage(M64MSG_VERBOSE, "TLBWI: start_even=%x end_even=%x phys_even=%x v=%d d=%d",tlb_e[Index&0x3F].start_even,tlb_e[Index&0x3F].end_even,tlb_e[Index&0x3F].phys_even,tlb_e[Index&0x3F].v_even,tlb_e[Index&0x3F].d_even); |
10955 | //DebugMessage(M64MSG_VERBOSE, "TLBWI: start_odd=%x end_odd=%x phys_odd=%x v=%d d=%d",tlb_e[Index&0x3F].start_odd,tlb_e[Index&0x3F].end_odd,tlb_e[Index&0x3F].phys_odd,tlb_e[Index&0x3F].v_odd,tlb_e[Index&0x3F].d_odd); |
10956 | /* Combine tlb_LUT_r, tlb_LUT_w, and invalid_code into a single table |
10957 | for fast look up. */ |
10958 | for (i=tlb_e[Index&0x3F].start_even>>12; i<=tlb_e[Index&0x3F].end_even>>12; i++) |
10959 | { |
10960 | //DebugMessage(M64MSG_VERBOSE, "%x: r:%8x w:%8x",i,tlb_LUT_r[i],tlb_LUT_w[i]); |
10961 | if(i<0x80000||i>0xBFFFF) |
10962 | { |
10963 | if(tlb_LUT_r[i]) { |
10964 | memory_map[i]=((tlb_LUT_r[i]&0xFFFFF000)-(i<<12)+(unsigned int)rdram-0x80000000)>>2; |
10965 | // FIXME: should make sure the physical page is invalid too |
10966 | if(!tlb_LUT_w[i]||!invalid_code[i]) { |
10967 | memory_map[i]|=0x40000000; // Write protect |
10968 | }else{ |
10969 | assert(tlb_LUT_r[i]==tlb_LUT_w[i]); |
10970 | } |
10971 | if(!using_tlb) DebugMessage(M64MSG_VERBOSE, "Enabled TLB"); |
10972 | // Tell the dynamic recompiler to generate tlb lookup code |
10973 | using_tlb=1; |
10974 | } |
10975 | else memory_map[i]=-1; |
10976 | } |
10977 | //DebugMessage(M64MSG_VERBOSE, "memory_map[%x]: %8x (+%8x)",i,memory_map[i],memory_map[i]<<2); |
10978 | } |
10979 | for (i=tlb_e[Index&0x3F].start_odd>>12; i<=tlb_e[Index&0x3F].end_odd>>12; i++) |
10980 | { |
10981 | //DebugMessage(M64MSG_VERBOSE, "%x: r:%8x w:%8x",i,tlb_LUT_r[i],tlb_LUT_w[i]); |
10982 | if(i<0x80000||i>0xBFFFF) |
10983 | { |
10984 | if(tlb_LUT_r[i]) { |
10985 | memory_map[i]=((tlb_LUT_r[i]&0xFFFFF000)-(i<<12)+(unsigned int)rdram-0x80000000)>>2; |
10986 | // FIXME: should make sure the physical page is invalid too |
10987 | if(!tlb_LUT_w[i]||!invalid_code[i]) { |
10988 | memory_map[i]|=0x40000000; // Write protect |
10989 | }else{ |
10990 | assert(tlb_LUT_r[i]==tlb_LUT_w[i]); |
10991 | } |
10992 | if(!using_tlb) DebugMessage(M64MSG_VERBOSE, "Enabled TLB"); |
10993 | // Tell the dynamic recompiler to generate tlb lookup code |
10994 | using_tlb=1; |
10995 | } |
10996 | else memory_map[i]=-1; |
10997 | } |
10998 | //DebugMessage(M64MSG_VERBOSE, "memory_map[%x]: %8x (+%8x)",i,memory_map[i],memory_map[i]<<2); |
10999 | } |
11000 | } |
11001 | |
11002 | void TLBWR_new(void) |
11003 | { |
11004 | unsigned int i; |
11005 | Random = (Count/2 % (32 - Wired)) + Wired; |
11006 | /* Remove old entries */ |
11007 | unsigned int old_start_even=tlb_e[Random&0x3F].start_even; |
11008 | unsigned int old_end_even=tlb_e[Random&0x3F].end_even; |
11009 | unsigned int old_start_odd=tlb_e[Random&0x3F].start_odd; |
11010 | unsigned int old_end_odd=tlb_e[Random&0x3F].end_odd; |
11011 | for (i=old_start_even>>12; i<=old_end_even>>12; i++) |
11012 | { |
11013 | if(i<0x80000||i>0xBFFFF) |
11014 | { |
11015 | invalidate_block(i); |
11016 | memory_map[i]=-1; |
11017 | } |
11018 | } |
11019 | for (i=old_start_odd>>12; i<=old_end_odd>>12; i++) |
11020 | { |
11021 | if(i<0x80000||i>0xBFFFF) |
11022 | { |
11023 | invalidate_block(i); |
11024 | memory_map[i]=-1; |
11025 | } |
11026 | } |
11027 | cached_interpreter_table.TLBWR(); |
11028 | /* Combine tlb_LUT_r, tlb_LUT_w, and invalid_code into a single table |
11029 | for fast look up. */ |
11030 | for (i=tlb_e[Random&0x3F].start_even>>12; i<=tlb_e[Random&0x3F].end_even>>12; i++) |
11031 | { |
11032 | //DebugMessage(M64MSG_VERBOSE, "%x: r:%8x w:%8x",i,tlb_LUT_r[i],tlb_LUT_w[i]); |
11033 | if(i<0x80000||i>0xBFFFF) |
11034 | { |
11035 | if(tlb_LUT_r[i]) { |
11036 | memory_map[i]=((tlb_LUT_r[i]&0xFFFFF000)-(i<<12)+(unsigned int)rdram-0x80000000)>>2; |
11037 | // FIXME: should make sure the physical page is invalid too |
11038 | if(!tlb_LUT_w[i]||!invalid_code[i]) { |
11039 | memory_map[i]|=0x40000000; // Write protect |
11040 | }else{ |
11041 | assert(tlb_LUT_r[i]==tlb_LUT_w[i]); |
11042 | } |
11043 | if(!using_tlb) DebugMessage(M64MSG_VERBOSE, "Enabled TLB"); |
11044 | // Tell the dynamic recompiler to generate tlb lookup code |
11045 | using_tlb=1; |
11046 | } |
11047 | else memory_map[i]=-1; |
11048 | } |
11049 | //DebugMessage(M64MSG_VERBOSE, "memory_map[%x]: %8x (+%8x)",i,memory_map[i],memory_map[i]<<2); |
11050 | } |
11051 | for (i=tlb_e[Random&0x3F].start_odd>>12; i<=tlb_e[Random&0x3F].end_odd>>12; i++) |
11052 | { |
11053 | //DebugMessage(M64MSG_VERBOSE, "%x: r:%8x w:%8x",i,tlb_LUT_r[i],tlb_LUT_w[i]); |
11054 | if(i<0x80000||i>0xBFFFF) |
11055 | { |
11056 | if(tlb_LUT_r[i]) { |
11057 | memory_map[i]=((tlb_LUT_r[i]&0xFFFFF000)-(i<<12)+(unsigned int)rdram-0x80000000)>>2; |
11058 | // FIXME: should make sure the physical page is invalid too |
11059 | if(!tlb_LUT_w[i]||!invalid_code[i]) { |
11060 | memory_map[i]|=0x40000000; // Write protect |
11061 | }else{ |
11062 | assert(tlb_LUT_r[i]==tlb_LUT_w[i]); |
11063 | } |
11064 | if(!using_tlb) DebugMessage(M64MSG_VERBOSE, "Enabled TLB"); |
11065 | // Tell the dynamic recompiler to generate tlb lookup code |
11066 | using_tlb=1; |
11067 | } |
11068 | else memory_map[i]=-1; |
11069 | } |
11070 | //DebugMessage(M64MSG_VERBOSE, "memory_map[%x]: %8x (+%8x)",i,memory_map[i],memory_map[i]<<2); |
11071 | } |
11072 | } |