source/mupen64plus-core/src/r4300/new_dynarec/new_dynarec.c

   1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
   2  *   Mupen64plus - new_dynarec.c                                           *
   3  *   Copyright (C) 2009-2011 Ari64                                         *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
  19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
  20
  21 #include <stdio.h>
  22 #include <string.h>
  23 #include <stdarg.h>
  24 #include <stdlib.h>
  25 #include <stdint.h> //include for uint64_t
  26 #include <assert.h>
  27
  28 #include "../recomp.h"
  29 #include "../recomph.h" //include for function prototypes
  30 #include "../macros.h"
  31 #include "../r4300.h"
  32 #include "../ops.h"
  33 #include "../interupt.h"
  34 #include "new_dynarec.h"
  35
  36 #include "../../memory/memory.h"
  37 #include "../../main/rom.h"
  38
  39 #include <sys/mman.h>
  40
  41 #if NEW_DYNAREC == NEW_DYNAREC_X86
  42 #include "assem_x86.h"
  43 #elif NEW_DYNAREC == NEW_DYNAREC_ARM
  44 #include "assem_arm.h"
  45 #else
  46 #error Unsupported dynarec architecture
  47 #endif
  48
  49 #define MAXBLOCK 4096
  50 #define MAX_OUTPUT_BLOCK_SIZE 262144
  51 #define CLOCK_DIVIDER 2
  52
  53 void *base_addr;
  54
  55 struct regstat
  56 {
  57   signed char regmap_entry[HOST_REGS];
  58   signed char regmap[HOST_REGS];
  59   uint64_t was32;
  60   uint64_t is32;
  61   uint64_t wasdirty;
  62   uint64_t dirty;
  63   uint64_t u;
  64   uint64_t uu;
  65   u_int wasconst;
  66   u_int isconst;
  67   uint64_t constmap[HOST_REGS];
  68 };
  69
  70 struct ll_entry
  71 {
  72   u_int vaddr;
  73   u_int reg32;
  74   void *addr;
  75   struct ll_entry *next;
  76 };
  77
  78 static u_int start;
  79 static u_int *source;
  80 static u_int pagelimit;
  81 static char insn[MAXBLOCK][10];
  82 static u_char itype[MAXBLOCK];
  83 static u_char opcode[MAXBLOCK];
  84 static u_char opcode2[MAXBLOCK];
  85 static u_char bt[MAXBLOCK];
  86 static u_char rs1[MAXBLOCK];
  87 static u_char rs2[MAXBLOCK];
  88 static u_char rt1[MAXBLOCK];
  89 static u_char rt2[MAXBLOCK];
  90 static u_char us1[MAXBLOCK];
  91 static u_char us2[MAXBLOCK];
  92 static u_char dep1[MAXBLOCK];
  93 static u_char dep2[MAXBLOCK];
  94 static u_char lt1[MAXBLOCK];
  95 static int imm[MAXBLOCK];
  96 static u_int ba[MAXBLOCK];
  97 static char likely[MAXBLOCK];
  98 static char is_ds[MAXBLOCK];
  99 static char ooo[MAXBLOCK];
 100 static uint64_t unneeded_reg[MAXBLOCK];
 101 static uint64_t unneeded_reg_upper[MAXBLOCK];
 102 static uint64_t branch_unneeded_reg[MAXBLOCK];
 103 static uint64_t branch_unneeded_reg_upper[MAXBLOCK];
 104 static uint64_t p32[MAXBLOCK];
 105 static uint64_t pr32[MAXBLOCK];
 106 static signed char regmap_pre[MAXBLOCK][HOST_REGS];
 107 #ifdef ASSEM_DEBUG
 108 static signed char regmap[MAXBLOCK][HOST_REGS];
 109 static signed char regmap_entry[MAXBLOCK][HOST_REGS];
 110 #endif
 111 static uint64_t constmap[MAXBLOCK][HOST_REGS];
 112 static struct regstat regs[MAXBLOCK];
 113 static struct regstat branch_regs[MAXBLOCK];
 114 static signed char minimum_free_regs[MAXBLOCK];
 115 static u_int needed_reg[MAXBLOCK];
 116 static uint64_t requires_32bit[MAXBLOCK];
 117 static u_int wont_dirty[MAXBLOCK];
 118 static u_int will_dirty[MAXBLOCK];
 119 static int ccadj[MAXBLOCK];
 120 static int slen;
 121 static u_int instr_addr[MAXBLOCK];
 122 static u_int link_addr[MAXBLOCK][3];
 123 static int linkcount;
 124 static u_int stubs[MAXBLOCK*3][8];
 125 static int stubcount;
 126 static int literalcount;
 127 static int is_delayslot;
 128 static int cop1_usable;
 129 u_char *out;
 130 struct ll_entry *jump_in[4096];
 131 static struct ll_entry *jump_out[4096];
 132 struct ll_entry *jump_dirty[4096];
 133 u_int hash_table[65536][4]  __attribute__((aligned(16)));
 134 static char shadow[2097152]  __attribute__((aligned(16)));
 135 static void *copy;
 136 static int expirep;
 137 u_int using_tlb;
 138 static u_int stop_after_jal;
 139 extern u_char restore_candidate[512];
 140 extern int cycle_count;
 141
 142   /* registers that may be allocated */
 143   /* 1-31 gpr */
 144 #define HIREG 32 // hi
 145 #define LOREG 33 // lo
 146 #define FSREG 34 // FPU status (FCSR)
 147 #define CSREG 35 // Coprocessor status
 148 #define CCREG 36 // Cycle count
 149 #define INVCP 37 // Pointer to invalid_code
 150 #define MMREG 38 // Pointer to memory_map
 151 #define ROREG 39 // ram offset (if rdram!=0x80000000)
 152 #define TEMPREG 40
 153 #define FTEMP 40 // FPU temporary register
 154 #define PTEMP 41 // Prefetch temporary register
 155 #define TLREG 42 // TLB mapping offset
 156 #define RHASH 43 // Return address hash
 157 #define RHTBL 44 // Return address hash table address
 158 #define RTEMP 45 // JR/JALR address register
 159 #define MAXREG 45
 160 #define AGEN1 46 // Address generation temporary register
 161 #define AGEN2 47 // Address generation temporary register
 162 #define MGEN1 48 // Maptable address generation temporary register
 163 #define MGEN2 49 // Maptable address generation temporary register
 164 #define BTREG 50 // Branch target temporary register
 165
 166   /* instruction types */
 167 #define NOP 0     // No operation
 168 #define LOAD 1    // Load
 169 #define STORE 2   // Store
 170 #define LOADLR 3  // Unaligned load
 171 #define STORELR 4 // Unaligned store
 172 #define MOV 5     // Move
 173 #define ALU 6     // Arithmetic/logic
 174 #define MULTDIV 7 // Multiply/divide
 175 #define SHIFT 8   // Shift by register
 176 #define SHIFTIMM 9// Shift by immediate
 177 #define IMM16 10  // 16-bit immediate
 178 #define RJUMP 11  // Unconditional jump to register
 179 #define UJUMP 12  // Unconditional jump
 180 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
 181 #define SJUMP 14  // Conditional branch (regimm format)
 182 #define COP0 15   // Coprocessor 0
 183 #define COP1 16   // Coprocessor 1
 184 #define C1LS 17   // Coprocessor 1 load/store
 185 #define FJUMP 18  // Conditional branch (floating point)
 186 #define FLOAT 19  // Floating point unit
 187 #define FCONV 20  // Convert integer to float
 188 #define FCOMP 21  // Floating point compare (sets FSREG)
 189 #define SYSCALL 22// SYSCALL
 190 #define OTHER 23  // Other
 191 #define SPAN 24   // Branch/delay slot spans 2 pages
 192 #define NI 25     // Not implemented
 193
 194   /* stubs */
 195 #define CC_STUB 1
 196 #define FP_STUB 2
 197 #define LOADB_STUB 3
 198 #define LOADH_STUB 4
 199 #define LOADW_STUB 5
 200 #define LOADD_STUB 6
 201 #define LOADBU_STUB 7
 202 #define LOADHU_STUB 8
 203 #define STOREB_STUB 9
 204 #define STOREH_STUB 10
 205 #define STOREW_STUB 11
 206 #define STORED_STUB 12
 207 #define STORELR_STUB 13
 208 #define INVCODE_STUB 14
 209
 210   /* branch codes */
 211 #define TAKEN 1
 212 #define NOTTAKEN 2
 213 #define NULLDS 3
 214
 215 /* bug-fix to implement __clear_cache (missing in Android; http://code.google.com/p/android/issues/detail?id=1803) */
 216 void __clear_cache_bugfix(char* begin, char *end);
 217 #ifdef ANDROID
 218         #define __clear_cache __clear_cache_bugfix
 219 #endif
 220
 221 // asm linkage
 222 int new_recompile_block(int addr);
 223 void *get_addr_ht(u_int vaddr);
 224 static void remove_hash(int vaddr);
 225 void dyna_linker();
 226 void dyna_linker_ds();
 227 void verify_code();
 228 void verify_code_vm();
 229 void verify_code_ds();
 230 void cc_interrupt();
 231 void fp_exception();
 232 void fp_exception_ds();
 233 void jump_syscall();
 234 void jump_eret();
 235 #if NEW_DYNAREC == NEW_DYNAREC_ARM
 236 static void invalidate_addr(u_int addr);
 237 #endif
 238
 239 // TLB
 240 void TLBWI_new();
 241 void TLBWR_new();
 242 void read_nomem_new();
 243 void read_nomemb_new();
 244 void read_nomemh_new();
 245 void read_nomemd_new();
 246 void write_nomem_new();
 247 void write_nomemb_new();
 248 void write_nomemh_new();
 249 void write_nomemd_new();
 250 void write_rdram_new();
 251 void write_rdramb_new();
 252 void write_rdramh_new();
 253 void write_rdramd_new();
 254 extern u_int memory_map[1048576];
 255
 256 // Needed by assembler
 257 static void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
 258 static void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
 259 static void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
 260 static void load_all_regs(signed char i_regmap[]);
 261 static void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
 262 static void load_regs_entry(int t);
 263 static void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
 264
 265 static void add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e);
 266 static void add_to_linker(int addr,int target,int ext);
 267 static int verify_dirty(void *addr);
 268
 269 //static int tracedebug=0;
 270
 271 //#define DEBUG_CYCLE_COUNT 1
 272
 273 // Uncomment these two lines to generate debug output:
 274 //#define ASSEM_DEBUG 1
 275 //#define INV_DEBUG 1
 276
 277 // Uncomment this line to output the number of NOTCOMPILED blocks as they occur:
 278 //#define COUNT_NOTCOMPILEDS 1
 279
 280 #if defined (COUNT_NOTCOMPILEDS )
 281         int notcompiledCount = 0;
 282 #endif
 283 static void nullf() {}
 284
 285 #if defined( ASSEM_DEBUG )
 286     #define assem_debug(...) DebugMessage(M64MSG_VERBOSE, __VA_ARGS__)
 287 #else
 288     #define assem_debug nullf
 289 #endif
 290 #if defined( INV_DEBUG )
 291     #define inv_debug(...) DebugMessage(M64MSG_VERBOSE, __VA_ARGS__)
 292 #else
 293     #define inv_debug nullf
 294 #endif
 295
 296 #define log_message(...) DebugMessage(M64MSG_VERBOSE, __VA_ARGS__)
 297
 298 static void tlb_hacks()
 299 {
 300   // Goldeneye hack
 301   if (strncmp((char *) ROM_HEADER.Name, "GOLDENEYE",9) == 0)
 302   {
 303     u_int addr;
 304     int n;
 305     switch (ROM_HEADER.Country_code&0xFF)
 306     {
 307       case 0x45: // U
 308         addr=0x34b30;
 309         break;
 310       case 0x4A: // J
 311         addr=0x34b70;
 312         break;
 313       case 0x50: // E
 314         addr=0x329f0;
 315         break;
 316       default:
 317         // Unknown country code
 318         addr=0;
 319         break;
 320     }
 321     u_int rom_addr=(u_int)rom;
 322     #ifdef ROM_COPY
 323     // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
 324     // in the lower 4G of memory to use this hack.  Copy it if necessary.
 325     if((void *)rom>(void *)0xffffffff) {
 326       munmap(ROM_COPY, 67108864);
 327       if(mmap(ROM_COPY, 12582912,
 328               PROT_READ | PROT_WRITE,
 329               MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
 330               -1, 0) <= 0) {DebugMessage(M64MSG_ERROR, "mmap() failed");}
 331       memcpy(ROM_COPY,rom,12582912);
 332       rom_addr=(u_int)ROM_COPY;
 333     }
 334     #endif
 335     if(addr) {
 336       for(n=0x7F000;n<0x80000;n++) {
 337         memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
 338       }
 339     }
 340   }
 341 }
 342
 343 // Get address from virtual address
 344 // This is called from the recompiled JR/JALR instructions
 345 void *get_addr(u_int vaddr)
 346 {
 347   u_int page=(vaddr^0x80000000)>>12;
 348   u_int vpage=page;
 349   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
 350   if(page>2048) page=2048+(page&2047);
 351   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
 352   if(vpage>2048) vpage=2048+(vpage&2047);
 353   struct ll_entry *head;
 354   //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr %x,page %d)",Count,next_interupt,vaddr,page);
 355   head=jump_in[page];
 356   while(head!=NULL) {
 357     if(head->vaddr==vaddr&&head->reg32==0) {
 358   //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr match %x: %x)",Count,next_interupt,vaddr,(int)head->addr);
 359       u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 360       ht_bin[3]=ht_bin[1];
 361       ht_bin[2]=ht_bin[0];
 362       ht_bin[1]=(int)head->addr;
 363       ht_bin[0]=vaddr;
 364       return head->addr;
 365     }
 366     head=head->next;
 367   }
 368   head=jump_dirty[vpage];
 369   while(head!=NULL) {
 370     if(head->vaddr==vaddr&&head->reg32==0) {
 371       //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr match dirty %x: %x)",Count,next_interupt,vaddr,(int)head->addr);
 372       // Don't restore blocks which are about to expire from the cache
 373       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 374       if(verify_dirty(head->addr)) {
 375         //DebugMessage(M64MSG_VERBOSE, "restore candidate: %x (%d) d=%d",vaddr,page,invalid_code[vaddr>>12]);
 376         invalid_code[vaddr>>12]=0;
 377         memory_map[vaddr>>12]|=0x40000000;
 378         if(vpage<2048) {
 379           if(tlb_LUT_r[vaddr>>12]) {
 380             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 381             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 382           }
 383           restore_candidate[vpage>>3]|=1<<(vpage&7);
 384         }
 385         else restore_candidate[page>>3]|=1<<(page&7);
 386         u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 387         if(ht_bin[0]==vaddr) {
 388           ht_bin[1]=(int)head->addr; // Replace existing entry
 389         }
 390         else
 391         {
 392           ht_bin[3]=ht_bin[1];
 393           ht_bin[2]=ht_bin[0];
 394           ht_bin[1]=(int)head->addr;
 395           ht_bin[0]=vaddr;
 396         }
 397         return head->addr;
 398       }
 399     }
 400     head=head->next;
 401   }
 402   //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr no-match %x)",Count,next_interupt,vaddr);
 403   int r=new_recompile_block(vaddr);
 404   if(r==0) return get_addr(vaddr);
 405   // Execute in unmapped page, generate pagefault execption
 406   Status|=2;
 407   Cause=(vaddr<<31)|0x8;
 408   EPC=(vaddr&1)?vaddr-5:vaddr;
 409   BadVAddr=(vaddr&~1);
 410   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 411   EntryHi=BadVAddr&0xFFFFE000;
 412   return get_addr_ht(0x80000000);
 413 }
 414 // Look up address in hash table first
 415 void *get_addr_ht(u_int vaddr)
 416 {
 417   //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr_ht %x)",Count,next_interupt,vaddr);
 418   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 419   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 420   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 421   return get_addr(vaddr);
 422 }
 423
 424 void *get_addr_32(u_int vaddr,u_int flags)
 425 {
 426   //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr_32 %x,flags %x)",Count,next_interupt,vaddr,flags);
 427   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 428   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 429   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 430   u_int page=(vaddr^0x80000000)>>12;
 431   u_int vpage=page;
 432   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
 433   if(page>2048) page=2048+(page&2047);
 434   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
 435   if(vpage>2048) vpage=2048+(vpage&2047);
 436   struct ll_entry *head;
 437   head=jump_in[page];
 438   while(head!=NULL) {
 439     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 440       //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr_32 match %x: %x)",Count,next_interupt,vaddr,(int)head->addr);
 441       if(head->reg32==0) {
 442         u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 443         if(ht_bin[0]==-1) {
 444           ht_bin[1]=(int)head->addr;
 445           ht_bin[0]=vaddr;
 446         }else if(ht_bin[2]==-1) {
 447           ht_bin[3]=(int)head->addr;
 448           ht_bin[2]=vaddr;
 449         }
 450         //ht_bin[3]=ht_bin[1];
 451         //ht_bin[2]=ht_bin[0];
 452         //ht_bin[1]=(int)head->addr;
 453         //ht_bin[0]=vaddr;
 454       }
 455       return head->addr;
 456     }
 457     head=head->next;
 458   }
 459   head=jump_dirty[vpage];
 460   while(head!=NULL) {
 461     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 462       //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)",Count,next_interupt,vaddr,(int)head->addr);
 463       // Don't restore blocks which are about to expire from the cache
 464       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 465       if(verify_dirty(head->addr)) {
 466         //DebugMessage(M64MSG_VERBOSE, "restore candidate: %x (%d) d=%d",vaddr,page,invalid_code[vaddr>>12]);
 467         invalid_code[vaddr>>12]=0;
 468         memory_map[vaddr>>12]|=0x40000000;
 469         if(vpage<2048) {
 470           if(tlb_LUT_r[vaddr>>12]) {
 471             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 472             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 473           }
 474           restore_candidate[vpage>>3]|=1<<(vpage&7);
 475         }
 476         else restore_candidate[page>>3]|=1<<(page&7);
 477         if(head->reg32==0) {
 478           u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 479           if(ht_bin[0]==-1) {
 480             ht_bin[1]=(int)head->addr;
 481             ht_bin[0]=vaddr;
 482           }else if(ht_bin[2]==-1) {
 483             ht_bin[3]=(int)head->addr;
 484             ht_bin[2]=vaddr;
 485           }
 486           //ht_bin[3]=ht_bin[1];
 487           //ht_bin[2]=ht_bin[0];
 488           //ht_bin[1]=(int)head->addr;
 489           //ht_bin[0]=vaddr;
 490         }
 491         return head->addr;
 492       }
 493     }
 494     head=head->next;
 495   }
 496   //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)",Count,next_interupt,vaddr,flags);
 497   int r=new_recompile_block(vaddr);
 498   if(r==0) return get_addr(vaddr);
 499   // Execute in unmapped page, generate pagefault execption
 500   Status|=2;
 501   Cause=(vaddr<<31)|0x8;
 502   EPC=(vaddr&1)?vaddr-5:vaddr;
 503   BadVAddr=(vaddr&~1);
 504   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 505   EntryHi=BadVAddr&0xFFFFE000;
 506   return get_addr_ht(0x80000000);
 507 }
 508
 509 static void clear_all_regs(signed char regmap[])
 510 {
 511   int hr;
 512   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
 513 }
 514
 515 static signed char get_reg(signed char regmap[],int r)
 516 {
 517   int hr;
 518   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
 519   return -1;
 520 }
 521
 522 // Find a register that is available for two consecutive cycles
 523 static signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
 524 {
 525   int hr;
 526   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
 527   return -1;
 528 }
 529
 530 static int count_free_regs(signed char regmap[])
 531 {
 532   int count=0;
 533   int hr;
 534   for(hr=0;hr<HOST_REGS;hr++)
 535   {
 536     if(hr!=EXCLUDE_REG) {
 537       if(regmap[hr]<0) count++;
 538     }
 539   }
 540   return count;
 541 }
 542
 543 static void dirty_reg(struct regstat *cur,signed char reg)
 544 {
 545   int hr;
 546   if(!reg) return;
 547   for (hr=0;hr<HOST_REGS;hr++) {
 548     if((cur->regmap[hr]&63)==reg) {
 549       cur->dirty|=1<<hr;
 550     }
 551   }
 552 }
 553
 554 // If we dirty the lower half of a 64 bit register which is now being
 555 // sign-extended, we need to dump the upper half.
 556 // Note: Do this only after completion of the instruction, because
 557 // some instructions may need to read the full 64-bit value even if
 558 // overwriting it (eg SLTI, DSRA32).
 559 static void flush_dirty_uppers(struct regstat *cur)
 560 {
 561   int hr,reg;
 562   for (hr=0;hr<HOST_REGS;hr++) {
 563     if((cur->dirty>>hr)&1) {
 564       reg=cur->regmap[hr];
 565       if(reg>=64)
 566         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
 567     }
 568   }
 569 }
 570
 571 static void set_const(struct regstat *cur,signed char reg,uint64_t value)
 572 {
 573   int hr;
 574   if(!reg) return;
 575   for (hr=0;hr<HOST_REGS;hr++) {
 576     if(cur->regmap[hr]==reg) {
 577       cur->isconst|=1<<hr;
 578       cur->constmap[hr]=value;
 579     }
 580     else if((cur->regmap[hr]^64)==reg) {
 581       cur->isconst|=1<<hr;
 582       cur->constmap[hr]=value>>32;
 583     }
 584   }
 585 }
 586
 587 static void clear_const(struct regstat *cur,signed char reg)
 588 {
 589   int hr;
 590   if(!reg) return;
 591   for (hr=0;hr<HOST_REGS;hr++) {
 592     if((cur->regmap[hr]&63)==reg) {
 593       cur->isconst&=~(1<<hr);
 594     }
 595   }
 596 }
 597
 598 static int is_const(struct regstat *cur,signed char reg)
 599 {
 600   int hr;
 601   if(reg<0) return 0;
 602   if(!reg) return 1;
 603   for (hr=0;hr<HOST_REGS;hr++) {
 604     if((cur->regmap[hr]&63)==reg) {
 605       return (cur->isconst>>hr)&1;
 606     }
 607   }
 608   return 0;
 609 }
 610 static uint64_t get_const(struct regstat *cur,signed char reg)
 611 {
 612   int hr;
 613   if(!reg) return 0;
 614   for (hr=0;hr<HOST_REGS;hr++) {
 615     if(cur->regmap[hr]==reg) {
 616       return cur->constmap[hr];
 617     }
 618   }
 619   DebugMessage(M64MSG_ERROR, "Unknown constant in r%d",reg);
 620   exit(1);
 621 }
 622
 623 // Least soon needed registers
 624 // Look at the next ten instructions and see which registers
 625 // will be used.  Try not to reallocate these.
 626 static void lsn(u_char hsn[], int i, int *preferred_reg)
 627 {
 628   int j;
 629   int b=-1;
 630   for(j=0;j<9;j++)
 631   {
 632     if(i+j>=slen) {
 633       j=slen-i-1;
 634       break;
 635     }
 636     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 637     {
 638       // Don't go past an unconditonal jump
 639       j++;
 640       break;
 641     }
 642   }
 643   for(;j>=0;j--)
 644   {
 645     if(rs1[i+j]) hsn[rs1[i+j]]=j;
 646     if(rs2[i+j]) hsn[rs2[i+j]]=j;
 647     if(rt1[i+j]) hsn[rt1[i+j]]=j;
 648     if(rt2[i+j]) hsn[rt2[i+j]]=j;
 649     if(itype[i+j]==STORE || itype[i+j]==STORELR) {
 650       // Stores can allocate zero
 651       hsn[rs1[i+j]]=j;
 652       hsn[rs2[i+j]]=j;
 653     }
 654     // On some architectures stores need invc_ptr
 655     #if defined(HOST_IMM8)
 656     if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39) {
 657       hsn[INVCP]=j;
 658     }
 659     #endif
 660     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 661     {
 662       hsn[CCREG]=j;
 663       b=j;
 664     }
 665   }
 666   if(b>=0)
 667   {
 668     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 669     {
 670       // Follow first branch
 671       int t=(ba[i+b]-start)>>2;
 672       j=7-b;if(t+j>=slen) j=slen-t-1;
 673       for(;j>=0;j--)
 674       {
 675         if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
 676         if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
 677         //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
 678         //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
 679       }
 680     }
 681     // TODO: preferred register based on backward branch
 682   }
 683   // Delay slot should preferably not overwrite branch conditions or cycle count
 684   if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
 685     if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
 686     if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
 687     hsn[CCREG]=1;
 688     // ...or hash tables
 689     hsn[RHASH]=1;
 690     hsn[RHTBL]=1;
 691   }
 692   // Coprocessor load/store needs FTEMP, even if not declared
 693   if(itype[i]==C1LS) {
 694     hsn[FTEMP]=0;
 695   }
 696   // Load L/R also uses FTEMP as a temporary register
 697   if(itype[i]==LOADLR) {
 698     hsn[FTEMP]=0;
 699   }
 700   // Also 64-bit SDL/SDR
 701   if(opcode[i]==0x2c||opcode[i]==0x2d) {
 702     hsn[FTEMP]=0;
 703   }
 704   // Don't remove the TLB registers either
 705   if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS ) {
 706     hsn[TLREG]=0;
 707   }
 708   // Don't remove the miniht registers
 709   if(itype[i]==UJUMP||itype[i]==RJUMP)
 710   {
 711     hsn[RHASH]=0;
 712     hsn[RHTBL]=0;
 713   }
 714 }
 715
 716 // We only want to allocate registers if we're going to use them again soon
 717 static int needed_again(int r, int i)
 718 {
 719   int j;
 720   /*int b=-1;*/
 721   int rn=10;
 722
 723   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
 724   {
 725     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
 726       return 0; // Don't need any registers if exiting the block
 727   }
 728   for(j=0;j<9;j++)
 729   {
 730     if(i+j>=slen) {
 731       j=slen-i-1;
 732       break;
 733     }
 734     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 735     {
 736       // Don't go past an unconditonal jump
 737       j++;
 738       break;
 739     }
 740     if(itype[i+j]==SYSCALL||((source[i+j]&0xfc00003f)==0x0d))
 741     {
 742       break;
 743     }
 744   }
 745   for(;j>=1;j--)
 746   {
 747     if(rs1[i+j]==r) rn=j;
 748     if(rs2[i+j]==r) rn=j;
 749     if((unneeded_reg[i+j]>>r)&1) rn=10;
 750     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 751     {
 752       /*b=j;*/
 753     }
 754   }
 755   /*
 756   if(b>=0)
 757   {
 758     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 759     {
 760       // Follow first branch
 761       int o=rn;
 762       int t=(ba[i+b]-start)>>2;
 763       j=7-b;if(t+j>=slen) j=slen-t-1;
 764       for(;j>=0;j--)
 765       {
 766         if(!((unneeded_reg[t+j]>>r)&1)) {
 767           if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 768           if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 769         }
 770         else rn=o;
 771       }
 772     }
 773   }*/
 774   if(rn<10) return 1;
 775   return 0;
 776 }
 777
 778 // Try to match register allocations at the end of a loop with those
 779 // at the beginning
 780 static int loop_reg(int i, int r, int hr)
 781 {
 782   int j,k;
 783   for(j=0;j<9;j++)
 784   {
 785     if(i+j>=slen) {
 786       j=slen-i-1;
 787       break;
 788     }
 789     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 790     {
 791       // Don't go past an unconditonal jump
 792       j++;
 793       break;
 794     }
 795   }
 796   k=0;
 797   if(i>0){
 798     if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
 799       k--;
 800   }
 801   for(;k<j;k++)
 802   {
 803     if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
 804     if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
 805     if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
 806     {
 807       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
 808       {
 809         int t=(ba[i+k]-start)>>2;
 810         int reg=get_reg(regs[t].regmap_entry,r);
 811         if(reg>=0) return reg;
 812         //reg=get_reg(regs[t+1].regmap_entry,r);
 813         //if(reg>=0) return reg;
 814       }
 815     }
 816   }
 817   return hr;
 818 }
 819
 820
 821 // Allocate every register, preserving source/target regs
 822 static void alloc_all(struct regstat *cur,int i)
 823 {
 824   int hr;
 825
 826   for(hr=0;hr<HOST_REGS;hr++) {
 827     if(hr!=EXCLUDE_REG) {
 828       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
 829          ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
 830       {
 831         cur->regmap[hr]=-1;
 832         cur->dirty&=~(1<<hr);
 833       }
 834       // Don't need zeros
 835       if((cur->regmap[hr]&63)==0)
 836       {
 837         cur->regmap[hr]=-1;
 838         cur->dirty&=~(1<<hr);
 839       }
 840     }
 841   }
 842 }
 843
 844
 845 static void div64(int64_t dividend,int64_t divisor)
 846 {
 847   lo=dividend/divisor;
 848   hi=dividend%divisor;
 849   //DebugMessage(M64MSG_VERBOSE, "TRACE: ddiv %8x%8x %8x%8x" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
 850   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 851 }
 852 static void divu64(uint64_t dividend,uint64_t divisor)
 853 {
 854   lo=dividend/divisor;
 855   hi=dividend%divisor;
 856   //DebugMessage(M64MSG_VERBOSE, "TRACE: ddivu %8x%8x %8x%8x",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 857   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 858 }
 859
 860 static void mult64(uint64_t m1,uint64_t m2)
 861 {
 862    unsigned long long int op1, op2, op3, op4;
 863    unsigned long long int result1, result2, result3, result4;
 864    unsigned long long int temp1, temp2, temp3, temp4;
 865    int sign = 0;
 866
 867    if (m1 < 0)
 868      {
 869     op2 = -m1;
 870     sign = 1 - sign;
 871      }
 872    else op2 = m1;
 873    if (m2 < 0)
 874      {
 875     op4 = -m2;
 876     sign = 1 - sign;
 877      }
 878    else op4 = m2;
 879
 880    op1 = op2 & 0xFFFFFFFF;
 881    op2 = (op2 >> 32) & 0xFFFFFFFF;
 882    op3 = op4 & 0xFFFFFFFF;
 883    op4 = (op4 >> 32) & 0xFFFFFFFF;
 884
 885    temp1 = op1 * op3;
 886    temp2 = (temp1 >> 32) + op1 * op4;
 887    temp3 = op2 * op3;
 888    temp4 = (temp3 >> 32) + op2 * op4;
 889
 890    result1 = temp1 & 0xFFFFFFFF;
 891    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 892    result3 = (result2 >> 32) + temp4;
 893    result4 = (result3 >> 32);
 894
 895    lo = result1 | (result2 << 32);
 896    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 897    if (sign)
 898      {
 899     hi = ~hi;
 900     if (!lo) hi++;
 901     else lo = ~lo + 1;
 902      }
 903 }
 904
 905 #if NEW_DYNAREC == NEW_DYNAREC_ARM
 906 static void multu64(uint64_t m1,uint64_t m2)
 907 {
 908    unsigned long long int op1, op2, op3, op4;
 909    unsigned long long int result1, result2, result3, result4;
 910    unsigned long long int temp1, temp2, temp3, temp4;
 911
 912    op1 = m1 & 0xFFFFFFFF;
 913    op2 = (m1 >> 32) & 0xFFFFFFFF;
 914    op3 = m2 & 0xFFFFFFFF;
 915    op4 = (m2 >> 32) & 0xFFFFFFFF;
 916
 917    temp1 = op1 * op3;
 918    temp2 = (temp1 >> 32) + op1 * op4;
 919    temp3 = op2 * op3;
 920    temp4 = (temp3 >> 32) + op2 * op4;
 921
 922    result1 = temp1 & 0xFFFFFFFF;
 923    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 924    result3 = (result2 >> 32) + temp4;
 925    result4 = (result3 >> 32);
 926
 927    lo = result1 | (result2 << 32);
 928    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 929
 930   //DebugMessage(M64MSG_VERBOSE, "TRACE: dmultu %8x%8x %8x%8x",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 931   //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 932 }
 933 #endif
 934
 935 static uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
 936 {
 937   if(bits) {
 938     original<<=64-bits;
 939     original>>=64-bits;
 940     loaded<<=bits;
 941     original|=loaded;
 942   }
 943   else original=loaded;
 944   return original;
 945 }
 946 static uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
 947 {
 948   if(bits^56) {
 949     original>>=64-(bits^56);
 950     original<<=64-(bits^56);
 951     loaded>>=bits^56;
 952     original|=loaded;
 953   }
 954   else original=loaded;
 955   return original;
 956 }
 957
 958 #if NEW_DYNAREC == NEW_DYNAREC_X86
 959 #include "assem_x86.c"
 960 #elif NEW_DYNAREC == NEW_DYNAREC_ARM
 961 #include "assem_arm.c"
 962 #else
 963 #error Unsupported dynarec architecture
 964 #endif
 965
 966 // Add virtual address mapping to linked list
 967 static void ll_add(struct ll_entry **head,int vaddr,void *addr)
 968 {
 969   struct ll_entry *new_entry;
 970   new_entry=malloc(sizeof(struct ll_entry));
 971   assert(new_entry!=NULL);
 972   new_entry->vaddr=vaddr;
 973   new_entry->reg32=0;
 974   new_entry->addr=addr;
 975   new_entry->next=*head;
 976   *head=new_entry;
 977 }
 978
 979 // Add virtual address mapping for 32-bit compiled block
 980 static void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
 981 {
 982   struct ll_entry *new_entry;
 983   new_entry=malloc(sizeof(struct ll_entry));
 984   assert(new_entry!=NULL);
 985   new_entry->vaddr=vaddr;
 986   new_entry->reg32=reg32;
 987   new_entry->addr=addr;
 988   new_entry->next=*head;
 989   *head=new_entry;
 990 }
 991
 992 // Check if an address is already compiled
 993 // but don't return addresses which are about to expire from the cache
 994 static void *check_addr(u_int vaddr)
 995 {
 996   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 997   if(ht_bin[0]==vaddr) {
 998     if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 999       if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1000   }
1001   if(ht_bin[2]==vaddr) {
1002     if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1003       if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1004   }
1005   u_int page=(vaddr^0x80000000)>>12;
1006   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
1007   if(page>2048) page=2048+(page&2047);
1008   struct ll_entry *head;
1009   head=jump_in[page];
1010   while(head!=NULL) {
1011     if(head->vaddr==vaddr&&head->reg32==0) {
1012       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1013         // Update existing entry with current address
1014         if(ht_bin[0]==vaddr) {
1015           ht_bin[1]=(int)head->addr;
1016           return head->addr;
1017         }
1018         if(ht_bin[2]==vaddr) {
1019           ht_bin[3]=(int)head->addr;
1020           return head->addr;
1021         }
1022         // Insert into hash table with low priority.
1023         // Don't evict existing entries, as they are probably
1024         // addresses that are being accessed frequently.
1025         if(ht_bin[0]==-1) {
1026           ht_bin[1]=(int)head->addr;
1027           ht_bin[0]=vaddr;
1028         }else if(ht_bin[2]==-1) {
1029           ht_bin[3]=(int)head->addr;
1030           ht_bin[2]=vaddr;
1031         }
1032         return head->addr;
1033       }
1034     }
1035     head=head->next;
1036   }
1037   return 0;
1038 }
1039
1040 static void remove_hash(int vaddr)
1041 {
1042   //DebugMessage(M64MSG_VERBOSE, "remove hash: %x",vaddr);
1043   u_int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1044   if(ht_bin[2]==vaddr) {
1045     ht_bin[2]=ht_bin[3]=-1;
1046   }
1047   if(ht_bin[0]==vaddr) {
1048     ht_bin[0]=ht_bin[2];
1049     ht_bin[1]=ht_bin[3];
1050     ht_bin[2]=ht_bin[3]=-1;
1051   }
1052 }
1053
1054 static void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1055 {
1056   struct ll_entry *next;
1057   while(*head) {
1058     if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1059        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1060     {
1061       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1062       remove_hash((*head)->vaddr);
1063       next=(*head)->next;
1064       free(*head);
1065       *head=next;
1066     }
1067     else
1068     {
1069       head=&((*head)->next);
1070     }
1071   }
1072 }
1073
1074 // Remove all entries from linked list
1075 static void ll_clear(struct ll_entry **head)
1076 {
1077   struct ll_entry *cur;
1078   struct ll_entry *next;
1079   if((cur=*head)) {
1080     *head=0;
1081     while(cur) {
1082       next=cur->next;
1083       free(cur);
1084       cur=next;
1085     }
1086   }
1087 }
1088
1089 // Dereference the pointers and remove if it matches
1090 static void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1091 {
1092   while(head) {
1093     int ptr=get_pointer(head->addr);
1094     inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1095     if(((ptr>>shift)==(addr>>shift)) ||
1096        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1097     {
1098       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1099       u_int host_addr=(int)kill_pointer(head->addr);
1100       #if NEW_DYNAREC == NEW_DYNAREC_ARM
1101         needs_clear_cache[(host_addr-(u_int)base_addr)>>17]|=1<<(((host_addr-(u_int)base_addr)>>12)&31);
1102       #endif
1103     }
1104     head=head->next;
1105   }
1106 }
1107
1108 // This is called when we write to a compiled block (see do_invstub)
1109 static void invalidate_page(u_int page)
1110 {
1111   struct ll_entry *head;
1112   struct ll_entry *next;
1113   head=jump_in[page];
1114   jump_in[page]=0;
1115   while(head!=NULL) {
1116     inv_debug("INVALIDATE: %x\n",head->vaddr);
1117     remove_hash(head->vaddr);
1118     next=head->next;
1119     free(head);
1120     head=next;
1121   }
1122   head=jump_out[page];
1123   jump_out[page]=0;
1124   while(head!=NULL) {
1125     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1126     u_int host_addr=(int)kill_pointer(head->addr);
1127     #if NEW_DYNAREC == NEW_DYNAREC_ARM
1128       needs_clear_cache[(host_addr-(u_int)base_addr)>>17]|=1<<(((host_addr-(u_int)base_addr)>>12)&31);
1129     #endif
1130     next=head->next;
1131     free(head);
1132     head=next;
1133   }
1134 }
1135 void invalidate_block(u_int block)
1136 {
1137   u_int page,vpage;
1138   page=vpage=block^0x80000;
1139   if(page>262143&&tlb_LUT_r[block]) page=(tlb_LUT_r[block]^0x80000000)>>12;
1140   if(page>2048) page=2048+(page&2047);
1141   if(vpage>262143&&tlb_LUT_r[block]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
1142   if(vpage>2048) vpage=2048+(vpage&2047);
1143   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1144   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1145   u_int first,last;
1146   first=last=page;
1147   struct ll_entry *head;
1148   head=jump_dirty[vpage];
1149   //DebugMessage(M64MSG_VERBOSE, "page=%d vpage=%d",page,vpage);
1150   while(head!=NULL) {
1151     u_int start,end;
1152     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1153       get_bounds((int)head->addr,&start,&end);
1154       //DebugMessage(M64MSG_VERBOSE, "start: %x end: %x",start,end);
1155       if(page<2048&&start>=0x80000000&&end<0x80800000) {
1156         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1157           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1158           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1159         }
1160       }
1161       if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1162         if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1163           if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1164           if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1165         }
1166       }
1167     }
1168     head=head->next;
1169   }
1170   //DebugMessage(M64MSG_VERBOSE, "first=%d last=%d",first,last);
1171   invalidate_page(page);
1172   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1173   assert(last<page+5);
1174   // Invalidate the adjacent pages if a block crosses a 4K boundary
1175   while(first<page) {
1176     invalidate_page(first);
1177     first++;
1178   }
1179   for(first=page+1;first<last;first++) {
1180     invalidate_page(first);
1181   }
1182   #if NEW_DYNAREC == NEW_DYNAREC_ARM
1183     do_clear_cache();
1184   #endif
1185
1186   // Don't trap writes
1187   invalid_code[block]=1;
1188   // If there is a valid TLB entry for this page, remove write protect
1189   if(tlb_LUT_w[block]) {
1190     assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1191     // CHECK: Is this right?
1192     memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1193     u_int real_block=tlb_LUT_w[block]>>12;
1194     invalid_code[real_block]=1;
1195     if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1196   }
1197   else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1198   #ifdef USE_MINI_HT
1199   memset(mini_ht,-1,sizeof(mini_ht));
1200   #endif
1201 }
1202
1203 #if NEW_DYNAREC == NEW_DYNAREC_ARM
1204 static void invalidate_addr(u_int addr)
1205 {
1206   invalidate_block(addr>>12);
1207 }
1208 #endif
1209
1210 // This is called when loading a save state.
1211 // Anything could have changed, so invalidate everything.
1212 void invalidate_all_pages()
1213 {
1214   u_int page;
1215   for(page=0;page<4096;page++)
1216     invalidate_page(page);
1217   for(page=0;page<1048576;page++)
1218     if(!invalid_code[page]) {
1219       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1220       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1221     }
1222   #if NEW_DYNAREC == NEW_DYNAREC_ARM
1223   __clear_cache((void *)base_addr,(void *)base_addr+(1<<TARGET_SIZE_2));
1224   //cacheflush((void *)base_addr,(void *)base_addr+(1<<TARGET_SIZE_2),0);
1225   #endif
1226   #ifdef USE_MINI_HT
1227   memset(mini_ht,-1,sizeof(mini_ht));
1228   #endif
1229   // TLB
1230   for(page=0;page<0x100000;page++) {
1231     if(tlb_LUT_r[page]) {
1232       memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1233       if(!tlb_LUT_w[page]||!invalid_code[page])
1234         memory_map[page]|=0x40000000; // Write protect
1235     }
1236     else memory_map[page]=-1;
1237     if(page==0x80000) page=0xC0000;
1238   }
1239   tlb_hacks();
1240 }
1241
1242 // Add an entry to jump_out after making a link
1243 void add_link(u_int vaddr,void *src)
1244 {
1245   u_int page=(vaddr^0x80000000)>>12;
1246   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
1247   if(page>4095) page=2048+(page&2047);
1248   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1249   ll_add(jump_out+page,vaddr,src);
1250   //int ptr=get_pointer(src);
1251   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1252 }
1253
1254 // If a code block was found to be unmodified (bit was set in
1255 // restore_candidate) and it remains unmodified (bit is clear
1256 // in invalid_code) then move the entries for that 4K page from
1257 // the dirty list to the clean list.
1258 void clean_blocks(u_int page)
1259 {
1260   struct ll_entry *head;
1261   inv_debug("INV: clean_blocks page=%d\n",page);
1262   head=jump_dirty[page];
1263   while(head!=NULL) {
1264     if(!invalid_code[head->vaddr>>12]) {
1265       // Don't restore blocks which are about to expire from the cache
1266       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1267         u_int start,end;
1268         if(verify_dirty(head->addr)) {
1269           //DebugMessage(M64MSG_VERBOSE, "Possibly Restore %x (%x)",head->vaddr, (int)head->addr);
1270           u_int i;
1271           u_int inv=0;
1272           get_bounds((int)head->addr,&start,&end);
1273           if(start-(u_int)rdram<0x800000) {
1274             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1275               inv|=invalid_code[i];
1276             }
1277           }
1278           if((signed int)head->vaddr>=(signed int)0xC0000000) {
1279             u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1280             //DebugMessage(M64MSG_VERBOSE, "addr=%x start=%x end=%x",addr,start,end);
1281             if(addr<start||addr>=end) inv=1;
1282           }
1283           else if((signed int)head->vaddr>=(signed int)0x80800000) {
1284             inv=1;
1285           }
1286           if(!inv) {
1287             void * clean_addr=(void *)get_clean_addr((int)head->addr);
1288             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1289               u_int ppage=page;
1290               if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1291               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1292               //DebugMessage(M64MSG_VERBOSE, "page=%x, addr=%x",page,head->vaddr);
1293               //assert(head->vaddr>>12==(page|0x80000));
1294               ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1295               u_int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1296               if(!head->reg32) {
1297                 if(ht_bin[0]==head->vaddr) {
1298                   ht_bin[1]=(int)clean_addr; // Replace existing entry
1299                 }
1300                 if(ht_bin[2]==head->vaddr) {
1301                   ht_bin[3]=(int)clean_addr; // Replace existing entry
1302                 }
1303               }
1304             }
1305           }
1306         }
1307       }
1308     }
1309     head=head->next;
1310   }
1311 }
1312
1313
1314 static void mov_alloc(struct regstat *current,int i)
1315 {
1316   // Note: Don't need to actually alloc the source registers
1317   if((~current->is32>>rs1[i])&1) {
1318     //alloc_reg64(current,i,rs1[i]);
1319     alloc_reg64(current,i,rt1[i]);
1320     current->is32&=~(1LL<<rt1[i]);
1321   } else {
1322     //alloc_reg(current,i,rs1[i]);
1323     alloc_reg(current,i,rt1[i]);
1324     current->is32|=(1LL<<rt1[i]);
1325   }
1326   clear_const(current,rs1[i]);
1327   clear_const(current,rt1[i]);
1328   dirty_reg(current,rt1[i]);
1329 }
1330
1331 static void shiftimm_alloc(struct regstat *current,int i)
1332 {
1333   clear_const(current,rs1[i]);
1334   clear_const(current,rt1[i]);
1335   if(opcode2[i]<=0x3) // SLL/SRL/SRA
1336   {
1337     if(rt1[i]) {
1338       if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1339       else lt1[i]=rs1[i];
1340       alloc_reg(current,i,rt1[i]);
1341       current->is32|=1LL<<rt1[i];
1342       dirty_reg(current,rt1[i]);
1343     }
1344   }
1345   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1346   {
1347     if(rt1[i]) {
1348       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1349       alloc_reg64(current,i,rt1[i]);
1350       current->is32&=~(1LL<<rt1[i]);
1351       dirty_reg(current,rt1[i]);
1352     }
1353   }
1354   if(opcode2[i]==0x3c) // DSLL32
1355   {
1356     if(rt1[i]) {
1357       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1358       alloc_reg64(current,i,rt1[i]);
1359       current->is32&=~(1LL<<rt1[i]);
1360       dirty_reg(current,rt1[i]);
1361     }
1362   }
1363   if(opcode2[i]==0x3e) // DSRL32
1364   {
1365     if(rt1[i]) {
1366       alloc_reg64(current,i,rs1[i]);
1367       if(imm[i]==32) {
1368         alloc_reg64(current,i,rt1[i]);
1369         current->is32&=~(1LL<<rt1[i]);
1370       } else {
1371         alloc_reg(current,i,rt1[i]);
1372         current->is32|=1LL<<rt1[i];
1373       }
1374       dirty_reg(current,rt1[i]);
1375     }
1376   }
1377   if(opcode2[i]==0x3f) // DSRA32
1378   {
1379     if(rt1[i]) {
1380       alloc_reg64(current,i,rs1[i]);
1381       alloc_reg(current,i,rt1[i]);
1382       current->is32|=1LL<<rt1[i];
1383       dirty_reg(current,rt1[i]);
1384     }
1385   }
1386 }
1387
1388 static void shift_alloc(struct regstat *current,int i)
1389 {
1390   if(rt1[i]) {
1391     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1392     {
1393       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1394       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1395       alloc_reg(current,i,rt1[i]);
1396       if(rt1[i]==rs2[i]) {
1397         alloc_reg_temp(current,i,-1);
1398         minimum_free_regs[i]=1;
1399       }
1400       current->is32|=1LL<<rt1[i];
1401     } else { // DSLLV/DSRLV/DSRAV
1402       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1403       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1404       alloc_reg64(current,i,rt1[i]);
1405       current->is32&=~(1LL<<rt1[i]);
1406       if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1407       {
1408         alloc_reg_temp(current,i,-1);
1409         minimum_free_regs[i]=1;
1410       }
1411     }
1412     clear_const(current,rs1[i]);
1413     clear_const(current,rs2[i]);
1414     clear_const(current,rt1[i]);
1415     dirty_reg(current,rt1[i]);
1416   }
1417 }
1418
1419 static void alu_alloc(struct regstat *current,int i)
1420 {
1421   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1422     if(rt1[i]) {
1423       if(rs1[i]&&rs2[i]) {
1424         alloc_reg(current,i,rs1[i]);
1425         alloc_reg(current,i,rs2[i]);
1426       }
1427       else {
1428         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1429         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1430       }
1431       alloc_reg(current,i,rt1[i]);
1432     }
1433     current->is32|=1LL<<rt1[i];
1434   }
1435   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1436     if(rt1[i]) {
1437       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1438       {
1439         alloc_reg64(current,i,rs1[i]);
1440         alloc_reg64(current,i,rs2[i]);
1441         alloc_reg(current,i,rt1[i]);
1442       } else {
1443         alloc_reg(current,i,rs1[i]);
1444         alloc_reg(current,i,rs2[i]);
1445         alloc_reg(current,i,rt1[i]);
1446       }
1447     }
1448     current->is32|=1LL<<rt1[i];
1449   }
1450   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1451     if(rt1[i]) {
1452       if(rs1[i]&&rs2[i]) {
1453         alloc_reg(current,i,rs1[i]);
1454         alloc_reg(current,i,rs2[i]);
1455       }
1456       else
1457       {
1458         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1459         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1460       }
1461       alloc_reg(current,i,rt1[i]);
1462       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1463       {
1464         if(!((current->uu>>rt1[i])&1)) {
1465           alloc_reg64(current,i,rt1[i]);
1466         }
1467         if(get_reg(current->regmap,rt1[i]|64)>=0) {
1468           if(rs1[i]&&rs2[i]) {
1469             alloc_reg64(current,i,rs1[i]);
1470             alloc_reg64(current,i,rs2[i]);
1471           }
1472           else
1473           {
1474             // Is is really worth it to keep 64-bit values in registers?
1475             #ifdef NATIVE_64BIT
1476             if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1477             if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1478             #endif
1479           }
1480         }
1481         current->is32&=~(1LL<<rt1[i]);
1482       } else {
1483         current->is32|=1LL<<rt1[i];
1484       }
1485     }
1486   }
1487   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1488     if(rt1[i]) {
1489       if(rs1[i]&&rs2[i]) {
1490         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1491           alloc_reg64(current,i,rs1[i]);
1492           alloc_reg64(current,i,rs2[i]);
1493           alloc_reg64(current,i,rt1[i]);
1494         } else {
1495           alloc_reg(current,i,rs1[i]);
1496           alloc_reg(current,i,rs2[i]);
1497           alloc_reg(current,i,rt1[i]);
1498         }
1499       }
1500       else {
1501         alloc_reg(current,i,rt1[i]);
1502         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1503           // DADD used as move, or zeroing
1504           // If we have a 64-bit source, then make the target 64 bits too
1505           if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1506             if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1507             alloc_reg64(current,i,rt1[i]);
1508           } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1509             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1510             alloc_reg64(current,i,rt1[i]);
1511           }
1512           if(opcode2[i]>=0x2e&&rs2[i]) {
1513             // DSUB used as negation - 64-bit result
1514             // If we have a 32-bit register, extend it to 64 bits
1515             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1516             alloc_reg64(current,i,rt1[i]);
1517           }
1518         }
1519       }
1520       if(rs1[i]&&rs2[i]) {
1521         current->is32&=~(1LL<<rt1[i]);
1522       } else if(rs1[i]) {
1523         current->is32&=~(1LL<<rt1[i]);
1524         if((current->is32>>rs1[i])&1)
1525           current->is32|=1LL<<rt1[i];
1526       } else if(rs2[i]) {
1527         current->is32&=~(1LL<<rt1[i]);
1528         if((current->is32>>rs2[i])&1)
1529           current->is32|=1LL<<rt1[i];
1530       } else {
1531         current->is32|=1LL<<rt1[i];
1532       }
1533     }
1534   }
1535   clear_const(current,rs1[i]);
1536   clear_const(current,rs2[i]);
1537   clear_const(current,rt1[i]);
1538   dirty_reg(current,rt1[i]);
1539 }
1540
1541 static void imm16_alloc(struct regstat *current,int i)
1542 {
1543   if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1544   else lt1[i]=rs1[i];
1545   if(rt1[i]) alloc_reg(current,i,rt1[i]);
1546   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1547     current->is32&=~(1LL<<rt1[i]);
1548     if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1549       // TODO: Could preserve the 32-bit flag if the immediate is zero
1550       alloc_reg64(current,i,rt1[i]);
1551       alloc_reg64(current,i,rs1[i]);
1552     }
1553     clear_const(current,rs1[i]);
1554     clear_const(current,rt1[i]);
1555   }
1556   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1557     if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1558     current->is32|=1LL<<rt1[i];
1559     clear_const(current,rs1[i]);
1560     clear_const(current,rt1[i]);
1561   }
1562   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1563     if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1564       if(rs1[i]!=rt1[i]) {
1565         if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1566         alloc_reg64(current,i,rt1[i]);
1567         current->is32&=~(1LL<<rt1[i]);
1568       }
1569     }
1570     else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1571     if(is_const(current,rs1[i])) {
1572       int v=get_const(current,rs1[i]);
1573       if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1574       if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1575       if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1576     }
1577     else clear_const(current,rt1[i]);
1578   }
1579   else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1580     if(is_const(current,rs1[i])) {
1581       int v=get_const(current,rs1[i]);
1582       set_const(current,rt1[i],v+imm[i]);
1583     }
1584     else clear_const(current,rt1[i]);
1585     current->is32|=1LL<<rt1[i];
1586   }
1587   else {
1588     set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1589     current->is32|=1LL<<rt1[i];
1590   }
1591   dirty_reg(current,rt1[i]);
1592 }
1593
1594 static void load_alloc(struct regstat *current,int i)
1595 {
1596   clear_const(current,rt1[i]);
1597   //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1598   if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1599   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1600   if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1601     alloc_reg(current,i,rt1[i]);
1602     assert(get_reg(current->regmap,rt1[i])>=0);
1603     if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1604     {
1605       current->is32&=~(1LL<<rt1[i]);
1606       alloc_reg64(current,i,rt1[i]);
1607     }
1608     else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1609     {
1610       current->is32&=~(1LL<<rt1[i]);
1611       alloc_reg64(current,i,rt1[i]);
1612       alloc_all(current,i);
1613       alloc_reg64(current,i,FTEMP);
1614       minimum_free_regs[i]=HOST_REGS;
1615     }
1616     else current->is32|=1LL<<rt1[i];
1617     dirty_reg(current,rt1[i]);
1618     // If using TLB, need a register for pointer to the mapping table
1619     if(using_tlb) alloc_reg(current,i,TLREG);
1620     // LWL/LWR need a temporary register for the old value
1621     if(opcode[i]==0x22||opcode[i]==0x26)
1622     {
1623       alloc_reg(current,i,FTEMP);
1624       alloc_reg_temp(current,i,-1);
1625       minimum_free_regs[i]=1;
1626     }
1627   }
1628   else
1629   {
1630     // Load to r0 or unneeded register (dummy load)
1631     // but we still need a register to calculate the address
1632     if(opcode[i]==0x22||opcode[i]==0x26)
1633     {
1634       alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1635     }
1636     // If using TLB, need a register for pointer to the mapping table
1637     if(using_tlb) alloc_reg(current,i,TLREG);
1638     alloc_reg_temp(current,i,-1);
1639     minimum_free_regs[i]=1;
1640     if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1641     {
1642       alloc_all(current,i);
1643       alloc_reg64(current,i,FTEMP);
1644       minimum_free_regs[i]=HOST_REGS;
1645     }
1646   }
1647 }
1648
1649 static void store_alloc(struct regstat *current,int i)
1650 {
1651   clear_const(current,rs2[i]);
1652   if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1653   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1654   alloc_reg(current,i,rs2[i]);
1655   if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1656     alloc_reg64(current,i,rs2[i]);
1657     if(rs2[i]) alloc_reg(current,i,FTEMP);
1658   }
1659   // If using TLB, need a register for pointer to the mapping table
1660   if(using_tlb) alloc_reg(current,i,TLREG);
1661   #if defined(HOST_IMM8)
1662   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1663   else alloc_reg(current,i,INVCP);
1664   #endif
1665   if(opcode[i]==0x2c||opcode[i]==0x2d) { // 64-bit SDL/SDR
1666     alloc_reg(current,i,FTEMP);
1667   }
1668   // We need a temporary register for address generation
1669   alloc_reg_temp(current,i,-1);
1670   minimum_free_regs[i]=1;
1671 }
1672
1673 static void c1ls_alloc(struct regstat *current,int i)
1674 {
1675   //clear_const(current,rs1[i]); // FIXME
1676   clear_const(current,rt1[i]);
1677   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1678   alloc_reg(current,i,CSREG); // Status
1679   alloc_reg(current,i,FTEMP);
1680   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1681     alloc_reg64(current,i,FTEMP);
1682   }
1683   // If using TLB, need a register for pointer to the mapping table
1684   if(using_tlb) alloc_reg(current,i,TLREG);
1685   #if defined(HOST_IMM8)
1686   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1687   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1688     alloc_reg(current,i,INVCP);
1689   #endif
1690   // We need a temporary register for address generation
1691   alloc_reg_temp(current,i,-1);
1692   minimum_free_regs[i]=1;
1693 }
1694
1695 #ifndef multdiv_alloc
1696 void multdiv_alloc(struct regstat *current,int i)
1697 {
1698   //  case 0x18: MULT
1699   //  case 0x19: MULTU
1700   //  case 0x1A: DIV
1701   //  case 0x1B: DIVU
1702   //  case 0x1C: DMULT
1703   //  case 0x1D: DMULTU
1704   //  case 0x1E: DDIV
1705   //  case 0x1F: DDIVU
1706   clear_const(current,rs1[i]);
1707   clear_const(current,rs2[i]);
1708   if(rs1[i]&&rs2[i])
1709   {
1710     if((opcode2[i]&4)==0) // 32-bit
1711     {
1712       current->u&=~(1LL<<HIREG);
1713       current->u&=~(1LL<<LOREG);
1714       alloc_reg(current,i,HIREG);
1715       alloc_reg(current,i,LOREG);
1716       alloc_reg(current,i,rs1[i]);
1717       alloc_reg(current,i,rs2[i]);
1718       current->is32|=1LL<<HIREG;
1719       current->is32|=1LL<<LOREG;
1720       dirty_reg(current,HIREG);
1721       dirty_reg(current,LOREG);
1722     }
1723     else // 64-bit
1724     {
1725       current->u&=~(1LL<<HIREG);
1726       current->u&=~(1LL<<LOREG);
1727       current->uu&=~(1LL<<HIREG);
1728       current->uu&=~(1LL<<LOREG);
1729       alloc_reg64(current,i,HIREG);
1730       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1731       alloc_reg64(current,i,rs1[i]);
1732       alloc_reg64(current,i,rs2[i]);
1733       alloc_all(current,i);
1734       current->is32&=~(1LL<<HIREG);
1735       current->is32&=~(1LL<<LOREG);
1736       dirty_reg(current,HIREG);
1737       dirty_reg(current,LOREG);
1738       minimum_free_regs[i]=HOST_REGS;
1739     }
1740   }
1741   else
1742   {
1743     // Multiply by zero is zero.
1744     // MIPS does not have a divide by zero exception.
1745     // The result is undefined, we return zero.
1746     alloc_reg(current,i,HIREG);
1747     alloc_reg(current,i,LOREG);
1748     current->is32|=1LL<<HIREG;
1749     current->is32|=1LL<<LOREG;
1750     dirty_reg(current,HIREG);
1751     dirty_reg(current,LOREG);
1752   }
1753 }
1754 #endif
1755
1756 static void cop0_alloc(struct regstat *current,int i)
1757 {
1758   if(opcode2[i]==0) // MFC0
1759   {
1760     if(rt1[i]) {
1761       clear_const(current,rt1[i]);
1762       alloc_all(current,i);
1763       alloc_reg(current,i,rt1[i]);
1764       current->is32|=1LL<<rt1[i];
1765       dirty_reg(current,rt1[i]);
1766     }
1767   }
1768   else if(opcode2[i]==4) // MTC0
1769   {
1770     if(rs1[i]){
1771       clear_const(current,rs1[i]);
1772       alloc_reg(current,i,rs1[i]);
1773       alloc_all(current,i);
1774     }
1775     else {
1776       alloc_all(current,i); // FIXME: Keep r0
1777       current->u&=~1LL;
1778       alloc_reg(current,i,0);
1779     }
1780   }
1781   else
1782   {
1783     // TLBR/TLBWI/TLBWR/TLBP/ERET
1784     assert(opcode2[i]==0x10);
1785     alloc_all(current,i);
1786   }
1787   minimum_free_regs[i]=HOST_REGS;
1788 }
1789
1790 static void cop1_alloc(struct regstat *current,int i)
1791 {
1792   alloc_reg(current,i,CSREG); // Load status
1793   if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1794   {
1795     assert(rt1[i]);
1796     clear_const(current,rt1[i]);
1797     if(opcode2[i]==1) {
1798       alloc_reg64(current,i,rt1[i]); // DMFC1
1799       current->is32&=~(1LL<<rt1[i]);
1800     }else{
1801       alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1802       current->is32|=1LL<<rt1[i];
1803     }
1804     dirty_reg(current,rt1[i]);
1805     alloc_reg_temp(current,i,-1);
1806   }
1807   else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1808   {
1809     if(rs1[i]){
1810       clear_const(current,rs1[i]);
1811       if(opcode2[i]==5)
1812         alloc_reg64(current,i,rs1[i]); // DMTC1
1813       else
1814         alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1815       alloc_reg_temp(current,i,-1);
1816     }
1817     else {
1818       current->u&=~1LL;
1819       alloc_reg(current,i,0);
1820       alloc_reg_temp(current,i,-1);
1821     }
1822   }
1823   minimum_free_regs[i]=1;
1824 }
1825 static void fconv_alloc(struct regstat *current,int i)
1826 {
1827   alloc_reg(current,i,CSREG); // Load status
1828   alloc_reg_temp(current,i,-1);
1829   minimum_free_regs[i]=1;
1830 }
1831 static void float_alloc(struct regstat *current,int i)
1832 {
1833   alloc_reg(current,i,CSREG); // Load status
1834   alloc_reg_temp(current,i,-1);
1835   minimum_free_regs[i]=1;
1836 }
1837 static void fcomp_alloc(struct regstat *current,int i)
1838 {
1839   alloc_reg(current,i,CSREG); // Load status
1840   alloc_reg(current,i,FSREG); // Load flags
1841   dirty_reg(current,FSREG); // Flag will be modified
1842   alloc_reg_temp(current,i,-1);
1843   minimum_free_regs[i]=1;
1844 }
1845
1846 static void syscall_alloc(struct regstat *current,int i)
1847 {
1848   alloc_cc(current,i);
1849   dirty_reg(current,CCREG);
1850   alloc_all(current,i);
1851   minimum_free_regs[i]=HOST_REGS;
1852   current->isconst=0;
1853 }
1854
1855 static void delayslot_alloc(struct regstat *current,int i)
1856 {
1857   switch(itype[i]) {
1858     case UJUMP:
1859     case CJUMP:
1860     case SJUMP:
1861     case RJUMP:
1862     case FJUMP:
1863     case SYSCALL:
1864     case SPAN:
1865       assem_debug("jump in the delay slot.  this shouldn't happen.");//exit(1);
1866       DebugMessage(M64MSG_VERBOSE, "Disabled speculative precompilation");
1867       stop_after_jal=1;
1868       break;
1869     case IMM16:
1870       imm16_alloc(current,i);
1871       break;
1872     case LOAD:
1873     case LOADLR:
1874       load_alloc(current,i);
1875       break;
1876     case STORE:
1877     case STORELR:
1878       store_alloc(current,i);
1879       break;
1880     case ALU:
1881       alu_alloc(current,i);
1882       break;
1883     case SHIFT:
1884       shift_alloc(current,i);
1885       break;
1886     case MULTDIV:
1887       multdiv_alloc(current,i);
1888       break;
1889     case SHIFTIMM:
1890       shiftimm_alloc(current,i);
1891       break;
1892     case MOV:
1893       mov_alloc(current,i);
1894       break;
1895     case COP0:
1896       cop0_alloc(current,i);
1897       break;
1898     case COP1:
1899       cop1_alloc(current,i);
1900       break;
1901     case C1LS:
1902       c1ls_alloc(current,i);
1903       break;
1904     case FCONV:
1905       fconv_alloc(current,i);
1906       break;
1907     case FLOAT:
1908       float_alloc(current,i);
1909       break;
1910     case FCOMP:
1911       fcomp_alloc(current,i);
1912       break;
1913   }
1914 }
1915
1916 // Special case where a branch and delay slot span two pages in virtual memory
1917 static void pagespan_alloc(struct regstat *current,int i)
1918 {
1919   current->isconst=0;
1920   current->wasconst=0;
1921   regs[i].wasconst=0;
1922   minimum_free_regs[i]=HOST_REGS;
1923   alloc_all(current,i);
1924   alloc_cc(current,i);
1925   dirty_reg(current,CCREG);
1926   if(opcode[i]==3) // JAL
1927   {
1928     alloc_reg(current,i,31);
1929     dirty_reg(current,31);
1930   }
1931   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1932   {
1933     alloc_reg(current,i,rs1[i]);
1934     if (rt1[i]!=0) {
1935       alloc_reg(current,i,rt1[i]);
1936       dirty_reg(current,rt1[i]);
1937     }
1938   }
1939   if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1940   {
1941     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1942     if(rs2[i]) alloc_reg(current,i,rs2[i]);
1943     if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1944     {
1945       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1946       if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1947     }
1948   }
1949   else
1950   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1951   {
1952     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1953     if(!((current->is32>>rs1[i])&1))
1954     {
1955       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1956     }
1957   }
1958   else
1959   if(opcode[i]==0x11) // BC1
1960   {
1961     alloc_reg(current,i,FSREG);
1962     alloc_reg(current,i,CSREG);
1963   }
1964   //else ...
1965 }
1966
1967 static void add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1968 {
1969   stubs[stubcount][0]=type;
1970   stubs[stubcount][1]=addr;
1971   stubs[stubcount][2]=retaddr;
1972   stubs[stubcount][3]=a;
1973   stubs[stubcount][4]=b;
1974   stubs[stubcount][5]=c;
1975   stubs[stubcount][6]=d;
1976   stubs[stubcount][7]=e;
1977   stubcount++;
1978 }
1979
1980 // Write out a single register
1981 static void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
1982 {
1983   int hr;
1984   for(hr=0;hr<HOST_REGS;hr++) {
1985     if(hr!=EXCLUDE_REG) {
1986       if((regmap[hr]&63)==r) {
1987         if((dirty>>hr)&1) {
1988           if(regmap[hr]<64) {
1989             emit_storereg(r,hr);
1990             if((is32>>regmap[hr])&1) {
1991               emit_sarimm(hr,31,hr);
1992               emit_storereg(r|64,hr);
1993             }
1994           }else{
1995             emit_storereg(r|64,hr);
1996           }
1997         }
1998       }
1999     }
2000   }
2001 }
2002 #if 0
2003 static int mchecksum()
2004 {
2005   //if(!tracedebug) return 0;
2006   int i;
2007   int sum=0;
2008   for(i=0;i<2097152;i++) {
2009     unsigned int temp=sum;
2010     sum<<=1;
2011     sum|=(~temp)>>31;
2012     sum^=((u_int *)rdram)[i];
2013   }
2014   return sum;
2015 }
2016
2017 static int rchecksum()
2018 {
2019   int i;
2020   int sum=0;
2021   for(i=0;i<64;i++)
2022     sum^=((u_int *)reg)[i];
2023   return sum;
2024 }
2025
2026 static void rlist()
2027 {
2028   int i;
2029   DebugMessage(M64MSG_VERBOSE, "TRACE: ");
2030   for(i=0;i<32;i++)
2031     DebugMessage(M64MSG_VERBOSE, "r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2032   DebugMessage(M64MSG_VERBOSE, "TRACE: ");
2033   for(i=0;i<32;i++)
2034     DebugMessage(M64MSG_VERBOSE, "f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2035 }
2036
2037 static void enabletrace()
2038 {
2039   tracedebug=1;
2040 }
2041
2042
2043 static void memdebug(int i)
2044 {
2045   //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (checksum %x) lo=%8x%8x",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2046   //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (rchecksum %x)",Count,next_interupt,rchecksum());
2047   //rlist();
2048   //if(tracedebug) {
2049   //if(Count>=-2084597794) {
2050   if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2051   //if(0) {
2052     DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (checksum %x)",Count,next_interupt,mchecksum());
2053     //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (checksum %x) Status=%x",Count,next_interupt,mchecksum(),Status);
2054     //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (checksum %x) hi=%8x%8x",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2055     rlist();
2056     #if NEW_DYNAREC == NEW_DYNAREC_X86
2057     DebugMessage(M64MSG_VERBOSE, "TRACE: %x",(&i)[-1]);
2058     #endif
2059     #if NEW_DYNAREC == NEW_DYNAREC_ARM
2060     int j;
2061     DebugMessage(M64MSG_VERBOSE, "TRACE: %x ",(&j)[10]);
2062     DebugMessage(M64MSG_VERBOSE, "TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2063     #endif
2064     //fflush(stdout);
2065   }
2066   //DebugMessage(M64MSG_VERBOSE, "TRACE: %x",(&i)[-1]);
2067 }
2068 #endif
2069
2070 /* Debug:
2071 static void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2072 {
2073   DebugMessage(M64MSG_VERBOSE, "TLB Exception: instruction=%x addr=%x cause=%x",iaddr, addr, cause);
2074 }
2075 end debug */
2076
2077 static void alu_assemble(int i,struct regstat *i_regs)
2078 {
2079   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2080     if(rt1[i]) {
2081       signed char s1,s2,t;
2082       t=get_reg(i_regs->regmap,rt1[i]);
2083       if(t>=0) {
2084         s1=get_reg(i_regs->regmap,rs1[i]);
2085         s2=get_reg(i_regs->regmap,rs2[i]);
2086         if(rs1[i]&&rs2[i]) {
2087           assert(s1>=0);
2088           assert(s2>=0);
2089           if(opcode2[i]&2) emit_sub(s1,s2,t);
2090           else emit_add(s1,s2,t);
2091         }
2092         else if(rs1[i]) {
2093           if(s1>=0) emit_mov(s1,t);
2094           else emit_loadreg(rs1[i],t);
2095         }
2096         else if(rs2[i]) {
2097           if(s2>=0) {
2098             if(opcode2[i]&2) emit_neg(s2,t);
2099             else emit_mov(s2,t);
2100           }
2101           else {
2102             emit_loadreg(rs2[i],t);
2103             if(opcode2[i]&2) emit_neg(t,t);
2104           }
2105         }
2106         else emit_zeroreg(t);
2107       }
2108     }
2109   }
2110   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2111     if(rt1[i]) {
2112       signed char s1l,s2l,s1h,s2h,tl,th;
2113       tl=get_reg(i_regs->regmap,rt1[i]);
2114       th=get_reg(i_regs->regmap,rt1[i]|64);
2115       if(tl>=0) {
2116         s1l=get_reg(i_regs->regmap,rs1[i]);
2117         s2l=get_reg(i_regs->regmap,rs2[i]);
2118         s1h=get_reg(i_regs->regmap,rs1[i]|64);
2119         s2h=get_reg(i_regs->regmap,rs2[i]|64);
2120         if(rs1[i]&&rs2[i]) {
2121           assert(s1l>=0);
2122           assert(s2l>=0);
2123           if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2124           else emit_adds(s1l,s2l,tl);
2125           if(th>=0) {
2126             #ifdef INVERTED_CARRY
2127             if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2128             #else
2129             if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2130             #endif
2131             else emit_add(s1h,s2h,th);
2132           }
2133         }
2134         else if(rs1[i]) {
2135           if(s1l>=0) emit_mov(s1l,tl);
2136           else emit_loadreg(rs1[i],tl);
2137           if(th>=0) {
2138             if(s1h>=0) emit_mov(s1h,th);
2139             else emit_loadreg(rs1[i]|64,th);
2140           }
2141         }
2142         else if(rs2[i]) {
2143           if(s2l>=0) {
2144             if(opcode2[i]&2) emit_negs(s2l,tl);
2145             else emit_mov(s2l,tl);
2146           }
2147           else {
2148             emit_loadreg(rs2[i],tl);
2149             if(opcode2[i]&2) emit_negs(tl,tl);
2150           }
2151           if(th>=0) {
2152             #ifdef INVERTED_CARRY
2153             if(s2h>=0) emit_mov(s2h,th);
2154             else emit_loadreg(rs2[i]|64,th);
2155             if(opcode2[i]&2) {
2156               emit_adcimm(-1,th); // x86 has inverted carry flag
2157               emit_not(th,th);
2158             }
2159             #else
2160             if(opcode2[i]&2) {
2161               if(s2h>=0) emit_rscimm(s2h,0,th);
2162               else {
2163                 emit_loadreg(rs2[i]|64,th);
2164                 emit_rscimm(th,0,th);
2165               }
2166             }else{
2167               if(s2h>=0) emit_mov(s2h,th);
2168               else emit_loadreg(rs2[i]|64,th);
2169             }
2170             #endif
2171           }
2172         }
2173         else {
2174           emit_zeroreg(tl);
2175           if(th>=0) emit_zeroreg(th);
2176         }
2177       }
2178     }
2179   }
2180   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2181     if(rt1[i]) {
2182       signed char s1l,s1h,s2l,s2h,t;
2183       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2184       {
2185         t=get_reg(i_regs->regmap,rt1[i]);
2186         //assert(t>=0);
2187         if(t>=0) {
2188           s1l=get_reg(i_regs->regmap,rs1[i]);
2189           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2190           s2l=get_reg(i_regs->regmap,rs2[i]);
2191           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2192           if(rs2[i]==0) // rx<r0
2193           {
2194             assert(s1h>=0);
2195             if(opcode2[i]==0x2a) // SLT
2196               emit_shrimm(s1h,31,t);
2197             else // SLTU (unsigned can not be less than zero)
2198               emit_zeroreg(t);
2199           }
2200           else if(rs1[i]==0) // r0<rx
2201           {
2202             assert(s2h>=0);
2203             if(opcode2[i]==0x2a) // SLT
2204               emit_set_gz64_32(s2h,s2l,t);
2205             else // SLTU (set if not zero)
2206               emit_set_nz64_32(s2h,s2l,t);
2207           }
2208           else {
2209             assert(s1l>=0);assert(s1h>=0);
2210             assert(s2l>=0);assert(s2h>=0);
2211             if(opcode2[i]==0x2a) // SLT
2212               emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2213             else // SLTU
2214               emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2215           }
2216         }
2217       } else {
2218         t=get_reg(i_regs->regmap,rt1[i]);
2219         //assert(t>=0);
2220         if(t>=0) {
2221           s1l=get_reg(i_regs->regmap,rs1[i]);
2222           s2l=get_reg(i_regs->regmap,rs2[i]);
2223           if(rs2[i]==0) // rx<r0
2224           {
2225             assert(s1l>=0);
2226             if(opcode2[i]==0x2a) // SLT
2227               emit_shrimm(s1l,31,t);
2228             else // SLTU (unsigned can not be less than zero)
2229               emit_zeroreg(t);
2230           }
2231           else if(rs1[i]==0) // r0<rx
2232           {
2233             assert(s2l>=0);
2234             if(opcode2[i]==0x2a) // SLT
2235               emit_set_gz32(s2l,t);
2236             else // SLTU (set if not zero)
2237               emit_set_nz32(s2l,t);
2238           }
2239           else{
2240             assert(s1l>=0);assert(s2l>=0);
2241             if(opcode2[i]==0x2a) // SLT
2242               emit_set_if_less32(s1l,s2l,t);
2243             else // SLTU
2244               emit_set_if_carry32(s1l,s2l,t);
2245           }
2246         }
2247       }
2248     }
2249   }
2250   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2251     if(rt1[i]) {
2252       signed char s1l,s1h,s2l,s2h,th,tl;
2253       tl=get_reg(i_regs->regmap,rt1[i]);
2254       th=get_reg(i_regs->regmap,rt1[i]|64);
2255       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2256       {
2257         assert(tl>=0);
2258         if(tl>=0) {
2259           s1l=get_reg(i_regs->regmap,rs1[i]);
2260           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2261           s2l=get_reg(i_regs->regmap,rs2[i]);
2262           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2263           if(rs1[i]&&rs2[i]) {
2264             assert(s1l>=0);assert(s1h>=0);
2265             assert(s2l>=0);assert(s2h>=0);
2266             if(opcode2[i]==0x24) { // AND
2267               emit_and(s1l,s2l,tl);
2268               emit_and(s1h,s2h,th);
2269             } else
2270             if(opcode2[i]==0x25) { // OR
2271               emit_or(s1l,s2l,tl);
2272               emit_or(s1h,s2h,th);
2273             } else
2274             if(opcode2[i]==0x26) { // XOR
2275               emit_xor(s1l,s2l,tl);
2276               emit_xor(s1h,s2h,th);
2277             } else
2278             if(opcode2[i]==0x27) { // NOR
2279               emit_or(s1l,s2l,tl);
2280               emit_or(s1h,s2h,th);
2281               emit_not(tl,tl);
2282               emit_not(th,th);
2283             }
2284           }
2285           else
2286           {
2287             if(opcode2[i]==0x24) { // AND
2288               emit_zeroreg(tl);
2289               emit_zeroreg(th);
2290             } else
2291             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2292               if(rs1[i]){
2293                 if(s1l>=0) emit_mov(s1l,tl);
2294                 else emit_loadreg(rs1[i],tl);
2295                 if(s1h>=0) emit_mov(s1h,th);
2296                 else emit_loadreg(rs1[i]|64,th);
2297               }
2298               else
2299               if(rs2[i]){
2300                 if(s2l>=0) emit_mov(s2l,tl);
2301                 else emit_loadreg(rs2[i],tl);
2302                 if(s2h>=0) emit_mov(s2h,th);
2303                 else emit_loadreg(rs2[i]|64,th);
2304               }
2305               else{
2306                 emit_zeroreg(tl);
2307                 emit_zeroreg(th);
2308               }
2309             } else
2310             if(opcode2[i]==0x27) { // NOR
2311               if(rs1[i]){
2312                 if(s1l>=0) emit_not(s1l,tl);
2313                 else{
2314                   emit_loadreg(rs1[i],tl);
2315                   emit_not(tl,tl);
2316                 }
2317                 if(s1h>=0) emit_not(s1h,th);
2318                 else{
2319                   emit_loadreg(rs1[i]|64,th);
2320                   emit_not(th,th);
2321                 }
2322               }
2323               else
2324               if(rs2[i]){
2325                 if(s2l>=0) emit_not(s2l,tl);
2326                 else{
2327                   emit_loadreg(rs2[i],tl);
2328                   emit_not(tl,tl);
2329                 }
2330                 if(s2h>=0) emit_not(s2h,th);
2331                 else{
2332                   emit_loadreg(rs2[i]|64,th);
2333                   emit_not(th,th);
2334                 }
2335               }
2336               else {
2337                 emit_movimm(-1,tl);
2338                 emit_movimm(-1,th);
2339               }
2340             }
2341           }
2342         }
2343       }
2344       else
2345       {
2346         // 32 bit
2347         if(tl>=0) {
2348           s1l=get_reg(i_regs->regmap,rs1[i]);
2349           s2l=get_reg(i_regs->regmap,rs2[i]);
2350           if(rs1[i]&&rs2[i]) {
2351             assert(s1l>=0);
2352             assert(s2l>=0);
2353             if(opcode2[i]==0x24) { // AND
2354               emit_and(s1l,s2l,tl);
2355             } else
2356             if(opcode2[i]==0x25) { // OR
2357               emit_or(s1l,s2l,tl);
2358             } else
2359             if(opcode2[i]==0x26) { // XOR
2360               emit_xor(s1l,s2l,tl);
2361             } else
2362             if(opcode2[i]==0x27) { // NOR
2363               emit_or(s1l,s2l,tl);
2364               emit_not(tl,tl);
2365             }
2366           }
2367           else
2368           {
2369             if(opcode2[i]==0x24) { // AND
2370               emit_zeroreg(tl);
2371             } else
2372             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2373               if(rs1[i]){
2374                 if(s1l>=0) emit_mov(s1l,tl);
2375                 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2376               }
2377               else
2378               if(rs2[i]){
2379                 if(s2l>=0) emit_mov(s2l,tl);
2380                 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2381               }
2382               else emit_zeroreg(tl);
2383             } else
2384             if(opcode2[i]==0x27) { // NOR
2385               if(rs1[i]){
2386                 if(s1l>=0) emit_not(s1l,tl);
2387                 else {
2388                   emit_loadreg(rs1[i],tl);
2389                   emit_not(tl,tl);
2390                 }
2391               }
2392               else
2393               if(rs2[i]){
2394                 if(s2l>=0) emit_not(s2l,tl);
2395                 else {
2396                   emit_loadreg(rs2[i],tl);
2397                   emit_not(tl,tl);
2398                 }
2399               }
2400               else emit_movimm(-1,tl);
2401             }
2402           }
2403         }
2404       }
2405     }
2406   }
2407 }
2408
2409 static void imm16_assemble(int i,struct regstat *i_regs)
2410 {
2411   if (opcode[i]==0x0f) { // LUI
2412     if(rt1[i]) {
2413       signed char t;
2414       t=get_reg(i_regs->regmap,rt1[i]);
2415       //assert(t>=0);
2416       if(t>=0) {
2417         if(!((i_regs->isconst>>t)&1))
2418           emit_movimm(imm[i]<<16,t);
2419       }
2420     }
2421   }
2422   if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2423     if(rt1[i]) {
2424       signed char s,t;
2425       t=get_reg(i_regs->regmap,rt1[i]);
2426       s=get_reg(i_regs->regmap,rs1[i]);
2427       if(rs1[i]) {
2428         //assert(t>=0);
2429         //assert(s>=0);
2430         if(t>=0) {
2431           if(!((i_regs->isconst>>t)&1)) {
2432             if(s<0) {
2433               if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2434               emit_addimm(t,imm[i],t);
2435             }else{
2436               if(!((i_regs->wasconst>>s)&1))
2437                 emit_addimm(s,imm[i],t);
2438               else
2439                 emit_movimm(constmap[i][s]+imm[i],t);
2440             }
2441           }
2442         }
2443       } else {
2444         if(t>=0) {
2445           if(!((i_regs->isconst>>t)&1))
2446             emit_movimm(imm[i],t);
2447         }
2448       }
2449     }
2450   }
2451   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2452     if(rt1[i]) {
2453       signed char sh,sl,th,tl;
2454       th=get_reg(i_regs->regmap,rt1[i]|64);
2455       tl=get_reg(i_regs->regmap,rt1[i]);
2456       sh=get_reg(i_regs->regmap,rs1[i]|64);
2457       sl=get_reg(i_regs->regmap,rs1[i]);
2458       if(tl>=0) {
2459         if(rs1[i]) {
2460           assert(sh>=0);
2461           assert(sl>=0);
2462           if(th>=0) {
2463             emit_addimm64_32(sh,sl,imm[i],th,tl);
2464           }
2465           else {
2466             emit_addimm(sl,imm[i],tl);
2467           }
2468         } else {
2469           emit_movimm(imm[i],tl);
2470           if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2471         }
2472       }
2473     }
2474   }
2475   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2476     if(rt1[i]) {
2477       //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2478       signed char sh,sl,t;
2479       t=get_reg(i_regs->regmap,rt1[i]);
2480       sh=get_reg(i_regs->regmap,rs1[i]|64);
2481       sl=get_reg(i_regs->regmap,rs1[i]);
2482       //assert(t>=0);
2483       if(t>=0) {
2484         if(rs1[i]>0) {
2485           if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2486           if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2487             if(opcode[i]==0x0a) { // SLTI
2488               if(sl<0) {
2489                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2490                 emit_slti32(t,imm[i],t);
2491               }else{
2492                 emit_slti32(sl,imm[i],t);
2493               }
2494             }
2495             else { // SLTIU
2496               if(sl<0) {
2497                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2498                 emit_sltiu32(t,imm[i],t);
2499               }else{
2500                 emit_sltiu32(sl,imm[i],t);
2501               }
2502             }
2503           }else{ // 64-bit
2504             assert(sl>=0);
2505             if(opcode[i]==0x0a) // SLTI
2506               emit_slti64_32(sh,sl,imm[i],t);
2507             else // SLTIU
2508               emit_sltiu64_32(sh,sl,imm[i],t);
2509           }
2510         }else{
2511           // SLTI(U) with r0 is just stupid,
2512           // nonetheless examples can be found
2513           if(opcode[i]==0x0a) // SLTI
2514             if(0<imm[i]) emit_movimm(1,t);
2515             else emit_zeroreg(t);
2516           else // SLTIU
2517           {
2518             if(imm[i]) emit_movimm(1,t);
2519             else emit_zeroreg(t);
2520           }
2521         }
2522       }
2523     }
2524   }
2525   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2526     if(rt1[i]) {
2527       signed char sh,sl,th,tl;
2528       th=get_reg(i_regs->regmap,rt1[i]|64);
2529       tl=get_reg(i_regs->regmap,rt1[i]);
2530       sh=get_reg(i_regs->regmap,rs1[i]|64);
2531       sl=get_reg(i_regs->regmap,rs1[i]);
2532       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2533         if(opcode[i]==0x0c) //ANDI
2534         {
2535           if(rs1[i]) {
2536             if(sl<0) {
2537               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2538               emit_andimm(tl,imm[i],tl);
2539             }else{
2540               if(!((i_regs->wasconst>>sl)&1))
2541                 emit_andimm(sl,imm[i],tl);
2542               else
2543                 emit_movimm(constmap[i][sl]&imm[i],tl);
2544             }
2545           }
2546           else
2547             emit_zeroreg(tl);
2548           if(th>=0) emit_zeroreg(th);
2549         }
2550         else
2551         {
2552           if(rs1[i]) {
2553             if(sl<0) {
2554               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2555             }
2556             if(th>=0) {
2557               if(sh<0) {
2558                 emit_loadreg(rs1[i]|64,th);
2559               }else{
2560                 emit_mov(sh,th);
2561               }
2562             }
2563             if(opcode[i]==0x0d) { //ORI
2564             if(sl<0) {
2565               emit_orimm(tl,imm[i],tl);
2566             }else{
2567               if(!((i_regs->wasconst>>sl)&1))
2568                 emit_orimm(sl,imm[i],tl);
2569               else
2570                 emit_movimm(constmap[i][sl]|imm[i],tl);
2571             }
2572             }
2573             if(opcode[i]==0x0e) { //XORI
2574             if(sl<0) {
2575               emit_xorimm(tl,imm[i],tl);
2576             }else{
2577               if(!((i_regs->wasconst>>sl)&1))
2578                 emit_xorimm(sl,imm[i],tl);
2579               else
2580                 emit_movimm(constmap[i][sl]^imm[i],tl);
2581             }
2582             }
2583           }
2584           else {
2585             emit_movimm(imm[i],tl);
2586             if(th>=0) emit_zeroreg(th);
2587           }
2588         }
2589       }
2590     }
2591   }
2592 }
2593
2594 static void shiftimm_assemble(int i,struct regstat *i_regs)
2595 {
2596   if(opcode2[i]<=0x3) // SLL/SRL/SRA
2597   {
2598     if(rt1[i]) {
2599       signed char s,t;
2600       t=get_reg(i_regs->regmap,rt1[i]);
2601       s=get_reg(i_regs->regmap,rs1[i]);
2602       //assert(t>=0);
2603       if(t>=0){
2604         if(rs1[i]==0)
2605         {
2606           emit_zeroreg(t);
2607         }
2608         else
2609         {
2610           if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2611           if(imm[i]) {
2612             if(opcode2[i]==0) // SLL
2613             {
2614               emit_shlimm(s<0?t:s,imm[i],t);
2615             }
2616             if(opcode2[i]==2) // SRL
2617             {
2618               emit_shrimm(s<0?t:s,imm[i],t);
2619             }
2620             if(opcode2[i]==3) // SRA
2621             {
2622               emit_sarimm(s<0?t:s,imm[i],t);
2623             }
2624           }else{
2625             // Shift by zero
2626             if(s>=0 && s!=t) emit_mov(s,t);
2627           }
2628         }
2629       }
2630       //emit_storereg(rt1[i],t); //DEBUG
2631     }
2632   }
2633   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2634   {
2635     if(rt1[i]) {
2636       signed char sh,sl,th,tl;
2637       th=get_reg(i_regs->regmap,rt1[i]|64);
2638       tl=get_reg(i_regs->regmap,rt1[i]);
2639       sh=get_reg(i_regs->regmap,rs1[i]|64);
2640       sl=get_reg(i_regs->regmap,rs1[i]);
2641       if(tl>=0) {
2642         if(rs1[i]==0)
2643         {
2644           emit_zeroreg(tl);
2645           if(th>=0) emit_zeroreg(th);
2646         }
2647         else
2648         {
2649           assert(sl>=0);
2650           assert(sh>=0);
2651           if(imm[i]) {
2652             if(opcode2[i]==0x38) // DSLL
2653             {
2654               if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2655               emit_shlimm(sl,imm[i],tl);
2656             }
2657             if(opcode2[i]==0x3a) // DSRL
2658             {
2659               emit_shrdimm(sl,sh,imm[i],tl);
2660               if(th>=0) emit_shrimm(sh,imm[i],th);
2661             }
2662             if(opcode2[i]==0x3b) // DSRA
2663             {
2664               emit_shrdimm(sl,sh,imm[i],tl);
2665               if(th>=0) emit_sarimm(sh,imm[i],th);
2666             }
2667           }else{
2668             // Shift by zero
2669             if(sl!=tl) emit_mov(sl,tl);
2670             if(th>=0&&sh!=th) emit_mov(sh,th);
2671           }
2672         }
2673       }
2674     }
2675   }
2676   if(opcode2[i]==0x3c) // DSLL32
2677   {
2678     if(rt1[i]) {
2679       signed char sl,tl,th;
2680       tl=get_reg(i_regs->regmap,rt1[i]);
2681       th=get_reg(i_regs->regmap,rt1[i]|64);
2682       sl=get_reg(i_regs->regmap,rs1[i]);
2683       if(th>=0||tl>=0){
2684         assert(tl>=0);
2685         assert(th>=0);
2686         assert(sl>=0);
2687         emit_mov(sl,th);
2688         emit_zeroreg(tl);
2689         if(imm[i]>32)
2690         {
2691           emit_shlimm(th,imm[i]&31,th);
2692         }
2693       }
2694     }
2695   }
2696   if(opcode2[i]==0x3e) // DSRL32
2697   {
2698     if(rt1[i]) {
2699       signed char sh,tl,th;
2700       tl=get_reg(i_regs->regmap,rt1[i]);
2701       th=get_reg(i_regs->regmap,rt1[i]|64);
2702       sh=get_reg(i_regs->regmap,rs1[i]|64);
2703       if(tl>=0){
2704         assert(sh>=0);
2705         emit_mov(sh,tl);
2706         if(th>=0) emit_zeroreg(th);
2707         if(imm[i]>32)
2708         {
2709           emit_shrimm(tl,imm[i]&31,tl);
2710         }
2711       }
2712     }
2713   }
2714   if(opcode2[i]==0x3f) // DSRA32
2715   {
2716     if(rt1[i]) {
2717       signed char sh,tl;
2718       tl=get_reg(i_regs->regmap,rt1[i]);
2719       sh=get_reg(i_regs->regmap,rs1[i]|64);
2720       if(tl>=0){
2721         assert(sh>=0);
2722         emit_mov(sh,tl);
2723         if(imm[i]>32)
2724         {
2725           emit_sarimm(tl,imm[i]&31,tl);
2726         }
2727       }
2728     }
2729   }
2730 }
2731
2732 #ifndef shift_assemble
2733 void shift_assemble(int i,struct regstat *i_regs)
2734 {
2735   DebugMessage(M64MSG_ERROR, "Need shift_assemble for this architecture.");
2736   exit(1);
2737 }
2738 #endif
2739
2740 static void load_assemble(int i,struct regstat *i_regs)
2741 {
2742   int s,th,tl,addr,map=-1,cache=-1;
2743   int offset;
2744   int jaddr=0;
2745   int memtarget,c=0;
2746   u_int hr,reglist=0;
2747   th=get_reg(i_regs->regmap,rt1[i]|64);
2748   tl=get_reg(i_regs->regmap,rt1[i]);
2749   s=get_reg(i_regs->regmap,rs1[i]);
2750   offset=imm[i];
2751   for(hr=0;hr<HOST_REGS;hr++) {
2752     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2753   }
2754   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2755   if(s>=0) {
2756     c=(i_regs->wasconst>>s)&1;
2757     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
2758     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2759   }
2760   if(tl<0) tl=get_reg(i_regs->regmap,-1);
2761   if(offset||s<0||c) addr=tl;
2762   else addr=s;
2763   //DebugMessage(M64MSG_VERBOSE, "load_assemble: c=%d",c);
2764   //if(c) DebugMessage(M64MSG_VERBOSE, "load_assemble: const=%x",(int)constmap[i][s]+offset);
2765   assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2766   reglist&=~(1<<tl);
2767   if(th>=0) reglist&=~(1<<th);
2768   if(!using_tlb) {
2769     if(!c) {
2770       #ifdef RAM_OFFSET
2771       map=get_reg(i_regs->regmap,ROREG);
2772       if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2773       #endif
2774 //#define R29_HACK 1
2775       #ifdef R29_HACK
2776       // Strmnnrmn's speed hack
2777       if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
2778       #endif
2779       {
2780         emit_cmpimm(addr,0x800000);
2781         jaddr=(int)out;
2782         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2783         // Hint to branch predictor that the branch is unlikely to be taken
2784         if(rs1[i]>=28)
2785           emit_jno_unlikely(0);
2786         else
2787         #endif
2788         emit_jno(0);
2789       }
2790     }
2791   }else{ // using tlb
2792     int x=0;
2793     if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2794     if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2795     map=get_reg(i_regs->regmap,TLREG);
2796     cache=get_reg(i_regs->regmap,MMREG);
2797     assert(map>=0);
2798     reglist&=~(1<<map);
2799     map=do_tlb_r(addr,tl,map,cache,x,-1,-1,c,constmap[i][s]+offset);
2800     do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2801   }
2802   int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2803   if (opcode[i]==0x20) { // LB
2804     if(!c||memtarget) {
2805       if(!dummy) {
2806         #ifdef HOST_IMM_ADDR32
2807         if(c)
2808           emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2809         else
2810         #endif
2811         {
2812           //emit_xorimm(addr,3,tl);
2813           //gen_tlb_addr_r(tl,map);
2814           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2815           int x=0;
2816           if(!c) emit_xorimm(addr,3,tl);
2817           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2818           emit_movsbl_indexed_tlb(x,tl,map,tl);
2819         }
2820       }
2821       if(jaddr)
2822         add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2823     }
2824     else
2825       inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2826   }
2827   if (opcode[i]==0x21) { // LH
2828     if(!c||memtarget) {
2829       if(!dummy) {
2830         #ifdef HOST_IMM_ADDR32
2831         if(c)
2832           emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2833         else
2834         #endif
2835         {
2836           int x=0;
2837           if(!c) emit_xorimm(addr,2,tl);
2838           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2839           //#ifdef
2840           //emit_movswl_indexed_tlb(x,tl,map,tl);
2841           //else
2842           if(map>=0) {
2843             gen_tlb_addr_r(tl,map);
2844             emit_movswl_indexed(x,tl,tl);
2845           }else{
2846             #ifdef RAM_OFFSET
2847             emit_movswl_indexed(x,tl,tl);
2848             #else
2849             emit_movswl_indexed((int)rdram-0x80000000+x,tl,tl);
2850             #endif
2851           }
2852         }
2853       }
2854       if(jaddr)
2855         add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2856     }
2857     else
2858       inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2859   }
2860   if (opcode[i]==0x23) { // LW
2861     if(!c||memtarget) {
2862       if(!dummy) {
2863         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2864         #ifdef HOST_IMM_ADDR32
2865         if(c)
2866           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2867         else
2868         #endif
2869         emit_readword_indexed_tlb(0,addr,map,tl);
2870       }
2871       if(jaddr)
2872         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2873     }
2874     else
2875       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2876   }
2877   if (opcode[i]==0x24) { // LBU
2878     if(!c||memtarget) {
2879       if(!dummy) {
2880         #ifdef HOST_IMM_ADDR32
2881         if(c)
2882           emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2883         else
2884         #endif
2885         {
2886           //emit_xorimm(addr,3,tl);
2887           //gen_tlb_addr_r(tl,map);
2888           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2889           int x=0;
2890           if(!c) emit_xorimm(addr,3,tl);
2891           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2892           emit_movzbl_indexed_tlb(x,tl,map,tl);
2893         }
2894       }
2895       if(jaddr)
2896         add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2897     }
2898     else
2899       inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2900   }
2901   if (opcode[i]==0x25) { // LHU
2902     if(!c||memtarget) {
2903       if(!dummy) {
2904         #ifdef HOST_IMM_ADDR32
2905         if(c)
2906           emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2907         else
2908         #endif
2909         {
2910           int x=0;
2911           if(!c) emit_xorimm(addr,2,tl);
2912           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2913           //#ifdef
2914           //emit_movzwl_indexed_tlb(x,tl,map,tl);
2915           //#else
2916           if(map>=0) {
2917             gen_tlb_addr_r(tl,map);
2918             emit_movzwl_indexed(x,tl,tl);
2919           }else{
2920             #ifdef RAM_OFFSET
2921             emit_movzwl_indexed(x,tl,tl);
2922             #else
2923             emit_movzwl_indexed((int)rdram-0x80000000+x,tl,tl);
2924             #endif
2925           }
2926         }
2927       }
2928       if(jaddr)
2929         add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2930     }
2931     else
2932       inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2933   }
2934   if (opcode[i]==0x27) { // LWU
2935     assert(th>=0);
2936     if(!c||memtarget) {
2937       if(!dummy) {
2938         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2939         #ifdef HOST_IMM_ADDR32
2940         if(c)
2941           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2942         else
2943         #endif
2944         emit_readword_indexed_tlb(0,addr,map,tl);
2945       }
2946       if(jaddr)
2947         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2948     }
2949     else {
2950       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2951     }
2952     emit_zeroreg(th);
2953   }
2954   if (opcode[i]==0x37) { // LD
2955     if(!c||memtarget) {
2956       if(!dummy) {
2957         //gen_tlb_addr_r(tl,map);
2958         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2959         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2960         #ifdef HOST_IMM_ADDR32
2961         if(c)
2962           emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
2963         else
2964         #endif
2965         emit_readdword_indexed_tlb(0,addr,map,th,tl);
2966       }
2967       if(jaddr)
2968         add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2969     }
2970     else
2971       inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2972   }
2973   //emit_storereg(rt1[i],tl); // DEBUG
2974   //if(opcode[i]==0x23)
2975   //if(opcode[i]==0x24)
2976   //if(opcode[i]==0x23||opcode[i]==0x24)
2977   /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
2978   {
2979     //emit_pusha();
2980     save_regs(0x100f);
2981         emit_readword((int)&last_count,ECX);
2982         #if NEW_DYNAREC == NEW_DYNAREC_X86
2983         if(get_reg(i_regs->regmap,CCREG)<0)
2984           emit_loadreg(CCREG,HOST_CCREG);
2985         emit_add(HOST_CCREG,ECX,HOST_CCREG);
2986         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2987         emit_writeword(HOST_CCREG,(int)&Count);
2988         #endif
2989         #if NEW_DYNAREC == NEW_DYNAREC_ARM
2990         if(get_reg(i_regs->regmap,CCREG)<0)
2991           emit_loadreg(CCREG,0);
2992         else
2993           emit_mov(HOST_CCREG,0);
2994         emit_add(0,ECX,0);
2995         emit_addimm(0,2*ccadj[i],0);
2996         emit_writeword(0,(int)&Count);
2997         #endif
2998     emit_call((int)memdebug);
2999     //emit_popa();
3000     restore_regs(0x100f);
3001   }*/
3002 }
3003
3004 #ifndef loadlr_assemble
3005 static void loadlr_assemble(int i,struct regstat *i_regs)
3006 {
3007   DebugMessage(M64MSG_ERROR, "Need loadlr_assemble for this architecture.");
3008   exit(1);
3009 }
3010 #endif
3011
3012 static void store_assemble(int i,struct regstat *i_regs)
3013 {
3014   int s,th,tl,map=-1,cache=-1;
3015   int addr,temp;
3016   int offset;
3017   int jaddr=0,jaddr2,type;
3018   int memtarget,c=0;
3019   int agr=AGEN1+(i&1);
3020   u_int hr,reglist=0;
3021   th=get_reg(i_regs->regmap,rs2[i]|64);
3022   tl=get_reg(i_regs->regmap,rs2[i]);
3023   s=get_reg(i_regs->regmap,rs1[i]);
3024   temp=get_reg(i_regs->regmap,agr);
3025   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3026   offset=imm[i];
3027   if(s>=0) {
3028     c=(i_regs->wasconst>>s)&1;
3029     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
3030     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3031   }
3032   assert(tl>=0);
3033   assert(temp>=0);
3034   for(hr=0;hr<HOST_REGS;hr++) {
3035     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3036   }
3037   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3038   if(offset||s<0||c) addr=temp;
3039   else addr=s;
3040   if(!using_tlb) {
3041     #ifdef RAM_OFFSET
3042     map=get_reg(i_regs->regmap,ROREG);
3043     if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3044     #endif
3045     if(!c) {
3046       #ifdef R29_HACK
3047       // Strmnnrmn's speed hack
3048       memtarget=1;
3049       if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
3050       #endif
3051       emit_cmpimm(addr,0x800000);
3052       #ifdef DESTRUCTIVE_SHIFT
3053       if(s==addr) emit_mov(s,temp);
3054       #endif
3055       #ifdef R29_HACK
3056       if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
3057       #endif
3058       {
3059         jaddr=(int)out;
3060         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3061         // Hint to branch predictor that the branch is unlikely to be taken
3062         if(rs1[i]>=28)
3063           emit_jno_unlikely(0);
3064         else
3065         #endif
3066         emit_jno(0);
3067       }
3068     }
3069   }else{ // using tlb
3070     int x=0;
3071     if (opcode[i]==0x28) x=3; // SB
3072     if (opcode[i]==0x29) x=2; // SH
3073     map=get_reg(i_regs->regmap,TLREG);
3074     cache=get_reg(i_regs->regmap,MMREG);
3075     assert(map>=0);
3076     reglist&=~(1<<map);
3077     map=do_tlb_w(addr,temp,map,cache,x,c,constmap[i][s]+offset);
3078     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3079   }
3080
3081   if (opcode[i]==0x28) { // SB
3082     if(!c||memtarget) {
3083       int x=0;
3084       if(!c) emit_xorimm(addr,3,temp);
3085       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3086       //gen_tlb_addr_w(temp,map);
3087       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3088       emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
3089     }
3090     type=STOREB_STUB;
3091   }
3092   if (opcode[i]==0x29) { // SH
3093     if(!c||memtarget) {
3094       int x=0;
3095       if(!c) emit_xorimm(addr,2,temp);
3096       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3097       //#ifdef
3098       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3099       //#else
3100       if(map>=0) {
3101         gen_tlb_addr_w(temp,map);
3102         emit_writehword_indexed(tl,x,temp);
3103       }else
3104         emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3105     }
3106     type=STOREH_STUB;
3107   }
3108   if (opcode[i]==0x2B) { // SW
3109     if(!c||memtarget)
3110       //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3111       emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3112     type=STOREW_STUB;
3113   }
3114   if (opcode[i]==0x3F) { // SD
3115     if(!c||memtarget) {
3116       if(rs2[i]) {
3117         assert(th>=0);
3118         //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3119         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3120         emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3121       }else{
3122         // Store zero
3123         //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3124         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3125         emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3126       }
3127     }
3128     type=STORED_STUB;
3129   }
3130   if(!using_tlb) {
3131     if(!c||memtarget) {
3132       #ifdef DESTRUCTIVE_SHIFT
3133       // The x86 shift operation is 'destructive'; it overwrites the
3134       // source register, so we need to make a copy first and use that.
3135       addr=temp;
3136       #endif
3137       #if defined(HOST_IMM8)
3138       int ir=get_reg(i_regs->regmap,INVCP);
3139       assert(ir>=0);
3140       emit_cmpmem_indexedsr12_reg(ir,addr,1);
3141       #else
3142       emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3143       #endif
3144       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3145       emit_callne(invalidate_addr_reg[addr]);
3146       #else
3147       jaddr2=(int)out;
3148       emit_jne(0);
3149       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3150       #endif
3151     }
3152   }
3153   if(jaddr) {
3154     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3155   } else if(c&&!memtarget) {
3156     inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3157   }
3158   //if(opcode[i]==0x2B || opcode[i]==0x3F)
3159   //if(opcode[i]==0x2B || opcode[i]==0x28)
3160   //if(opcode[i]==0x2B || opcode[i]==0x29)
3161   //if(opcode[i]==0x2B)
3162
3163 // Uncomment for extra debug output:
3164 /*
3165   if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3166   {
3167     #if NEW_DYNAREC == NEW_DYNAREC_X86
3168     emit_pusha();
3169     #endif
3170     #if NEW_DYNAREC == NEW_DYNAREC_ARM
3171     save_regs(0x100f);
3172     #endif
3173         emit_readword((int)&last_count,ECX);
3174         #if NEW_DYNAREC == NEW_DYNAREC_X86
3175         if(get_reg(i_regs->regmap,CCREG)<0)
3176           emit_loadreg(CCREG,HOST_CCREG);
3177         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3178         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3179         emit_writeword(HOST_CCREG,(int)&Count);
3180         #endif
3181         #if NEW_DYNAREC == NEW_DYNAREC_ARM
3182         if(get_reg(i_regs->regmap,CCREG)<0)
3183           emit_loadreg(CCREG,0);
3184         else
3185           emit_mov(HOST_CCREG,0);
3186         emit_add(0,ECX,0);
3187         emit_addimm(0,2*ccadj[i],0);
3188         emit_writeword(0,(int)&Count);
3189         #endif
3190     emit_call((int)memdebug);
3191     #if NEW_DYNAREC == NEW_DYNAREC_X86
3192     emit_popa();
3193     #endif
3194     #if NEW_DYNAREC == NEW_DYNAREC_ARM
3195     restore_regs(0x100f);
3196     #endif
3197   }
3198 */
3199 }
3200
3201 static void storelr_assemble(int i,struct regstat *i_regs)
3202 {
3203   int s,th,tl;
3204   int temp;
3205   int temp2;
3206   int offset;
3207   int jaddr=0,jaddr2;
3208   int case1,case2,case3;
3209   int done0,done1,done2;
3210   int memtarget,c=0;
3211   int agr=AGEN1+(i&1);
3212   u_int hr,reglist=0;
3213   th=get_reg(i_regs->regmap,rs2[i]|64);
3214   tl=get_reg(i_regs->regmap,rs2[i]);
3215   s=get_reg(i_regs->regmap,rs1[i]);
3216   temp=get_reg(i_regs->regmap,agr);
3217   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3218   offset=imm[i];
3219   if(s>=0) {
3220     c=(i_regs->isconst>>s)&1;
3221     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
3222     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3223   }
3224   assert(tl>=0);
3225   for(hr=0;hr<HOST_REGS;hr++) {
3226     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3227   }
3228   assert(temp>=0);
3229   if(!using_tlb) {
3230     if(!c) {
3231       emit_cmpimm(s<0||offset?temp:s,0x800000);
3232       if(!offset&&s!=temp) emit_mov(s,temp);
3233       jaddr=(int)out;
3234       emit_jno(0);
3235     }
3236     else
3237     {
3238       if(!memtarget||!rs1[i]) {
3239         jaddr=(int)out;
3240         emit_jmp(0);
3241       }
3242     }
3243     #ifdef RAM_OFFSET
3244     int map=get_reg(i_regs->regmap,ROREG);
3245     if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3246     gen_tlb_addr_w(temp,map);
3247     #else
3248     if((u_int)rdram!=0x80000000)
3249       emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3250     #endif
3251   }else{ // using tlb
3252     int map=get_reg(i_regs->regmap,TLREG);
3253     int cache=get_reg(i_regs->regmap,MMREG);
3254     assert(map>=0);
3255     reglist&=~(1<<map);
3256     map=do_tlb_w(c||s<0||offset?temp:s,temp,map,cache,0,c,constmap[i][s]+offset);
3257     if(!c&&!offset&&s>=0) emit_mov(s,temp);
3258     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3259     if(!jaddr&&!memtarget) {
3260       jaddr=(int)out;
3261       emit_jmp(0);
3262     }
3263     gen_tlb_addr_w(temp,map);
3264   }
3265
3266   if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3267     temp2=get_reg(i_regs->regmap,FTEMP);
3268     if(!rs2[i]) temp2=th=tl;
3269   }
3270
3271   emit_testimm(temp,2);
3272   case2=(int)out;
3273   emit_jne(0);
3274   emit_testimm(temp,1);
3275   case1=(int)out;
3276   emit_jne(0);
3277   // 0
3278   if (opcode[i]==0x2A) { // SWL
3279     emit_writeword_indexed(tl,0,temp);
3280   }
3281   if (opcode[i]==0x2E) { // SWR
3282     emit_writebyte_indexed(tl,3,temp);
3283   }
3284   if (opcode[i]==0x2C) { // SDL
3285     emit_writeword_indexed(th,0,temp);
3286     if(rs2[i]) emit_mov(tl,temp2);
3287   }
3288   if (opcode[i]==0x2D) { // SDR
3289     emit_writebyte_indexed(tl,3,temp);
3290     if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3291   }
3292   done0=(int)out;
3293   emit_jmp(0);
3294   // 1
3295   set_jump_target(case1,(int)out);
3296   if (opcode[i]==0x2A) { // SWL
3297     // Write 3 msb into three least significant bytes
3298     if(rs2[i]) emit_rorimm(tl,8,tl);
3299     emit_writehword_indexed(tl,-1,temp);
3300     if(rs2[i]) emit_rorimm(tl,16,tl);
3301     emit_writebyte_indexed(tl,1,temp);
3302     if(rs2[i]) emit_rorimm(tl,8,tl);
3303   }
3304   if (opcode[i]==0x2E) { // SWR
3305     // Write two lsb into two most significant bytes
3306     emit_writehword_indexed(tl,1,temp);
3307   }
3308   if (opcode[i]==0x2C) { // SDL
3309     if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3310     // Write 3 msb into three least significant bytes
3311     if(rs2[i]) emit_rorimm(th,8,th);
3312     emit_writehword_indexed(th,-1,temp);
3313     if(rs2[i]) emit_rorimm(th,16,th);
3314     emit_writebyte_indexed(th,1,temp);
3315     if(rs2[i]) emit_rorimm(th,8,th);
3316   }
3317   if (opcode[i]==0x2D) { // SDR
3318     if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3319     // Write two lsb into two most significant bytes
3320     emit_writehword_indexed(tl,1,temp);
3321   }
3322   done1=(int)out;
3323   emit_jmp(0);
3324   // 2
3325   set_jump_target(case2,(int)out);
3326   emit_testimm(temp,1);
3327   case3=(int)out;
3328   emit_jne(0);
3329   if (opcode[i]==0x2A) { // SWL
3330     // Write two msb into two least significant bytes
3331     if(rs2[i]) emit_rorimm(tl,16,tl);
3332     emit_writehword_indexed(tl,-2,temp);
3333     if(rs2[i]) emit_rorimm(tl,16,tl);
3334   }
3335   if (opcode[i]==0x2E) { // SWR
3336     // Write 3 lsb into three most significant bytes
3337     emit_writebyte_indexed(tl,-1,temp);
3338     if(rs2[i]) emit_rorimm(tl,8,tl);
3339     emit_writehword_indexed(tl,0,temp);
3340     if(rs2[i]) emit_rorimm(tl,24,tl);
3341   }
3342   if (opcode[i]==0x2C) { // SDL
3343     if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3344     // Write two msb into two least significant bytes
3345     if(rs2[i]) emit_rorimm(th,16,th);
3346     emit_writehword_indexed(th,-2,temp);
3347     if(rs2[i]) emit_rorimm(th,16,th);
3348   }
3349   if (opcode[i]==0x2D) { // SDR
3350     if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3351     // Write 3 lsb into three most significant bytes
3352     emit_writebyte_indexed(tl,-1,temp);
3353     if(rs2[i]) emit_rorimm(tl,8,tl);
3354     emit_writehword_indexed(tl,0,temp);
3355     if(rs2[i]) emit_rorimm(tl,24,tl);
3356   }
3357   done2=(int)out;
3358   emit_jmp(0);
3359   // 3
3360   set_jump_target(case3,(int)out);
3361   if (opcode[i]==0x2A) { // SWL
3362     // Write msb into least significant byte
3363     if(rs2[i]) emit_rorimm(tl,24,tl);
3364     emit_writebyte_indexed(tl,-3,temp);
3365     if(rs2[i]) emit_rorimm(tl,8,tl);
3366   }
3367   if (opcode[i]==0x2E) { // SWR
3368     // Write entire word
3369     emit_writeword_indexed(tl,-3,temp);
3370   }
3371   if (opcode[i]==0x2C) { // SDL
3372     if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3373     // Write msb into least significant byte
3374     if(rs2[i]) emit_rorimm(th,24,th);
3375     emit_writebyte_indexed(th,-3,temp);
3376     if(rs2[i]) emit_rorimm(th,8,th);
3377   }
3378   if (opcode[i]==0x2D) { // SDR
3379     if(rs2[i]) emit_mov(th,temp2);
3380     // Write entire word
3381     emit_writeword_indexed(tl,-3,temp);
3382   }
3383   set_jump_target(done0,(int)out);
3384   set_jump_target(done1,(int)out);
3385   set_jump_target(done2,(int)out);
3386   if (opcode[i]==0x2C) { // SDL
3387     emit_testimm(temp,4);
3388     done0=(int)out;
3389     emit_jne(0);
3390     emit_andimm(temp,~3,temp);
3391     emit_writeword_indexed(temp2,4,temp);
3392     set_jump_target(done0,(int)out);
3393   }
3394   if (opcode[i]==0x2D) { // SDR
3395     emit_testimm(temp,4);
3396     done0=(int)out;
3397     emit_jeq(0);
3398     emit_andimm(temp,~3,temp);
3399     emit_writeword_indexed(temp2,-4,temp);
3400     set_jump_target(done0,(int)out);
3401   }
3402   if(!c||!memtarget)
3403     add_stub(STORELR_STUB,jaddr,(int)out,0,(int)i_regs,rs2[i],ccadj[i],reglist);
3404   if(!using_tlb) {
3405     #ifdef RAM_OFFSET
3406     int map=get_reg(i_regs->regmap,ROREG);
3407     if(map<0) map=HOST_TEMPREG;
3408     gen_orig_addr_w(temp,map);
3409     #else
3410     emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3411     #endif
3412     #if defined(HOST_IMM8)
3413     int ir=get_reg(i_regs->regmap,INVCP);
3414     assert(ir>=0);
3415     emit_cmpmem_indexedsr12_reg(ir,temp,1);
3416     #else
3417     emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3418     #endif
3419     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3420     emit_callne(invalidate_addr_reg[temp]);
3421     #else
3422     jaddr2=(int)out;
3423     emit_jne(0);
3424     add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3425     #endif
3426   }
3427   /*
3428     emit_pusha();
3429     //save_regs(0x100f);
3430         emit_readword((int)&last_count,ECX);
3431         if(get_reg(i_regs->regmap,CCREG)<0)
3432           emit_loadreg(CCREG,HOST_CCREG);
3433         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3434         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3435         emit_writeword(HOST_CCREG,(int)&Count);
3436     emit_call((int)memdebug);
3437     emit_popa();
3438     //restore_regs(0x100f);
3439   */
3440 }
3441
3442 static void c1ls_assemble(int i,struct regstat *i_regs)
3443 {
3444   int s,th,tl;
3445   int temp,ar;
3446   int map=-1;
3447   int offset;
3448   int c=0;
3449   int jaddr,jaddr2=0,jaddr3,type;
3450   int agr=AGEN1+(i&1);
3451   u_int hr,reglist=0;
3452   th=get_reg(i_regs->regmap,FTEMP|64);
3453   tl=get_reg(i_regs->regmap,FTEMP);
3454   s=get_reg(i_regs->regmap,rs1[i]);
3455   temp=get_reg(i_regs->regmap,agr);
3456   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3457   offset=imm[i];
3458   assert(tl>=0);
3459   assert(rs1[i]>0);
3460   assert(temp>=0);
3461   for(hr=0;hr<HOST_REGS;hr++) {
3462     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3463   }
3464   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3465   if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3466   {
3467     // Loads use a temporary register which we need to save
3468     reglist|=1<<temp;
3469   }
3470   if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3471     ar=temp;
3472   else // LWC1/LDC1
3473     ar=tl;
3474   //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3475   //else c=(i_regs->wasconst>>s)&1;
3476   if(s>=0) c=(i_regs->wasconst>>s)&1;
3477   // Check cop1 unusable
3478   if(!cop1_usable) {
3479     signed char rs=get_reg(i_regs->regmap,CSREG);
3480     assert(rs>=0);
3481     emit_testimm(rs,0x20000000);
3482     jaddr=(int)out;
3483     emit_jeq(0);
3484     add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3485     cop1_usable=1;
3486   }
3487   if (opcode[i]==0x39) { // SWC1 (get float address)
3488     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3489   }
3490   if (opcode[i]==0x3D) { // SDC1 (get double address)
3491     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3492   }
3493   // Generate address + offset
3494   if(!using_tlb) {
3495     #ifdef RAM_OFFSET
3496     if (!c||opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3497     {
3498       map=get_reg(i_regs->regmap,ROREG);
3499       if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3500     }
3501     #endif
3502     if(!c)
3503       emit_cmpimm(offset||c||s<0?ar:s,0x800000);
3504   }
3505   else
3506   {
3507     map=get_reg(i_regs->regmap,TLREG);
3508     int cache=get_reg(i_regs->regmap,MMREG);
3509     assert(map>=0);
3510     reglist&=~(1<<map);
3511     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3512       map=do_tlb_r(offset||c||s<0?ar:s,ar,map,cache,0,-1,-1,c,constmap[i][s]+offset);
3513     }
3514     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3515       map=do_tlb_w(offset||c||s<0?ar:s,ar,map,cache,0,c,constmap[i][s]+offset);
3516     }
3517   }
3518   if (opcode[i]==0x39) { // SWC1 (read float)
3519     emit_readword_indexed(0,tl,tl);
3520   }
3521   if (opcode[i]==0x3D) { // SDC1 (read double)
3522     emit_readword_indexed(4,tl,th);
3523     emit_readword_indexed(0,tl,tl);
3524   }
3525   if (opcode[i]==0x31) { // LWC1 (get target address)
3526     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3527   }
3528   if (opcode[i]==0x35) { // LDC1 (get target address)
3529     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3530   }
3531   if(!using_tlb) {
3532     if(!c) {
3533       jaddr2=(int)out;
3534       emit_jno(0);
3535     }
3536     else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80800000) {
3537       jaddr2=(int)out;
3538       emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
3539     }
3540     #ifdef DESTRUCTIVE_SHIFT
3541     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3542       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3543     }
3544     #endif
3545   }else{
3546     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3547       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3548     }
3549     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3550       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3551     }
3552   }
3553   if (opcode[i]==0x31) { // LWC1
3554     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3555     //gen_tlb_addr_r(ar,map);
3556     //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3557     #ifdef HOST_IMM_ADDR32
3558     if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3559     else
3560     #endif
3561     emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3562     type=LOADW_STUB;
3563   }
3564   if (opcode[i]==0x35) { // LDC1
3565     assert(th>=0);
3566     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3567     //gen_tlb_addr_r(ar,map);
3568     //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3569     //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3570     #ifdef HOST_IMM_ADDR32
3571     if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3572     else
3573     #endif
3574     emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3575     type=LOADD_STUB;
3576   }
3577   if (opcode[i]==0x39) { // SWC1
3578     //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3579     emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3580     type=STOREW_STUB;
3581   }
3582   if (opcode[i]==0x3D) { // SDC1
3583     assert(th>=0);
3584     //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3585     //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3586     emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3587     type=STORED_STUB;
3588   }
3589   if(!using_tlb) {
3590     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3591       #ifndef DESTRUCTIVE_SHIFT
3592       temp=offset||c||s<0?ar:s;
3593       #endif
3594       #if defined(HOST_IMM8)
3595       int ir=get_reg(i_regs->regmap,INVCP);
3596       assert(ir>=0);
3597       emit_cmpmem_indexedsr12_reg(ir,temp,1);
3598       #else
3599       emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3600       #endif
3601       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3602       emit_callne(invalidate_addr_reg[temp]);
3603       #else
3604       jaddr3=(int)out;
3605       emit_jne(0);
3606       add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3607       #endif
3608     }
3609   }
3610   if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3611   if (opcode[i]==0x31) { // LWC1 (write float)
3612     emit_writeword_indexed(tl,0,temp);
3613   }
3614   if (opcode[i]==0x35) { // LDC1 (write double)
3615     emit_writeword_indexed(th,4,temp);
3616     emit_writeword_indexed(tl,0,temp);
3617   }
3618   //if(opcode[i]==0x39)
3619   /*if(opcode[i]==0x39||opcode[i]==0x31)
3620   {
3621     emit_pusha();
3622         emit_readword((int)&last_count,ECX);
3623         if(get_reg(i_regs->regmap,CCREG)<0)
3624           emit_loadreg(CCREG,HOST_CCREG);
3625         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3626         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3627         emit_writeword(HOST_CCREG,(int)&Count);
3628     emit_call((int)memdebug);
3629     emit_popa();
3630   }*/
3631 }
3632
3633 #ifndef multdiv_assemble
3634 void multdiv_assemble(int i,struct regstat *i_regs)
3635 {
3636   DebugMessage(M64MSG_ERROR, "Need multdiv_assemble for this architecture.");
3637   exit(1);
3638 }
3639 #endif
3640
3641 static void mov_assemble(int i,struct regstat *i_regs)
3642 {
3643   //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3644   //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3645   if(rt1[i]) {
3646     signed char sh,sl,th,tl;
3647     th=get_reg(i_regs->regmap,rt1[i]|64);
3648     tl=get_reg(i_regs->regmap,rt1[i]);
3649     //assert(tl>=0);
3650     if(tl>=0) {
3651       sh=get_reg(i_regs->regmap,rs1[i]|64);
3652       sl=get_reg(i_regs->regmap,rs1[i]);
3653       if(sl>=0) emit_mov(sl,tl);
3654       else emit_loadreg(rs1[i],tl);
3655       if(th>=0) {
3656         if(sh>=0) emit_mov(sh,th);
3657         else emit_loadreg(rs1[i]|64,th);
3658       }
3659     }
3660   }
3661 }
3662
3663 #ifndef fconv_assemble
3664 void fconv_assemble(int i,struct regstat *i_regs)
3665 {
3666   DebugMessage(M64MSG_ERROR, "Need fconv_assemble for this architecture.");
3667   exit(1);
3668 }
3669 #endif
3670
3671 #if 0
3672 static void float_assemble(int i,struct regstat *i_regs)
3673 {
3674   DebugMessage(M64MSG_ERROR, "Need float_assemble for this architecture.");
3675   exit(1);
3676 }
3677 #endif
3678
3679 static void syscall_assemble(int i,struct regstat *i_regs)
3680 {
3681   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3682   assert(ccreg==HOST_CCREG);
3683   assert(!is_delayslot);
3684   emit_movimm(start+i*4,EAX); // Get PC
3685   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right?  There should probably be an extra cycle...
3686   emit_jmp((int)jump_syscall);
3687 }
3688
3689 static void ds_assemble(int i,struct regstat *i_regs)
3690 {
3691   is_delayslot=1;
3692   switch(itype[i]) {
3693     case ALU:
3694       alu_assemble(i,i_regs);break;
3695     case IMM16:
3696       imm16_assemble(i,i_regs);break;
3697     case SHIFT:
3698       shift_assemble(i,i_regs);break;
3699     case SHIFTIMM:
3700       shiftimm_assemble(i,i_regs);break;
3701     case LOAD:
3702       load_assemble(i,i_regs);break;
3703     case LOADLR:
3704       loadlr_assemble(i,i_regs);break;
3705     case STORE:
3706       store_assemble(i,i_regs);break;
3707     case STORELR:
3708       storelr_assemble(i,i_regs);break;
3709     case COP0:
3710       cop0_assemble(i,i_regs);break;
3711     case COP1:
3712       cop1_assemble(i,i_regs);break;
3713     case C1LS:
3714       c1ls_assemble(i,i_regs);break;
3715     case FCONV:
3716       fconv_assemble(i,i_regs);break;
3717     case FLOAT:
3718       float_assemble(i,i_regs);break;
3719     case FCOMP:
3720       fcomp_assemble(i,i_regs);break;
3721     case MULTDIV:
3722       multdiv_assemble(i,i_regs);break;
3723     case MOV:
3724       mov_assemble(i,i_regs);break;
3725     case SYSCALL:
3726     case SPAN:
3727     case UJUMP:
3728     case RJUMP:
3729     case CJUMP:
3730     case SJUMP:
3731     case FJUMP:
3732       DebugMessage(M64MSG_VERBOSE, "Jump in the delay slot.  This is probably a bug.");
3733   }
3734   is_delayslot=0;
3735 }
3736
3737 // Is the branch target a valid internal jump?
3738 static int internal_branch(uint64_t i_is32,int addr)
3739 {
3740   if(addr&1) return 0; // Indirect (register) jump
3741   if(addr>=start && addr<start+slen*4-4)
3742   {
3743     int t=(addr-start)>>2;
3744     // Delay slots are not valid branch targets
3745     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3746     // 64 -> 32 bit transition requires a recompile
3747     /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3748     {
3749       if(requires_32bit[t]&~i_is32) DebugMessage(M64MSG_VERBOSE, "optimizable: no");
3750       else DebugMessage(M64MSG_VERBOSE, "optimizable: yes");
3751     }*/
3752     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3753     if(requires_32bit[t]&~i_is32) return 0;
3754     else return 1;
3755   }
3756   return 0;
3757 }
3758
3759 #ifndef wb_invalidate
3760 static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3761   uint64_t u,uint64_t uu)
3762 {
3763   int hr;
3764   for(hr=0;hr<HOST_REGS;hr++) {
3765     if(hr!=EXCLUDE_REG) {
3766       if(pre[hr]!=entry[hr]) {
3767         if(pre[hr]>=0) {
3768           if((dirty>>hr)&1) {
3769             if(get_reg(entry,pre[hr])<0) {
3770               if(pre[hr]<64) {
3771                 if(!((u>>pre[hr])&1)) {
3772                   emit_storereg(pre[hr],hr);
3773                   if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3774                     emit_sarimm(hr,31,hr);
3775                     emit_storereg(pre[hr]|64,hr);
3776                   }
3777                 }
3778               }else{
3779                 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3780                   emit_storereg(pre[hr],hr);
3781                 }
3782               }
3783             }
3784           }
3785         }
3786       }
3787     }
3788   }
3789   // Move from one register to another (no writeback)
3790   for(hr=0;hr<HOST_REGS;hr++) {
3791     if(hr!=EXCLUDE_REG) {
3792       if(pre[hr]!=entry[hr]) {
3793         if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3794           int nr;
3795           if((nr=get_reg(entry,pre[hr]))>=0) {
3796             emit_mov(hr,nr);
3797           }
3798         }
3799       }
3800     }
3801   }
3802 }
3803 #endif
3804
3805 // Load the specified registers
3806 // This only loads the registers given as arguments because
3807 // we don't want to load things that will be overwritten
3808 static void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3809 {
3810   int hr;
3811   // Load 32-bit regs
3812   for(hr=0;hr<HOST_REGS;hr++) {
3813     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3814       if(entry[hr]!=regmap[hr]) {
3815         if(regmap[hr]==rs1||regmap[hr]==rs2)
3816         {
3817           if(regmap[hr]==0) {
3818             emit_zeroreg(hr);
3819           }
3820           else
3821           {
3822             emit_loadreg(regmap[hr],hr);
3823           }
3824         }
3825       }
3826     }
3827   }
3828   //Load 64-bit regs
3829   for(hr=0;hr<HOST_REGS;hr++) {
3830     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3831       if(entry[hr]!=regmap[hr]) {
3832         if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
3833         {
3834           assert(regmap[hr]!=64);
3835           if((is32>>(regmap[hr]&63))&1) {
3836             int lr=get_reg(regmap,regmap[hr]-64);
3837             if(lr>=0)
3838               emit_sarimm(lr,31,hr);
3839             else
3840               emit_loadreg(regmap[hr],hr);
3841           }
3842           else
3843           {
3844             emit_loadreg(regmap[hr],hr);
3845           }
3846         }
3847       }
3848     }
3849   }
3850 }
3851
3852 // Load registers prior to the start of a loop
3853 // so that they are not loaded within the loop
3854 static void loop_preload(signed char pre[],signed char entry[])
3855 {
3856   int hr;
3857   for(hr=0;hr<HOST_REGS;hr++) {
3858     if(hr!=EXCLUDE_REG) {
3859       if(pre[hr]!=entry[hr]) {
3860         if(entry[hr]>=0) {
3861           if(get_reg(pre,entry[hr])<0) {
3862             assem_debug("loop preload:");
3863             //DebugMessage(M64MSG_VERBOSE, "loop preload: %d",hr);
3864             if(entry[hr]==0) {
3865               emit_zeroreg(hr);
3866             }
3867             else if(entry[hr]<TEMPREG)
3868             {
3869               emit_loadreg(entry[hr],hr);
3870             }
3871             else if(entry[hr]-64<TEMPREG)
3872             {
3873               emit_loadreg(entry[hr],hr);
3874             }
3875           }
3876         }
3877       }
3878     }
3879   }
3880 }
3881
3882 // Generate address for load/store instruction
3883 static void address_generation(int i,struct regstat *i_regs,signed char entry[])
3884 {
3885   if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
3886     int ra;
3887     int agr=AGEN1+(i&1);
3888     int mgr=MGEN1+(i&1);
3889     if(itype[i]==LOAD) {
3890       ra=get_reg(i_regs->regmap,rt1[i]);
3891       if(ra<0) ra=get_reg(i_regs->regmap,-1);
3892       assert(ra>=0);
3893     }
3894     if(itype[i]==LOADLR) {
3895       ra=get_reg(i_regs->regmap,FTEMP);
3896     }
3897     if(itype[i]==STORE||itype[i]==STORELR) {
3898       ra=get_reg(i_regs->regmap,agr);
3899       if(ra<0) ra=get_reg(i_regs->regmap,-1);
3900     }
3901     if(itype[i]==C1LS) {
3902       if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3903         ra=get_reg(i_regs->regmap,FTEMP);
3904       else { // SWC1/SDC1
3905         ra=get_reg(i_regs->regmap,agr);
3906         if(ra<0) ra=get_reg(i_regs->regmap,-1);
3907       }
3908     }
3909     int rs=get_reg(i_regs->regmap,rs1[i]);
3910     int rm=get_reg(i_regs->regmap,TLREG);
3911     if(ra>=0) {
3912       int offset=imm[i];
3913       int c=(i_regs->wasconst>>rs)&1;
3914       if(rs1[i]==0) {
3915         // Using r0 as a base address
3916         /*if(rm>=0) {
3917           if(!entry||entry[rm]!=mgr) {
3918             generate_map_const(offset,rm);
3919           } // else did it in the previous cycle
3920         }*/
3921         if(!entry||entry[ra]!=agr) {
3922           if (opcode[i]==0x22||opcode[i]==0x26) {
3923             emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
3924           }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3925             emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
3926           }else{
3927             emit_movimm(offset,ra);
3928           }
3929         } // else did it in the previous cycle
3930       }
3931       else if(rs<0) {
3932         if(!entry||entry[ra]!=rs1[i])
3933           emit_loadreg(rs1[i],ra);
3934         //if(!entry||entry[ra]!=rs1[i])
3935         //  DebugMessage(M64MSG_VERBOSE, "poor load scheduling!");
3936       }
3937       else if(c) {
3938         if(rm>=0) {
3939           if(!entry||entry[rm]!=mgr) {
3940             if(itype[i]==STORE||itype[i]==STORELR||opcode[i]==0x39||opcode[i]==0x3D) {
3941               // Stores to memory go thru the mapper to detect self-modifying
3942               // code, loads don't.
3943               if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
3944                  (unsigned int)(constmap[i][rs]+offset)<0x80800000 )
3945                 generate_map_const(constmap[i][rs]+offset,rm);
3946             }else{
3947               if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
3948                 generate_map_const(constmap[i][rs]+offset,rm);
3949             }
3950           }
3951         }
3952         if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
3953           if(!entry||entry[ra]!=agr) {
3954             if (opcode[i]==0x22||opcode[i]==0x26) { // LWL/LWR
3955               #ifdef RAM_OFFSET
3956               if((signed int)constmap[i][rs]+offset<(signed int)0x80800000)
3957                 emit_movimm(((constmap[i][rs]+offset)&0xFFFFFFFC)+(int)rdram-0x80000000,ra);
3958               else
3959               #endif
3960               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra);
3961             }else if (opcode[i]==0x1a||opcode[i]==0x1b) { // LDL/LDR
3962               #ifdef RAM_OFFSET
3963               if((signed int)constmap[i][rs]+offset<(signed int)0x80800000)
3964                 emit_movimm(((constmap[i][rs]+offset)&0xFFFFFFF8)+(int)rdram-0x80000000,ra);
3965               else
3966               #endif
3967               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra);
3968             }else{
3969               #ifdef HOST_IMM_ADDR32
3970               if((itype[i]!=LOAD&&opcode[i]!=0x31&&opcode[i]!=0x35) ||
3971                  (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
3972               #endif
3973               #ifdef RAM_OFFSET
3974               if((itype[i]==LOAD||opcode[i]==0x31||opcode[i]==0x35)&&(signed int)constmap[i][rs]+offset<(signed int)0x80800000)
3975                 emit_movimm(constmap[i][rs]+offset+(int)rdram-0x80000000,ra);
3976               else
3977               #endif
3978               emit_movimm(constmap[i][rs]+offset,ra);
3979             }
3980           } // else did it in the previous cycle
3981         } // else load_consts already did it
3982       }
3983       if(offset&&!c&&rs1[i]) {
3984         if(rs>=0) {
3985           emit_addimm(rs,offset,ra);
3986         }else{
3987           emit_addimm(ra,offset,ra);
3988         }
3989       }
3990     }
3991   }
3992   // Preload constants for next instruction
3993   if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS) {
3994     int agr,ra;
3995     #ifndef HOST_IMM_ADDR32
3996     // Mapper entry
3997     agr=MGEN1+((i+1)&1);
3998     ra=get_reg(i_regs->regmap,agr);
3999     if(ra>=0) {
4000       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4001       int offset=imm[i+1];
4002       int c=(regs[i+1].wasconst>>rs)&1;
4003       if(c) {
4004         if(itype[i+1]==STORE||itype[i+1]==STORELR||opcode[i+1]==0x39||opcode[i+1]==0x3D) {
4005           // Stores to memory go thru the mapper to detect self-modifying
4006           // code, loads don't.
4007           if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4008              (unsigned int)(constmap[i+1][rs]+offset)<0x80800000 )
4009             generate_map_const(constmap[i+1][rs]+offset,ra);
4010         }else{
4011           if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4012             generate_map_const(constmap[i+1][rs]+offset,ra);
4013         }
4014       }
4015       /*else if(rs1[i]==0) {
4016         generate_map_const(offset,ra);
4017       }*/
4018     }
4019     #endif
4020     // Actual address
4021     agr=AGEN1+((i+1)&1);
4022     ra=get_reg(i_regs->regmap,agr);
4023     if(ra>=0) {
4024       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4025       int offset=imm[i+1];
4026       int c=(regs[i+1].wasconst>>rs)&1;
4027       if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4028         if (opcode[i+1]==0x22||opcode[i+1]==0x26) { // LWL/LWR
4029           #ifdef RAM_OFFSET
4030           if((signed int)constmap[i+1][rs]+offset<(signed int)0x80800000)
4031             emit_movimm(((constmap[i+1][rs]+offset)&0xFFFFFFFC)+(int)rdram-0x80000000,ra);
4032           else
4033           #endif
4034           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra);
4035         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) { // LDL/LDR
4036           #ifdef RAM_OFFSET
4037           if((signed int)constmap[i+1][rs]+offset<(signed int)0x80800000)
4038             emit_movimm(((constmap[i+1][rs]+offset)&0xFFFFFFF8)+(int)rdram-0x80000000,ra);
4039           else
4040           #endif
4041           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra);
4042         }else{
4043           #ifdef HOST_IMM_ADDR32
4044           if((itype[i+1]!=LOAD&&opcode[i+1]!=0x31&&opcode[i+1]!=0x35) ||
4045              (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4046           #endif
4047           #ifdef RAM_OFFSET
4048           if((itype[i+1]==LOAD||opcode[i+1]==0x31||opcode[i+1]==0x35)&&(signed int)constmap[i+1][rs]+offset<(signed int)0x80800000)
4049             emit_movimm(constmap[i+1][rs]+offset+(int)rdram-0x80000000,ra);
4050           else
4051           #endif
4052           emit_movimm(constmap[i+1][rs]+offset,ra);
4053         }
4054       }
4055       else if(rs1[i+1]==0) {
4056         // Using r0 as a base address
4057         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4058           emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4059         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4060           emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4061         }else{
4062           emit_movimm(offset,ra);
4063         }
4064       }
4065     }
4066   }
4067 }
4068
4069 static int get_final_value(int hr, int i, int *value)
4070 {
4071   int reg=regs[i].regmap[hr];
4072   while(i<slen-1) {
4073     if(regs[i+1].regmap[hr]!=reg) break;
4074     if(!((regs[i+1].isconst>>hr)&1)) break;
4075     if(bt[i+1]) break;
4076     i++;
4077   }
4078   if(i<slen-1) {
4079     if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4080       *value=constmap[i][hr];
4081       return 1;
4082     }
4083     if(!bt[i+1]) {
4084       if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4085         // Load in delay slot, out-of-order execution
4086         if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4087         {
4088           #ifdef HOST_IMM_ADDR32
4089           if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4090           #endif
4091           #ifdef RAM_OFFSET
4092           if((signed int)constmap[i][hr]+imm[i+2]<(signed int)0x80800000)
4093             *value=constmap[i][hr]+imm[i+2]+(int)rdram-0x80000000;
4094           else
4095           #endif
4096           // Precompute load address
4097           *value=constmap[i][hr]+imm[i+2];
4098           return 1;
4099         }
4100       }
4101       if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4102       {
4103         #ifdef HOST_IMM_ADDR32
4104         if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4105         #endif
4106         #ifdef RAM_OFFSET
4107         if((signed int)constmap[i][hr]+imm[i+1]<(signed int)0x80800000)
4108           *value=constmap[i][hr]+imm[i+1]+(int)rdram-0x80000000;
4109         else
4110         #endif
4111         // Precompute load address
4112         *value=constmap[i][hr]+imm[i+1];
4113         //DebugMessage(M64MSG_VERBOSE, "c=%x imm=%x",(int)constmap[i][hr],imm[i+1]);
4114         return 1;
4115       }
4116     }
4117   }
4118   *value=constmap[i][hr];
4119   //DebugMessage(M64MSG_VERBOSE, "c=%x",(int)constmap[i][hr]);
4120   if(i==slen-1) return 1;
4121   if(reg<64) {
4122     return !((unneeded_reg[i+1]>>reg)&1);
4123   }else{
4124     return !((unneeded_reg_upper[i+1]>>reg)&1);
4125   }
4126 }
4127
4128 // Load registers with known constants
4129 static void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4130 {
4131   int hr;
4132   // Load 32-bit regs
4133   for(hr=0;hr<HOST_REGS;hr++) {
4134     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4135       //if(entry[hr]!=regmap[hr]) {
4136       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4137         if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4138           int value;
4139           if(get_final_value(hr,i,&value)) {
4140             if(value==0) {
4141               emit_zeroreg(hr);
4142             }
4143             else {
4144               emit_movimm(value,hr);
4145             }
4146           }
4147         }
4148       }
4149     }
4150   }
4151   // Load 64-bit regs
4152   for(hr=0;hr<HOST_REGS;hr++) {
4153     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4154       //if(entry[hr]!=regmap[hr]) {
4155       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4156         if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4157           if((is32>>(regmap[hr]&63))&1) {
4158             int lr=get_reg(regmap,regmap[hr]-64);
4159             assert(lr>=0);
4160             emit_sarimm(lr,31,hr);
4161           }
4162           else
4163           {
4164             int value;
4165             if(get_final_value(hr,i,&value)) {
4166               if(value==0) {
4167                 emit_zeroreg(hr);
4168               }
4169               else {
4170                 emit_movimm(value,hr);
4171               }
4172             }
4173           }
4174         }
4175       }
4176     }
4177   }
4178 }
4179 static void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4180 {
4181   int hr;
4182   // Load 32-bit regs
4183   for(hr=0;hr<HOST_REGS;hr++) {
4184     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4185       if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4186         int value=constmap[i][hr];
4187         if(value==0) {
4188           emit_zeroreg(hr);
4189         }
4190         else {
4191           emit_movimm(value,hr);
4192         }
4193       }
4194     }
4195   }
4196   // Load 64-bit regs
4197   for(hr=0;hr<HOST_REGS;hr++) {
4198     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4199       if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4200         if((is32>>(regmap[hr]&63))&1) {
4201           int lr=get_reg(regmap,regmap[hr]-64);
4202           assert(lr>=0);
4203           emit_sarimm(lr,31,hr);
4204         }
4205         else
4206         {
4207           int value=constmap[i][hr];
4208           if(value==0) {
4209             emit_zeroreg(hr);
4210           }
4211           else {
4212             emit_movimm(value,hr);
4213           }
4214         }
4215       }
4216     }
4217   }
4218 }
4219
4220 // Write out all dirty registers (except cycle count)
4221 static void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4222 {
4223   int hr;
4224   for(hr=0;hr<HOST_REGS;hr++) {
4225     if(hr!=EXCLUDE_REG) {
4226       if(i_regmap[hr]>0) {
4227         if(i_regmap[hr]!=CCREG) {
4228           if((i_dirty>>hr)&1) {
4229             if(i_regmap[hr]<64) {
4230               emit_storereg(i_regmap[hr],hr);
4231               if( ((i_is32>>i_regmap[hr])&1) ) {
4232                 #ifdef DESTRUCTIVE_WRITEBACK
4233                 emit_sarimm(hr,31,hr);
4234                 emit_storereg(i_regmap[hr]|64,hr);
4235                 #else
4236                 emit_sarimm(hr,31,HOST_TEMPREG);
4237                 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4238                 #endif
4239               }
4240             }else{
4241               if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4242                 emit_storereg(i_regmap[hr],hr);
4243               }
4244             }
4245           }
4246         }
4247       }
4248     }
4249   }
4250 }
4251 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4252 // This writes the registers not written by store_regs_bt
4253 static void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4254 {
4255   int hr;
4256   int t=(addr-start)>>2;
4257   for(hr=0;hr<HOST_REGS;hr++) {
4258     if(hr!=EXCLUDE_REG) {
4259       if(i_regmap[hr]>0) {
4260         if(i_regmap[hr]!=CCREG) {
4261           if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4262             if((i_dirty>>hr)&1) {
4263               if(i_regmap[hr]<64) {
4264                 emit_storereg(i_regmap[hr],hr);
4265                 if( ((i_is32>>i_regmap[hr])&1) ) {
4266                   #ifdef DESTRUCTIVE_WRITEBACK
4267                   emit_sarimm(hr,31,hr);
4268                   emit_storereg(i_regmap[hr]|64,hr);
4269                   #else
4270                   emit_sarimm(hr,31,HOST_TEMPREG);
4271                   emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4272                   #endif
4273                 }
4274               }else{
4275                 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4276                   emit_storereg(i_regmap[hr],hr);
4277                 }
4278               }
4279             }
4280           }
4281         }
4282       }
4283     }
4284   }
4285 }
4286
4287 // Load all registers (except cycle count)
4288 static void load_all_regs(signed char i_regmap[])
4289 {
4290   int hr;
4291   for(hr=0;hr<HOST_REGS;hr++) {
4292     if(hr!=EXCLUDE_REG) {
4293       if(i_regmap[hr]==0) {
4294         emit_zeroreg(hr);
4295       }
4296       else
4297       if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4298       {
4299         emit_loadreg(i_regmap[hr],hr);
4300       }
4301     }
4302   }
4303 }
4304
4305 // Load all current registers also needed by next instruction
4306 static void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4307 {
4308   int hr;
4309   for(hr=0;hr<HOST_REGS;hr++) {
4310     if(hr!=EXCLUDE_REG) {
4311       if(get_reg(next_regmap,i_regmap[hr])>=0) {
4312         if(i_regmap[hr]==0) {
4313           emit_zeroreg(hr);
4314         }
4315         else
4316         if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4317         {
4318           emit_loadreg(i_regmap[hr],hr);
4319         }
4320       }
4321     }
4322   }
4323 }
4324
4325 // Load all regs, storing cycle count if necessary
4326 static void load_regs_entry(int t)
4327 {
4328   int hr;
4329   if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4330   else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4331   if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4332     emit_storereg(CCREG,HOST_CCREG);
4333   }
4334   // Load 32-bit regs
4335   for(hr=0;hr<HOST_REGS;hr++) {
4336     if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4337       if(regs[t].regmap_entry[hr]==0) {
4338         emit_zeroreg(hr);
4339       }
4340       else if(regs[t].regmap_entry[hr]!=CCREG)
4341       {
4342         emit_loadreg(regs[t].regmap_entry[hr],hr);
4343       }
4344     }
4345   }
4346   // Load 64-bit regs
4347   for(hr=0;hr<HOST_REGS;hr++) {
4348     if(regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
4349       assert(regs[t].regmap_entry[hr]!=64);
4350       if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4351         int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4352         if(lr<0) {
4353           emit_loadreg(regs[t].regmap_entry[hr],hr);
4354         }
4355         else
4356         {
4357           emit_sarimm(lr,31,hr);
4358         }
4359       }
4360       else
4361       {
4362         emit_loadreg(regs[t].regmap_entry[hr],hr);
4363       }
4364     }
4365   }
4366 }
4367
4368 // Store dirty registers prior to branch
4369 static void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4370 {
4371   if(internal_branch(i_is32,addr))
4372   {
4373     int t=(addr-start)>>2;
4374     int hr;
4375     for(hr=0;hr<HOST_REGS;hr++) {
4376       if(hr!=EXCLUDE_REG) {
4377         if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4378           if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4379             if((i_dirty>>hr)&1) {
4380               if(i_regmap[hr]<64) {
4381                 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4382                   emit_storereg(i_regmap[hr],hr);
4383                   if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4384                     #ifdef DESTRUCTIVE_WRITEBACK
4385                     emit_sarimm(hr,31,hr);
4386                     emit_storereg(i_regmap[hr]|64,hr);
4387                     #else
4388                     emit_sarimm(hr,31,HOST_TEMPREG);
4389                     emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4390                     #endif
4391                   }
4392                 }
4393               }else{
4394                 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4395                   emit_storereg(i_regmap[hr],hr);
4396                 }
4397               }
4398             }
4399           }
4400         }
4401       }
4402     }
4403   }
4404   else
4405   {
4406     // Branch out of this block, write out all dirty regs
4407     wb_dirtys(i_regmap,i_is32,i_dirty);
4408   }
4409 }
4410
4411 // Load all needed registers for branch target
4412 static void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4413 {
4414   //if(addr>=start && addr<(start+slen*4))
4415   if(internal_branch(i_is32,addr))
4416   {
4417     int t=(addr-start)>>2;
4418     int hr;
4419     // Store the cycle count before loading something else
4420     if(i_regmap[HOST_CCREG]!=CCREG) {
4421       assert(i_regmap[HOST_CCREG]==-1);
4422     }
4423     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4424       emit_storereg(CCREG,HOST_CCREG);
4425     }
4426     // Load 32-bit regs
4427     for(hr=0;hr<HOST_REGS;hr++) {
4428       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4429         #ifdef DESTRUCTIVE_WRITEBACK
4430         if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4431         #else
4432         if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4433         #endif
4434           if(regs[t].regmap_entry[hr]==0) {
4435             emit_zeroreg(hr);
4436           }
4437           else if(regs[t].regmap_entry[hr]!=CCREG)
4438           {
4439             emit_loadreg(regs[t].regmap_entry[hr],hr);
4440           }
4441         }
4442       }
4443     }
4444     //Load 64-bit regs
4445     for(hr=0;hr<HOST_REGS;hr++) {
4446       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
4447         if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4448           assert(regs[t].regmap_entry[hr]!=64);
4449           if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4450             int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4451             if(lr<0) {
4452               emit_loadreg(regs[t].regmap_entry[hr],hr);
4453             }
4454             else
4455             {
4456               emit_sarimm(lr,31,hr);
4457             }
4458           }
4459           else
4460           {
4461             emit_loadreg(regs[t].regmap_entry[hr],hr);
4462           }
4463         }
4464         else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4465           int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4466           assert(lr>=0);
4467           emit_sarimm(lr,31,hr);
4468         }
4469       }
4470     }
4471   }
4472 }
4473
4474 static int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4475 {
4476   if(addr>=start && addr<start+slen*4-4)
4477   {
4478     int t=(addr-start)>>2;
4479     int hr;
4480     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4481     for(hr=0;hr<HOST_REGS;hr++)
4482     {
4483       if(hr!=EXCLUDE_REG)
4484       {
4485         if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4486         {
4487           if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4488           {
4489             return 0;
4490           }
4491           else
4492           if((i_dirty>>hr)&1)
4493           {
4494             if(i_regmap[hr]<TEMPREG)
4495             {
4496               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4497                 return 0;
4498             }
4499             else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4500             {
4501               if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4502                 return 0;
4503             }
4504           }
4505         }
4506         else // Same register but is it 32-bit or dirty?
4507         if(i_regmap[hr]>=0)
4508         {
4509           if(!((regs[t].dirty>>hr)&1))
4510           {
4511             if((i_dirty>>hr)&1)
4512             {
4513               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4514               {
4515                 //DebugMessage(M64MSG_VERBOSE, "%x: dirty no match",addr);
4516                 return 0;
4517               }
4518             }
4519           }
4520           if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4521           {
4522             //DebugMessage(M64MSG_VERBOSE, "%x: is32 no match",addr);
4523             return 0;
4524           }
4525         }
4526       }
4527     }
4528     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4529     if(requires_32bit[t]&~i_is32) return 0;
4530     // Delay slots are not valid branch targets
4531     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4532     // Delay slots require additional processing, so do not match
4533     if(is_ds[t]) return 0;
4534   }
4535   else
4536   {
4537     int hr;
4538     for(hr=0;hr<HOST_REGS;hr++)
4539     {
4540       if(hr!=EXCLUDE_REG)
4541       {
4542         if(i_regmap[hr]>=0)
4543         {
4544           if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4545           {
4546             if((i_dirty>>hr)&1)
4547             {
4548               return 0;
4549             }
4550           }
4551         }
4552       }
4553     }
4554   }
4555   return 1;
4556 }
4557
4558 // Used when a branch jumps into the delay slot of another branch
4559 static void ds_assemble_entry(int i)
4560 {
4561   int t=(ba[i]-start)>>2;
4562   if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4563   assem_debug("Assemble delay slot at %x",ba[i]);
4564   assem_debug("<->");
4565   if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4566     wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4567   load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4568   address_generation(t,&regs[t],regs[t].regmap_entry);
4569   if(itype[t]==LOAD||itype[t]==LOADLR||itype[t]==STORE||itype[t]==STORELR||itype[t]==C1LS)
4570     load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,MMREG,ROREG);
4571   if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39)
4572     load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4573   cop1_usable=0;
4574   is_delayslot=0;
4575   switch(itype[t]) {
4576     case ALU:
4577       alu_assemble(t,&regs[t]);break;
4578     case IMM16:
4579       imm16_assemble(t,&regs[t]);break;
4580     case SHIFT:
4581       shift_assemble(t,&regs[t]);break;
4582     case SHIFTIMM:
4583       shiftimm_assemble(t,&regs[t]);break;
4584     case LOAD:
4585       load_assemble(t,&regs[t]);break;
4586     case LOADLR:
4587       loadlr_assemble(t,&regs[t]);break;
4588     case STORE:
4589       store_assemble(t,&regs[t]);break;
4590     case STORELR:
4591       storelr_assemble(t,&regs[t]);break;
4592     case COP0:
4593       cop0_assemble(t,&regs[t]);break;
4594     case COP1:
4595       cop1_assemble(t,&regs[t]);break;
4596     case C1LS:
4597       c1ls_assemble(t,&regs[t]);break;
4598     case FCONV:
4599       fconv_assemble(t,&regs[t]);break;
4600     case FLOAT:
4601       float_assemble(t,&regs[t]);break;
4602     case FCOMP:
4603       fcomp_assemble(t,&regs[t]);break;
4604     case MULTDIV:
4605       multdiv_assemble(t,&regs[t]);break;
4606     case MOV:
4607       mov_assemble(t,&regs[t]);break;
4608     case SYSCALL:
4609     case SPAN:
4610     case UJUMP:
4611     case RJUMP:
4612     case CJUMP:
4613     case SJUMP:
4614     case FJUMP:
4615       DebugMessage(M64MSG_VERBOSE, "Jump in the delay slot.  This is probably a bug.");
4616   }
4617   store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4618   load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4619   if(internal_branch(regs[t].is32,ba[i]+4))
4620     assem_debug("branch: internal");
4621   else
4622     assem_debug("branch: external");
4623   assert(internal_branch(regs[t].is32,ba[i]+4));
4624   add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4625   emit_jmp(0);
4626 }
4627
4628 static void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4629 {
4630   int count;
4631   int jaddr;
4632   int idle=0;
4633   if(itype[i]==RJUMP)
4634   {
4635     *adj=0;
4636   }
4637   //if(ba[i]>=start && ba[i]<(start+slen*4))
4638   if(internal_branch(branch_regs[i].is32,ba[i]))
4639   {
4640     int t=(ba[i]-start)>>2;
4641     if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4642     else *adj=ccadj[t];
4643   }
4644   else
4645   {
4646     *adj=0;
4647   }
4648   count=ccadj[i];
4649   if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4650     // Idle loop
4651     if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4652     idle=(int)out;
4653     //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4654     emit_andimm(HOST_CCREG,3,HOST_CCREG);
4655     jaddr=(int)out;
4656     emit_jmp(0);
4657   }
4658   else if(*adj==0||invert) {
4659     emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4660     jaddr=(int)out;
4661     emit_jns(0);
4662   }
4663   else
4664   {
4665     emit_cmpimm(HOST_CCREG,-CLOCK_DIVIDER*(count+2));
4666     jaddr=(int)out;
4667     emit_jns(0);
4668   }
4669   add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4670 }
4671
4672 static void do_ccstub(int n)
4673 {
4674   literal_pool(256);
4675   assem_debug("do_ccstub %x",start+stubs[n][4]*4);
4676   set_jump_target(stubs[n][1],(int)out);
4677   int i=stubs[n][4];
4678   if(stubs[n][6]==NULLDS) {
4679     // Delay slot instruction is nullified ("likely" branch)
4680     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4681   }
4682   else if(stubs[n][6]!=TAKEN) {
4683     wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4684   }
4685   else {
4686     if(internal_branch(branch_regs[i].is32,ba[i]))
4687       wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4688   }
4689   if(stubs[n][5]!=-1)
4690   {
4691     // Save PC as return address
4692     emit_movimm(stubs[n][5],EAX);
4693     emit_writeword(EAX,(int)&pcaddr);
4694   }
4695   else
4696   {
4697     // Return address depends on which way the branch goes
4698     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4699     {
4700       int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4701       int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4702       int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4703       int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4704       if(rs1[i]==0)
4705       {
4706         s1l=s2l;s1h=s2h;
4707         s2l=s2h=-1;
4708       }
4709       else if(rs2[i]==0)
4710       {
4711         s2l=s2h=-1;
4712       }
4713       if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4714         s1h=s2h=-1;
4715       }
4716       assert(s1l>=0);
4717       #ifdef DESTRUCTIVE_WRITEBACK
4718       if(rs1[i]) {
4719         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4720           emit_loadreg(rs1[i],s1l);
4721       }
4722       else {
4723         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4724           emit_loadreg(rs2[i],s1l);
4725       }
4726       if(s2l>=0)
4727         if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4728           emit_loadreg(rs2[i],s2l);
4729       #endif
4730       int hr=0;
4731       int addr,alt,ntaddr;
4732       while(hr<HOST_REGS)
4733       {
4734         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4735            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4736            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4737         {
4738           addr=hr++;break;
4739         }
4740         hr++;
4741       }
4742       while(hr<HOST_REGS)
4743       {
4744         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4745            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4746            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4747         {
4748           alt=hr++;break;
4749         }
4750         hr++;
4751       }
4752       if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4753       {
4754         while(hr<HOST_REGS)
4755         {
4756           if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4757              (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4758              (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4759           {
4760             ntaddr=hr;break;
4761           }
4762           hr++;
4763         }
4764         assert(hr<HOST_REGS);
4765       }
4766       if((opcode[i]&0x2f)==4) // BEQ
4767       {
4768         #ifdef HAVE_CMOV_IMM
4769         if(s1h<0) {
4770           if(s2l>=0) emit_cmp(s1l,s2l);
4771           else emit_test(s1l,s1l);
4772           emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4773         }
4774         else
4775         #endif
4776         {
4777           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4778           if(s1h>=0) {
4779             if(s2h>=0) emit_cmp(s1h,s2h);
4780             else emit_test(s1h,s1h);
4781             emit_cmovne_reg(alt,addr);
4782           }
4783           if(s2l>=0) emit_cmp(s1l,s2l);
4784           else emit_test(s1l,s1l);
4785           emit_cmovne_reg(alt,addr);
4786         }
4787       }
4788       if((opcode[i]&0x2f)==5) // BNE
4789       {
4790         #ifdef HAVE_CMOV_IMM
4791         if(s1h<0) {
4792           if(s2l>=0) emit_cmp(s1l,s2l);
4793           else emit_test(s1l,s1l);
4794           emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4795         }
4796         else
4797         #endif
4798         {
4799           emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4800           if(s1h>=0) {
4801             if(s2h>=0) emit_cmp(s1h,s2h);
4802             else emit_test(s1h,s1h);
4803             emit_cmovne_reg(alt,addr);
4804           }
4805           if(s2l>=0) emit_cmp(s1l,s2l);
4806           else emit_test(s1l,s1l);
4807           emit_cmovne_reg(alt,addr);
4808         }
4809       }
4810       if((opcode[i]&0x2f)==6) // BLEZ
4811       {
4812         //emit_movimm(ba[i],alt);
4813         //emit_movimm(start+i*4+8,addr);
4814         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4815         emit_cmpimm(s1l,1);
4816         if(s1h>=0) emit_mov(addr,ntaddr);
4817         emit_cmovl_reg(alt,addr);
4818         if(s1h>=0) {
4819           emit_test(s1h,s1h);
4820           emit_cmovne_reg(ntaddr,addr);
4821           emit_cmovs_reg(alt,addr);
4822         }
4823       }
4824       if((opcode[i]&0x2f)==7) // BGTZ
4825       {
4826         //emit_movimm(ba[i],addr);
4827         //emit_movimm(start+i*4+8,ntaddr);
4828         emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
4829         emit_cmpimm(s1l,1);
4830         if(s1h>=0) emit_mov(addr,alt);
4831         emit_cmovl_reg(ntaddr,addr);
4832         if(s1h>=0) {
4833           emit_test(s1h,s1h);
4834           emit_cmovne_reg(alt,addr);
4835           emit_cmovs_reg(ntaddr,addr);
4836         }
4837       }
4838       if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
4839       {
4840         //emit_movimm(ba[i],alt);
4841         //emit_movimm(start+i*4+8,addr);
4842         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4843         if(s1h>=0) emit_test(s1h,s1h);
4844         else emit_test(s1l,s1l);
4845         emit_cmovs_reg(alt,addr);
4846       }
4847       if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
4848       {
4849         //emit_movimm(ba[i],addr);
4850         //emit_movimm(start+i*4+8,alt);
4851         emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4852         if(s1h>=0) emit_test(s1h,s1h);
4853         else emit_test(s1l,s1l);
4854         emit_cmovs_reg(alt,addr);
4855       }
4856       if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
4857         if(source[i]&0x10000) // BC1T
4858         {
4859           //emit_movimm(ba[i],alt);
4860           //emit_movimm(start+i*4+8,addr);
4861           emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4862           emit_testimm(s1l,0x800000);
4863           emit_cmovne_reg(alt,addr);
4864         }
4865         else // BC1F
4866         {
4867           //emit_movimm(ba[i],addr);
4868           //emit_movimm(start+i*4+8,alt);
4869           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4870           emit_testimm(s1l,0x800000);
4871           emit_cmovne_reg(alt,addr);
4872         }
4873       }
4874       emit_writeword(addr,(int)&pcaddr);
4875     }
4876     else
4877     if(itype[i]==RJUMP)
4878     {
4879       int r=get_reg(branch_regs[i].regmap,rs1[i]);
4880       if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
4881         r=get_reg(branch_regs[i].regmap,RTEMP);
4882       }
4883       emit_writeword(r,(int)&pcaddr);
4884     }
4885     else {DebugMessage(M64MSG_ERROR, "Unknown branch type in do_ccstub");exit(1);}
4886   }
4887   // Update cycle count
4888   assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
4889   if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
4890   emit_call((int)cc_interrupt);
4891   if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
4892   if(stubs[n][6]==TAKEN) {
4893     if(internal_branch(branch_regs[i].is32,ba[i]))
4894       load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
4895     else if(itype[i]==RJUMP) {
4896       if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
4897         emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
4898       else
4899         emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
4900     }
4901   }else if(stubs[n][6]==NOTTAKEN) {
4902     if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
4903     else load_all_regs(branch_regs[i].regmap);
4904   }else if(stubs[n][6]==NULLDS) {
4905     // Delay slot instruction is nullified ("likely" branch)
4906     if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
4907     else load_all_regs(regs[i].regmap);
4908   }else{
4909     load_all_regs(branch_regs[i].regmap);
4910   }
4911   emit_jmp(stubs[n][2]); // return address
4912
4913   /* This works but uses a lot of memory...
4914   emit_readword((int)&last_count,ECX);
4915   emit_add(HOST_CCREG,ECX,EAX);
4916   emit_writeword(EAX,(int)&Count);
4917   emit_call((int)gen_interupt);
4918   emit_readword((int)&Count,HOST_CCREG);
4919   emit_readword((int)&next_interupt,EAX);
4920   emit_readword((int)&pending_exception,EBX);
4921   emit_writeword(EAX,(int)&last_count);
4922   emit_sub(HOST_CCREG,EAX,HOST_CCREG);
4923   emit_test(EBX,EBX);
4924   int jne_instr=(int)out;
4925   emit_jne(0);
4926   if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
4927   load_all_regs(branch_regs[i].regmap);
4928   emit_jmp(stubs[n][2]); // return address
4929   set_jump_target(jne_instr,(int)out);
4930   emit_readword((int)&pcaddr,EAX);
4931   // Call get_addr_ht instead of doing the hash table here.
4932   // This code is executed infrequently and takes up a lot of space
4933   // so smaller is better.
4934   emit_storereg(CCREG,HOST_CCREG);
4935   emit_pushreg(EAX);
4936   emit_call((int)get_addr_ht);
4937   emit_loadreg(CCREG,HOST_CCREG);
4938   emit_addimm(ESP,4,ESP);
4939   emit_jmpreg(EAX);*/
4940 }
4941
4942 static void add_to_linker(int addr,int target,int ext)
4943 {
4944   link_addr[linkcount][0]=addr;
4945   link_addr[linkcount][1]=target;
4946   link_addr[linkcount][2]=ext;
4947   linkcount++;
4948 }
4949
4950 static void ujump_assemble(int i,struct regstat *i_regs)
4951 {
4952   #ifdef REG_PREFETCH
4953   signed char *i_regmap=i_regs->regmap;
4954   #endif
4955   if(i==(ba[i]-start)>>2) assem_debug("idle loop");
4956   address_generation(i+1,i_regs,regs[i].regmap_entry);
4957   #ifdef REG_PREFETCH
4958   int temp=get_reg(branch_regs[i].regmap,PTEMP);
4959   if(rt1[i]==31&&temp>=0)
4960   {
4961     int return_address=start+i*4+8;
4962     if(get_reg(branch_regs[i].regmap,31)>0)
4963     if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
4964   }
4965   #endif
4966   ds_assemble(i+1,i_regs);
4967   uint64_t bc_unneeded=branch_regs[i].u;
4968   uint64_t bc_unneeded_upper=branch_regs[i].uu;
4969   bc_unneeded|=1|(1LL<<rt1[i]);
4970   bc_unneeded_upper|=1|(1LL<<rt1[i]);
4971   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
4972                 bc_unneeded,bc_unneeded_upper);
4973   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
4974   if(rt1[i]==31) {
4975     int rt;
4976     unsigned int return_address;
4977     assert(rt1[i+1]!=31);
4978     assert(rt2[i+1]!=31);
4979     rt=get_reg(branch_regs[i].regmap,31);
4980     assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
4981     //assert(rt>=0);
4982     return_address=start+i*4+8;
4983     if(rt>=0) {
4984       #ifdef USE_MINI_HT
4985       if(internal_branch(branch_regs[i].is32,return_address)) {
4986         int temp=rt+1;
4987         if(temp==EXCLUDE_REG||temp>=HOST_REGS||
4988            branch_regs[i].regmap[temp]>=0)
4989         {
4990           temp=get_reg(branch_regs[i].regmap,-1);
4991         }
4992         #ifdef HOST_TEMPREG
4993         if(temp<0) temp=HOST_TEMPREG;
4994         #endif
4995         if(temp>=0) do_miniht_insert(return_address,rt,temp);
4996         else emit_movimm(return_address,rt);
4997       }
4998       else
4999       #endif
5000       {
5001         #ifdef REG_PREFETCH
5002         if(temp>=0)
5003         {
5004           if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5005         }
5006         #endif
5007         emit_movimm(return_address,rt); // PC into link register
5008         #ifdef IMM_PREFETCH
5009         emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5010         #endif
5011       }
5012     }
5013   }
5014   int cc,adj;
5015   cc=get_reg(branch_regs[i].regmap,CCREG);
5016   assert(cc==HOST_CCREG);
5017   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5018   #ifdef REG_PREFETCH
5019   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5020   #endif
5021   do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5022   if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5023   load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5024   if(internal_branch(branch_regs[i].is32,ba[i]))
5025     assem_debug("branch: internal");
5026   else
5027     assem_debug("branch: external");
5028   if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5029     ds_assemble_entry(i);
5030   }
5031   else {
5032     add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5033     emit_jmp(0);
5034   }
5035 }
5036
5037 static void rjump_assemble(int i,struct regstat *i_regs)
5038 {
5039   #ifdef REG_PREFETCH
5040   signed char *i_regmap=i_regs->regmap;
5041   #endif
5042   int temp;
5043   int rs,cc;
5044   rs=get_reg(branch_regs[i].regmap,rs1[i]);
5045   assert(rs>=0);
5046   if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5047     // Delay slot abuse, make a copy of the branch address register
5048     temp=get_reg(branch_regs[i].regmap,RTEMP);
5049     assert(temp>=0);
5050     assert(regs[i].regmap[temp]==RTEMP);
5051     emit_mov(rs,temp);
5052     rs=temp;
5053   }
5054   address_generation(i+1,i_regs,regs[i].regmap_entry);
5055   #ifdef REG_PREFETCH
5056   if(rt1[i]==31)
5057   {
5058     if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5059       int return_address=start+i*4+8;
5060       if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5061     }
5062   }
5063   #endif
5064   #ifdef USE_MINI_HT
5065   if(rs1[i]==31) {
5066     int rh=get_reg(regs[i].regmap,RHASH);
5067     if(rh>=0) do_preload_rhash(rh);
5068   }
5069   #endif
5070   ds_assemble(i+1,i_regs);
5071   uint64_t bc_unneeded=branch_regs[i].u;
5072   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5073   bc_unneeded|=1|(1LL<<rt1[i]);
5074   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5075   bc_unneeded&=~(1LL<<rs1[i]);
5076   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5077                 bc_unneeded,bc_unneeded_upper);
5078   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5079   if(rt1[i]!=0) {
5080     int rt,return_address;
5081     assert(rt1[i+1]!=rt1[i]);
5082     assert(rt2[i+1]!=rt1[i]);
5083     rt=get_reg(branch_regs[i].regmap,rt1[i]);
5084     assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5085     assert(rt>=0);
5086     return_address=start+i*4+8;
5087     #ifdef REG_PREFETCH
5088     if(temp>=0)
5089     {
5090       if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5091     }
5092     #endif
5093     emit_movimm(return_address,rt); // PC into link register
5094     #ifdef IMM_PREFETCH
5095     emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5096     #endif
5097   }
5098   cc=get_reg(branch_regs[i].regmap,CCREG);
5099   assert(cc==HOST_CCREG);
5100   #ifdef USE_MINI_HT
5101   int rh=get_reg(branch_regs[i].regmap,RHASH);
5102   int ht=get_reg(branch_regs[i].regmap,RHTBL);
5103   if(rs1[i]==31) {
5104     if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5105     do_preload_rhtbl(ht);
5106     do_rhash(rs,rh);
5107   }
5108   #endif
5109   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5110   #ifdef DESTRUCTIVE_WRITEBACK
5111   if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5112     if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5113       emit_loadreg(rs1[i],rs);
5114     }
5115   }
5116   #endif
5117   #ifdef REG_PREFETCH
5118   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5119   #endif
5120   #ifdef USE_MINI_HT
5121   if(rs1[i]==31) {
5122     do_miniht_load(ht,rh);
5123   }
5124   #endif
5125   //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5126   //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5127   //assert(adj==0);
5128   emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5129   add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5130   emit_jns(0);
5131   //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5132   #ifdef USE_MINI_HT
5133   if(rs1[i]==31) {
5134     do_miniht_jump(rs,rh,ht);
5135   }
5136   else
5137   #endif
5138   {
5139     //if(rs!=EAX) emit_mov(rs,EAX);
5140     //emit_jmp((int)jump_vaddr_eax);
5141     emit_jmp(jump_vaddr_reg[rs]);
5142   }
5143   /* Check hash table
5144   temp=!rs;
5145   emit_mov(rs,temp);
5146   emit_shrimm(rs,16,rs);
5147   emit_xor(temp,rs,rs);
5148   emit_movzwl_reg(rs,rs);
5149   emit_shlimm(rs,4,rs);
5150   emit_cmpmem_indexed((int)hash_table,rs,temp);
5151   emit_jne((int)out+14);
5152   emit_readword_indexed((int)hash_table+4,rs,rs);
5153   emit_jmpreg(rs);
5154   emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5155   emit_addimm_no_flags(8,rs);
5156   emit_jeq((int)out-17);
5157   // No hit on hash table, call compiler
5158   emit_pushreg(temp);
5159 //DEBUG >
5160 #ifdef DEBUG_CYCLE_COUNT
5161   emit_readword((int)&last_count,ECX);
5162   emit_add(HOST_CCREG,ECX,HOST_CCREG);
5163   emit_readword((int)&next_interupt,ECX);
5164   emit_writeword(HOST_CCREG,(int)&Count);
5165   emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5166   emit_writeword(ECX,(int)&last_count);
5167 #endif
5168 //DEBUG <
5169   emit_storereg(CCREG,HOST_CCREG);
5170   emit_call((int)get_addr);
5171   emit_loadreg(CCREG,HOST_CCREG);
5172   emit_addimm(ESP,4,ESP);
5173   emit_jmpreg(EAX);*/
5174   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5175   if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5176   #endif
5177 }
5178
5179 static void cjump_assemble(int i,struct regstat *i_regs)
5180 {
5181   signed char *i_regmap=i_regs->regmap;
5182   int cc;
5183   int match;
5184   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5185   assem_debug("match=%d",match);
5186   int s1h,s1l,s2h,s2l;
5187   int prev_cop1_usable=cop1_usable;
5188   int unconditional=0,nop=0;
5189   int only32=0;
5190   int invert=0;
5191   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5192   if(i==(ba[i]-start)>>2) assem_debug("idle loop");
5193   if(!match) invert=1;
5194   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5195   if(i>(ba[i]-start)>>2) invert=1;
5196   #endif
5197
5198   if(ooo[i]) {
5199     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5200     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5201     s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5202     s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5203   }
5204   else {
5205     s1l=get_reg(i_regmap,rs1[i]);
5206     s1h=get_reg(i_regmap,rs1[i]|64);
5207     s2l=get_reg(i_regmap,rs2[i]);
5208     s2h=get_reg(i_regmap,rs2[i]|64);
5209   }
5210   if(rs1[i]==0&&rs2[i]==0)
5211   {
5212     if(opcode[i]&1) nop=1;
5213     else unconditional=1;
5214     //assert(opcode[i]!=5);
5215     //assert(opcode[i]!=7);
5216     //assert(opcode[i]!=0x15);
5217     //assert(opcode[i]!=0x17);
5218   }
5219   else if(rs1[i]==0)
5220   {
5221     s1l=s2l;s1h=s2h;
5222     s2l=s2h=-1;
5223     only32=(regs[i].was32>>rs2[i])&1;
5224   }
5225   else if(rs2[i]==0)
5226   {
5227     s2l=s2h=-1;
5228     only32=(regs[i].was32>>rs1[i])&1;
5229   }
5230   else {
5231     only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5232   }
5233
5234   if(ooo[i]) {
5235     // Out of order execution (delay slot first)
5236     //DebugMessage(M64MSG_VERBOSE, "OOOE");
5237     address_generation(i+1,i_regs,regs[i].regmap_entry);
5238     ds_assemble(i+1,i_regs);
5239     int adj;
5240     uint64_t bc_unneeded=branch_regs[i].u;
5241     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5242     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5243     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5244     bc_unneeded|=1;
5245     bc_unneeded_upper|=1;
5246     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5247                   bc_unneeded,bc_unneeded_upper);
5248     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5249     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5250     cc=get_reg(branch_regs[i].regmap,CCREG);
5251     assert(cc==HOST_CCREG);
5252     if(unconditional)
5253       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5254     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5255     //assem_debug("cycle count (adj)");
5256     if(unconditional) {
5257       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5258       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5259         if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5260         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5261         if(internal)
5262           assem_debug("branch: internal");
5263         else
5264           assem_debug("branch: external");
5265         if(internal&&is_ds[(ba[i]-start)>>2]) {
5266           ds_assemble_entry(i);
5267         }
5268         else {
5269           add_to_linker((int)out,ba[i],internal);
5270           emit_jmp(0);
5271         }
5272         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5273         if(((u_int)out)&7) emit_addnop(0);
5274         #endif
5275       }
5276     }
5277     else if(nop) {
5278       emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5279       int jaddr=(int)out;
5280       emit_jns(0);
5281       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5282     }
5283     else {
5284       int taken=0,nottaken=0,nottaken1=0;
5285       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5286       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5287       if(!only32)
5288       {
5289         assert(s1h>=0);
5290         if(opcode[i]==4) // BEQ
5291         {
5292           if(s2h>=0) emit_cmp(s1h,s2h);
5293           else emit_test(s1h,s1h);
5294           nottaken1=(int)out;
5295           emit_jne(1);
5296         }
5297         if(opcode[i]==5) // BNE
5298         {
5299           if(s2h>=0) emit_cmp(s1h,s2h);
5300           else emit_test(s1h,s1h);
5301           if(invert) taken=(int)out;
5302           else add_to_linker((int)out,ba[i],internal);
5303           emit_jne(0);
5304         }
5305         if(opcode[i]==6) // BLEZ
5306         {
5307           emit_test(s1h,s1h);
5308           if(invert) taken=(int)out;
5309           else add_to_linker((int)out,ba[i],internal);
5310           emit_js(0);
5311           nottaken1=(int)out;
5312           emit_jne(1);
5313         }
5314         if(opcode[i]==7) // BGTZ
5315         {
5316           emit_test(s1h,s1h);
5317           nottaken1=(int)out;
5318           emit_js(1);
5319           if(invert) taken=(int)out;
5320           else add_to_linker((int)out,ba[i],internal);
5321           emit_jne(0);
5322         }
5323       } // if(!only32)
5324
5325       //DebugMessage(M64MSG_VERBOSE, "branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5326       assert(s1l>=0);
5327       if(opcode[i]==4) // BEQ
5328       {
5329         if(s2l>=0) emit_cmp(s1l,s2l);
5330         else emit_test(s1l,s1l);
5331         if(invert){
5332           nottaken=(int)out;
5333           emit_jne(1);
5334         }else{
5335           add_to_linker((int)out,ba[i],internal);
5336           emit_jeq(0);
5337         }
5338       }
5339       if(opcode[i]==5) // BNE
5340       {
5341         if(s2l>=0) emit_cmp(s1l,s2l);
5342         else emit_test(s1l,s1l);
5343         if(invert){
5344           nottaken=(int)out;
5345           emit_jeq(1);
5346         }else{
5347           add_to_linker((int)out,ba[i],internal);
5348           emit_jne(0);
5349         }
5350       }
5351       if(opcode[i]==6) // BLEZ
5352       {
5353         emit_cmpimm(s1l,1);
5354         if(invert){
5355           nottaken=(int)out;
5356           emit_jge(1);
5357         }else{
5358           add_to_linker((int)out,ba[i],internal);
5359           emit_jl(0);
5360         }
5361       }
5362       if(opcode[i]==7) // BGTZ
5363       {
5364         emit_cmpimm(s1l,1);
5365         if(invert){
5366           nottaken=(int)out;
5367           emit_jl(1);
5368         }else{
5369           add_to_linker((int)out,ba[i],internal);
5370           emit_jge(0);
5371         }
5372       }
5373       if(invert) {
5374         if(taken) set_jump_target(taken,(int)out);
5375         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5376         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5377           if(adj) {
5378             emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5379             add_to_linker((int)out,ba[i],internal);
5380           }else{
5381             emit_addnop(13);
5382             add_to_linker((int)out,ba[i],internal*2);
5383           }
5384           emit_jmp(0);
5385         }else
5386         #endif
5387         {
5388           if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5389           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5390           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5391           if(internal)
5392             assem_debug("branch: internal");
5393           else
5394             assem_debug("branch: external");
5395           if(internal&&is_ds[(ba[i]-start)>>2]) {
5396             ds_assemble_entry(i);
5397           }
5398           else {
5399             add_to_linker((int)out,ba[i],internal);
5400             emit_jmp(0);
5401           }
5402         }
5403         set_jump_target(nottaken,(int)out);
5404       }
5405
5406       if(nottaken1) set_jump_target(nottaken1,(int)out);
5407       if(adj) {
5408         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5409       }
5410     } // (!unconditional)
5411   } // if(ooo)
5412   else
5413   {
5414     // In-order execution (branch first)
5415     //if(likely[i]) DebugMessage(M64MSG_VERBOSE, "IOL");
5416     //else
5417     //DebugMessage(M64MSG_VERBOSE, "IOE");
5418     int taken=0,nottaken=0,nottaken1=0;
5419     if(!unconditional&&!nop) {
5420       if(!only32)
5421       {
5422         assert(s1h>=0);
5423         if((opcode[i]&0x2f)==4) // BEQ
5424         {
5425           if(s2h>=0) emit_cmp(s1h,s2h);
5426           else emit_test(s1h,s1h);
5427           nottaken1=(int)out;
5428           emit_jne(2);
5429         }
5430         if((opcode[i]&0x2f)==5) // BNE
5431         {
5432           if(s2h>=0) emit_cmp(s1h,s2h);
5433           else emit_test(s1h,s1h);
5434           taken=(int)out;
5435           emit_jne(1);
5436         }
5437         if((opcode[i]&0x2f)==6) // BLEZ
5438         {
5439           emit_test(s1h,s1h);
5440           taken=(int)out;
5441           emit_js(1);
5442           nottaken1=(int)out;
5443           emit_jne(2);
5444         }
5445         if((opcode[i]&0x2f)==7) // BGTZ
5446         {
5447           emit_test(s1h,s1h);
5448           nottaken1=(int)out;
5449           emit_js(2);
5450           taken=(int)out;
5451           emit_jne(1);
5452         }
5453       } // if(!only32)
5454
5455       //DebugMessage(M64MSG_VERBOSE, "branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5456       assert(s1l>=0);
5457       if((opcode[i]&0x2f)==4) // BEQ
5458       {
5459         if(s2l>=0) emit_cmp(s1l,s2l);
5460         else emit_test(s1l,s1l);
5461         nottaken=(int)out;
5462         emit_jne(2);
5463       }
5464       if((opcode[i]&0x2f)==5) // BNE
5465       {
5466         if(s2l>=0) emit_cmp(s1l,s2l);
5467         else emit_test(s1l,s1l);
5468         nottaken=(int)out;
5469         emit_jeq(2);
5470       }
5471       if((opcode[i]&0x2f)==6) // BLEZ
5472       {
5473         emit_cmpimm(s1l,1);
5474         nottaken=(int)out;
5475         emit_jge(2);
5476       }
5477       if((opcode[i]&0x2f)==7) // BGTZ
5478       {
5479         emit_cmpimm(s1l,1);
5480         nottaken=(int)out;
5481         emit_jl(2);
5482       }
5483     } // if(!unconditional)
5484     int adj;
5485     uint64_t ds_unneeded=branch_regs[i].u;
5486     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5487     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5488     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5489     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5490     ds_unneeded|=1;
5491     ds_unneeded_upper|=1;
5492     // branch taken
5493     if(!nop) {
5494       if(taken) set_jump_target(taken,(int)out);
5495       assem_debug("1:");
5496       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5497                     ds_unneeded,ds_unneeded_upper);
5498       // load regs
5499       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5500       address_generation(i+1,&branch_regs[i],0);
5501       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5502       ds_assemble(i+1,&branch_regs[i]);
5503       cc=get_reg(branch_regs[i].regmap,CCREG);
5504       if(cc==-1) {
5505         emit_loadreg(CCREG,cc=HOST_CCREG);
5506         // CHECK: Is the following instruction (fall thru) allocated ok?
5507       }
5508       assert(cc==HOST_CCREG);
5509       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5510       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5511       assem_debug("cycle count (adj)");
5512       if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5513       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5514       if(internal)
5515         assem_debug("branch: internal");
5516       else
5517         assem_debug("branch: external");
5518       if(internal&&is_ds[(ba[i]-start)>>2]) {
5519         ds_assemble_entry(i);
5520       }
5521       else {
5522         add_to_linker((int)out,ba[i],internal);
5523         emit_jmp(0);
5524       }
5525     }
5526     // branch not taken
5527     cop1_usable=prev_cop1_usable;
5528     if(!unconditional) {
5529       if(nottaken1) set_jump_target(nottaken1,(int)out);
5530       set_jump_target(nottaken,(int)out);
5531       assem_debug("2:");
5532       if(!likely[i]) {
5533         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5534                       ds_unneeded,ds_unneeded_upper);
5535         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5536         address_generation(i+1,&branch_regs[i],0);
5537         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5538         ds_assemble(i+1,&branch_regs[i]);
5539       }
5540       cc=get_reg(branch_regs[i].regmap,CCREG);
5541       if(cc==-1&&!likely[i]) {
5542         // Cycle count isn't in a register, temporarily load it then write it out
5543         emit_loadreg(CCREG,HOST_CCREG);
5544         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5545         int jaddr=(int)out;
5546         emit_jns(0);
5547         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5548         emit_storereg(CCREG,HOST_CCREG);
5549       }
5550       else{
5551         cc=get_reg(i_regmap,CCREG);
5552         assert(cc==HOST_CCREG);
5553         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5554         int jaddr=(int)out;
5555         emit_jns(0);
5556         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5557       }
5558     }
5559   }
5560 }
5561
5562 static void sjump_assemble(int i,struct regstat *i_regs)
5563 {
5564   signed char *i_regmap=i_regs->regmap;
5565   int cc;
5566   int match;
5567   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5568   assem_debug("smatch=%d",match);
5569   int s1h,s1l;
5570   int prev_cop1_usable=cop1_usable;
5571   int unconditional=0,nevertaken=0;
5572   int only32=0;
5573   int invert=0;
5574   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5575   if(i==(ba[i]-start)>>2) assem_debug("idle loop");
5576   if(!match) invert=1;
5577   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5578   if(i>(ba[i]-start)>>2) invert=1;
5579   #endif
5580
5581   //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5582   assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5583
5584   if(ooo[i]) {
5585     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5586     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5587   }
5588   else {
5589     s1l=get_reg(i_regmap,rs1[i]);
5590     s1h=get_reg(i_regmap,rs1[i]|64);
5591   }
5592   if(rs1[i]==0)
5593   {
5594     if(opcode2[i]&1) unconditional=1;
5595     else nevertaken=1;
5596     // These are never taken (r0 is never less than zero)
5597     //assert(opcode2[i]!=0);
5598     //assert(opcode2[i]!=2);
5599     //assert(opcode2[i]!=0x10);
5600     //assert(opcode2[i]!=0x12);
5601   }
5602   else {
5603     only32=(regs[i].was32>>rs1[i])&1;
5604   }
5605
5606   if(ooo[i]) {
5607     // Out of order execution (delay slot first)
5608     //DebugMessage(M64MSG_VERBOSE, "OOOE");
5609     address_generation(i+1,i_regs,regs[i].regmap_entry);
5610     ds_assemble(i+1,i_regs);
5611     int adj;
5612     uint64_t bc_unneeded=branch_regs[i].u;
5613     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5614     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5615     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5616     bc_unneeded|=1;
5617     bc_unneeded_upper|=1;
5618     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5619                   bc_unneeded,bc_unneeded_upper);
5620     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5621     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5622     if(rt1[i]==31) {
5623       int rt,return_address;
5624       assert(rt1[i+1]!=31);
5625       assert(rt2[i+1]!=31);
5626       rt=get_reg(branch_regs[i].regmap,31);
5627       assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5628       if(rt>=0) {
5629         // Save the PC even if the branch is not taken
5630         return_address=start+i*4+8;
5631         emit_movimm(return_address,rt); // PC into link register
5632         #ifdef IMM_PREFETCH
5633         if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5634         #endif
5635       }
5636     }
5637     cc=get_reg(branch_regs[i].regmap,CCREG);
5638     assert(cc==HOST_CCREG);
5639     if(unconditional)
5640       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5641     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5642     assem_debug("cycle count (adj)");
5643     if(unconditional) {
5644       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5645       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5646         if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5647         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5648         if(internal)
5649           assem_debug("branch: internal");
5650         else
5651           assem_debug("branch: external");
5652         if(internal&&is_ds[(ba[i]-start)>>2]) {
5653           ds_assemble_entry(i);
5654         }
5655         else {
5656           add_to_linker((int)out,ba[i],internal);
5657           emit_jmp(0);
5658         }
5659         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5660         if(((u_int)out)&7) emit_addnop(0);
5661         #endif
5662       }
5663     }
5664     else if(nevertaken) {
5665       emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5666       int jaddr=(int)out;
5667       emit_jns(0);
5668       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5669     }
5670     else {
5671       int nottaken=0;
5672       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5673       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5674       if(!only32)
5675       {
5676         assert(s1h>=0);
5677         if(opcode2[i]==0) // BLTZ
5678         {
5679           emit_test(s1h,s1h);
5680           if(invert){
5681             nottaken=(int)out;
5682             emit_jns(1);
5683           }else{
5684             add_to_linker((int)out,ba[i],internal);
5685             emit_js(0);
5686           }
5687         }
5688         if(opcode2[i]==1) // BGEZ
5689         {
5690           emit_test(s1h,s1h);
5691           if(invert){
5692             nottaken=(int)out;
5693             emit_js(1);
5694           }else{
5695             add_to_linker((int)out,ba[i],internal);
5696             emit_jns(0);
5697           }
5698         }
5699       } // if(!only32)
5700       else
5701       {
5702         assert(s1l>=0);
5703         if(opcode2[i]==0) // BLTZ
5704         {
5705           emit_test(s1l,s1l);
5706           if(invert){
5707             nottaken=(int)out;
5708             emit_jns(1);
5709           }else{
5710             add_to_linker((int)out,ba[i],internal);
5711             emit_js(0);
5712           }
5713         }
5714         if(opcode2[i]==1) // BGEZ
5715         {
5716           emit_test(s1l,s1l);
5717           if(invert){
5718             nottaken=(int)out;
5719             emit_js(1);
5720           }else{
5721             add_to_linker((int)out,ba[i],internal);
5722             emit_jns(0);
5723           }
5724         }
5725       } // if(!only32)
5726
5727       if(invert) {
5728         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5729         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5730           if(adj) {
5731             emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5732             add_to_linker((int)out,ba[i],internal);
5733           }else{
5734             emit_addnop(13);
5735             add_to_linker((int)out,ba[i],internal*2);
5736           }
5737           emit_jmp(0);
5738         }else
5739         #endif
5740         {
5741           if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5742           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5743           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5744           if(internal)
5745             assem_debug("branch: internal");
5746           else
5747             assem_debug("branch: external");
5748           if(internal&&is_ds[(ba[i]-start)>>2]) {
5749             ds_assemble_entry(i);
5750           }
5751           else {
5752             add_to_linker((int)out,ba[i],internal);
5753             emit_jmp(0);
5754           }
5755         }
5756         set_jump_target(nottaken,(int)out);
5757       }
5758
5759       if(adj) {
5760         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5761       }
5762     } // (!unconditional)
5763   } // if(ooo)
5764   else
5765   {
5766     // In-order execution (branch first)
5767     //DebugMessage(M64MSG_VERBOSE, "IOE");
5768     int nottaken=0;
5769     if(!unconditional) {
5770       //DebugMessage(M64MSG_VERBOSE, "branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5771       if(!only32)
5772       {
5773         assert(s1h>=0);
5774         if((opcode2[i]&0x1d)==0) // BLTZ/BLTZL
5775         {
5776           emit_test(s1h,s1h);
5777           nottaken=(int)out;
5778           emit_jns(1);
5779         }
5780         if((opcode2[i]&0x1d)==1) // BGEZ/BGEZL
5781         {
5782           emit_test(s1h,s1h);
5783           nottaken=(int)out;
5784           emit_js(1);
5785         }
5786       } // if(!only32)
5787       else
5788       {
5789         assert(s1l>=0);
5790         if((opcode2[i]&0x1d)==0) // BLTZ/BLTZL
5791         {
5792           emit_test(s1l,s1l);
5793           nottaken=(int)out;
5794           emit_jns(1);
5795         }
5796         if((opcode2[i]&0x1d)==1) // BGEZ/BGEZL
5797         {
5798           emit_test(s1l,s1l);
5799           nottaken=(int)out;
5800           emit_js(1);
5801         }
5802       }
5803     } // if(!unconditional)
5804     int adj;
5805     uint64_t ds_unneeded=branch_regs[i].u;
5806     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5807     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5808     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5809     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5810     ds_unneeded|=1;
5811     ds_unneeded_upper|=1;
5812     // branch taken
5813     if(!nevertaken) {
5814       //assem_debug("1:");
5815       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5816                     ds_unneeded,ds_unneeded_upper);
5817       // load regs
5818       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5819       address_generation(i+1,&branch_regs[i],0);
5820       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5821       ds_assemble(i+1,&branch_regs[i]);
5822       cc=get_reg(branch_regs[i].regmap,CCREG);
5823       if(cc==-1) {
5824         emit_loadreg(CCREG,cc=HOST_CCREG);
5825         // CHECK: Is the following instruction (fall thru) allocated ok?
5826       }
5827       assert(cc==HOST_CCREG);
5828       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5829       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5830       assem_debug("cycle count (adj)");
5831       if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5832       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5833       if(internal)
5834         assem_debug("branch: internal");
5835       else
5836         assem_debug("branch: external");
5837       if(internal&&is_ds[(ba[i]-start)>>2]) {
5838         ds_assemble_entry(i);
5839       }
5840       else {
5841         add_to_linker((int)out,ba[i],internal);
5842         emit_jmp(0);
5843       }
5844     }
5845     // branch not taken
5846     cop1_usable=prev_cop1_usable;
5847     if(!unconditional) {
5848       set_jump_target(nottaken,(int)out);
5849       assem_debug("1:");
5850       if(!likely[i]) {
5851         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5852                       ds_unneeded,ds_unneeded_upper);
5853         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5854         address_generation(i+1,&branch_regs[i],0);
5855         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5856         ds_assemble(i+1,&branch_regs[i]);
5857       }
5858       cc=get_reg(branch_regs[i].regmap,CCREG);
5859       if(cc==-1&&!likely[i]) {
5860         // Cycle count isn't in a register, temporarily load it then write it out
5861         emit_loadreg(CCREG,HOST_CCREG);
5862         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5863         int jaddr=(int)out;
5864         emit_jns(0);
5865         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5866         emit_storereg(CCREG,HOST_CCREG);
5867       }
5868       else{
5869         cc=get_reg(i_regmap,CCREG);
5870         assert(cc==HOST_CCREG);
5871         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5872         int jaddr=(int)out;
5873         emit_jns(0);
5874         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5875       }
5876     }
5877   }
5878 }
5879
5880 static void fjump_assemble(int i,struct regstat *i_regs)
5881 {
5882   signed char *i_regmap=i_regs->regmap;
5883   int cc;
5884   int match;
5885   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5886   assem_debug("fmatch=%d",match);
5887   int fs,cs;
5888   int eaddr;
5889   int invert=0;
5890   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5891   if(i==(ba[i]-start)>>2) assem_debug("idle loop");
5892   if(!match) invert=1;
5893   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5894   if(i>(ba[i]-start)>>2) invert=1;
5895   #endif
5896
5897   if(ooo[i]) {
5898     fs=get_reg(branch_regs[i].regmap,FSREG);
5899     address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
5900   }
5901   else {
5902     fs=get_reg(i_regmap,FSREG);
5903   }
5904
5905   // Check cop1 unusable
5906   if(!cop1_usable) {
5907     cs=get_reg(i_regmap,CSREG);
5908     assert(cs>=0);
5909     emit_testimm(cs,0x20000000);
5910     eaddr=(int)out;
5911     emit_jeq(0);
5912     add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
5913     cop1_usable=1;
5914   }
5915
5916   if(ooo[i]) {
5917     // Out of order execution (delay slot first)
5918     //DebugMessage(M64MSG_VERBOSE, "OOOE");
5919     ds_assemble(i+1,i_regs);
5920     int adj;
5921     uint64_t bc_unneeded=branch_regs[i].u;
5922     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5923     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5924     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5925     bc_unneeded|=1;
5926     bc_unneeded_upper|=1;
5927     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5928                   bc_unneeded,bc_unneeded_upper);
5929     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5930     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5931     cc=get_reg(branch_regs[i].regmap,CCREG);
5932     assert(cc==HOST_CCREG);
5933     do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5934     assem_debug("cycle count (adj)");
5935     if(1) {
5936       int nottaken=0;
5937       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5938       if(1) {
5939         assert(fs>=0);
5940         emit_testimm(fs,0x800000);
5941         if(source[i]&0x10000) // BC1T
5942         {
5943           if(invert){
5944             nottaken=(int)out;
5945             emit_jeq(1);
5946           }else{
5947             add_to_linker((int)out,ba[i],internal);
5948             emit_jne(0);
5949           }
5950         }
5951         else // BC1F
5952           if(invert){
5953             nottaken=(int)out;
5954             emit_jne(1);
5955           }else{
5956             add_to_linker((int)out,ba[i],internal);
5957             emit_jeq(0);
5958           }
5959         {
5960         }
5961       } // if(!only32)
5962
5963       if(invert) {
5964         if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5965         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5966         else if(match) emit_addnop(13);
5967         #endif
5968         store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5969         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5970         if(internal)
5971           assem_debug("branch: internal");
5972         else
5973           assem_debug("branch: external");
5974         if(internal&&is_ds[(ba[i]-start)>>2]) {
5975           ds_assemble_entry(i);
5976         }
5977         else {
5978           add_to_linker((int)out,ba[i],internal);
5979           emit_jmp(0);
5980         }
5981         set_jump_target(nottaken,(int)out);
5982       }
5983
5984       if(adj) {
5985         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5986       }
5987     } // (!unconditional)
5988   } // if(ooo)
5989   else
5990   {
5991     // In-order execution (branch first)
5992     //DebugMessage(M64MSG_VERBOSE, "IOE");
5993     int nottaken=0;
5994     if(1) {
5995       //DebugMessage(M64MSG_VERBOSE, "branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5996       if(1) {
5997         assert(fs>=0);
5998         emit_testimm(fs,0x800000);
5999         if(source[i]&0x10000) // BC1T
6000         {
6001           nottaken=(int)out;
6002           emit_jeq(1);
6003         }
6004         else // BC1F
6005         {
6006           nottaken=(int)out;
6007           emit_jne(1);
6008         }
6009       }
6010     } // if(!unconditional)
6011     int adj;
6012     uint64_t ds_unneeded=branch_regs[i].u;
6013     uint64_t ds_unneeded_upper=branch_regs[i].uu;
6014     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6015     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6016     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6017     ds_unneeded|=1;
6018     ds_unneeded_upper|=1;
6019     // branch taken
6020     //assem_debug("1:");
6021     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6022                   ds_unneeded,ds_unneeded_upper);
6023     // load regs
6024     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6025     address_generation(i+1,&branch_regs[i],0);
6026     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6027     ds_assemble(i+1,&branch_regs[i]);
6028     cc=get_reg(branch_regs[i].regmap,CCREG);
6029     if(cc==-1) {
6030       emit_loadreg(CCREG,cc=HOST_CCREG);
6031       // CHECK: Is the following instruction (fall thru) allocated ok?
6032     }
6033     assert(cc==HOST_CCREG);
6034     store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6035     do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6036     assem_debug("cycle count (adj)");
6037     if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6038     load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6039     if(internal)
6040       assem_debug("branch: internal");
6041     else
6042       assem_debug("branch: external");
6043     if(internal&&is_ds[(ba[i]-start)>>2]) {
6044       ds_assemble_entry(i);
6045     }
6046     else {
6047       add_to_linker((int)out,ba[i],internal);
6048       emit_jmp(0);
6049     }
6050
6051     // branch not taken
6052     if(1) { // <- FIXME (don't need this)
6053       set_jump_target(nottaken,(int)out);
6054       assem_debug("1:");
6055       if(!likely[i]) {
6056         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6057                       ds_unneeded,ds_unneeded_upper);
6058         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6059         address_generation(i+1,&branch_regs[i],0);
6060         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6061         ds_assemble(i+1,&branch_regs[i]);
6062       }
6063       cc=get_reg(branch_regs[i].regmap,CCREG);
6064       if(cc==-1&&!likely[i]) {
6065         // Cycle count isn't in a register, temporarily load it then write it out
6066         emit_loadreg(CCREG,HOST_CCREG);
6067         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6068         int jaddr=(int)out;
6069         emit_jns(0);
6070         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6071         emit_storereg(CCREG,HOST_CCREG);
6072       }
6073       else{
6074         cc=get_reg(i_regmap,CCREG);
6075         assert(cc==HOST_CCREG);
6076         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6077         int jaddr=(int)out;
6078         emit_jns(0);
6079         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6080       }
6081     }
6082   }
6083 }
6084
6085 static void pagespan_assemble(int i,struct regstat *i_regs)
6086 {
6087   int s1l=get_reg(i_regs->regmap,rs1[i]);
6088   int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6089   int s2l=get_reg(i_regs->regmap,rs2[i]);
6090   int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6091   int taken=0;
6092   int nottaken=0;
6093   int unconditional=0;
6094   if(rs1[i]==0)
6095   {
6096     s1l=s2l;s1h=s2h;
6097     s2l=s2h=-1;
6098   }
6099   else if(rs2[i]==0)
6100   {
6101     s2l=s2h=-1;
6102   }
6103   if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6104     s1h=s2h=-1;
6105   }
6106   int hr=0;
6107   int addr,alt,ntaddr;
6108   if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6109   else {
6110     while(hr<HOST_REGS)
6111     {
6112       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6113          (i_regs->regmap[hr]&63)!=rs1[i] &&
6114          (i_regs->regmap[hr]&63)!=rs2[i] )
6115       {
6116         addr=hr++;break;
6117       }
6118       hr++;
6119     }
6120   }
6121   while(hr<HOST_REGS)
6122   {
6123     if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6124        (i_regs->regmap[hr]&63)!=rs1[i] &&
6125        (i_regs->regmap[hr]&63)!=rs2[i] )
6126     {
6127       alt=hr++;break;
6128     }
6129     hr++;
6130   }
6131   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6132   {
6133     while(hr<HOST_REGS)
6134     {
6135       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6136          (i_regs->regmap[hr]&63)!=rs1[i] &&
6137          (i_regs->regmap[hr]&63)!=rs2[i] )
6138       {
6139         ntaddr=hr;break;
6140       }
6141       hr++;
6142     }
6143   }
6144   assert(hr<HOST_REGS);
6145   if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6146     load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6147   }
6148   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6149   if(opcode[i]==2) // J
6150   {
6151     unconditional=1;
6152   }
6153   if(opcode[i]==3) // JAL
6154   {
6155     // TODO: mini_ht
6156     int rt=get_reg(i_regs->regmap,31);
6157     emit_movimm(start+i*4+8,rt);
6158     unconditional=1;
6159   }
6160   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6161   {
6162     emit_mov(s1l,addr);
6163     if(opcode2[i]==9) // JALR
6164     {
6165       int rt=get_reg(i_regs->regmap,rt1[i]);
6166       emit_movimm(start+i*4+8,rt);
6167     }
6168   }
6169   if((opcode[i]&0x3f)==4) // BEQ
6170   {
6171     if(rs1[i]==rs2[i])
6172     {
6173       unconditional=1;
6174     }
6175     else
6176     #ifdef HAVE_CMOV_IMM
6177     if(s1h<0) {
6178       if(s2l>=0) emit_cmp(s1l,s2l);
6179       else emit_test(s1l,s1l);
6180       emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6181     }
6182     else
6183     #endif
6184     {
6185       assert(s1l>=0);
6186       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6187       if(s1h>=0) {
6188         if(s2h>=0) emit_cmp(s1h,s2h);
6189         else emit_test(s1h,s1h);
6190         emit_cmovne_reg(alt,addr);
6191       }
6192       if(s2l>=0) emit_cmp(s1l,s2l);
6193       else emit_test(s1l,s1l);
6194       emit_cmovne_reg(alt,addr);
6195     }
6196   }
6197   if((opcode[i]&0x3f)==5) // BNE
6198   {
6199     #ifdef HAVE_CMOV_IMM
6200     if(s1h<0) {
6201       if(s2l>=0) emit_cmp(s1l,s2l);
6202       else emit_test(s1l,s1l);
6203       emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6204     }
6205     else
6206     #endif
6207     {
6208       assert(s1l>=0);
6209       emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6210       if(s1h>=0) {
6211         if(s2h>=0) emit_cmp(s1h,s2h);
6212         else emit_test(s1h,s1h);
6213         emit_cmovne_reg(alt,addr);
6214       }
6215       if(s2l>=0) emit_cmp(s1l,s2l);
6216       else emit_test(s1l,s1l);
6217       emit_cmovne_reg(alt,addr);
6218     }
6219   }
6220   if((opcode[i]&0x3f)==0x14) // BEQL
6221   {
6222     if(s1h>=0) {
6223       if(s2h>=0) emit_cmp(s1h,s2h);
6224       else emit_test(s1h,s1h);
6225       nottaken=(int)out;
6226       emit_jne(0);
6227     }
6228     if(s2l>=0) emit_cmp(s1l,s2l);
6229     else emit_test(s1l,s1l);
6230     if(nottaken) set_jump_target(nottaken,(int)out);
6231     nottaken=(int)out;
6232     emit_jne(0);
6233   }
6234   if((opcode[i]&0x3f)==0x15) // BNEL
6235   {
6236     if(s1h>=0) {
6237       if(s2h>=0) emit_cmp(s1h,s2h);
6238       else emit_test(s1h,s1h);
6239       taken=(int)out;
6240       emit_jne(0);
6241     }
6242     if(s2l>=0) emit_cmp(s1l,s2l);
6243     else emit_test(s1l,s1l);
6244     nottaken=(int)out;
6245     emit_jeq(0);
6246     if(taken) set_jump_target(taken,(int)out);
6247   }
6248   if((opcode[i]&0x3f)==6) // BLEZ
6249   {
6250     emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6251     emit_cmpimm(s1l,1);
6252     if(s1h>=0) emit_mov(addr,ntaddr);
6253     emit_cmovl_reg(alt,addr);
6254     if(s1h>=0) {
6255       emit_test(s1h,s1h);
6256       emit_cmovne_reg(ntaddr,addr);
6257       emit_cmovs_reg(alt,addr);
6258     }
6259   }
6260   if((opcode[i]&0x3f)==7) // BGTZ
6261   {
6262     emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6263     emit_cmpimm(s1l,1);
6264     if(s1h>=0) emit_mov(addr,alt);
6265     emit_cmovl_reg(ntaddr,addr);
6266     if(s1h>=0) {
6267       emit_test(s1h,s1h);
6268       emit_cmovne_reg(alt,addr);
6269       emit_cmovs_reg(ntaddr,addr);
6270     }
6271   }
6272   if((opcode[i]&0x3f)==0x16) // BLEZL
6273   {
6274     assert((opcode[i]&0x3f)!=0x16);
6275   }
6276   if((opcode[i]&0x3f)==0x17) // BGTZL
6277   {
6278     assert((opcode[i]&0x3f)!=0x17);
6279   }
6280   assert(opcode[i]!=1); // BLTZ/BGEZ
6281
6282   //FIXME: Check CSREG
6283   if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6284     if((source[i]&0x30000)==0) // BC1F
6285     {
6286       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6287       emit_testimm(s1l,0x800000);
6288       emit_cmovne_reg(alt,addr);
6289     }
6290     if((source[i]&0x30000)==0x10000) // BC1T
6291     {
6292       emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6293       emit_testimm(s1l,0x800000);
6294       emit_cmovne_reg(alt,addr);
6295     }
6296     if((source[i]&0x30000)==0x20000) // BC1FL
6297     {
6298       emit_testimm(s1l,0x800000);
6299       nottaken=(int)out;
6300       emit_jne(0);
6301     }
6302     if((source[i]&0x30000)==0x30000) // BC1TL
6303     {
6304       emit_testimm(s1l,0x800000);
6305       nottaken=(int)out;
6306       emit_jeq(0);
6307     }
6308   }
6309
6310   assert(i_regs->regmap[HOST_CCREG]==CCREG);
6311   wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6312   if(likely[i]||unconditional)
6313   {
6314     emit_movimm(ba[i],HOST_BTREG);
6315   }
6316   else if(addr!=HOST_BTREG)
6317   {
6318     emit_mov(addr,HOST_BTREG);
6319   }
6320   void *branch_addr=out;
6321   emit_jmp(0);
6322   int target_addr=start+i*4+5;
6323   void *stub=out;
6324   void *compiled_target_addr=check_addr(target_addr);
6325   emit_extjump_ds((int)branch_addr,target_addr);
6326   if(compiled_target_addr) {
6327     set_jump_target((int)branch_addr,(int)compiled_target_addr);
6328     add_link(target_addr,stub);
6329   }
6330   else set_jump_target((int)branch_addr,(int)stub);
6331   if(likely[i]) {
6332     // Not-taken path
6333     set_jump_target((int)nottaken,(int)out);
6334     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6335     void *branch_addr=out;
6336     emit_jmp(0);
6337     int target_addr=start+i*4+8;
6338     void *stub=out;
6339     void *compiled_target_addr=check_addr(target_addr);
6340     emit_extjump_ds((int)branch_addr,target_addr);
6341     if(compiled_target_addr) {
6342       set_jump_target((int)branch_addr,(int)compiled_target_addr);
6343       add_link(target_addr,stub);
6344     }
6345     else set_jump_target((int)branch_addr,(int)stub);
6346   }
6347 }
6348
6349 // Assemble the delay slot for the above
6350 static void pagespan_ds()
6351 {
6352   assem_debug("initial delay slot:");
6353   u_int vaddr=start+1;
6354   u_int page=(0x80000000^vaddr)>>12;
6355   u_int vpage=page;
6356   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[page^0x80000]^0x80000000)>>12;
6357   if(page>2048) page=2048+(page&2047);
6358   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
6359   if(vpage>2048) vpage=2048+(vpage&2047);
6360   ll_add(jump_dirty+vpage,vaddr,(void *)out);
6361   do_dirty_stub_ds();
6362   ll_add(jump_in+page,vaddr,(void *)out);
6363   assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6364   if(regs[0].regmap[HOST_CCREG]!=CCREG)
6365     wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6366   if(regs[0].regmap[HOST_BTREG]!=BTREG)
6367     emit_writeword(HOST_BTREG,(int)&branch_target);
6368   load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6369   address_generation(0,&regs[0],regs[0].regmap_entry);
6370   if(itype[0]==LOAD||itype[0]==LOADLR||itype[0]==STORE||itype[0]==STORELR||itype[0]==C1LS)
6371     load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,MMREG,ROREG);
6372   if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39)
6373     load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6374   cop1_usable=0;
6375   is_delayslot=0;
6376   switch(itype[0]) {
6377     case ALU:
6378       alu_assemble(0,&regs[0]);break;
6379     case IMM16:
6380       imm16_assemble(0,&regs[0]);break;
6381     case SHIFT:
6382       shift_assemble(0,&regs[0]);break;
6383     case SHIFTIMM:
6384       shiftimm_assemble(0,&regs[0]);break;
6385     case LOAD:
6386       load_assemble(0,&regs[0]);break;
6387     case LOADLR:
6388       loadlr_assemble(0,&regs[0]);break;
6389     case STORE:
6390       store_assemble(0,&regs[0]);break;
6391     case STORELR:
6392       storelr_assemble(0,&regs[0]);break;
6393     case COP0:
6394       cop0_assemble(0,&regs[0]);break;
6395     case COP1:
6396       cop1_assemble(0,&regs[0]);break;
6397     case C1LS:
6398       c1ls_assemble(0,&regs[0]);break;
6399     case FCONV:
6400       fconv_assemble(0,&regs[0]);break;
6401     case FLOAT:
6402       float_assemble(0,&regs[0]);break;
6403     case FCOMP:
6404       fcomp_assemble(0,&regs[0]);break;
6405     case MULTDIV:
6406       multdiv_assemble(0,&regs[0]);break;
6407     case MOV:
6408       mov_assemble(0,&regs[0]);break;
6409     case SYSCALL:
6410     case SPAN:
6411     case UJUMP:
6412     case RJUMP:
6413     case CJUMP:
6414     case SJUMP:
6415     case FJUMP:
6416       DebugMessage(M64MSG_VERBOSE, "Jump in the delay slot.  This is probably a bug.");
6417   }
6418   int btaddr=get_reg(regs[0].regmap,BTREG);
6419   if(btaddr<0) {
6420     btaddr=get_reg(regs[0].regmap,-1);
6421     emit_readword((int)&branch_target,btaddr);
6422   }
6423   assert(btaddr!=HOST_CCREG);
6424   if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6425 #ifdef HOST_IMM8
6426   emit_movimm(start+4,HOST_TEMPREG);
6427   emit_cmp(btaddr,HOST_TEMPREG);
6428 #else
6429   emit_cmpimm(btaddr,start+4);
6430 #endif
6431   int branch=(int)out;
6432   emit_jeq(0);
6433   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6434   emit_jmp(jump_vaddr_reg[btaddr]);
6435   set_jump_target(branch,(int)out);
6436   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6437   load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6438 }
6439
6440 // Basic liveness analysis for MIPS registers
6441 static void unneeded_registers(int istart,int iend,int r)
6442 {
6443   int i;
6444   uint64_t u,uu,b,bu;
6445   uint64_t temp_u,temp_uu;
6446   uint64_t tdep;
6447   if(iend==slen-1) {
6448     u=1;uu=1;
6449   }else{
6450     u=unneeded_reg[iend+1];
6451     uu=unneeded_reg_upper[iend+1];
6452     u=1;uu=1;
6453   }
6454   for (i=iend;i>=istart;i--)
6455   {
6456     //DebugMessage(M64MSG_VERBOSE, "unneeded registers i=%d (%d,%d) r=%d",i,istart,iend,r);
6457     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6458     {
6459       // If subroutine call, flag return address as a possible branch target
6460       if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6461
6462       if(ba[i]<start || ba[i]>=(start+slen*4))
6463       {
6464         // Branch out of this block, flush all regs
6465         u=1;
6466         uu=1;
6467         /* Hexagon hack
6468         if(itype[i]==UJUMP&&rt1[i]==31)
6469         {
6470           uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6471         }
6472         if(itype[i]==RJUMP&&rs1[i]==31)
6473         {
6474           uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6475         }
6476         if(start>0x80000400&&start<0x80800000) {
6477           if(itype[i]==UJUMP&&rt1[i]==31)
6478           {
6479             //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6480             uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6481           }
6482           if(itype[i]==RJUMP&&rs1[i]==31)
6483           {
6484             //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6485             uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6486           }
6487         }*/
6488         branch_unneeded_reg[i]=u;
6489         branch_unneeded_reg_upper[i]=uu;
6490         // Merge in delay slot
6491         tdep=(~uu>>rt1[i+1])&1;
6492         u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6493         uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6494         u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6495         uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6496         uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6497         u|=1;uu|=1;
6498         // If branch is "likely" (and conditional)
6499         // then we skip the delay slot on the fall-thru path
6500         if(likely[i]) {
6501           if(i<slen-1) {
6502             u&=unneeded_reg[i+2];
6503             uu&=unneeded_reg_upper[i+2];
6504           }
6505           else
6506           {
6507             u=1;
6508             uu=1;
6509           }
6510         }
6511       }
6512       else
6513       {
6514         // Internal branch, flag target
6515         bt[(ba[i]-start)>>2]=1;
6516         if(ba[i]<=start+i*4) {
6517           // Backward branch
6518           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6519           {
6520             // Unconditional branch
6521             temp_u=1;temp_uu=1;
6522           } else {
6523             // Conditional branch (not taken case)
6524             temp_u=unneeded_reg[i+2];
6525             temp_uu=unneeded_reg_upper[i+2];
6526           }
6527           // Merge in delay slot
6528           tdep=(~temp_uu>>rt1[i+1])&1;
6529           temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6530           temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6531           temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6532           temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6533           temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6534           temp_u|=1;temp_uu|=1;
6535           // If branch is "likely" (and conditional)
6536           // then we skip the delay slot on the fall-thru path
6537           if(likely[i]) {
6538             if(i<slen-1) {
6539               temp_u&=unneeded_reg[i+2];
6540               temp_uu&=unneeded_reg_upper[i+2];
6541             }
6542             else
6543             {
6544               temp_u=1;
6545               temp_uu=1;
6546             }
6547           }
6548           tdep=(~temp_uu>>rt1[i])&1;
6549           temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6550           temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6551           temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6552           temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6553           temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6554           temp_u|=1;temp_uu|=1;
6555           unneeded_reg[i]=temp_u;
6556           unneeded_reg_upper[i]=temp_uu;
6557           // Only go three levels deep.  This recursion can take an
6558           // excessive amount of time if there are a lot of nested loops.
6559           if(r<2) {
6560             unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6561           }else{
6562             unneeded_reg[(ba[i]-start)>>2]=1;
6563             unneeded_reg_upper[(ba[i]-start)>>2]=1;
6564           }
6565         } /*else*/ if(1) {
6566           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6567           {
6568             // Unconditional branch
6569             u=unneeded_reg[(ba[i]-start)>>2];
6570             uu=unneeded_reg_upper[(ba[i]-start)>>2];
6571             branch_unneeded_reg[i]=u;
6572             branch_unneeded_reg_upper[i]=uu;
6573         //u=1;
6574         //uu=1;
6575         //branch_unneeded_reg[i]=u;
6576         //branch_unneeded_reg_upper[i]=uu;
6577             // Merge in delay slot
6578             tdep=(~uu>>rt1[i+1])&1;
6579             u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6580             uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6581             u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6582             uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6583             uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6584             u|=1;uu|=1;
6585           } else {
6586             // Conditional branch
6587             b=unneeded_reg[(ba[i]-start)>>2];
6588             bu=unneeded_reg_upper[(ba[i]-start)>>2];
6589             branch_unneeded_reg[i]=b;
6590             branch_unneeded_reg_upper[i]=bu;
6591         //b=1;
6592         //bu=1;
6593         //branch_unneeded_reg[i]=b;
6594         //branch_unneeded_reg_upper[i]=bu;
6595             // Branch delay slot
6596             tdep=(~uu>>rt1[i+1])&1;
6597             b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6598             bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6599             b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6600             bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6601             bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6602             b|=1;bu|=1;
6603             // If branch is "likely" then we skip the
6604             // delay slot on the fall-thru path
6605             if(likely[i]) {
6606               u=b;
6607               uu=bu;
6608               if(i<slen-1) {
6609                 u&=unneeded_reg[i+2];
6610                 uu&=unneeded_reg_upper[i+2];
6611         //u=1;
6612         //uu=1;
6613               }
6614             } else {
6615               u&=b;
6616               uu&=bu;
6617         //u=1;
6618         //uu=1;
6619             }
6620             if(i<slen-1) {
6621               branch_unneeded_reg[i]&=unneeded_reg[i+2];
6622               branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6623         //branch_unneeded_reg[i]=1;
6624         //branch_unneeded_reg_upper[i]=1;
6625             } else {
6626               branch_unneeded_reg[i]=1;
6627               branch_unneeded_reg_upper[i]=1;
6628             }
6629           }
6630         }
6631       }
6632     }
6633     else if(itype[i]==SYSCALL)
6634     {
6635       // SYSCALL instruction (software interrupt)
6636       u=1;
6637       uu=1;
6638     }
6639     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6640     {
6641       // ERET instruction (return from interrupt)
6642       u=1;
6643       uu=1;
6644     }
6645     //u=uu=1; // DEBUG
6646     tdep=(~uu>>rt1[i])&1;
6647     // Written registers are unneeded
6648     u|=1LL<<rt1[i];
6649     u|=1LL<<rt2[i];
6650     uu|=1LL<<rt1[i];
6651     uu|=1LL<<rt2[i];
6652     // Accessed registers are needed
6653     u&=~(1LL<<rs1[i]);
6654     u&=~(1LL<<rs2[i]);
6655     uu&=~(1LL<<us1[i]);
6656     uu&=~(1LL<<us2[i]);
6657     // Source-target dependencies
6658     uu&=~(tdep<<dep1[i]);
6659     uu&=~(tdep<<dep2[i]);
6660     // R0 is always unneeded
6661     u|=1;uu|=1;
6662     // Save it
6663     unneeded_reg[i]=u;
6664     unneeded_reg_upper[i]=uu;
6665     /*
6666     DebugMessage(M64MSG_VERBOSE, "ur (%d,%d) %x: ",istart,iend,start+i*4);
6667     DebugMessage(M64MSG_VERBOSE, "U:");
6668     int r;
6669     for(r=1;r<=CCREG;r++) {
6670       if((unneeded_reg[i]>>r)&1) {
6671         if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI");
6672         else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO");
6673         else DebugMessage(M64MSG_VERBOSE, " r%d",r);
6674       }
6675     }
6676     DebugMessage(M64MSG_VERBOSE, " UU:");
6677     for(r=1;r<=CCREG;r++) {
6678       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6679         if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI");
6680         else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO");
6681         else DebugMessage(M64MSG_VERBOSE, " r%d",r);
6682       }
6683     }*/
6684   }
6685 }
6686
6687 // Identify registers which are likely to contain 32-bit values
6688 // This is used to predict whether any branches will jump to a
6689 // location with 64-bit values in registers.
6690 static void provisional_32bit()
6691 {
6692   int i,j;
6693   uint64_t is32=1;
6694   uint64_t lastbranch=1;
6695
6696   for(i=0;i<slen;i++)
6697   {
6698     if(i>0) {
6699       if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
6700         if(i>1) is32=lastbranch;
6701         else is32=1;
6702       }
6703     }
6704     if(i>1)
6705     {
6706       if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
6707         if(likely[i-2]) {
6708           if(i>2) is32=lastbranch;
6709           else is32=1;
6710         }
6711       }
6712       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
6713       {
6714         if(rs1[i-2]==0||rs2[i-2]==0)
6715         {
6716           if(rs1[i-2]) {
6717             is32|=1LL<<rs1[i-2];
6718           }
6719           if(rs2[i-2]) {
6720             is32|=1LL<<rs2[i-2];
6721           }
6722         }
6723       }
6724     }
6725     // If something jumps here with 64-bit values
6726     // then promote those registers to 64 bits
6727     if(bt[i])
6728     {
6729       uint64_t temp_is32=is32;
6730       for(j=i-1;j>=0;j--)
6731       {
6732         if(ba[j]==start+i*4)
6733           //temp_is32&=branch_regs[j].is32;
6734           temp_is32&=p32[j];
6735       }
6736       for(j=i;j<slen;j++)
6737       {
6738         if(ba[j]==start+i*4)
6739           temp_is32=1;
6740       }
6741       is32=temp_is32;
6742     }
6743     int type=itype[i];
6744     int op=opcode[i];
6745     int op2=opcode2[i];
6746     int rt=rt1[i];
6747     int s1=rs1[i];
6748     int s2=rs2[i];
6749     if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
6750       // Branches don't write registers, consider the delay slot instead.
6751       type=itype[i+1];
6752       op=opcode[i+1];
6753       op2=opcode2[i+1];
6754       rt=rt1[i+1];
6755       s1=rs1[i+1];
6756       s2=rs2[i+1];
6757       lastbranch=is32;
6758     }
6759     switch(type) {
6760       case LOAD:
6761         if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
6762            opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
6763           is32&=~(1LL<<rt);
6764         else
6765           is32|=1LL<<rt;
6766         break;
6767       case STORE:
6768       case STORELR:
6769         break;
6770       case LOADLR:
6771         if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
6772         if(op==0x22) is32|=1LL<<rt; // LWL
6773         break;
6774       case IMM16:
6775         if (op==0x08||op==0x09|| // ADDI/ADDIU
6776             op==0x0a||op==0x0b|| // SLTI/SLTIU
6777             op==0x0c|| // ANDI
6778             op==0x0f)  // LUI
6779         {
6780           is32|=1LL<<rt;
6781         }
6782         if(op==0x18||op==0x19) { // DADDI/DADDIU
6783           is32&=~(1LL<<rt);
6784           //if(imm[i]==0)
6785           //  is32|=((is32>>s1)&1LL)<<rt;
6786         }
6787         if(op==0x0d||op==0x0e) { // ORI/XORI
6788           uint64_t sr=((is32>>s1)&1LL);
6789           is32&=~(1LL<<rt);
6790           is32|=sr<<rt;
6791         }
6792         break;
6793       case UJUMP:
6794         break;
6795       case RJUMP:
6796         break;
6797       case CJUMP:
6798         break;
6799       case SJUMP:
6800         break;
6801       case FJUMP:
6802         break;
6803       case ALU:
6804         if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
6805           is32|=1LL<<rt;
6806         }
6807         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
6808           is32|=1LL<<rt;
6809         }
6810         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
6811           uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
6812           is32&=~(1LL<<rt);
6813           is32|=sr<<rt;
6814         }
6815         else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
6816           if(s1==0&&s2==0) {
6817             is32|=1LL<<rt;
6818           }
6819           else if(s2==0) {
6820             uint64_t sr=((is32>>s1)&1LL);
6821             is32&=~(1LL<<rt);
6822             is32|=sr<<rt;
6823           }
6824           else if(s1==0) {
6825             uint64_t sr=((is32>>s2)&1LL);
6826             is32&=~(1LL<<rt);
6827             is32|=sr<<rt;
6828           }
6829           else {
6830             is32&=~(1LL<<rt);
6831           }
6832         }
6833         else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
6834           if(s1==0&&s2==0) {
6835             is32|=1LL<<rt;
6836           }
6837           else if(s2==0) {
6838             uint64_t sr=((is32>>s1)&1LL);
6839             is32&=~(1LL<<rt);
6840             is32|=sr<<rt;
6841           }
6842           else {
6843             is32&=~(1LL<<rt);
6844           }
6845         }
6846         break;
6847       case MULTDIV:
6848         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
6849           is32&=~((1LL<<HIREG)|(1LL<<LOREG));
6850         }
6851         else {
6852           is32|=(1LL<<HIREG)|(1LL<<LOREG);
6853         }
6854         break;
6855       case MOV:
6856         {
6857           uint64_t sr=((is32>>s1)&1LL);
6858           is32&=~(1LL<<rt);
6859           is32|=sr<<rt;
6860         }
6861         break;
6862       case SHIFT:
6863         if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
6864         else is32|=1LL<<rt; // SLLV/SRLV/SRAV
6865         break;
6866       case SHIFTIMM:
6867         is32|=1LL<<rt;
6868         // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
6869         if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
6870         break;
6871       case COP0:
6872         if(op2==0) is32|=1LL<<rt; // MFC0
6873         break;
6874       case COP1:
6875         if(op2==0) is32|=1LL<<rt; // MFC1
6876         if(op2==1) is32&=~(1LL<<rt); // DMFC1
6877         if(op2==2) is32|=1LL<<rt; // CFC1
6878         break;
6879       case C1LS:
6880         break;
6881       case FLOAT:
6882       case FCONV:
6883         break;
6884       case FCOMP:
6885         break;
6886       case SYSCALL:
6887         break;
6888       default:
6889         break;
6890     }
6891     is32|=1;
6892     p32[i]=is32;
6893
6894     if(i>0)
6895     {
6896       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
6897       {
6898         if(rt1[i-1]==31) // JAL/JALR
6899         {
6900           // Subroutine call will return here, don't alloc any registers
6901           is32=1;
6902         }
6903         else if(i+1<slen)
6904         {
6905           // Internal branch will jump here, match registers to caller
6906           is32=0x3FFFFFFFFLL;
6907         }
6908       }
6909     }
6910   }
6911 }
6912
6913 // Identify registers which may be assumed to contain 32-bit values
6914 // and where optimizations will rely on this.
6915 // This is used to determine whether backward branches can safely
6916 // jump to a location with 64-bit values in registers.
6917 static void provisional_r32()
6918 {
6919   u_int r32=0;
6920   int i;
6921
6922   for (i=slen-1;i>=0;i--)
6923   {
6924     int hr;
6925     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6926     {
6927       if(ba[i]<start || ba[i]>=(start+slen*4))
6928       {
6929         // Branch out of this block, don't need anything
6930         r32=0;
6931       }
6932       else
6933       {
6934         // Internal branch
6935         // Need whatever matches the target
6936         // (and doesn't get overwritten by the delay slot instruction)
6937         r32=0;
6938         int t=(ba[i]-start)>>2;
6939         if(ba[i]>start+i*4) {
6940           // Forward branch
6941           //if(!(requires_32bit[t]&~regs[i].was32))
6942           //  r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
6943           if(!(pr32[t]&~regs[i].was32))
6944             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
6945         }else{
6946           // Backward branch
6947           if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
6948             r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
6949         }
6950       }
6951       // Conditional branch may need registers for following instructions
6952       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
6953       {
6954         if(i<slen-2) {
6955           //r32|=requires_32bit[i+2];
6956           r32|=pr32[i+2];
6957           r32&=regs[i].was32;
6958           // Mark this address as a branch target since it may be called
6959           // upon return from interrupt
6960           //bt[i+2]=1;
6961         }
6962       }
6963       // Merge in delay slot
6964       if(!likely[i]) {
6965         // These are overwritten unless the branch is "likely"
6966         // and the delay slot is nullified if not taken
6967         r32&=~(1LL<<rt1[i+1]);
6968         r32&=~(1LL<<rt2[i+1]);
6969       }
6970       // Assume these are needed (delay slot)
6971       if(us1[i+1]>0)
6972       {
6973         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
6974       }
6975       if(us2[i+1]>0)
6976       {
6977         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
6978       }
6979       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
6980       {
6981         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
6982       }
6983       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
6984       {
6985         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
6986       }
6987     }
6988     else if(itype[i]==SYSCALL)
6989     {
6990       // SYSCALL instruction (software interrupt)
6991       r32=0;
6992     }
6993     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6994     {
6995       // ERET instruction (return from interrupt)
6996       r32=0;
6997     }
6998     // Check 32 bits
6999     r32&=~(1LL<<rt1[i]);
7000     r32&=~(1LL<<rt2[i]);
7001     if(us1[i]>0)
7002     {
7003       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7004     }
7005     if(us2[i]>0)
7006     {
7007       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7008     }
7009     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7010     {
7011       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7012     }
7013     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7014     {
7015       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7016     }
7017     //requires_32bit[i]=r32;
7018     pr32[i]=r32;
7019
7020     // Dirty registers which are 32-bit, require 32-bit input
7021     // as they will be written as 32-bit values
7022     for(hr=0;hr<HOST_REGS;hr++)
7023     {
7024       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7025         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7026           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7027           pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7028           //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7029         }
7030       }
7031     }
7032   }
7033 }
7034
7035 // Write back dirty registers as soon as we will no longer modify them,
7036 // so that we don't end up with lots of writes at the branches.
7037 static void clean_registers(int istart,int iend,int wr)
7038 {
7039   int i;
7040   int r;
7041   u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7042   u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7043   if(iend==slen-1) {
7044     will_dirty_i=will_dirty_next=0;
7045     wont_dirty_i=wont_dirty_next=0;
7046   }else{
7047     will_dirty_i=will_dirty_next=will_dirty[iend+1];
7048     wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7049   }
7050   for (i=iend;i>=istart;i--)
7051   {
7052     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7053     {
7054       if(ba[i]<start || ba[i]>=(start+slen*4))
7055       {
7056         // Branch out of this block, flush all regs
7057         if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7058         {
7059           // Unconditional branch
7060           will_dirty_i=0;
7061           wont_dirty_i=0;
7062           // Merge in delay slot (will dirty)
7063           for(r=0;r<HOST_REGS;r++) {
7064             if(r!=EXCLUDE_REG) {
7065               if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7066               if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7067               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7068               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7069               if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7070               if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7071               if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7072               if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7073               if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7074               if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7075               if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7076               if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7077               if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7078               if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7079             }
7080           }
7081         }
7082         else
7083         {
7084           // Conditional branch
7085           will_dirty_i=0;
7086           wont_dirty_i=wont_dirty_next;
7087           // Merge in delay slot (will dirty)
7088           for(r=0;r<HOST_REGS;r++) {
7089             if(r!=EXCLUDE_REG) {
7090               if(!likely[i]) {
7091                 // Might not dirty if likely branch is not taken
7092                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7093                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7094                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7095                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7096                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7097                 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7098                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7099                 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7100                 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7101                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7102                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7103                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7104                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7105                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7106               }
7107             }
7108           }
7109         }
7110         // Merge in delay slot (wont dirty)
7111         for(r=0;r<HOST_REGS;r++) {
7112           if(r!=EXCLUDE_REG) {
7113             if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7114             if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7115             if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7116             if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7117             if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7118             if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7119             if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7120             if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7121             if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7122             if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7123           }
7124         }
7125         if(wr) {
7126           #ifndef DESTRUCTIVE_WRITEBACK
7127           branch_regs[i].dirty&=wont_dirty_i;
7128           #endif
7129           branch_regs[i].dirty|=will_dirty_i;
7130         }
7131       }
7132       else
7133       {
7134         // Internal branch
7135         if(ba[i]<=start+i*4) {
7136           // Backward branch
7137           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7138           {
7139             // Unconditional branch
7140             temp_will_dirty=0;
7141             temp_wont_dirty=0;
7142             // Merge in delay slot (will dirty)
7143             for(r=0;r<HOST_REGS;r++) {
7144               if(r!=EXCLUDE_REG) {
7145                 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7146                 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7147                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7148                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7149                 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7150                 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7151                 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7152                 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7153                 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7154                 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7155                 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7156                 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7157                 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7158                 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7159               }
7160             }
7161           } else {
7162             // Conditional branch (not taken case)
7163             temp_will_dirty=will_dirty_next;
7164             temp_wont_dirty=wont_dirty_next;
7165             // Merge in delay slot (will dirty)
7166             for(r=0;r<HOST_REGS;r++) {
7167               if(r!=EXCLUDE_REG) {
7168                 if(!likely[i]) {
7169                   // Will not dirty if likely branch is not taken
7170                   if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7171                   if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7172                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7173                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7174                   if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7175                   if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7176                   if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7177                   //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7178                   //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7179                   if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7180                   if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7181                   if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7182                   if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7183                   if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7184                 }
7185               }
7186             }
7187           }
7188           // Merge in delay slot (wont dirty)
7189           for(r=0;r<HOST_REGS;r++) {
7190             if(r!=EXCLUDE_REG) {
7191               if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7192               if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7193               if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7194               if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7195               if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7196               if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7197               if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7198               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7199               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7200               if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7201             }
7202           }
7203           // Deal with changed mappings
7204           if(i<iend) {
7205             for(r=0;r<HOST_REGS;r++) {
7206               if(r!=EXCLUDE_REG) {
7207                 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7208                   temp_will_dirty&=~(1<<r);
7209                   temp_wont_dirty&=~(1<<r);
7210                   if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7211                     temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7212                     temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7213                   } else {
7214                     temp_will_dirty|=1<<r;
7215                     temp_wont_dirty|=1<<r;
7216                   }
7217                 }
7218               }
7219             }
7220           }
7221           if(wr) {
7222             will_dirty[i]=temp_will_dirty;
7223             wont_dirty[i]=temp_wont_dirty;
7224             clean_registers((ba[i]-start)>>2,i-1,0);
7225           }else{
7226             // Limit recursion.  It can take an excessive amount
7227             // of time if there are a lot of nested loops.
7228             will_dirty[(ba[i]-start)>>2]=0;
7229             wont_dirty[(ba[i]-start)>>2]=-1;
7230           }
7231         }
7232         /*else*/ if(1)
7233         {
7234           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7235           {
7236             // Unconditional branch
7237             will_dirty_i=0;
7238             wont_dirty_i=0;
7239           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7240             for(r=0;r<HOST_REGS;r++) {
7241               if(r!=EXCLUDE_REG) {
7242                 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7243                   will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7244                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7245                 }
7246                 if(branch_regs[i].regmap[r]>=0) {
7247                   will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7248                   wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7249                 }
7250               }
7251             }
7252           //}
7253             // Merge in delay slot
7254             for(r=0;r<HOST_REGS;r++) {
7255               if(r!=EXCLUDE_REG) {
7256                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7257                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7258                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7259                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7260                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7261                 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7262                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7263                 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7264                 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7265                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7266                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7267                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7268                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7269                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7270               }
7271             }
7272           } else {
7273             // Conditional branch
7274             will_dirty_i=will_dirty_next;
7275             wont_dirty_i=wont_dirty_next;
7276           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7277             for(r=0;r<HOST_REGS;r++) {
7278               if(r!=EXCLUDE_REG) {
7279                 signed char target_reg=branch_regs[i].regmap[r];
7280                 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7281                   will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7282                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7283                 }
7284                 else if(target_reg>=0) {
7285                   will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7286                   wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7287                 }
7288                 // Treat delay slot as part of branch too
7289                 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7290                   will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7291                   wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7292                 }
7293                 else
7294                 {
7295                   will_dirty[i+1]&=~(1<<r);
7296                 }*/
7297               }
7298             }
7299           //}
7300             // Merge in delay slot
7301             for(r=0;r<HOST_REGS;r++) {
7302               if(r!=EXCLUDE_REG) {
7303                 if(!likely[i]) {
7304                   // Might not dirty if likely branch is not taken
7305                   if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7306                   if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7307                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7308                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7309                   if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7310                   if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7311                   if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7312                   //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7313                   //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7314                   if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7315                   if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7316                   if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7317                   if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7318                   if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7319                 }
7320               }
7321             }
7322           }
7323           // Merge in delay slot (won't dirty)
7324           for(r=0;r<HOST_REGS;r++) {
7325             if(r!=EXCLUDE_REG) {
7326               if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7327               if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7328               if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7329               if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7330               if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7331               if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7332               if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7333               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7334               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7335               if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7336             }
7337           }
7338           if(wr) {
7339             #ifndef DESTRUCTIVE_WRITEBACK
7340             branch_regs[i].dirty&=wont_dirty_i;
7341             #endif
7342             branch_regs[i].dirty|=will_dirty_i;
7343           }
7344         }
7345       }
7346     }
7347     else if(itype[i]==SYSCALL)
7348     {
7349       // SYSCALL instruction (software interrupt)
7350       will_dirty_i=0;
7351       wont_dirty_i=0;
7352     }
7353     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7354     {
7355       // ERET instruction (return from interrupt)
7356       will_dirty_i=0;
7357       wont_dirty_i=0;
7358     }
7359     will_dirty_next=will_dirty_i;
7360     wont_dirty_next=wont_dirty_i;
7361     for(r=0;r<HOST_REGS;r++) {
7362       if(r!=EXCLUDE_REG) {
7363         if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7364         if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7365         if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7366         if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7367         if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7368         if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7369         if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7370         if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7371         if(i>istart) {
7372           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7373           {
7374             // Don't store a register immediately after writing it,
7375             // may prevent dual-issue.
7376             if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7377             if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7378           }
7379         }
7380       }
7381     }
7382     // Save it
7383     will_dirty[i]=will_dirty_i;
7384     wont_dirty[i]=wont_dirty_i;
7385     // Mark registers that won't be dirtied as not dirty
7386     if(wr) {
7387       /*DebugMessage(M64MSG_VERBOSE, "wr (%d,%d) %x will:",istart,iend,start+i*4);
7388       for(r=0;r<HOST_REGS;r++) {
7389         if((will_dirty_i>>r)&1) {
7390           DebugMessage(M64MSG_VERBOSE, " r%d",r);
7391         }
7392       }*/
7393
7394       //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7395         regs[i].dirty|=will_dirty_i;
7396         #ifndef DESTRUCTIVE_WRITEBACK
7397         regs[i].dirty&=wont_dirty_i;
7398         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7399         {
7400           if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7401             for(r=0;r<HOST_REGS;r++) {
7402               if(r!=EXCLUDE_REG) {
7403                 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7404                   regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7405                 }else {/*DebugMessage(M64MSG_VERBOSE, "i: %x (%d) mismatch(+2): %d",start+i*4,i,r); / *assert(!((wont_dirty_i>>r)&1));*/}
7406               }
7407             }
7408           }
7409         }
7410         else
7411         {
7412           if(i<iend) {
7413             for(r=0;r<HOST_REGS;r++) {
7414               if(r!=EXCLUDE_REG) {
7415                 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7416                   regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7417                 }else {/*DebugMessage(M64MSG_VERBOSE, "i: %x (%d) mismatch(+1): %d",start+i*4,i,r);/ *assert(!((wont_dirty_i>>r)&1));*/}
7418               }
7419             }
7420           }
7421         }
7422         #endif
7423       //}
7424     }
7425     // Deal with changed mappings
7426     temp_will_dirty=will_dirty_i;
7427     temp_wont_dirty=wont_dirty_i;
7428     for(r=0;r<HOST_REGS;r++) {
7429       if(r!=EXCLUDE_REG) {
7430         int nr;
7431         if(regs[i].regmap[r]==regmap_pre[i][r]) {
7432           if(wr) {
7433             #ifndef DESTRUCTIVE_WRITEBACK
7434             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7435             #endif
7436             regs[i].wasdirty|=will_dirty_i&(1<<r);
7437           }
7438         }
7439         else if((nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7440           // Register moved to a different register
7441           will_dirty_i&=~(1<<r);
7442           wont_dirty_i&=~(1<<r);
7443           will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7444           wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7445           if(wr) {
7446             #ifndef DESTRUCTIVE_WRITEBACK
7447             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7448             #endif
7449             regs[i].wasdirty|=will_dirty_i&(1<<r);
7450           }
7451         }
7452         else {
7453           will_dirty_i&=~(1<<r);
7454           wont_dirty_i&=~(1<<r);
7455           if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7456             will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7457             wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7458           } else {
7459             wont_dirty_i|=1<<r;
7460             /*DebugMessage(M64MSG_VERBOSE, "i: %x (%d) mismatch: %d",start+i*4,i,r);/ *assert(!((will_dirty>>r)&1));*/
7461           }
7462         }
7463       }
7464     }
7465   }
7466 }
7467
7468 #ifdef ASSEM_DEBUG
7469   /* disassembly */
7470 static void disassemble_inst(int i)
7471 {
7472     if (bt[i]) DebugMessage(M64MSG_VERBOSE, "*"); else DebugMessage(M64MSG_VERBOSE, " ");
7473     switch(itype[i]) {
7474       case UJUMP:
7475         printf (" %x: %s %8x",start+i*4,insn[i],ba[i]);break;
7476       case CJUMP:
7477         printf (" %x: %s r%d,r%d,%8x",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7478       case SJUMP:
7479         printf (" %x: %s r%d,%8x",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7480       case FJUMP:
7481         printf (" %x: %s %8x",start+i*4,insn[i],ba[i]);break;
7482       case RJUMP:
7483         if ((opcode2[i]&1)&&rt1[i]!=31)
7484           printf (" %x: %s r%d,r%d",start+i*4,insn[i],rt1[i],rs1[i]);
7485         else
7486           printf (" %x: %s r%d",start+i*4,insn[i],rs1[i]);
7487         break;
7488       case SPAN:
7489         printf (" %x: %s (pagespan) r%d,r%d,%8x",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7490       case IMM16:
7491         if(opcode[i]==0xf) //LUI
7492           printf (" %x: %s r%d,%4x0000",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7493         else
7494           printf (" %x: %s r%d,r%d,%d",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7495         break;
7496       case LOAD:
7497       case LOADLR:
7498         printf (" %x: %s r%d,r%d+%x",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7499         break;
7500       case STORE:
7501       case STORELR:
7502         printf (" %x: %s r%d,r%d+%x",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7503         break;
7504       case ALU:
7505       case SHIFT:
7506         printf (" %x: %s r%d,r%d,r%d",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7507         break;
7508       case MULTDIV:
7509         printf (" %x: %s r%d,r%d",start+i*4,insn[i],rs1[i],rs2[i]);
7510         break;
7511       case SHIFTIMM:
7512         printf (" %x: %s r%d,r%d,%d",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7513         break;
7514       case MOV:
7515         if((opcode2[i]&0x1d)==0x10)
7516           printf (" %x: %s r%d",start+i*4,insn[i],rt1[i]);
7517         else if((opcode2[i]&0x1d)==0x11)
7518           printf (" %x: %s r%d",start+i*4,insn[i],rs1[i]);
7519         else
7520           printf (" %x: %s",start+i*4,insn[i]);
7521         break;
7522       case COP0:
7523         if(opcode2[i]==0)
7524           printf (" %x: %s r%d,cpr0[%d]",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7525         else if(opcode2[i]==4)
7526           printf (" %x: %s r%d,cpr0[%d]",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7527         else printf (" %x: %s",start+i*4,insn[i]);
7528         break;
7529       case COP1:
7530         if(opcode2[i]<3)
7531           printf (" %x: %s r%d,cpr1[%d]",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7532         else if(opcode2[i]>3)
7533           printf (" %x: %s r%d,cpr1[%d]",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7534         else printf (" %x: %s",start+i*4,insn[i]);
7535         break;
7536       case C1LS:
7537         printf (" %x: %s cpr1[%d],r%d+%x",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7538         break;
7539       default:
7540         //printf (" %s %8x",insn[i],source[i]);
7541         printf (" %x: %s",start+i*4,insn[i]);
7542     }
7543 }
7544 #endif
7545
7546 void new_dynarec_init()
7547 {
7548   DebugMessage(M64MSG_INFO, "Init new dynarec");
7549
7550 #if NEW_DYNAREC == NEW_DYNAREC_ARM
7551   if ((base_addr = mmap ((u_char *)BASE_ADDR, 1<<TARGET_SIZE_2,
7552             PROT_READ | PROT_WRITE | PROT_EXEC,
7553             MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7554             -1, 0)) <= 0) {DebugMessage(M64MSG_ERROR, "mmap() failed");}
7555 #else
7556   if ((base_addr = mmap (NULL, 1<<TARGET_SIZE_2,
7557             PROT_READ | PROT_WRITE | PROT_EXEC,
7558             MAP_PRIVATE | MAP_ANONYMOUS,
7559             -1, 0)) <= 0) {DebugMessage(M64MSG_ERROR, "mmap() failed");}
7560 #endif
7561   out=(u_char *)base_addr;
7562
7563   rdword=&readmem_dword;
7564   fake_pc.f.r.rs=(long long int *)&readmem_dword;
7565   fake_pc.f.r.rt=(long long int *)&readmem_dword;
7566   fake_pc.f.r.rd=(long long int *)&readmem_dword;
7567   int n;
7568   for(n=0x80000;n<0x80800;n++)
7569     invalid_code[n]=1;
7570   for(n=0;n<65536;n++)
7571     hash_table[n][0]=hash_table[n][2]=-1;
7572   memset(mini_ht,-1,sizeof(mini_ht));
7573   memset(restore_candidate,0,sizeof(restore_candidate));
7574   copy=shadow;
7575   expirep=16384; // Expiry pointer, +2 blocks
7576   pending_exception=0;
7577   literalcount=0;
7578 #ifdef HOST_IMM8
7579   // Copy this into local area so we don't have to put it in every literal pool
7580   invc_ptr=invalid_code;
7581 #endif
7582   stop_after_jal=0;
7583   // TLB
7584   using_tlb=0;
7585   for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7586     memory_map[n]=-1;
7587   for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7588     memory_map[n]=((u_int)rdram-0x80000000)>>2;
7589   for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7590     memory_map[n]=-1;
7591   for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7592     writemem[n] = write_nomem_new;
7593     writememb[n] = write_nomemb_new;
7594     writememh[n] = write_nomemh_new;
7595     writememd[n] = write_nomemd_new;
7596     readmem[n] = read_nomem_new;
7597     readmemb[n] = read_nomemb_new;
7598     readmemh[n] = read_nomemh_new;
7599     readmemd[n] = read_nomemd_new;
7600   }
7601   for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7602     writemem[n] = write_rdram_new;
7603     writememb[n] = write_rdramb_new;
7604     writememh[n] = write_rdramh_new;
7605     writememd[n] = write_rdramd_new;
7606   }
7607   for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7608     writemem[n] = write_nomem_new;
7609     writememb[n] = write_nomemb_new;
7610     writememh[n] = write_nomemh_new;
7611     writememd[n] = write_nomemd_new;
7612     readmem[n] = read_nomem_new;
7613     readmemb[n] = read_nomemb_new;
7614     readmemh[n] = read_nomemh_new;
7615     readmemd[n] = read_nomemd_new;
7616   }
7617   tlb_hacks();
7618   arch_init();
7619 }
7620
7621 void new_dynarec_cleanup()
7622 {
7623   int n;
7624   if (munmap (base_addr, 1<<TARGET_SIZE_2) < 0) {DebugMessage(M64MSG_ERROR, "munmap() failed");}
7625   for(n=0;n<4096;n++) ll_clear(jump_in+n);
7626   for(n=0;n<4096;n++) ll_clear(jump_out+n);
7627   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7628   #ifdef ROM_COPY
7629   if (munmap (ROM_COPY, 67108864) < 0) {DebugMessage(M64MSG_ERROR, "munmap() failed");}
7630   #endif
7631 }
7632
7633 int new_recompile_block(int addr)
7634 {
7635 /*
7636   if(addr==0x800cd050) {
7637     int block;
7638     for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7639     int n;
7640     for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7641   }
7642 */
7643   //if(Count==365117028) tracedebug=1;
7644   assem_debug("NOTCOMPILED: addr = %x -> %x", (int)addr, (int)out);
7645 #if defined (COUNT_NOTCOMPILEDS )
7646   notcompiledCount++;
7647   log_message( "notcompiledCount=%i", notcompiledCount );
7648 #endif
7649   //DebugMessage(M64MSG_VERBOSE, "NOTCOMPILED: addr = %x -> %x", (int)addr, (int)out);
7650   //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (compile %x)",Count,next_interupt,addr);
7651   //if(debug)
7652   //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (checksum %x)",Count,next_interupt,mchecksum());
7653   //DebugMessage(M64MSG_VERBOSE, "fpu mapping=%x enabled=%x",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7654   /*if(Count>=312978186) {
7655     rlist();
7656   }*/
7657   //rlist();
7658   start = (u_int)addr&~3;
7659   //assert(((u_int)addr&1)==0);
7660   if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
7661     source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
7662     pagelimit = 0xa4001000;
7663   }
7664   else if ((int)addr >= 0x80000000 && (int)addr < 0x80800000) {
7665     source = (u_int *)((u_int)rdram+start-0x80000000);
7666     pagelimit = 0x80800000;
7667   }
7668   else if ((signed int)addr >= (signed int)0xC0000000) {
7669     //DebugMessage(M64MSG_VERBOSE, "addr=%x mm=%x",(u_int)addr,(memory_map[start>>12]<<2));
7670     //if(tlb_LUT_r[start>>12])
7671       //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
7672     if((signed int)memory_map[start>>12]>=0) {
7673       source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
7674       pagelimit=(start+4096)&0xFFFFF000;
7675       int map=memory_map[start>>12];
7676       int i;
7677       for(i=0;i<5;i++) {
7678         //DebugMessage(M64MSG_VERBOSE, "start: %x next: %x",map,memory_map[pagelimit>>12]);
7679         if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
7680       }
7681       assem_debug("pagelimit=%x",pagelimit);
7682       assem_debug("mapping=%x (%x)",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
7683     }
7684     else {
7685       assem_debug("Compile at unmapped memory address: %x ", (int)addr);
7686       //assem_debug("start: %x next: %x",memory_map[start>>12],memory_map[(start+4096)>>12]);
7687       return 1; // Caller will invoke exception handler
7688     }
7689     //DebugMessage(M64MSG_VERBOSE, "source= %x",(int)source);
7690   }
7691   else {
7692     //DebugMessage(M64MSG_VERBOSE, "Compile at bogus memory address: %x ", (int)addr);
7693     log_message("Compile at bogus memory address: %x", (int)addr);
7694     exit(1);
7695   }
7696
7697   /* Pass 1: disassemble */
7698   /* Pass 2: register dependencies, branch targets */
7699   /* Pass 3: register allocation */
7700   /* Pass 4: branch dependencies */
7701   /* Pass 5: pre-alloc */
7702   /* Pass 6: optimize clean/dirty state */
7703   /* Pass 7: flag 32-bit registers */
7704   /* Pass 8: assembly */
7705   /* Pass 9: linker */
7706   /* Pass 10: garbage collection / free memory */
7707
7708   int i,j;
7709   int done=0;
7710   unsigned int type,op,op2;
7711
7712   //DebugMessage(M64MSG_VERBOSE, "addr = %x source = %x %x", addr,source,source[0]);
7713
7714   /* Pass 1 disassembly */
7715
7716   for(i=0;!done;i++) {
7717     bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
7718     minimum_free_regs[i]=0;
7719     opcode[i]=op=source[i]>>26;
7720     switch(op)
7721     {
7722       case 0x00: strcpy(insn[i],"special"); type=NI;
7723         op2=source[i]&0x3f;
7724         switch(op2)
7725         {
7726           case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7727           case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7728           case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7729           case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7730           case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7731           case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7732           case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7733           case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7734           case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7735           case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7736           case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7737           case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7738           case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7739           case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7740           case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
7741           case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7742           case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7743           case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7744           case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7745           case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7746           case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7747           case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
7748           case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7749           case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7750           case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7751           case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7752           case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7753           case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7754           case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7755           case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7756           case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7757           case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7758           case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7759           case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7760           case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7761           case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
7762           case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7763           case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7764           case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7765           case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
7766           case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7767           case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7768           case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7769           case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7770           case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7771           case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7772           case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7773           case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7774           case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7775           case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7776           case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7777           case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7778         }
7779         break;
7780       case 0x01: strcpy(insn[i],"regimm"); type=NI;
7781         op2=(source[i]>>16)&0x1f;
7782         switch(op2)
7783         {
7784           case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7785           case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
7786           case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7787           case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7788           case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7789           case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7790           case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7791           case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7792           case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7793           case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
7794           case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7795           case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
7796           case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7797           case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
7798         }
7799         break;
7800       case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7801       case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7802       case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7803       case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7804       case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7805       case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7806       case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7807       case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7808       case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
7809       case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
7810       case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
7811       case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
7812       case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
7813       case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
7814       case 0x10: strcpy(insn[i],"cop0"); type=NI;
7815         op2=(source[i]>>21)&0x1f;
7816         switch(op2)
7817         {
7818           case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
7819           case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
7820           case 0x10: strcpy(insn[i],"tlb"); type=NI;
7821           switch(source[i]&0x3f)
7822           {
7823             case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
7824             case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
7825             case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
7826             case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
7827             case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
7828           }
7829         }
7830         break;
7831       case 0x11: strcpy(insn[i],"cop1"); type=NI;
7832         op2=(source[i]>>21)&0x1f;
7833         switch(op2)
7834         {
7835           case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
7836           case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
7837           case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
7838           case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
7839           case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
7840           case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
7841           case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
7842           switch((source[i]>>16)&0x3)
7843           {
7844             case 0x00: strcpy(insn[i],"BC1F"); break;
7845             case 0x01: strcpy(insn[i],"BC1T"); break;
7846             case 0x02: strcpy(insn[i],"BC1FL"); break;
7847             case 0x03: strcpy(insn[i],"BC1TL"); break;
7848           }
7849           break;
7850           case 0x10: strcpy(insn[i],"C1.S"); type=NI;
7851           switch(source[i]&0x3f)
7852           {
7853             case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
7854             case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
7855             case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
7856             case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
7857             case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
7858             case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
7859             case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
7860             case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
7861             case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
7862             case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
7863             case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
7864             case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
7865             case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
7866             case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
7867             case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
7868             case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
7869             case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
7870             case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
7871             case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
7872             case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
7873             case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
7874             case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
7875             case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
7876             case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
7877             case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
7878             case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
7879             case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
7880             case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
7881             case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
7882             case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
7883             case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
7884             case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
7885             case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
7886             case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
7887             case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
7888           }
7889           break;
7890           case 0x11: strcpy(insn[i],"C1.D"); type=NI;
7891           switch(source[i]&0x3f)
7892           {
7893             case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
7894             case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
7895             case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
7896             case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
7897             case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
7898             case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
7899             case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
7900             case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
7901             case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
7902             case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
7903             case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
7904             case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
7905             case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
7906             case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
7907             case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
7908             case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
7909             case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
7910             case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
7911             case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
7912             case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
7913             case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
7914             case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
7915             case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
7916             case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
7917             case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
7918             case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
7919             case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
7920             case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
7921             case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
7922             case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
7923             case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
7924             case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
7925             case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
7926             case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
7927             case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
7928           }
7929           break;
7930           case 0x14: strcpy(insn[i],"C1.W"); type=NI;
7931           switch(source[i]&0x3f)
7932           {
7933             case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
7934             case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
7935           }
7936           break;
7937           case 0x15: strcpy(insn[i],"C1.L"); type=NI;
7938           switch(source[i]&0x3f)
7939           {
7940             case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
7941             case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
7942           }
7943           break;
7944         }
7945         break;
7946       case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
7947       case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
7948       case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
7949       case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
7950       case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
7951       case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
7952       case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
7953       case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
7954       case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
7955       case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
7956       case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
7957       case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
7958       case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
7959       case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
7960       case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
7961       case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
7962       case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
7963       case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
7964       case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
7965       case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
7966       case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
7967       case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
7968       case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
7969       case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
7970       case 0x30: strcpy(insn[i],"LL"); type=NI; break;
7971       case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
7972       case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
7973       case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
7974       case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
7975       case 0x38: strcpy(insn[i],"SC"); type=NI; break;
7976       case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
7977       case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
7978       case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
7979       case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
7980       default: strcpy(insn[i],"???"); type=NI; break;
7981     }
7982     itype[i]=type;
7983     opcode2[i]=op2;
7984     /* Get registers/immediates */
7985     lt1[i]=0;
7986     us1[i]=0;
7987     us2[i]=0;
7988     dep1[i]=0;
7989     dep2[i]=0;
7990     switch(type) {
7991       case LOAD:
7992         rs1[i]=(source[i]>>21)&0x1f;
7993         rs2[i]=0;
7994         rt1[i]=(source[i]>>16)&0x1f;
7995         rt2[i]=0;
7996         imm[i]=(short)source[i];
7997         break;
7998       case STORE:
7999       case STORELR:
8000         rs1[i]=(source[i]>>21)&0x1f;
8001         rs2[i]=(source[i]>>16)&0x1f;
8002         rt1[i]=0;
8003         rt2[i]=0;
8004         imm[i]=(short)source[i];
8005         if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8006         break;
8007       case LOADLR:
8008         // LWL/LWR only load part of the register,
8009         // therefore the target register must be treated as a source too
8010         rs1[i]=(source[i]>>21)&0x1f;
8011         rs2[i]=(source[i]>>16)&0x1f;
8012         rt1[i]=(source[i]>>16)&0x1f;
8013         rt2[i]=0;
8014         imm[i]=(short)source[i];
8015         if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8016         if(op==0x26) dep1[i]=rt1[i]; // LWR
8017         break;
8018       case IMM16:
8019         if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8020         else rs1[i]=(source[i]>>21)&0x1f;
8021         rs2[i]=0;
8022         rt1[i]=(source[i]>>16)&0x1f;
8023         rt2[i]=0;
8024         if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8025           imm[i]=(unsigned short)source[i];
8026         }else{
8027           imm[i]=(short)source[i];
8028         }
8029         if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8030         if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8031         if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8032         break;
8033       case UJUMP:
8034         rs1[i]=0;
8035         rs2[i]=0;
8036         rt1[i]=0;
8037         rt2[i]=0;
8038         // The JAL instruction writes to r31.
8039         if (op&1) {
8040           rt1[i]=31;
8041         }
8042         rs2[i]=CCREG;
8043         break;
8044       case RJUMP:
8045         rs1[i]=(source[i]>>21)&0x1f;
8046         rs2[i]=0;
8047         rt1[i]=0;
8048         rt2[i]=0;
8049         // The JALR instruction writes to rd.
8050         if (op2&1) {
8051           rt1[i]=(source[i]>>11)&0x1f;
8052         }
8053         rs2[i]=CCREG;
8054         break;
8055       case CJUMP:
8056         rs1[i]=(source[i]>>21)&0x1f;
8057         rs2[i]=(source[i]>>16)&0x1f;
8058         rt1[i]=0;
8059         rt2[i]=0;
8060         if(op&2) { // BGTZ/BLEZ
8061           rs2[i]=0;
8062         }
8063         us1[i]=rs1[i];
8064         us2[i]=rs2[i];
8065         likely[i]=op>>4;
8066         break;
8067       case SJUMP:
8068         rs1[i]=(source[i]>>21)&0x1f;
8069         rs2[i]=CCREG;
8070         rt1[i]=0;
8071         rt2[i]=0;
8072         us1[i]=rs1[i];
8073         if(op2&0x10) { // BxxAL
8074           rt1[i]=31;
8075           // NOTE: If the branch is not taken, r31 is still overwritten
8076         }
8077         likely[i]=(op2&2)>>1;
8078         break;
8079       case FJUMP:
8080         rs1[i]=FSREG;
8081         rs2[i]=CSREG;
8082         rt1[i]=0;
8083         rt2[i]=0;
8084         likely[i]=((source[i])>>17)&1;
8085         break;
8086       case ALU:
8087         rs1[i]=(source[i]>>21)&0x1f; // source
8088         rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8089         rt1[i]=(source[i]>>11)&0x1f; // destination
8090         rt2[i]=0;
8091         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8092           us1[i]=rs1[i];us2[i]=rs2[i];
8093         }
8094         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8095           dep1[i]=rs1[i];dep2[i]=rs2[i];
8096         }
8097         else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8098           dep1[i]=rs1[i];dep2[i]=rs2[i];
8099         }
8100         break;
8101       case MULTDIV:
8102         rs1[i]=(source[i]>>21)&0x1f; // source
8103         rs2[i]=(source[i]>>16)&0x1f; // divisor
8104         rt1[i]=HIREG;
8105         rt2[i]=LOREG;
8106         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8107           us1[i]=rs1[i];us2[i]=rs2[i];
8108         }
8109         break;
8110       case MOV:
8111         rs1[i]=0;
8112         rs2[i]=0;
8113         rt1[i]=0;
8114         rt2[i]=0;
8115         if(op2==0x10) rs1[i]=HIREG; // MFHI
8116         if(op2==0x11) rt1[i]=HIREG; // MTHI
8117         if(op2==0x12) rs1[i]=LOREG; // MFLO
8118         if(op2==0x13) rt1[i]=LOREG; // MTLO
8119         if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8120         if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8121         dep1[i]=rs1[i];
8122         break;
8123       case SHIFT:
8124         rs1[i]=(source[i]>>16)&0x1f; // target of shift
8125         rs2[i]=(source[i]>>21)&0x1f; // shift amount
8126         rt1[i]=(source[i]>>11)&0x1f; // destination
8127         rt2[i]=0;
8128         // DSLLV/DSRLV/DSRAV are 64-bit
8129         if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8130         break;
8131       case SHIFTIMM:
8132         rs1[i]=(source[i]>>16)&0x1f;
8133         rs2[i]=0;
8134         rt1[i]=(source[i]>>11)&0x1f;
8135         rt2[i]=0;
8136         imm[i]=(source[i]>>6)&0x1f;
8137         // DSxx32 instructions
8138         if(op2>=0x3c) imm[i]|=0x20;
8139         // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8140         if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8141         break;
8142       case COP0:
8143         rs1[i]=0;
8144         rs2[i]=0;
8145         rt1[i]=0;
8146         rt2[i]=0;
8147         if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8148         if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8149         if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8150         if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8151         break;
8152       case COP1:
8153         rs1[i]=0;
8154         rs2[i]=0;
8155         rt1[i]=0;
8156         rt2[i]=0;
8157         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8158         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8159         if(op2==5) us1[i]=rs1[i]; // DMTC1
8160         rs2[i]=CSREG;
8161         break;
8162       case C1LS:
8163         rs1[i]=(source[i]>>21)&0x1F;
8164         rs2[i]=CSREG;
8165         rt1[i]=0;
8166         rt2[i]=0;
8167         imm[i]=(short)source[i];
8168         break;
8169       case FLOAT:
8170       case FCONV:
8171         rs1[i]=0;
8172         rs2[i]=CSREG;
8173         rt1[i]=0;
8174         rt2[i]=0;
8175         break;
8176       case FCOMP:
8177         rs1[i]=FSREG;
8178         rs2[i]=CSREG;
8179         rt1[i]=FSREG;
8180         rt2[i]=0;
8181         break;
8182       case SYSCALL:
8183         rs1[i]=CCREG;
8184         rs2[i]=0;
8185         rt1[i]=0;
8186         rt2[i]=0;
8187         break;
8188       default:
8189         rs1[i]=0;
8190         rs2[i]=0;
8191         rt1[i]=0;
8192         rt2[i]=0;
8193     }
8194     /* Calculate branch target addresses */
8195     if(type==UJUMP)
8196       ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8197     else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8198       ba[i]=start+i*4+8; // Ignore never taken branch
8199     else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8200       ba[i]=start+i*4+8; // Ignore never taken branch
8201     else if(type==CJUMP||type==SJUMP||type==FJUMP)
8202       ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8203     else ba[i]=-1;
8204     /* Is this the end of the block? */
8205     if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8206       if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8207         done=1;
8208         // Does the block continue due to a branch?
8209         for(j=i-1;j>=0;j--)
8210         {
8211           if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
8212           if(ba[j]==start+i*4+4) done=j=0;
8213           if(ba[j]==start+i*4+8) done=j=0;
8214         }
8215       }
8216       else {
8217         if(stop_after_jal) done=1;
8218         // Stop on BREAK
8219         if((source[i+1]&0xfc00003f)==0x0d) done=1;
8220       }
8221       // Don't recompile stuff that's already compiled
8222       if(check_addr(start+i*4+4)) done=1;
8223       // Don't get too close to the limit
8224       if(i>MAXBLOCK/2) done=1;
8225     }
8226     if(i>0&&itype[i-1]==SYSCALL&&stop_after_jal) done=1;
8227     assert(i<MAXBLOCK-1);
8228     if(start+i*4==pagelimit-4) done=1;
8229     assert(start+i*4<pagelimit);
8230     if (i==MAXBLOCK-1) done=1;
8231     // Stop if we're compiling junk
8232     if(itype[i]==NI&&opcode[i]==0x11) {
8233       done=stop_after_jal=1;
8234       DebugMessage(M64MSG_VERBOSE, "Disabled speculative precompilation");
8235     }
8236   }
8237   slen=i;
8238   if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8239     if(start+i*4==pagelimit) {
8240       itype[i-1]=SPAN;
8241     }
8242   }
8243   assert(slen>0);
8244
8245   /* Pass 2 - Register dependencies and branch targets */
8246
8247   unneeded_registers(0,slen-1,0);
8248
8249   /* Pass 3 - Register allocation */
8250
8251   struct regstat current; // Current register allocations/status
8252   current.is32=1;
8253   current.dirty=0;
8254   current.u=unneeded_reg[0];
8255   current.uu=unneeded_reg_upper[0];
8256   clear_all_regs(current.regmap);
8257   alloc_reg(&current,0,CCREG);
8258   dirty_reg(&current,CCREG);
8259   current.isconst=0;
8260   current.wasconst=0;
8261   int ds=0;
8262   int cc=0;
8263   int hr;
8264
8265   provisional_32bit();
8266
8267   if((u_int)addr&1) {
8268     // First instruction is delay slot
8269     cc=-1;
8270     bt[1]=1;
8271     ds=1;
8272     unneeded_reg[0]=1;
8273     unneeded_reg_upper[0]=1;
8274     current.regmap[HOST_BTREG]=BTREG;
8275   }
8276
8277   for(i=0;i<slen;i++)
8278   {
8279     if(bt[i])
8280     {
8281       int hr;
8282       for(hr=0;hr<HOST_REGS;hr++)
8283       {
8284         // Is this really necessary?
8285         if(current.regmap[hr]==0) current.regmap[hr]=-1;
8286       }
8287       current.isconst=0;
8288     }
8289     if(i>1)
8290     {
8291       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8292       {
8293         if(rs1[i-2]==0||rs2[i-2]==0)
8294         {
8295           if(rs1[i-2]) {
8296             current.is32|=1LL<<rs1[i-2];
8297             int hr=get_reg(current.regmap,rs1[i-2]|64);
8298             if(hr>=0) current.regmap[hr]=-1;
8299           }
8300           if(rs2[i-2]) {
8301             current.is32|=1LL<<rs2[i-2];
8302             int hr=get_reg(current.regmap,rs2[i-2]|64);
8303             if(hr>=0) current.regmap[hr]=-1;
8304           }
8305         }
8306       }
8307     }
8308     // If something jumps here with 64-bit values
8309     // then promote those registers to 64 bits
8310     if(bt[i])
8311     {
8312       uint64_t temp_is32=current.is32;
8313       for(j=i-1;j>=0;j--)
8314       {
8315         if(ba[j]==start+i*4)
8316           temp_is32&=branch_regs[j].is32;
8317       }
8318       for(j=i;j<slen;j++)
8319       {
8320         if(ba[j]==start+i*4)
8321           //temp_is32=1;
8322           temp_is32&=p32[j];
8323       }
8324       if(temp_is32!=current.is32) {
8325         //DebugMessage(M64MSG_VERBOSE, "dumping 32-bit regs (%x)",start+i*4);
8326         #ifndef DESTRUCTIVE_WRITEBACK
8327         if(ds)
8328         #endif
8329         for(hr=0;hr<HOST_REGS;hr++)
8330         {
8331           int r=current.regmap[hr];
8332           if(r>0&&r<64)
8333           {
8334             if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8335               temp_is32|=1LL<<r;
8336               //DebugMessage(M64MSG_VERBOSE, "restore %d",r);
8337             }
8338           }
8339         }
8340         current.is32=temp_is32;
8341       }
8342     }
8343     memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8344     regs[i].wasconst=current.isconst;
8345     regs[i].was32=current.is32;
8346     regs[i].wasdirty=current.dirty;
8347     #ifdef DESTRUCTIVE_WRITEBACK
8348     // To change a dirty register from 32 to 64 bits, we must write
8349     // it out during the previous cycle (for branches, 2 cycles)
8350     if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8351     {
8352       uint64_t temp_is32=current.is32;
8353       for(j=i-1;j>=0;j--)
8354       {
8355         if(ba[j]==start+i*4+4)
8356           temp_is32&=branch_regs[j].is32;
8357       }
8358       for(j=i;j<slen;j++)
8359       {
8360         if(ba[j]==start+i*4+4)
8361           //temp_is32=1;
8362           temp_is32&=p32[j];
8363       }
8364       if(temp_is32!=current.is32) {
8365         //DebugMessage(M64MSG_VERBOSE, "pre-dumping 32-bit regs (%x)",start+i*4);
8366         for(hr=0;hr<HOST_REGS;hr++)
8367         {
8368           int r=current.regmap[hr];
8369           if(r>0)
8370           {
8371             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8372               if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8373               {
8374                 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8375                 {
8376                   //DebugMessage(M64MSG_VERBOSE, "dump %d/r%d",hr,r);
8377                   current.regmap[hr]=-1;
8378                   if(get_reg(current.regmap,r|64)>=0)
8379                     current.regmap[get_reg(current.regmap,r|64)]=-1;
8380                 }
8381               }
8382             }
8383           }
8384         }
8385       }
8386     }
8387     else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8388     {
8389       uint64_t temp_is32=current.is32;
8390       for(j=i-1;j>=0;j--)
8391       {
8392         if(ba[j]==start+i*4+8)
8393           temp_is32&=branch_regs[j].is32;
8394       }
8395       for(j=i;j<slen;j++)
8396       {
8397         if(ba[j]==start+i*4+8)
8398           //temp_is32=1;
8399           temp_is32&=p32[j];
8400       }
8401       if(temp_is32!=current.is32) {
8402         //DebugMessage(M64MSG_VERBOSE, "pre-dumping 32-bit regs (%x)",start+i*4);
8403         for(hr=0;hr<HOST_REGS;hr++)
8404         {
8405           int r=current.regmap[hr];
8406           if(r>0)
8407           {
8408             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8409               if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8410               {
8411                 //DebugMessage(M64MSG_VERBOSE, "dump %d/r%d",hr,r);
8412                 current.regmap[hr]=-1;
8413                 if(get_reg(current.regmap,r|64)>=0)
8414                   current.regmap[get_reg(current.regmap,r|64)]=-1;
8415               }
8416             }
8417           }
8418         }
8419       }
8420     }
8421     #endif
8422     if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8423       if(i+1<slen) {
8424         current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8425         current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8426         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8427         current.u|=1;
8428         current.uu|=1;
8429       } else {
8430         current.u=1;
8431         current.uu=1;
8432       }
8433     } else {
8434       if(i+1<slen) {
8435         current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8436         current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8437         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8438         current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8439         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8440         current.u|=1;
8441         current.uu|=1;
8442       } else { DebugMessage(M64MSG_ERROR, "oops, branch at end of block with no delay slot");exit(1); }
8443     }
8444     is_ds[i]=ds;
8445     if(ds) {
8446       ds=0; // Skip delay slot, already allocated as part of branch
8447       // ...but we need to alloc it in case something jumps here
8448       if(i+1<slen) {
8449         current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8450         current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8451       }else{
8452         current.u=branch_unneeded_reg[i-1];
8453         current.uu=branch_unneeded_reg_upper[i-1];
8454       }
8455       current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8456       current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8457       if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8458       current.u|=1;
8459       current.uu|=1;
8460       struct regstat temp;
8461       memcpy(&temp,&current,sizeof(current));
8462       temp.wasdirty=temp.dirty;
8463       temp.was32=temp.is32;
8464       // TODO: Take into account unconditional branches, as below
8465       delayslot_alloc(&temp,i);
8466       memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8467       regs[i].wasdirty=temp.wasdirty;
8468       regs[i].was32=temp.was32;
8469       regs[i].dirty=temp.dirty;
8470       regs[i].is32=temp.is32;
8471       regs[i].isconst=0;
8472       regs[i].wasconst=0;
8473       current.isconst=0;
8474       // Create entry (branch target) regmap
8475       for(hr=0;hr<HOST_REGS;hr++)
8476       {
8477         int r=temp.regmap[hr];
8478         if(r>=0) {
8479           if(r!=regmap_pre[i][hr]) {
8480             regs[i].regmap_entry[hr]=-1;
8481           }
8482           else
8483           {
8484             if(r<64){
8485               if((current.u>>r)&1) {
8486                 regs[i].regmap_entry[hr]=-1;
8487                 regs[i].regmap[hr]=-1;
8488                 //Don't clear regs in the delay slot as the branch might need them
8489                 //current.regmap[hr]=-1;
8490               }else
8491                 regs[i].regmap_entry[hr]=r;
8492             }
8493             else {
8494               if((current.uu>>(r&63))&1) {
8495                 regs[i].regmap_entry[hr]=-1;
8496                 regs[i].regmap[hr]=-1;
8497                 //Don't clear regs in the delay slot as the branch might need them
8498                 //current.regmap[hr]=-1;
8499               }else
8500                 regs[i].regmap_entry[hr]=r;
8501             }
8502           }
8503         } else {
8504           // First instruction expects CCREG to be allocated
8505           if(i==0&&hr==HOST_CCREG)
8506             regs[i].regmap_entry[hr]=CCREG;
8507           else
8508             regs[i].regmap_entry[hr]=-1;
8509         }
8510       }
8511     }
8512     else { // Not delay slot
8513       switch(itype[i]) {
8514         case UJUMP:
8515           //current.isconst=0; // DEBUG
8516           //current.wasconst=0; // DEBUG
8517           //regs[i].wasconst=0; // DEBUG
8518           clear_const(&current,rt1[i]);
8519           alloc_cc(&current,i);
8520           dirty_reg(&current,CCREG);
8521           if (rt1[i]==31) {
8522             alloc_reg(&current,i,31);
8523             dirty_reg(&current,31);
8524             assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8525             #ifdef REG_PREFETCH
8526             alloc_reg(&current,i,PTEMP);
8527             #endif
8528             //current.is32|=1LL<<rt1[i];
8529           }
8530           ooo[i]=1;
8531           delayslot_alloc(&current,i+1);
8532           //current.isconst=0; // DEBUG
8533           ds=1;
8534           //DebugMessage(M64MSG_VERBOSE, "i=%d, isconst=%x",i,current.isconst);
8535           break;
8536         case RJUMP:
8537           //current.isconst=0;
8538           //current.wasconst=0;
8539           //regs[i].wasconst=0;
8540           clear_const(&current,rs1[i]);
8541           clear_const(&current,rt1[i]);
8542           alloc_cc(&current,i);
8543           dirty_reg(&current,CCREG);
8544           if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8545             alloc_reg(&current,i,rs1[i]);
8546             if (rt1[i]!=0) {
8547               alloc_reg(&current,i,rt1[i]);
8548               dirty_reg(&current,rt1[i]);
8549               assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8550               #ifdef REG_PREFETCH
8551               alloc_reg(&current,i,PTEMP);
8552               #endif
8553             }
8554             #ifdef USE_MINI_HT
8555             if(rs1[i]==31) { // JALR
8556               alloc_reg(&current,i,RHASH);
8557               #ifndef HOST_IMM_ADDR32
8558               alloc_reg(&current,i,RHTBL);
8559               #endif
8560             }
8561             #endif
8562             delayslot_alloc(&current,i+1);
8563           } else {
8564             // The delay slot overwrites our source register,
8565             // allocate a temporary register to hold the old value.
8566             current.isconst=0;
8567             current.wasconst=0;
8568             regs[i].wasconst=0;
8569             delayslot_alloc(&current,i+1);
8570             current.isconst=0;
8571             alloc_reg(&current,i,RTEMP);
8572           }
8573           //current.isconst=0; // DEBUG
8574           ooo[i]=1;
8575           ds=1;
8576           break;
8577         case CJUMP:
8578           //current.isconst=0;
8579           //current.wasconst=0;
8580           //regs[i].wasconst=0;
8581           clear_const(&current,rs1[i]);
8582           clear_const(&current,rs2[i]);
8583           if((opcode[i]&0x3E)==4) // BEQ/BNE
8584           {
8585             alloc_cc(&current,i);
8586             dirty_reg(&current,CCREG);
8587             if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8588             if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8589             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8590             {
8591               if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8592               if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8593             }
8594             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8595                (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8596               // The delay slot overwrites one of our conditions.
8597               // Allocate the branch condition registers instead.
8598               current.isconst=0;
8599               current.wasconst=0;
8600               regs[i].wasconst=0;
8601               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8602               if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8603               if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8604               {
8605                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8606                 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8607               }
8608             }
8609             else
8610             {
8611               ooo[i]=1;
8612               delayslot_alloc(&current,i+1);
8613             }
8614           }
8615           else
8616           if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8617           {
8618             alloc_cc(&current,i);
8619             dirty_reg(&current,CCREG);
8620             alloc_reg(&current,i,rs1[i]);
8621             if(!(current.is32>>rs1[i]&1))
8622             {
8623               alloc_reg64(&current,i,rs1[i]);
8624             }
8625             if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8626               // The delay slot overwrites one of our conditions.
8627               // Allocate the branch condition registers instead.
8628               current.isconst=0;
8629               current.wasconst=0;
8630               regs[i].wasconst=0;
8631               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8632               if(!((current.is32>>rs1[i])&1))
8633               {
8634                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8635               }
8636             }
8637             else
8638             {
8639               ooo[i]=1;
8640               delayslot_alloc(&current,i+1);
8641             }
8642           }
8643           else
8644           // Don't alloc the delay slot yet because we might not execute it
8645           if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
8646           {
8647             current.isconst=0;
8648             current.wasconst=0;
8649             regs[i].wasconst=0;
8650             alloc_cc(&current,i);
8651             dirty_reg(&current,CCREG);
8652             alloc_reg(&current,i,rs1[i]);
8653             alloc_reg(&current,i,rs2[i]);
8654             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8655             {
8656               alloc_reg64(&current,i,rs1[i]);
8657               alloc_reg64(&current,i,rs2[i]);
8658             }
8659           }
8660           else
8661           if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
8662           {
8663             current.isconst=0;
8664             current.wasconst=0;
8665             regs[i].wasconst=0;
8666             alloc_cc(&current,i);
8667             dirty_reg(&current,CCREG);
8668             alloc_reg(&current,i,rs1[i]);
8669             if(!(current.is32>>rs1[i]&1))
8670             {
8671               alloc_reg64(&current,i,rs1[i]);
8672             }
8673           }
8674           ds=1;
8675           //current.isconst=0;
8676           break;
8677         case SJUMP:
8678           //current.isconst=0;
8679           //current.wasconst=0;
8680           //regs[i].wasconst=0;
8681           clear_const(&current,rs1[i]);
8682           clear_const(&current,rt1[i]);
8683           //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
8684           if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
8685           {
8686             alloc_cc(&current,i);
8687             dirty_reg(&current,CCREG);
8688             alloc_reg(&current,i,rs1[i]);
8689             if(!(current.is32>>rs1[i]&1))
8690             {
8691               alloc_reg64(&current,i,rs1[i]);
8692             }
8693             if (rt1[i]==31) { // BLTZAL/BGEZAL
8694               alloc_reg(&current,i,31);
8695               dirty_reg(&current,31);
8696               assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8697               //#ifdef REG_PREFETCH
8698               //alloc_reg(&current,i,PTEMP);
8699               //#endif
8700               //current.is32|=1LL<<rt1[i];
8701             }
8702             if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8703               // The delay slot overwrites the branch condition.
8704               // Allocate the branch condition registers instead.
8705               current.isconst=0;
8706               current.wasconst=0;
8707               regs[i].wasconst=0;
8708               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8709               if(!((current.is32>>rs1[i])&1))
8710               {
8711                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8712               }
8713             }
8714             else
8715             {
8716               ooo[i]=1;
8717               delayslot_alloc(&current,i+1);
8718             }
8719           }
8720           else
8721           // Don't alloc the delay slot yet because we might not execute it
8722           if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
8723           {
8724             current.isconst=0;
8725             current.wasconst=0;
8726             regs[i].wasconst=0;
8727             alloc_cc(&current,i);
8728             dirty_reg(&current,CCREG);
8729             alloc_reg(&current,i,rs1[i]);
8730             if(!(current.is32>>rs1[i]&1))
8731             {
8732               alloc_reg64(&current,i,rs1[i]);
8733             }
8734           }
8735           ds=1;
8736           //current.isconst=0;
8737           break;
8738         case FJUMP:
8739           current.isconst=0;
8740           current.wasconst=0;
8741           regs[i].wasconst=0;
8742           if(likely[i]==0) // BC1F/BC1T
8743           {
8744             // TODO: Theoretically we can run out of registers here on x86.
8745             // The delay slot can allocate up to six, and we need to check
8746             // CSREG before executing the delay slot.  Possibly we can drop
8747             // the cycle count and then reload it after checking that the
8748             // FPU is in a usable state, or don't do out-of-order execution.
8749             alloc_cc(&current,i);
8750             dirty_reg(&current,CCREG);
8751             alloc_reg(&current,i,FSREG);
8752             alloc_reg(&current,i,CSREG);
8753             if(itype[i+1]==FCOMP) {
8754               // The delay slot overwrites the branch condition.
8755               // Allocate the branch condition registers instead.
8756               alloc_cc(&current,i);
8757               dirty_reg(&current,CCREG);
8758               alloc_reg(&current,i,CSREG);
8759               alloc_reg(&current,i,FSREG);
8760             }
8761             else {
8762               ooo[i]=1;
8763               delayslot_alloc(&current,i+1);
8764               alloc_reg(&current,i+1,CSREG);
8765             }
8766           }
8767           else
8768           // Don't alloc the delay slot yet because we might not execute it
8769           if(likely[i]) // BC1FL/BC1TL
8770           {
8771             alloc_cc(&current,i);
8772             dirty_reg(&current,CCREG);
8773             alloc_reg(&current,i,CSREG);
8774             alloc_reg(&current,i,FSREG);
8775           }
8776           ds=1;
8777           current.isconst=0;
8778           break;
8779         case IMM16:
8780           imm16_alloc(&current,i);
8781           break;
8782         case LOAD:
8783         case LOADLR:
8784           load_alloc(&current,i);
8785           break;
8786         case STORE:
8787         case STORELR:
8788           store_alloc(&current,i);
8789           break;
8790         case ALU:
8791           alu_alloc(&current,i);
8792           break;
8793         case SHIFT:
8794           shift_alloc(&current,i);
8795           break;
8796         case MULTDIV:
8797           multdiv_alloc(&current,i);
8798           break;
8799         case SHIFTIMM:
8800           shiftimm_alloc(&current,i);
8801           break;
8802         case MOV:
8803           mov_alloc(&current,i);
8804           break;
8805         case COP0:
8806           cop0_alloc(&current,i);
8807           break;
8808         case COP1:
8809           cop1_alloc(&current,i);
8810           break;
8811         case C1LS:
8812           c1ls_alloc(&current,i);
8813           break;
8814         case FCONV:
8815           fconv_alloc(&current,i);
8816           break;
8817         case FLOAT:
8818           float_alloc(&current,i);
8819           break;
8820         case FCOMP:
8821           fcomp_alloc(&current,i);
8822           break;
8823         case SYSCALL:
8824           syscall_alloc(&current,i);
8825           break;
8826         case SPAN:
8827           pagespan_alloc(&current,i);
8828           break;
8829       }
8830
8831       // Drop the upper half of registers that have become 32-bit
8832       current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
8833       if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8834         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8835         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8836         current.uu|=1;
8837       } else {
8838         current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
8839         current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8840         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8841         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8842         current.uu|=1;
8843       }
8844
8845       // Create entry (branch target) regmap
8846       for(hr=0;hr<HOST_REGS;hr++)
8847       {
8848         int r,or;
8849         r=current.regmap[hr];
8850         if(r>=0) {
8851           if(r!=regmap_pre[i][hr]) {
8852             // TODO: delay slot (?)
8853             or=get_reg(regmap_pre[i],r); // Get old mapping for this register
8854             if(or<0||(r&63)>=TEMPREG){
8855               regs[i].regmap_entry[hr]=-1;
8856             }
8857             else
8858             {
8859               // Just move it to a different register
8860               regs[i].regmap_entry[hr]=r;
8861               // If it was dirty before, it's still dirty
8862               if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
8863             }
8864           }
8865           else
8866           {
8867             // Unneeded
8868             if(r==0){
8869               regs[i].regmap_entry[hr]=0;
8870             }
8871             else
8872             if(r<64){
8873               if((current.u>>r)&1) {
8874                 regs[i].regmap_entry[hr]=-1;
8875                 //regs[i].regmap[hr]=-1;
8876                 current.regmap[hr]=-1;
8877               }else
8878                 regs[i].regmap_entry[hr]=r;
8879             }
8880             else {
8881               if((current.uu>>(r&63))&1) {
8882                 regs[i].regmap_entry[hr]=-1;
8883                 //regs[i].regmap[hr]=-1;
8884                 current.regmap[hr]=-1;
8885               }else
8886                 regs[i].regmap_entry[hr]=r;
8887             }
8888           }
8889         } else {
8890           // Branches expect CCREG to be allocated at the target
8891           if(regmap_pre[i][hr]==CCREG)
8892             regs[i].regmap_entry[hr]=CCREG;
8893           else
8894             regs[i].regmap_entry[hr]=-1;
8895         }
8896       }
8897       memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
8898     }
8899     /* Branch post-alloc */
8900     if(i>0)
8901     {
8902       current.was32=current.is32;
8903       current.wasdirty=current.dirty;
8904       switch(itype[i-1]) {
8905         case UJUMP:
8906           memcpy(&branch_regs[i-1],&current,sizeof(current));
8907           branch_regs[i-1].isconst=0;
8908           branch_regs[i-1].wasconst=0;
8909           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
8910           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
8911           alloc_cc(&branch_regs[i-1],i-1);
8912           dirty_reg(&branch_regs[i-1],CCREG);
8913           if(rt1[i-1]==31) { // JAL
8914             alloc_reg(&branch_regs[i-1],i-1,31);
8915             dirty_reg(&branch_regs[i-1],31);
8916             branch_regs[i-1].is32|=1LL<<31;
8917           }
8918           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8919           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
8920           break;
8921         case RJUMP:
8922           memcpy(&branch_regs[i-1],&current,sizeof(current));
8923           branch_regs[i-1].isconst=0;
8924           branch_regs[i-1].wasconst=0;
8925           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
8926           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
8927           alloc_cc(&branch_regs[i-1],i-1);
8928           dirty_reg(&branch_regs[i-1],CCREG);
8929           alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
8930           if(rt1[i-1]!=0) { // JALR
8931             alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
8932             dirty_reg(&branch_regs[i-1],rt1[i-1]);
8933             branch_regs[i-1].is32|=1LL<<rt1[i-1];
8934           }
8935           #ifdef USE_MINI_HT
8936           if(rs1[i-1]==31) { // JALR
8937             alloc_reg(&branch_regs[i-1],i-1,RHASH);
8938             #ifndef HOST_IMM_ADDR32
8939             alloc_reg(&branch_regs[i-1],i-1,RHTBL);
8940             #endif
8941           }
8942           #endif
8943           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8944           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
8945           break;
8946         case CJUMP:
8947           if((opcode[i-1]&0x3E)==4) // BEQ/BNE
8948           {
8949             alloc_cc(&current,i-1);
8950             dirty_reg(&current,CCREG);
8951             if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
8952                (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
8953               // The delay slot overwrote one of our conditions
8954               // Delay slot goes after the test (in order)
8955               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8956               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8957               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8958               current.u|=1;
8959               current.uu|=1;
8960               delayslot_alloc(&current,i);
8961               current.isconst=0;
8962             }
8963             else
8964             {
8965               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
8966               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
8967               // Alloc the branch condition registers
8968               if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
8969               if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
8970               if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
8971               {
8972                 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
8973                 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
8974               }
8975             }
8976             memcpy(&branch_regs[i-1],&current,sizeof(current));
8977             branch_regs[i-1].isconst=0;
8978             branch_regs[i-1].wasconst=0;
8979             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
8980             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
8981           }
8982           else
8983           if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
8984           {
8985             alloc_cc(&current,i-1);
8986             dirty_reg(&current,CCREG);
8987             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
8988               // The delay slot overwrote the branch condition
8989               // Delay slot goes after the test (in order)
8990               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8991               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8992               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8993               current.u|=1;
8994               current.uu|=1;
8995               delayslot_alloc(&current,i);
8996               current.isconst=0;
8997             }
8998             else
8999             {
9000               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9001               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9002               // Alloc the branch condition register
9003               alloc_reg(&current,i-1,rs1[i-1]);
9004               if(!(current.is32>>rs1[i-1]&1))
9005               {
9006                 alloc_reg64(&current,i-1,rs1[i-1]);
9007               }
9008             }
9009             memcpy(&branch_regs[i-1],&current,sizeof(current));
9010             branch_regs[i-1].isconst=0;
9011             branch_regs[i-1].wasconst=0;
9012             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9013             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9014           }
9015           else
9016           // Alloc the delay slot in case the branch is taken
9017           if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9018           {
9019             memcpy(&branch_regs[i-1],&current,sizeof(current));
9020             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9021             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9022             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9023             alloc_cc(&branch_regs[i-1],i);
9024             dirty_reg(&branch_regs[i-1],CCREG);
9025             delayslot_alloc(&branch_regs[i-1],i);
9026             branch_regs[i-1].isconst=0;
9027             alloc_reg(&current,i,CCREG); // Not taken path
9028             dirty_reg(&current,CCREG);
9029             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9030           }
9031           else
9032           if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9033           {
9034             memcpy(&branch_regs[i-1],&current,sizeof(current));
9035             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9036             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9037             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9038             alloc_cc(&branch_regs[i-1],i);
9039             dirty_reg(&branch_regs[i-1],CCREG);
9040             delayslot_alloc(&branch_regs[i-1],i);
9041             branch_regs[i-1].isconst=0;
9042             alloc_reg(&current,i,CCREG); // Not taken path
9043             dirty_reg(&current,CCREG);
9044             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9045           }
9046           break;
9047         case SJUMP:
9048           //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9049           if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9050           {
9051             alloc_cc(&current,i-1);
9052             dirty_reg(&current,CCREG);
9053             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9054               // The delay slot overwrote the branch condition
9055               // Delay slot goes after the test (in order)
9056               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9057               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9058               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9059               current.u|=1;
9060               current.uu|=1;
9061               delayslot_alloc(&current,i);
9062               current.isconst=0;
9063             }
9064             else
9065             {
9066               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9067               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9068               // Alloc the branch condition register
9069               alloc_reg(&current,i-1,rs1[i-1]);
9070               if(!(current.is32>>rs1[i-1]&1))
9071               {
9072                 alloc_reg64(&current,i-1,rs1[i-1]);
9073               }
9074             }
9075             memcpy(&branch_regs[i-1],&current,sizeof(current));
9076             branch_regs[i-1].isconst=0;
9077             branch_regs[i-1].wasconst=0;
9078             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9079             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9080           }
9081           else
9082           // Alloc the delay slot in case the branch is taken
9083           if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9084           {
9085             memcpy(&branch_regs[i-1],&current,sizeof(current));
9086             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9087             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9088             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9089             alloc_cc(&branch_regs[i-1],i);
9090             dirty_reg(&branch_regs[i-1],CCREG);
9091             delayslot_alloc(&branch_regs[i-1],i);
9092             branch_regs[i-1].isconst=0;
9093             alloc_reg(&current,i,CCREG); // Not taken path
9094             dirty_reg(&current,CCREG);
9095             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9096           }
9097           // FIXME: BLTZAL/BGEZAL
9098           if(opcode2[i-1]&0x10) { // BxxZAL
9099             alloc_reg(&branch_regs[i-1],i-1,31);
9100             dirty_reg(&branch_regs[i-1],31);
9101             branch_regs[i-1].is32|=1LL<<31;
9102           }
9103           break;
9104         case FJUMP:
9105           if(likely[i-1]==0) // BC1F/BC1T
9106           {
9107             alloc_cc(&current,i-1);
9108             dirty_reg(&current,CCREG);
9109             if(itype[i]==FCOMP) {
9110               // The delay slot overwrote the branch condition
9111               // Delay slot goes after the test (in order)
9112               delayslot_alloc(&current,i);
9113               current.isconst=0;
9114             }
9115             else
9116             {
9117               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9118               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9119               // Alloc the branch condition register
9120               alloc_reg(&current,i-1,FSREG);
9121             }
9122             memcpy(&branch_regs[i-1],&current,sizeof(current));
9123             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9124           }
9125           else // BC1FL/BC1TL
9126           {
9127             // Alloc the delay slot in case the branch is taken
9128             memcpy(&branch_regs[i-1],&current,sizeof(current));
9129             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9130             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9131             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9132             alloc_cc(&branch_regs[i-1],i);
9133             dirty_reg(&branch_regs[i-1],CCREG);
9134             delayslot_alloc(&branch_regs[i-1],i);
9135             branch_regs[i-1].isconst=0;
9136             alloc_reg(&current,i,CCREG); // Not taken path
9137             dirty_reg(&current,CCREG);
9138             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9139           }
9140           break;
9141       }
9142
9143       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9144       {
9145         if(rt1[i-1]==31) // JAL/JALR
9146         {
9147           // Subroutine call will return here, don't alloc any registers
9148           current.is32=1;
9149           current.dirty=0;
9150           clear_all_regs(current.regmap);
9151           alloc_reg(&current,i,CCREG);
9152           dirty_reg(&current,CCREG);
9153         }
9154         else if(i+1<slen)
9155         {
9156           // Internal branch will jump here, match registers to caller
9157           current.is32=0x3FFFFFFFFLL;
9158           current.dirty=0;
9159           clear_all_regs(current.regmap);
9160           alloc_reg(&current,i,CCREG);
9161           dirty_reg(&current,CCREG);
9162           for(j=i-1;j>=0;j--)
9163           {
9164             if(ba[j]==start+i*4+4) {
9165               memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9166               current.is32=branch_regs[j].is32;
9167               current.dirty=branch_regs[j].dirty;
9168               break;
9169             }
9170           }
9171           while(j>=0) {
9172             if(ba[j]==start+i*4+4) {
9173               for(hr=0;hr<HOST_REGS;hr++) {
9174                 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9175                   current.regmap[hr]=-1;
9176                 }
9177                 current.is32&=branch_regs[j].is32;
9178                 current.dirty&=branch_regs[j].dirty;
9179               }
9180             }
9181             j--;
9182           }
9183         }
9184       }
9185     }
9186
9187     // Count cycles in between branches
9188     ccadj[i]=cc;
9189     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL))
9190     {
9191       cc=0;
9192     }
9193     else
9194     {
9195       cc++;
9196     }
9197
9198     flush_dirty_uppers(&current);
9199     if(!is_ds[i]) {
9200       regs[i].is32=current.is32;
9201       regs[i].dirty=current.dirty;
9202       regs[i].isconst=current.isconst;
9203       memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9204     }
9205     for(hr=0;hr<HOST_REGS;hr++) {
9206       if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9207         if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9208           regs[i].wasconst&=~(1<<hr);
9209         }
9210       }
9211     }
9212     if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9213   }
9214
9215   /* Pass 4 - Cull unused host registers */
9216
9217   uint64_t nr=0;
9218
9219   for (i=slen-1;i>=0;i--)
9220   {
9221     int hr;
9222     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9223     {
9224       if(ba[i]<start || ba[i]>=(start+slen*4))
9225       {
9226         // Branch out of this block, don't need anything
9227         nr=0;
9228       }
9229       else
9230       {
9231         // Internal branch
9232         // Need whatever matches the target
9233         nr=0;
9234         int t=(ba[i]-start)>>2;
9235         for(hr=0;hr<HOST_REGS;hr++)
9236         {
9237           if(regs[i].regmap_entry[hr]>=0) {
9238             if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9239           }
9240         }
9241       }
9242       // Conditional branch may need registers for following instructions
9243       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9244       {
9245         if(i<slen-2) {
9246           nr|=needed_reg[i+2];
9247           for(hr=0;hr<HOST_REGS;hr++)
9248           {
9249             if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9250             //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) DebugMessage(M64MSG_VERBOSE, "%x-bogus(%d=%d)",start+i*4,hr,regmap_entry[i+2][hr]);
9251           }
9252         }
9253       }
9254       // Don't need stuff which is overwritten
9255       if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9256       if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9257       // Merge in delay slot
9258       for(hr=0;hr<HOST_REGS;hr++)
9259       {
9260         if(!likely[i]) {
9261           // These are overwritten unless the branch is "likely"
9262           // and the delay slot is nullified if not taken
9263           if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9264           if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9265         }
9266         if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9267         if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9268         if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9269         if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9270         if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9271         if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9272         if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9273         if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9274         if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9275           if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9276           if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9277         }
9278         if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9279           if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9280           if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9281         }
9282         if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39) {
9283           if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9284           if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9285         }
9286       }
9287     }
9288     else if(itype[i]==SYSCALL)
9289     {
9290       // SYSCALL instruction (software interrupt)
9291       nr=0;
9292     }
9293     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9294     {
9295       // ERET instruction (return from interrupt)
9296       nr=0;
9297     }
9298     else // Non-branch
9299     {
9300       if(i<slen-1) {
9301         for(hr=0;hr<HOST_REGS;hr++) {
9302           if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9303           if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9304           if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9305           if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9306         }
9307       }
9308     }
9309     for(hr=0;hr<HOST_REGS;hr++)
9310     {
9311       // Overwritten registers are not needed
9312       if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9313       if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9314       if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9315       // Source registers are needed
9316       if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9317       if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9318       if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9319       if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9320       if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9321       if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9322       if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9323       if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9324       if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9325         if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9326         if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9327       }
9328       if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9329         if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9330         if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9331       }
9332       if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39) {
9333         if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9334         if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9335       }
9336       // Don't store a register immediately after writing it,
9337       // may prevent dual-issue.
9338       // But do so if this is a branch target, otherwise we
9339       // might have to load the register before the branch.
9340       if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9341         if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9342            (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9343           if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9344           if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9345         }
9346         if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9347            (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9348           if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9349           if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9350         }
9351       }
9352     }
9353     // Cycle count is needed at branches.  Assume it is needed at the target too.
9354     if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9355       if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9356       if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9357     }
9358     // Save it
9359     needed_reg[i]=nr;
9360
9361     // Deallocate unneeded registers
9362     for(hr=0;hr<HOST_REGS;hr++)
9363     {
9364       if(!((nr>>hr)&1)) {
9365         if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9366         if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9367            (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9368            (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9369         {
9370           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9371           {
9372             if(likely[i]) {
9373               regs[i].regmap[hr]=-1;
9374               regs[i].isconst&=~(1<<hr);
9375               if(i<slen-2) {
9376                 regmap_pre[i+2][hr]=-1;
9377                 regs[i+2].wasconst&=~(1<<hr);
9378               }
9379             }
9380           }
9381         }
9382         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9383         {
9384           int d1=0,d2=0,map=0,temp=0;
9385           if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9386           {
9387             d1=dep1[i+1];
9388             d2=dep2[i+1];
9389           }
9390           if(using_tlb) {
9391             if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9392                itype[i+1]==STORE || itype[i+1]==STORELR ||
9393                itype[i+1]==C1LS )
9394             map=TLREG;
9395           } else
9396           if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39) {
9397             map=INVCP;
9398           }
9399           if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
9400              itype[i+1]==C1LS )
9401             temp=FTEMP;
9402           if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9403              (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9404              (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9405              (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9406              (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9407              regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9408              (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9409              regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9410              regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9411              regs[i].regmap[hr]!=map )
9412           {
9413             regs[i].regmap[hr]=-1;
9414             regs[i].isconst&=~(1<<hr);
9415             if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9416                (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9417                (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9418                (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9419                (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9420                branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9421                (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9422                branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9423                branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9424                branch_regs[i].regmap[hr]!=map)
9425             {
9426               branch_regs[i].regmap[hr]=-1;
9427               branch_regs[i].regmap_entry[hr]=-1;
9428               if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9429               {
9430                 if(!likely[i]&&i<slen-2) {
9431                   regmap_pre[i+2][hr]=-1;
9432                   regs[i+2].wasconst&=~(1<<hr);
9433                 }
9434               }
9435             }
9436           }
9437         }
9438         else
9439         {
9440           // Non-branch
9441           if(i>0)
9442           {
9443             int d1=0,d2=0,map=-1,temp=-1;
9444             if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9445             {
9446               d1=dep1[i];
9447               d2=dep2[i];
9448             }
9449             if(using_tlb) {
9450               if(itype[i]==LOAD || itype[i]==LOADLR ||
9451                  itype[i]==STORE || itype[i]==STORELR ||
9452                  itype[i]==C1LS )
9453               map=TLREG;
9454             } else if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39) {
9455               map=INVCP;
9456             }
9457             if(itype[i]==LOADLR || itype[i]==STORELR ||
9458                itype[i]==C1LS )
9459               temp=FTEMP;
9460             if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9461                (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9462                (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9463                regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9464                (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9465                (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9466             {
9467               if(i<slen-1&&!is_ds[i]) {
9468                 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9469                 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9470                 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9471                 {
9472                   DebugMessage(M64MSG_VERBOSE, "fail: %x (%d %d!=%d)",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9473                   assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9474                 }
9475                 regmap_pre[i+1][hr]=-1;
9476                 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
9477                 regs[i+1].wasconst&=~(1<<hr);
9478               }
9479               regs[i].regmap[hr]=-1;
9480               regs[i].isconst&=~(1<<hr);
9481             }
9482           }
9483         }
9484       }
9485     }
9486   }
9487
9488   /* Pass 5 - Pre-allocate registers */
9489
9490   // If a register is allocated during a loop, try to allocate it for the
9491   // entire loop, if possible.  This avoids loading/storing registers
9492   // inside of the loop.
9493
9494   signed char f_regmap[HOST_REGS];
9495   clear_all_regs(f_regmap);
9496   for(i=0;i<slen-1;i++)
9497   {
9498     if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9499     {
9500       if(ba[i]>=start && ba[i]<(start+i*4))
9501       if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9502       ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9503       ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9504       ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9505       ||itype[i+1]==FCOMP||itype[i+1]==FCONV)
9506       {
9507         int t=(ba[i]-start)>>2;
9508         if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
9509         if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
9510         for(hr=0;hr<HOST_REGS;hr++)
9511         {
9512           if(regs[i].regmap[hr]>64) {
9513             if(!((regs[i].dirty>>hr)&1))
9514               f_regmap[hr]=regs[i].regmap[hr];
9515             else f_regmap[hr]=-1;
9516           }
9517           else if(regs[i].regmap[hr]>=0) {
9518             if(f_regmap[hr]!=regs[i].regmap[hr]) {
9519               // dealloc old register
9520               int n;
9521               for(n=0;n<HOST_REGS;n++)
9522               {
9523                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9524               }
9525               // and alloc new one
9526               f_regmap[hr]=regs[i].regmap[hr];
9527             }
9528           }
9529           if(branch_regs[i].regmap[hr]>64) {
9530             if(!((branch_regs[i].dirty>>hr)&1))
9531               f_regmap[hr]=branch_regs[i].regmap[hr];
9532             else f_regmap[hr]=-1;
9533           }
9534           else if(branch_regs[i].regmap[hr]>=0) {
9535             if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
9536               // dealloc old register
9537               int n;
9538               for(n=0;n<HOST_REGS;n++)
9539               {
9540                 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
9541               }
9542               // and alloc new one
9543               f_regmap[hr]=branch_regs[i].regmap[hr];
9544             }
9545           }
9546           if(ooo[i]) {
9547             if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
9548               f_regmap[hr]=branch_regs[i].regmap[hr];
9549           }else{
9550             if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
9551               f_regmap[hr]=branch_regs[i].regmap[hr];
9552           }
9553           // Avoid dirty->clean transition
9554           #ifdef DESTRUCTIVE_WRITEBACK
9555           if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
9556           #endif
9557           // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
9558           // case above, however it's always a good idea.  We can't hoist the
9559           // load if the register was already allocated, so there's no point
9560           // wasting time analyzing most of these cases.  It only "succeeds"
9561           // when the mapping was different and the load can be replaced with
9562           // a mov, which is of negligible benefit.  So such cases are
9563           // skipped below.
9564           if(f_regmap[hr]>0) {
9565             if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
9566               int r=f_regmap[hr];
9567               for(j=t;j<=i;j++)
9568               {
9569                 //DebugMessage(M64MSG_VERBOSE, "Test %x -> %x, %x %d/%d",start+i*4,ba[i],start+j*4,hr,r);
9570                 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9571                 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9572                 if(r>63) {
9573                   // NB This can exclude the case where the upper-half
9574                   // register is lower numbered than the lower-half
9575                   // register.  Not sure if it's worth fixing...
9576                   if(get_reg(regs[j].regmap,r&63)<0) break;
9577                   if(get_reg(regs[j].regmap_entry,r&63)<0) break;
9578                   if(regs[j].is32&(1LL<<(r&63))) break;
9579                 }
9580                 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9581                   //DebugMessage(M64MSG_VERBOSE, "Hit %x -> %x, %x %d/%d",start+i*4,ba[i],start+j*4,hr,r);
9582                   int k;
9583                   if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9584                     if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9585                     if(r>63) {
9586                       if(get_reg(regs[i].regmap,r&63)<0) break;
9587                       if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9588                     }
9589                     k=i;
9590                     while(k>1&&regs[k-1].regmap[hr]==-1) {
9591                       if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
9592                         //DebugMessage(M64MSG_VERBOSE, "no free regs for store %x",start+(k-1)*4);
9593                         break;
9594                       }
9595                       if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9596                         //DebugMessage(M64MSG_VERBOSE, "no-match due to different register");
9597                         break;
9598                       }
9599                       if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9600                         //DebugMessage(M64MSG_VERBOSE, "no-match due to branch");
9601                         break;
9602                       }
9603                       // call/ret fast path assumes no registers allocated
9604                       if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
9605                         break;
9606                       }
9607                       if(r>63) {
9608                         // NB This can exclude the case where the upper-half
9609                         // register is lower numbered than the lower-half
9610                         // register.  Not sure if it's worth fixing...
9611                         if(get_reg(regs[k-1].regmap,r&63)<0) break;
9612                         if(regs[k-1].is32&(1LL<<(r&63))) break;
9613                       }
9614                       k--;
9615                     }
9616                     if(i<slen-1) {
9617                       if((regs[k].is32&(1LL<<f_regmap[hr]))!=
9618                         (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
9619                         //DebugMessage(M64MSG_VERBOSE, "bad match after branch");
9620                         break;
9621                       }
9622                     }
9623                     if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
9624                       //DebugMessage(M64MSG_VERBOSE, "Extend r%d, %x ->",hr,start+k*4);
9625                       while(k<i) {
9626                         regs[k].regmap_entry[hr]=f_regmap[hr];
9627                         regs[k].regmap[hr]=f_regmap[hr];
9628                         regmap_pre[k+1][hr]=f_regmap[hr];
9629                         regs[k].wasdirty&=~(1<<hr);
9630                         regs[k].dirty&=~(1<<hr);
9631                         regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
9632                         regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
9633                         regs[k].wasconst&=~(1<<hr);
9634                         regs[k].isconst&=~(1<<hr);
9635                         k++;
9636                       }
9637                     }
9638                     else {
9639                       //DebugMessage(M64MSG_VERBOSE, "Fail Extend r%d, %x ->",hr,start+k*4);
9640                       break;
9641                     }
9642                     assert(regs[i-1].regmap[hr]==f_regmap[hr]);
9643                     if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
9644                       //DebugMessage(M64MSG_VERBOSE, "OK fill %x (r%d)",start+i*4,hr);
9645                       regs[i].regmap_entry[hr]=f_regmap[hr];
9646                       regs[i].regmap[hr]=f_regmap[hr];
9647                       regs[i].wasdirty&=~(1<<hr);
9648                       regs[i].dirty&=~(1<<hr);
9649                       regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
9650                       regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
9651                       regs[i].wasconst&=~(1<<hr);
9652                       regs[i].isconst&=~(1<<hr);
9653                       branch_regs[i].regmap_entry[hr]=f_regmap[hr];
9654                       branch_regs[i].wasdirty&=~(1<<hr);
9655                       branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
9656                       branch_regs[i].regmap[hr]=f_regmap[hr];
9657                       branch_regs[i].dirty&=~(1<<hr);
9658                       branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
9659                       branch_regs[i].wasconst&=~(1<<hr);
9660                       branch_regs[i].isconst&=~(1<<hr);
9661                       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
9662                         regmap_pre[i+2][hr]=f_regmap[hr];
9663                         regs[i+2].wasdirty&=~(1<<hr);
9664                         regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
9665                         assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
9666                           (regs[i+2].was32&(1LL<<f_regmap[hr])));
9667                       }
9668                     }
9669                   }
9670                   for(k=t;k<j;k++) {
9671                     // Alloc register clean at beginning of loop,
9672                     // but may dirty it in pass 6
9673                     regs[k].regmap_entry[hr]=f_regmap[hr];
9674                     regs[k].regmap[hr]=f_regmap[hr];
9675                     regs[k].dirty&=~(1<<hr);
9676                     regs[k].wasconst&=~(1<<hr);
9677                     regs[k].isconst&=~(1<<hr);
9678                     if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
9679                       branch_regs[k].regmap_entry[hr]=f_regmap[hr];
9680                       branch_regs[k].regmap[hr]=f_regmap[hr];
9681                       branch_regs[k].dirty&=~(1<<hr);
9682                       branch_regs[k].wasconst&=~(1<<hr);
9683                       branch_regs[k].isconst&=~(1<<hr);
9684                       if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
9685                         regmap_pre[k+2][hr]=f_regmap[hr];
9686                         regs[k+2].wasdirty&=~(1<<hr);
9687                         assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
9688                           (regs[k+2].was32&(1LL<<f_regmap[hr])));
9689                       }
9690                     }
9691                     else
9692                     {
9693                       regmap_pre[k+1][hr]=f_regmap[hr];
9694                       regs[k+1].wasdirty&=~(1<<hr);
9695                     }
9696                   }
9697                   if(regs[j].regmap[hr]==f_regmap[hr])
9698                     regs[j].regmap_entry[hr]=f_regmap[hr];
9699                   break;
9700                 }
9701                 if(j==i) break;
9702                 if(regs[j].regmap[hr]>=0)
9703                   break;
9704                 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
9705                   //DebugMessage(M64MSG_VERBOSE, "no-match due to different register");
9706                   break;
9707                 }
9708                 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
9709                   //DebugMessage(M64MSG_VERBOSE, "32/64 mismatch %x %d",start+j*4,hr);
9710                   break;
9711                 }
9712                 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
9713                 {
9714                   // Stop on unconditional branch
9715                   break;
9716                 }
9717                 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
9718                 {
9719                   if(ooo[j]) {
9720                     if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
9721                       break;
9722                   }else{
9723                     if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
9724                       break;
9725                   }
9726                   if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
9727                     //DebugMessage(M64MSG_VERBOSE, "no-match due to different register (branch)");
9728                     break;
9729                   }
9730                 }
9731                 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
9732                   //DebugMessage(M64MSG_VERBOSE, "No free regs for store %x",start+j*4);
9733                   break;
9734                 }
9735                 if(f_regmap[hr]>=64) {
9736                   if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
9737                     break;
9738                   }
9739                   else
9740                   {
9741                     if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
9742                       break;
9743                     }
9744                   }
9745                 }
9746               }
9747             }
9748           }
9749         }
9750       }
9751     }else{
9752       // Non branch or undetermined branch target
9753       for(hr=0;hr<HOST_REGS;hr++)
9754       {
9755         if(hr!=EXCLUDE_REG) {
9756           if(regs[i].regmap[hr]>64) {
9757             if(!((regs[i].dirty>>hr)&1))
9758               f_regmap[hr]=regs[i].regmap[hr];
9759           }
9760           else if(regs[i].regmap[hr]>=0) {
9761             if(f_regmap[hr]!=regs[i].regmap[hr]) {
9762               // dealloc old register
9763               int n;
9764               for(n=0;n<HOST_REGS;n++)
9765               {
9766                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9767               }
9768               // and alloc new one
9769               f_regmap[hr]=regs[i].regmap[hr];
9770             }
9771           }
9772         }
9773       }
9774       // Try to restore cycle count at branch targets
9775       if(bt[i]) {
9776         for(j=i;j<slen-1;j++) {
9777           if(regs[j].regmap[HOST_CCREG]!=-1) break;
9778           if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
9779             //DebugMessage(M64MSG_VERBOSE, "no free regs for store %x",start+j*4);
9780             break;
9781           }
9782         }
9783         if(regs[j].regmap[HOST_CCREG]==CCREG) {
9784           int k=i;
9785           //DebugMessage(M64MSG_VERBOSE, "Extend CC, %x -> %x",start+k*4,start+j*4);
9786           while(k<j) {
9787             regs[k].regmap_entry[HOST_CCREG]=CCREG;
9788             regs[k].regmap[HOST_CCREG]=CCREG;
9789             regmap_pre[k+1][HOST_CCREG]=CCREG;
9790             regs[k+1].wasdirty|=1<<HOST_CCREG;
9791             regs[k].dirty|=1<<HOST_CCREG;
9792             regs[k].wasconst&=~(1<<HOST_CCREG);
9793             regs[k].isconst&=~(1<<HOST_CCREG);
9794             k++;
9795           }
9796           regs[j].regmap_entry[HOST_CCREG]=CCREG;
9797         }
9798         // Work backwards from the branch target
9799         if(j>i&&f_regmap[HOST_CCREG]==CCREG)
9800         {
9801           //DebugMessage(M64MSG_VERBOSE, "Extend backwards");
9802           int k;
9803           k=i;
9804           while(regs[k-1].regmap[HOST_CCREG]==-1) {
9805             if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
9806               //DebugMessage(M64MSG_VERBOSE, "no free regs for store %x",start+(k-1)*4);
9807               break;
9808             }
9809             k--;
9810           }
9811           if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
9812             //DebugMessage(M64MSG_VERBOSE, "Extend CC, %x ->",start+k*4);
9813             while(k<=i) {
9814               regs[k].regmap_entry[HOST_CCREG]=CCREG;
9815               regs[k].regmap[HOST_CCREG]=CCREG;
9816               regmap_pre[k+1][HOST_CCREG]=CCREG;
9817               regs[k+1].wasdirty|=1<<HOST_CCREG;
9818               regs[k].dirty|=1<<HOST_CCREG;
9819               regs[k].wasconst&=~(1<<HOST_CCREG);
9820               regs[k].isconst&=~(1<<HOST_CCREG);
9821               k++;
9822             }
9823           }
9824           else {
9825             //DebugMessage(M64MSG_VERBOSE, "Fail Extend CC, %x ->",start+k*4);
9826           }
9827         }
9828       }
9829       if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
9830          itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
9831          itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
9832          itype[i]!=FCONV&&itype[i]!=FCOMP)
9833       {
9834         memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
9835       }
9836     }
9837   }
9838
9839   // Cache memory offset or tlb map pointer if a register is available
9840   #ifndef HOST_IMM_ADDR32
9841   #ifndef RAM_OFFSET
9842   if(using_tlb)
9843   #endif
9844   {
9845     int earliest_available[HOST_REGS];
9846     int loop_start[HOST_REGS];
9847     int score[HOST_REGS];
9848     int end[HOST_REGS];
9849     int reg=using_tlb?MMREG:ROREG;
9850
9851     // Init
9852     for(hr=0;hr<HOST_REGS;hr++) {
9853       score[hr]=0;earliest_available[hr]=0;
9854       loop_start[hr]=MAXBLOCK;
9855     }
9856     for(i=0;i<slen-1;i++)
9857     {
9858       // Can't do anything if no registers are available
9859       if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
9860         for(hr=0;hr<HOST_REGS;hr++) {
9861           score[hr]=0;earliest_available[hr]=i+1;
9862           loop_start[hr]=MAXBLOCK;
9863         }
9864       }
9865       if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
9866         if(!ooo[i]) {
9867           if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
9868             for(hr=0;hr<HOST_REGS;hr++) {
9869               score[hr]=0;earliest_available[hr]=i+1;
9870               loop_start[hr]=MAXBLOCK;
9871             }
9872           }
9873         }else{
9874           if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
9875             for(hr=0;hr<HOST_REGS;hr++) {
9876               score[hr]=0;earliest_available[hr]=i+1;
9877               loop_start[hr]=MAXBLOCK;
9878             }
9879           }
9880         }
9881       }
9882       // Mark unavailable registers
9883       for(hr=0;hr<HOST_REGS;hr++) {
9884         if(regs[i].regmap[hr]>=0) {
9885           score[hr]=0;earliest_available[hr]=i+1;
9886           loop_start[hr]=MAXBLOCK;
9887         }
9888         if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
9889           if(branch_regs[i].regmap[hr]>=0) {
9890             score[hr]=0;earliest_available[hr]=i+2;
9891             loop_start[hr]=MAXBLOCK;
9892           }
9893         }
9894       }
9895       // No register allocations after unconditional jumps
9896       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
9897       {
9898         for(hr=0;hr<HOST_REGS;hr++) {
9899           score[hr]=0;earliest_available[hr]=i+2;
9900           loop_start[hr]=MAXBLOCK;
9901         }
9902         i++; // Skip delay slot too
9903         //DebugMessage(M64MSG_VERBOSE, "skip delay slot: %x",start+i*4);
9904       }
9905       else
9906       // Possible match
9907       if(itype[i]==LOAD||itype[i]==LOADLR||
9908          itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
9909         for(hr=0;hr<HOST_REGS;hr++) {
9910           if(hr!=EXCLUDE_REG) {
9911             end[hr]=i-1;
9912             for(j=i;j<slen-1;j++) {
9913               if(regs[j].regmap[hr]>=0) break;
9914               if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
9915                 if(branch_regs[j].regmap[hr]>=0) break;
9916                 if(ooo[j]) {
9917                   if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
9918                 }else{
9919                   if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
9920                 }
9921               }
9922               else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
9923               if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
9924                 int t=(ba[j]-start)>>2;
9925                 if(t<j&&t>=earliest_available[hr]) {
9926                   if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
9927                     // Score a point for hoisting loop invariant
9928                     if(t<loop_start[hr]) loop_start[hr]=t;
9929                     //DebugMessage(M64MSG_VERBOSE, "set loop_start: i=%x j=%x (%x)",start+i*4,start+j*4,start+t*4);
9930                     score[hr]++;
9931                     end[hr]=j;
9932                   }
9933                 }
9934                 else if(t<j) {
9935                   if(regs[t].regmap[hr]==reg) {
9936                     // Score a point if the branch target matches this register
9937                     score[hr]++;
9938                     end[hr]=j;
9939                   }
9940                 }
9941                 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
9942                    itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
9943                   score[hr]++;
9944                   end[hr]=j;
9945                 }
9946               }
9947               if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
9948               {
9949                 // Stop on unconditional branch
9950                 break;
9951               }
9952               else
9953               if(itype[j]==LOAD||itype[j]==LOADLR||
9954                  itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
9955                 score[hr]++;
9956                 end[hr]=j;
9957               }
9958             }
9959           }
9960         }
9961         // Find highest score and allocate that register
9962         int maxscore=0;
9963         for(hr=0;hr<HOST_REGS;hr++) {
9964           if(hr!=EXCLUDE_REG) {
9965             if(score[hr]>score[maxscore]) {
9966               maxscore=hr;
9967               //DebugMessage(M64MSG_VERBOSE, "highest score: %d %d (%x->%x)",score[hr],hr,start+i*4,start+end[hr]*4);
9968             }
9969           }
9970         }
9971         if(score[maxscore]>1)
9972         {
9973           if(i<loop_start[maxscore]) loop_start[maxscore]=i;
9974           for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
9975             //if(regs[j].regmap[maxscore]>=0) {DebugMessage(M64MSG_ERROR, "oops: %x %x was %d=%d",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
9976             assert(regs[j].regmap[maxscore]<0);
9977             if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
9978             regs[j].regmap[maxscore]=reg;
9979             regs[j].dirty&=~(1<<maxscore);
9980             regs[j].wasconst&=~(1<<maxscore);
9981             regs[j].isconst&=~(1<<maxscore);
9982             if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
9983               branch_regs[j].regmap[maxscore]=reg;
9984               branch_regs[j].wasdirty&=~(1<<maxscore);
9985               branch_regs[j].dirty&=~(1<<maxscore);
9986               branch_regs[j].wasconst&=~(1<<maxscore);
9987               branch_regs[j].isconst&=~(1<<maxscore);
9988               if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
9989                 regmap_pre[j+2][maxscore]=reg;
9990                 regs[j+2].wasdirty&=~(1<<maxscore);
9991               }
9992               // loop optimization (loop_preload)
9993               int t=(ba[j]-start)>>2;
9994               if(t==loop_start[maxscore]) {
9995                 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
9996                   regs[t].regmap_entry[maxscore]=reg;
9997               }
9998             }
9999             else
10000             {
10001               if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
10002                 regmap_pre[j+1][maxscore]=reg;
10003                 regs[j+1].wasdirty&=~(1<<maxscore);
10004               }
10005             }
10006           }
10007           i=j-1;
10008           if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
10009           for(hr=0;hr<HOST_REGS;hr++) {
10010             score[hr]=0;earliest_available[hr]=i+i;
10011             loop_start[hr]=MAXBLOCK;
10012           }
10013         }
10014       }
10015     }
10016   }
10017   #endif
10018
10019   // This allocates registers (if possible) one instruction prior
10020   // to use, which can avoid a load-use penalty on certain CPUs.
10021   for(i=0;i<slen-1;i++)
10022   {
10023     if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10024     {
10025       if(!bt[i+1])
10026       {
10027         if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16||(itype[i]==COP1&&opcode2[i]<3))
10028         {
10029           if(rs1[i+1]) {
10030             if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10031             {
10032               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10033               {
10034                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10035                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10036                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10037                 regs[i].isconst&=~(1<<hr);
10038                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10039                 constmap[i][hr]=constmap[i+1][hr];
10040                 regs[i+1].wasdirty&=~(1<<hr);
10041                 regs[i].dirty&=~(1<<hr);
10042               }
10043             }
10044           }
10045           if(rs2[i+1]) {
10046             if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10047             {
10048               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10049               {
10050                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10051                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10052                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10053                 regs[i].isconst&=~(1<<hr);
10054                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10055                 constmap[i][hr]=constmap[i+1][hr];
10056                 regs[i+1].wasdirty&=~(1<<hr);
10057                 regs[i].dirty&=~(1<<hr);
10058               }
10059             }
10060           }
10061           // Preload target address for load instruction (non-constant)
10062           if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10063             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10064             {
10065               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10066               {
10067                 regs[i].regmap[hr]=rs1[i+1];
10068                 regmap_pre[i+1][hr]=rs1[i+1];
10069                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10070                 regs[i].isconst&=~(1<<hr);
10071                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10072                 constmap[i][hr]=constmap[i+1][hr];
10073                 regs[i+1].wasdirty&=~(1<<hr);
10074                 regs[i].dirty&=~(1<<hr);
10075               }
10076             }
10077           }
10078           // Load source into target register
10079           if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10080             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10081             {
10082               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10083               {
10084                 regs[i].regmap[hr]=rs1[i+1];
10085                 regmap_pre[i+1][hr]=rs1[i+1];
10086                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10087                 regs[i].isconst&=~(1<<hr);
10088                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10089                 constmap[i][hr]=constmap[i+1][hr];
10090                 regs[i+1].wasdirty&=~(1<<hr);
10091                 regs[i].dirty&=~(1<<hr);
10092               }
10093             }
10094           }
10095           // Preload map address
10096           #ifndef HOST_IMM_ADDR32
10097           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS) {
10098             hr=get_reg(regs[i+1].regmap,TLREG);
10099             if(hr>=0) {
10100               int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10101               if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10102                 int nr;
10103                 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10104                 {
10105                   regs[i].regmap[hr]=MGEN1+((i+1)&1);
10106                   regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10107                   regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10108                   regs[i].isconst&=~(1<<hr);
10109                   regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10110                   constmap[i][hr]=constmap[i+1][hr];
10111                   regs[i+1].wasdirty&=~(1<<hr);
10112                   regs[i].dirty&=~(1<<hr);
10113                 }
10114                 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10115                 {
10116                   // move it to another register
10117                   regs[i+1].regmap[hr]=-1;
10118                   regmap_pre[i+2][hr]=-1;
10119                   regs[i+1].regmap[nr]=TLREG;
10120                   regmap_pre[i+2][nr]=TLREG;
10121                   regs[i].regmap[nr]=MGEN1+((i+1)&1);
10122                   regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10123                   regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10124                   regs[i].isconst&=~(1<<nr);
10125                   regs[i+1].isconst&=~(1<<nr);
10126                   regs[i].dirty&=~(1<<nr);
10127                   regs[i+1].wasdirty&=~(1<<nr);
10128                   regs[i+1].dirty&=~(1<<nr);
10129                   regs[i+2].wasdirty&=~(1<<nr);
10130                 }
10131               }
10132             }
10133           }
10134           #endif
10135           // Address for store instruction (non-constant)
10136           if(itype[i+1]==STORE||itype[i+1]==STORELR||opcode[i+1]==0x39||opcode[i+1]==0x3D) { // SB/SH/SW/SD/SWC1/SDC1
10137             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10138               hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10139               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10140               else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10141               assert(hr>=0);
10142               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10143               {
10144                 regs[i].regmap[hr]=rs1[i+1];
10145                 regmap_pre[i+1][hr]=rs1[i+1];
10146                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10147                 regs[i].isconst&=~(1<<hr);
10148                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10149                 constmap[i][hr]=constmap[i+1][hr];
10150                 regs[i+1].wasdirty&=~(1<<hr);
10151                 regs[i].dirty&=~(1<<hr);
10152               }
10153             }
10154           }
10155           if(itype[i+1]==LOADLR||opcode[i+1]==0x31||opcode[i+1]==0x35) { // LWC1/LDC1
10156             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10157               int nr;
10158               hr=get_reg(regs[i+1].regmap,FTEMP);
10159               assert(hr>=0);
10160               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10161               {
10162                 regs[i].regmap[hr]=rs1[i+1];
10163                 regmap_pre[i+1][hr]=rs1[i+1];
10164                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10165                 regs[i].isconst&=~(1<<hr);
10166                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10167                 constmap[i][hr]=constmap[i+1][hr];
10168                 regs[i+1].wasdirty&=~(1<<hr);
10169                 regs[i].dirty&=~(1<<hr);
10170               }
10171               else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10172               {
10173                 // move it to another register
10174                 regs[i+1].regmap[hr]=-1;
10175                 regmap_pre[i+2][hr]=-1;
10176                 regs[i+1].regmap[nr]=FTEMP;
10177                 regmap_pre[i+2][nr]=FTEMP;
10178                 regs[i].regmap[nr]=rs1[i+1];
10179                 regmap_pre[i+1][nr]=rs1[i+1];
10180                 regs[i+1].regmap_entry[nr]=rs1[i+1];
10181                 regs[i].isconst&=~(1<<nr);
10182                 regs[i+1].isconst&=~(1<<nr);
10183                 regs[i].dirty&=~(1<<nr);
10184                 regs[i+1].wasdirty&=~(1<<nr);
10185                 regs[i+1].dirty&=~(1<<nr);
10186                 regs[i+2].wasdirty&=~(1<<nr);
10187               }
10188             }
10189           }
10190           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS*/) {
10191             if(itype[i+1]==LOAD)
10192               hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10193             if(itype[i+1]==LOADLR||opcode[i+1]==0x31||opcode[i+1]==0x35) // LWC1/LDC1
10194               hr=get_reg(regs[i+1].regmap,FTEMP);
10195             if(itype[i+1]==STORE||itype[i+1]==STORELR||opcode[i+1]==0x39||opcode[i+1]==0x3D) { // SWC1/SDC1
10196               hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10197               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10198             }
10199             if(hr>=0&&regs[i].regmap[hr]<0) {
10200               int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10201               if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10202                 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10203                 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10204                 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10205                 regs[i].isconst&=~(1<<hr);
10206                 regs[i+1].wasdirty&=~(1<<hr);
10207                 regs[i].dirty&=~(1<<hr);
10208               }
10209             }
10210           }
10211         }
10212       }
10213     }
10214   }
10215
10216   /* Pass 6 - Optimize clean/dirty state */
10217   clean_registers(0,slen-1,1);
10218
10219   /* Pass 7 - Identify 32-bit registers */
10220
10221   provisional_r32();
10222
10223   u_int r32=0;
10224
10225   for (i=slen-1;i>=0;i--)
10226   {
10227     int hr;
10228     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10229     {
10230       if(ba[i]<start || ba[i]>=(start+slen*4))
10231       {
10232         // Branch out of this block, don't need anything
10233         r32=0;
10234       }
10235       else
10236       {
10237         // Internal branch
10238         // Need whatever matches the target
10239         // (and doesn't get overwritten by the delay slot instruction)
10240         r32=0;
10241         int t=(ba[i]-start)>>2;
10242         if(ba[i]>start+i*4) {
10243           // Forward branch
10244           if(!(requires_32bit[t]&~regs[i].was32))
10245             r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10246         }else{
10247           // Backward branch
10248           //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10249           //  r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10250           if(!(pr32[t]&~regs[i].was32))
10251             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10252         }
10253       }
10254       // Conditional branch may need registers for following instructions
10255       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10256       {
10257         if(i<slen-2) {
10258           r32|=requires_32bit[i+2];
10259           r32&=regs[i].was32;
10260           // Mark this address as a branch target since it may be called
10261           // upon return from interrupt
10262           bt[i+2]=1;
10263         }
10264       }
10265       // Merge in delay slot
10266       if(!likely[i]) {
10267         // These are overwritten unless the branch is "likely"
10268         // and the delay slot is nullified if not taken
10269         r32&=~(1LL<<rt1[i+1]);
10270         r32&=~(1LL<<rt2[i+1]);
10271       }
10272       // Assume these are needed (delay slot)
10273       if(us1[i+1]>0)
10274       {
10275         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10276       }
10277       if(us2[i+1]>0)
10278       {
10279         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10280       }
10281       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10282       {
10283         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10284       }
10285       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10286       {
10287         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10288       }
10289     }
10290     else if(itype[i]==SYSCALL)
10291     {
10292       // SYSCALL instruction (software interrupt)
10293       r32=0;
10294     }
10295     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10296     {
10297       // ERET instruction (return from interrupt)
10298       r32=0;
10299     }
10300     // Check 32 bits
10301     r32&=~(1LL<<rt1[i]);
10302     r32&=~(1LL<<rt2[i]);
10303     if(us1[i]>0)
10304     {
10305       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10306     }
10307     if(us2[i]>0)
10308     {
10309       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10310     }
10311     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10312     {
10313       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10314     }
10315     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10316     {
10317       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10318     }
10319     requires_32bit[i]=r32;
10320
10321     // Dirty registers which are 32-bit, require 32-bit input
10322     // as they will be written as 32-bit values
10323     for(hr=0;hr<HOST_REGS;hr++)
10324     {
10325       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
10326         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10327           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10328           requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10329         }
10330       }
10331     }
10332     //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10333   }
10334
10335   if(itype[slen-1]==SPAN) {
10336     bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10337   }
10338
10339   /* Debug/disassembly */
10340 //  if((void*)assem_debug==(void*)printf)
10341 #if defined( ASSEM_DEBUG )
10342   for(i=0;i<slen;i++)
10343   {
10344     DebugMessage(M64MSG_VERBOSE, "U:");
10345     int r;
10346     for(r=1;r<=CCREG;r++) {
10347       if((unneeded_reg[i]>>r)&1) {
10348         if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI");
10349         else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO");
10350         else DebugMessage(M64MSG_VERBOSE, " r%d",r);
10351       }
10352     }
10353     DebugMessage(M64MSG_VERBOSE, " UU:");
10354     for(r=1;r<=CCREG;r++) {
10355       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10356         if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI");
10357         else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO");
10358         else DebugMessage(M64MSG_VERBOSE, " r%d",r);
10359       }
10360     }
10361     DebugMessage(M64MSG_VERBOSE, " 32:");
10362     for(r=0;r<=CCREG;r++) {
10363       //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10364       if((regs[i].was32>>r)&1) {
10365         if(r==CCREG) DebugMessage(M64MSG_VERBOSE, " CC");
10366         else if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI");
10367         else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO");
10368         else DebugMessage(M64MSG_VERBOSE, " r%d",r);
10369       }
10370     }
10371     #if NEW_DYNAREC == NEW_DYNAREC_X86
10372     DebugMessage(M64MSG_VERBOSE, "pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10373     #endif
10374     #if NEW_DYNAREC == NEW_DYNAREC_ARM
10375     DebugMessage(M64MSG_VERBOSE, "pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10376     #endif
10377     DebugMessage(M64MSG_VERBOSE, "needs: ");
10378     if(needed_reg[i]&1) DebugMessage(M64MSG_VERBOSE, "eax ");
10379     if((needed_reg[i]>>1)&1) DebugMessage(M64MSG_VERBOSE, "ecx ");
10380     if((needed_reg[i]>>2)&1) DebugMessage(M64MSG_VERBOSE, "edx ");
10381     if((needed_reg[i]>>3)&1) DebugMessage(M64MSG_VERBOSE, "ebx ");
10382     if((needed_reg[i]>>5)&1) DebugMessage(M64MSG_VERBOSE, "ebp ");
10383     if((needed_reg[i]>>6)&1) DebugMessage(M64MSG_VERBOSE, "esi ");
10384     if((needed_reg[i]>>7)&1) DebugMessage(M64MSG_VERBOSE, "edi ");
10385     DebugMessage(M64MSG_VERBOSE, "r:");
10386     for(r=0;r<=CCREG;r++) {
10387       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10388       if((requires_32bit[i]>>r)&1) {
10389         if(r==CCREG) DebugMessage(M64MSG_VERBOSE, " CC");
10390         else if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI");
10391         else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO");
10392         else DebugMessage(M64MSG_VERBOSE, " r%d",r);
10393       }
10394     }
10395     /*DebugMessage(M64MSG_VERBOSE, "pr:");
10396     for(r=0;r<=CCREG;r++) {
10397       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10398       if((pr32[i]>>r)&1) {
10399         if(r==CCREG) DebugMessage(M64MSG_VERBOSE, " CC");
10400         else if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI");
10401         else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO");
10402         else DebugMessage(M64MSG_VERBOSE, " r%d",r);
10403       }
10404     }
10405     if(pr32[i]!=requires_32bit[i]) DebugMessage(M64MSG_ERROR, " OOPS");*/
10406     #if NEW_DYNAREC == NEW_DYNAREC_X86
10407     DebugMessage(M64MSG_VERBOSE, "entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10408     DebugMessage(M64MSG_VERBOSE, "dirty: ");
10409     if(regs[i].wasdirty&1) DebugMessage(M64MSG_VERBOSE, "eax ");
10410     if((regs[i].wasdirty>>1)&1) DebugMessage(M64MSG_VERBOSE, "ecx ");
10411     if((regs[i].wasdirty>>2)&1) DebugMessage(M64MSG_VERBOSE, "edx ");
10412     if((regs[i].wasdirty>>3)&1) DebugMessage(M64MSG_VERBOSE, "ebx ");
10413     if((regs[i].wasdirty>>5)&1) DebugMessage(M64MSG_VERBOSE, "ebp ");
10414     if((regs[i].wasdirty>>6)&1) DebugMessage(M64MSG_VERBOSE, "esi ");
10415     if((regs[i].wasdirty>>7)&1) DebugMessage(M64MSG_VERBOSE, "edi ");
10416     #endif
10417     #if NEW_DYNAREC == NEW_DYNAREC_ARM
10418     DebugMessage(M64MSG_VERBOSE, "entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10419     DebugMessage(M64MSG_VERBOSE, "dirty: ");
10420     if(regs[i].wasdirty&1) DebugMessage(M64MSG_VERBOSE, "r0 ");
10421     if((regs[i].wasdirty>>1)&1) DebugMessage(M64MSG_VERBOSE, "r1 ");
10422     if((regs[i].wasdirty>>2)&1) DebugMessage(M64MSG_VERBOSE, "r2 ");
10423     if((regs[i].wasdirty>>3)&1) DebugMessage(M64MSG_VERBOSE, "r3 ");
10424     if((regs[i].wasdirty>>4)&1) DebugMessage(M64MSG_VERBOSE, "r4 ");
10425     if((regs[i].wasdirty>>5)&1) DebugMessage(M64MSG_VERBOSE, "r5 ");
10426     if((regs[i].wasdirty>>6)&1) DebugMessage(M64MSG_VERBOSE, "r6 ");
10427     if((regs[i].wasdirty>>7)&1) DebugMessage(M64MSG_VERBOSE, "r7 ");
10428     if((regs[i].wasdirty>>8)&1) DebugMessage(M64MSG_VERBOSE, "r8 ");
10429     if((regs[i].wasdirty>>9)&1) DebugMessage(M64MSG_VERBOSE, "r9 ");
10430     if((regs[i].wasdirty>>10)&1) DebugMessage(M64MSG_VERBOSE, "r10 ");
10431     if((regs[i].wasdirty>>12)&1) DebugMessage(M64MSG_VERBOSE, "r12 ");
10432     #endif
10433     disassemble_inst(i);
10434     //printf ("ccadj[%d] = %d",i,ccadj[i]);
10435     #if NEW_DYNAREC == NEW_DYNAREC_X86
10436     DebugMessage(M64MSG_VERBOSE, "eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10437     if(regs[i].dirty&1) DebugMessage(M64MSG_VERBOSE, "eax ");
10438     if((regs[i].dirty>>1)&1) DebugMessage(M64MSG_VERBOSE, "ecx ");
10439     if((regs[i].dirty>>2)&1) DebugMessage(M64MSG_VERBOSE, "edx ");
10440     if((regs[i].dirty>>3)&1) DebugMessage(M64MSG_VERBOSE, "ebx ");
10441     if((regs[i].dirty>>5)&1) DebugMessage(M64MSG_VERBOSE, "ebp ");
10442     if((regs[i].dirty>>6)&1) DebugMessage(M64MSG_VERBOSE, "esi ");
10443     if((regs[i].dirty>>7)&1) DebugMessage(M64MSG_VERBOSE, "edi ");
10444     #endif
10445     #if NEW_DYNAREC == NEW_DYNAREC_ARM
10446     DebugMessage(M64MSG_VERBOSE, "r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
10447     if(regs[i].dirty&1) DebugMessage(M64MSG_VERBOSE, "r0 ");
10448     if((regs[i].dirty>>1)&1) DebugMessage(M64MSG_VERBOSE, "r1 ");
10449     if((regs[i].dirty>>2)&1) DebugMessage(M64MSG_VERBOSE, "r2 ");
10450     if((regs[i].dirty>>3)&1) DebugMessage(M64MSG_VERBOSE, "r3 ");
10451     if((regs[i].dirty>>4)&1) DebugMessage(M64MSG_VERBOSE, "r4 ");
10452     if((regs[i].dirty>>5)&1) DebugMessage(M64MSG_VERBOSE, "r5 ");
10453     if((regs[i].dirty>>6)&1) DebugMessage(M64MSG_VERBOSE, "r6 ");
10454     if((regs[i].dirty>>7)&1) DebugMessage(M64MSG_VERBOSE, "r7 ");
10455     if((regs[i].dirty>>8)&1) DebugMessage(M64MSG_VERBOSE, "r8 ");
10456     if((regs[i].dirty>>9)&1) DebugMessage(M64MSG_VERBOSE, "r9 ");
10457     if((regs[i].dirty>>10)&1) DebugMessage(M64MSG_VERBOSE, "r10 ");
10458     if((regs[i].dirty>>12)&1) DebugMessage(M64MSG_VERBOSE, "r12 ");
10459     #endif
10460     if(regs[i].isconst) {
10461       DebugMessage(M64MSG_VERBOSE, "constants: ");
10462       #if NEW_DYNAREC == NEW_DYNAREC_X86
10463       if(regs[i].isconst&1) DebugMessage(M64MSG_VERBOSE, "eax=%x ",(int)constmap[i][0]);
10464       if((regs[i].isconst>>1)&1) DebugMessage(M64MSG_VERBOSE, "ecx=%x ",(int)constmap[i][1]);
10465       if((regs[i].isconst>>2)&1) DebugMessage(M64MSG_VERBOSE, "edx=%x ",(int)constmap[i][2]);
10466       if((regs[i].isconst>>3)&1) DebugMessage(M64MSG_VERBOSE, "ebx=%x ",(int)constmap[i][3]);
10467       if((regs[i].isconst>>5)&1) DebugMessage(M64MSG_VERBOSE, "ebp=%x ",(int)constmap[i][5]);
10468       if((regs[i].isconst>>6)&1) DebugMessage(M64MSG_VERBOSE, "esi=%x ",(int)constmap[i][6]);
10469       if((regs[i].isconst>>7)&1) DebugMessage(M64MSG_VERBOSE, "edi=%x ",(int)constmap[i][7]);
10470       #endif
10471       #if NEW_DYNAREC == NEW_DYNAREC_ARM
10472       if(regs[i].isconst&1) DebugMessage(M64MSG_VERBOSE, "r0=%x ",(int)constmap[i][0]);
10473       if((regs[i].isconst>>1)&1) DebugMessage(M64MSG_VERBOSE, "r1=%x ",(int)constmap[i][1]);
10474       if((regs[i].isconst>>2)&1) DebugMessage(M64MSG_VERBOSE, "r2=%x ",(int)constmap[i][2]);
10475       if((regs[i].isconst>>3)&1) DebugMessage(M64MSG_VERBOSE, "r3=%x ",(int)constmap[i][3]);
10476       if((regs[i].isconst>>4)&1) DebugMessage(M64MSG_VERBOSE, "r4=%x ",(int)constmap[i][4]);
10477       if((regs[i].isconst>>5)&1) DebugMessage(M64MSG_VERBOSE, "r5=%x ",(int)constmap[i][5]);
10478       if((regs[i].isconst>>6)&1) DebugMessage(M64MSG_VERBOSE, "r6=%x ",(int)constmap[i][6]);
10479       if((regs[i].isconst>>7)&1) DebugMessage(M64MSG_VERBOSE, "r7=%x ",(int)constmap[i][7]);
10480       if((regs[i].isconst>>8)&1) DebugMessage(M64MSG_VERBOSE, "r8=%x ",(int)constmap[i][8]);
10481       if((regs[i].isconst>>9)&1) DebugMessage(M64MSG_VERBOSE, "r9=%x ",(int)constmap[i][9]);
10482       if((regs[i].isconst>>10)&1) DebugMessage(M64MSG_VERBOSE, "r10=%x ",(int)constmap[i][10]);
10483       if((regs[i].isconst>>12)&1) DebugMessage(M64MSG_VERBOSE, "r12=%x ",(int)constmap[i][12]);
10484       #endif
10485     }
10486     DebugMessage(M64MSG_VERBOSE, " 32:");
10487     for(r=0;r<=CCREG;r++) {
10488       if((regs[i].is32>>r)&1) {
10489         if(r==CCREG) DebugMessage(M64MSG_VERBOSE, " CC");
10490         else if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI");
10491         else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO");
10492         else DebugMessage(M64MSG_VERBOSE, " r%d",r);
10493       }
10494     }
10495     /*DebugMessage(M64MSG_VERBOSE, " p32:");
10496     for(r=0;r<=CCREG;r++) {
10497       if((p32[i]>>r)&1) {
10498         if(r==CCREG) DebugMessage(M64MSG_VERBOSE, " CC");
10499         else if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI");
10500         else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO");
10501         else DebugMessage(M64MSG_VERBOSE, " r%d",r);
10502       }
10503     }
10504     if(p32[i]!=regs[i].is32) DebugMessage(M64MSG_VERBOSE, " NO MATCH");*/
10505     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10506       #if NEW_DYNAREC == NEW_DYNAREC_X86
10507       DebugMessage(M64MSG_VERBOSE, "branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
10508       if(branch_regs[i].dirty&1) DebugMessage(M64MSG_VERBOSE, "eax ");
10509       if((branch_regs[i].dirty>>1)&1) DebugMessage(M64MSG_VERBOSE, "ecx ");
10510       if((branch_regs[i].dirty>>2)&1) DebugMessage(M64MSG_VERBOSE, "edx ");
10511       if((branch_regs[i].dirty>>3)&1) DebugMessage(M64MSG_VERBOSE, "ebx ");
10512       if((branch_regs[i].dirty>>5)&1) DebugMessage(M64MSG_VERBOSE, "ebp ");
10513       if((branch_regs[i].dirty>>6)&1) DebugMessage(M64MSG_VERBOSE, "esi ");
10514       if((branch_regs[i].dirty>>7)&1) DebugMessage(M64MSG_VERBOSE, "edi ");
10515       #endif
10516       #if NEW_DYNAREC == NEW_DYNAREC_ARM
10517       DebugMessage(M64MSG_VERBOSE, "branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
10518       if(branch_regs[i].dirty&1) DebugMessage(M64MSG_VERBOSE, "r0 ");
10519       if((branch_regs[i].dirty>>1)&1) DebugMessage(M64MSG_VERBOSE, "r1 ");
10520       if((branch_regs[i].dirty>>2)&1) DebugMessage(M64MSG_VERBOSE, "r2 ");
10521       if((branch_regs[i].dirty>>3)&1) DebugMessage(M64MSG_VERBOSE, "r3 ");
10522       if((branch_regs[i].dirty>>4)&1) DebugMessage(M64MSG_VERBOSE, "r4 ");
10523       if((branch_regs[i].dirty>>5)&1) DebugMessage(M64MSG_VERBOSE, "r5 ");
10524       if((branch_regs[i].dirty>>6)&1) DebugMessage(M64MSG_VERBOSE, "r6 ");
10525       if((branch_regs[i].dirty>>7)&1) DebugMessage(M64MSG_VERBOSE, "r7 ");
10526       if((branch_regs[i].dirty>>8)&1) DebugMessage(M64MSG_VERBOSE, "r8 ");
10527       if((branch_regs[i].dirty>>9)&1) DebugMessage(M64MSG_VERBOSE, "r9 ");
10528       if((branch_regs[i].dirty>>10)&1) DebugMessage(M64MSG_VERBOSE, "r10 ");
10529       if((branch_regs[i].dirty>>12)&1) DebugMessage(M64MSG_VERBOSE, "r12 ");
10530       #endif
10531       DebugMessage(M64MSG_VERBOSE, " 32:");
10532       for(r=0;r<=CCREG;r++) {
10533         if((branch_regs[i].is32>>r)&1) {
10534           if(r==CCREG) DebugMessage(M64MSG_VERBOSE, " CC");
10535           else if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI");
10536           else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO");
10537           else DebugMessage(M64MSG_VERBOSE, " r%d",r);
10538         }
10539       }
10540     }
10541   }
10542 #endif
10543
10544   /* Pass 8 - Assembly */
10545   linkcount=0;stubcount=0;
10546   ds=0;is_delayslot=0;
10547   cop1_usable=0;
10548   #ifndef DESTRUCTIVE_WRITEBACK
10549   uint64_t is32_pre=0;
10550   u_int dirty_pre=0;
10551   #endif
10552   u_int beginning=(u_int)out;
10553   if((u_int)addr&1) {
10554     ds=1;
10555     pagespan_ds();
10556   }
10557   for(i=0;i<slen;i++)
10558   {
10559     //if(ds) DebugMessage(M64MSG_VERBOSE, "ds: ");
10560 //    if((void*)assem_debug==(void*)printf) disassemble_inst(i);
10561 #if defined( ASSEM_DEBUG )
10562           disassemble_inst(i);
10563 #endif
10564     if(ds) {
10565       ds=0; // Skip delay slot
10566       if(bt[i]) assem_debug("OOPS - branch into delay slot");
10567       instr_addr[i]=0;
10568     } else {
10569       #ifndef DESTRUCTIVE_WRITEBACK
10570       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10571       {
10572         wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
10573               unneeded_reg[i],unneeded_reg_upper[i]);
10574         wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
10575               unneeded_reg[i],unneeded_reg_upper[i]);
10576       }
10577       is32_pre=regs[i].is32;
10578       dirty_pre=regs[i].dirty;
10579       #endif
10580       // write back
10581       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10582       {
10583         wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
10584                       unneeded_reg[i],unneeded_reg_upper[i]);
10585         loop_preload(regmap_pre[i],regs[i].regmap_entry);
10586       }
10587       // branch target entry point
10588       instr_addr[i]=(u_int)out;
10589       assem_debug("<->");
10590       // load regs
10591       if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
10592         wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
10593       load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
10594       address_generation(i,&regs[i],regs[i].regmap_entry);
10595       load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
10596       if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10597       {
10598         // Load the delay slot registers if necessary
10599         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10600           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10601         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10602           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10603         if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39)
10604           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10605       }
10606       else if(i+1<slen)
10607       {
10608         // Preload registers for following instruction
10609         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10610           if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
10611             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10612         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10613           if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
10614             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10615       }
10616       // TODO: if(is_ooo(i)) address_generation(i+1);
10617       if(itype[i]==CJUMP||itype[i]==FJUMP)
10618         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
10619       if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS)
10620         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,MMREG,ROREG);
10621       if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39)
10622         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10623       if(bt[i]) cop1_usable=0;
10624       // assemble
10625       switch(itype[i]) {
10626         case ALU:
10627           alu_assemble(i,&regs[i]);break;
10628         case IMM16:
10629           imm16_assemble(i,&regs[i]);break;
10630         case SHIFT:
10631           shift_assemble(i,&regs[i]);break;
10632         case SHIFTIMM:
10633           shiftimm_assemble(i,&regs[i]);break;
10634         case LOAD:
10635           load_assemble(i,&regs[i]);break;
10636         case LOADLR:
10637           loadlr_assemble(i,&regs[i]);break;
10638         case STORE:
10639           store_assemble(i,&regs[i]);break;
10640         case STORELR:
10641           storelr_assemble(i,&regs[i]);break;
10642         case COP0:
10643           cop0_assemble(i,&regs[i]);break;
10644         case COP1:
10645           cop1_assemble(i,&regs[i]);break;
10646         case C1LS:
10647           c1ls_assemble(i,&regs[i]);break;
10648         case FCONV:
10649           fconv_assemble(i,&regs[i]);break;
10650         case FLOAT:
10651           float_assemble(i,&regs[i]);break;
10652         case FCOMP:
10653           fcomp_assemble(i,&regs[i]);break;
10654         case MULTDIV:
10655           multdiv_assemble(i,&regs[i]);break;
10656         case MOV:
10657           mov_assemble(i,&regs[i]);break;
10658         case SYSCALL:
10659           syscall_assemble(i,&regs[i]);break;
10660         case UJUMP:
10661           ujump_assemble(i,&regs[i]);ds=1;break;
10662         case RJUMP:
10663           rjump_assemble(i,&regs[i]);ds=1;break;
10664         case CJUMP:
10665           cjump_assemble(i,&regs[i]);ds=1;break;
10666         case SJUMP:
10667           sjump_assemble(i,&regs[i]);ds=1;break;
10668         case FJUMP:
10669           fjump_assemble(i,&regs[i]);ds=1;break;
10670         case SPAN:
10671           pagespan_assemble(i,&regs[i]);break;
10672       }
10673       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10674         literal_pool(1024);
10675       else
10676         literal_pool_jumpover(256);
10677     }
10678   }
10679   //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
10680   // If the block did not end with an unconditional branch,
10681   // add a jump to the next instruction.
10682   if(i>1) {
10683     if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
10684       assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10685       assert(i==slen);
10686       if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
10687         store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10688         if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10689           emit_loadreg(CCREG,HOST_CCREG);
10690         emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10691       }
10692       else if(!likely[i-2])
10693       {
10694         store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
10695         assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
10696       }
10697       else
10698       {
10699         store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
10700         assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
10701       }
10702       add_to_linker((int)out,start+i*4,0);
10703       emit_jmp(0);
10704     }
10705   }
10706   else
10707   {
10708     assert(i>0);
10709     assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10710     store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10711     if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10712       emit_loadreg(CCREG,HOST_CCREG);
10713     emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10714     add_to_linker((int)out,start+i*4,0);
10715     emit_jmp(0);
10716   }
10717
10718   // TODO: delay slot stubs?
10719   // Stubs
10720   for(i=0;i<stubcount;i++)
10721   {
10722     switch(stubs[i][0])
10723     {
10724       case LOADB_STUB:
10725       case LOADH_STUB:
10726       case LOADW_STUB:
10727       case LOADD_STUB:
10728       case LOADBU_STUB:
10729       case LOADHU_STUB:
10730         do_readstub(i);break;
10731       case STOREB_STUB:
10732       case STOREH_STUB:
10733       case STOREW_STUB:
10734       case STORED_STUB:
10735         do_writestub(i);break;
10736       case CC_STUB:
10737         do_ccstub(i);break;
10738       case INVCODE_STUB:
10739         do_invstub(i);break;
10740       case FP_STUB:
10741         do_cop1stub(i);break;
10742       case STORELR_STUB:
10743         do_unalignedwritestub(i);break;
10744     }
10745   }
10746
10747   /* Pass 9 - Linker */
10748   for(i=0;i<linkcount;i++)
10749   {
10750     assem_debug("%8x -> %8x",link_addr[i][0],link_addr[i][1]);
10751     literal_pool(64);
10752     if(!link_addr[i][2])
10753     {
10754       void *stub=out;
10755       void *addr=check_addr(link_addr[i][1]);
10756       emit_extjump(link_addr[i][0],link_addr[i][1]);
10757       if(addr) {
10758         set_jump_target(link_addr[i][0],(int)addr);
10759         add_link(link_addr[i][1],stub);
10760       }
10761       else set_jump_target(link_addr[i][0],(int)stub);
10762     }
10763     else
10764     {
10765       // Internal branch
10766       int target=(link_addr[i][1]-start)>>2;
10767       assert(target>=0&&target<slen);
10768       assert(instr_addr[target]);
10769       //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10770       //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
10771       //#else
10772       set_jump_target(link_addr[i][0],instr_addr[target]);
10773       //#endif
10774     }
10775   }
10776   // External Branch Targets (jump_in)
10777   if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
10778   for(i=0;i<slen;i++)
10779   {
10780     if(bt[i]||i==0)
10781     {
10782       if(instr_addr[i]) // TODO - delay slots (=null)
10783       {
10784         u_int vaddr=start+i*4;
10785         u_int page=(0x80000000^vaddr)>>12;
10786         u_int vpage=page;
10787         if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[page^0x80000]^0x80000000)>>12;
10788         if(page>2048) page=2048+(page&2047);
10789         if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
10790         if(vpage>2048) vpage=2048+(vpage&2047);
10791         literal_pool(256);
10792         //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
10793         if(!requires_32bit[i])
10794         {
10795           assem_debug("%8x (%d) <- %8x",instr_addr[i],i,start+i*4);
10796           assem_debug("jump_in: %x",start+i*4);
10797           ll_add(jump_dirty+vpage,vaddr,(void *)out);
10798           int entry_point=do_dirty_stub(i);
10799           ll_add(jump_in+page,vaddr,(void *)entry_point);
10800           // If there was an existing entry in the hash table,
10801           // replace it with the new address.
10802           // Don't add new entries.  We'll insert the
10803           // ones that actually get used in check_addr().
10804           u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
10805           if(ht_bin[0]==vaddr) {
10806             ht_bin[1]=entry_point;
10807           }
10808           if(ht_bin[2]==vaddr) {
10809             ht_bin[3]=entry_point;
10810           }
10811         }
10812         else
10813         {
10814           u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
10815           assem_debug("%8x (%d) <- %8x",instr_addr[i],i,start+i*4);
10816           assem_debug("jump_in: %x (restricted - %x)",start+i*4,r);
10817           //int entry_point=(int)out;
10818           ////assem_debug("entry_point: %x",entry_point);
10819           //load_regs_entry(i);
10820           //if(entry_point==(int)out)
10821           //  entry_point=instr_addr[i];
10822           //else
10823           //  emit_jmp(instr_addr[i]);
10824           //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10825           ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
10826           int entry_point=do_dirty_stub(i);
10827           ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10828         }
10829       }
10830     }
10831   }
10832   // Write out the literal pool if necessary
10833   literal_pool(0);
10834   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10835   // Align code
10836   if(((u_int)out)&7) emit_addnop(13);
10837   #endif
10838   assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
10839   //DebugMessage(M64MSG_VERBOSE, "shadow buffer: %x-%x",(int)copy,(int)copy+slen*4);
10840   memcpy(copy,source,slen*4);
10841   copy+=slen*4;
10842
10843   #if NEW_DYNAREC == NEW_DYNAREC_ARM
10844   __clear_cache((void *)beginning,out);
10845   //cacheflush((void *)beginning,out,0);
10846   #endif
10847
10848   // If we're within 256K of the end of the buffer,
10849   // start over from the beginning. (Is 256K enough?)
10850   if(out > (u_char *)(base_addr+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE-JUMP_TABLE_SIZE))
10851     out=(u_char *)base_addr;
10852
10853   // Trap writes to any of the pages we compiled
10854   for(i=start>>12;i<=(start+slen*4)>>12;i++) {
10855     invalid_code[i]=0;
10856     memory_map[i]|=0x40000000;
10857     if((signed int)start>=(signed int)0xC0000000) {
10858       assert(using_tlb);
10859       j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
10860       invalid_code[j]=0;
10861       memory_map[j]|=0x40000000;
10862       //DebugMessage(M64MSG_VERBOSE, "write protect physical page: %x (virtual %x)",j<<12,start);
10863     }
10864   }
10865
10866   /* Pass 10 - Free memory by expiring oldest blocks */
10867
10868   int end=((((intptr_t)out-(intptr_t)base_addr)>>(TARGET_SIZE_2-16))+16384)&65535;
10869   while(expirep!=end)
10870   {
10871     int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
10872     int base=(int)base_addr+((expirep>>13)<<shift); // Base address of this block
10873     inv_debug("EXP: Phase %d\n",expirep);
10874     switch((expirep>>11)&3)
10875     {
10876       case 0:
10877         // Clear jump_in and jump_dirty
10878         ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
10879         ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
10880         ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
10881         ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
10882         break;
10883       case 1:
10884         // Clear pointers
10885         ll_kill_pointers(jump_out[expirep&2047],base,shift);
10886         ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
10887         break;
10888       case 2:
10889         // Clear hash table
10890         for(i=0;i<32;i++) {
10891           u_int *ht_bin=hash_table[((expirep&2047)<<5)+i];
10892           if((ht_bin[3]>>shift)==(base>>shift) ||
10893              ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10894             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
10895             ht_bin[2]=ht_bin[3]=-1;
10896           }
10897           if((ht_bin[1]>>shift)==(base>>shift) ||
10898              ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10899             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
10900             ht_bin[0]=ht_bin[2];
10901             ht_bin[1]=ht_bin[3];
10902             ht_bin[2]=ht_bin[3]=-1;
10903           }
10904         }
10905         break;
10906       case 3:
10907         // Clear jump_out
10908         #if NEW_DYNAREC == NEW_DYNAREC_ARM
10909         if((expirep&2047)==0)
10910           do_clear_cache();
10911         #endif
10912         ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
10913         ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
10914         break;
10915     }
10916     expirep=(expirep+1)&65535;
10917   }
10918   return 0;
10919 }
10920
10921 void TLBWI_new(void)
10922 {
10923   unsigned int i;
10924   /* Remove old entries */
10925   unsigned int old_start_even=tlb_e[Index&0x3F].start_even;
10926   unsigned int old_end_even=tlb_e[Index&0x3F].end_even;
10927   unsigned int old_start_odd=tlb_e[Index&0x3F].start_odd;
10928   unsigned int old_end_odd=tlb_e[Index&0x3F].end_odd;
10929   for (i=old_start_even>>12; i<=old_end_even>>12; i++)
10930   {
10931     if(i<0x80000||i>0xBFFFF)
10932     {
10933       invalidate_block(i);
10934       memory_map[i]=-1;
10935     }
10936   }
10937   for (i=old_start_odd>>12; i<=old_end_odd>>12; i++)
10938   {
10939     if(i<0x80000||i>0xBFFFF)
10940     {
10941       invalidate_block(i);
10942       memory_map[i]=-1;
10943     }
10944   }
10945   cached_interpreter_table.TLBWI();
10946   //DebugMessage(M64MSG_VERBOSE, "TLBWI: index=%d",Index);
10947   //DebugMessage(M64MSG_VERBOSE, "TLBWI: start_even=%x end_even=%x phys_even=%x v=%d d=%d",tlb_e[Index&0x3F].start_even,tlb_e[Index&0x3F].end_even,tlb_e[Index&0x3F].phys_even,tlb_e[Index&0x3F].v_even,tlb_e[Index&0x3F].d_even);
10948   //DebugMessage(M64MSG_VERBOSE, "TLBWI: start_odd=%x end_odd=%x phys_odd=%x v=%d d=%d",tlb_e[Index&0x3F].start_odd,tlb_e[Index&0x3F].end_odd,tlb_e[Index&0x3F].phys_odd,tlb_e[Index&0x3F].v_odd,tlb_e[Index&0x3F].d_odd);
10949   /* Combine tlb_LUT_r, tlb_LUT_w, and invalid_code into a single table
10950      for fast look up. */
10951   for (i=tlb_e[Index&0x3F].start_even>>12; i<=tlb_e[Index&0x3F].end_even>>12; i++)
10952   {
10953     //DebugMessage(M64MSG_VERBOSE, "%x: r:%8x w:%8x",i,tlb_LUT_r[i],tlb_LUT_w[i]);
10954     if(i<0x80000||i>0xBFFFF)
10955     {
10956       if(tlb_LUT_r[i]) {
10957         memory_map[i]=((tlb_LUT_r[i]&0xFFFFF000)-(i<<12)+(unsigned int)rdram-0x80000000)>>2;
10958         // FIXME: should make sure the physical page is invalid too
10959         if(!tlb_LUT_w[i]||!invalid_code[i]) {
10960           memory_map[i]|=0x40000000; // Write protect
10961         }else{
10962           assert(tlb_LUT_r[i]==tlb_LUT_w[i]);
10963         }
10964         if(!using_tlb) DebugMessage(M64MSG_VERBOSE, "Enabled TLB");
10965         // Tell the dynamic recompiler to generate tlb lookup code
10966         using_tlb=1;
10967       }
10968       else memory_map[i]=-1;
10969     }
10970     //DebugMessage(M64MSG_VERBOSE, "memory_map[%x]: %8x (+%8x)",i,memory_map[i],memory_map[i]<<2);
10971   }
10972   for (i=tlb_e[Index&0x3F].start_odd>>12; i<=tlb_e[Index&0x3F].end_odd>>12; i++)
10973   {
10974     //DebugMessage(M64MSG_VERBOSE, "%x: r:%8x w:%8x",i,tlb_LUT_r[i],tlb_LUT_w[i]);
10975     if(i<0x80000||i>0xBFFFF)
10976     {
10977       if(tlb_LUT_r[i]) {
10978         memory_map[i]=((tlb_LUT_r[i]&0xFFFFF000)-(i<<12)+(unsigned int)rdram-0x80000000)>>2;
10979         // FIXME: should make sure the physical page is invalid too
10980         if(!tlb_LUT_w[i]||!invalid_code[i]) {
10981           memory_map[i]|=0x40000000; // Write protect
10982         }else{
10983           assert(tlb_LUT_r[i]==tlb_LUT_w[i]);
10984         }
10985         if(!using_tlb) DebugMessage(M64MSG_VERBOSE, "Enabled TLB");
10986         // Tell the dynamic recompiler to generate tlb lookup code
10987         using_tlb=1;
10988       }
10989       else memory_map[i]=-1;
10990     }
10991     //DebugMessage(M64MSG_VERBOSE, "memory_map[%x]: %8x (+%8x)",i,memory_map[i],memory_map[i]<<2);
10992   }
10993 }
10994
10995 void TLBWR_new(void)
10996 {
10997   unsigned int i;
10998   Random = (Count/2 % (32 - Wired)) + Wired;
10999   /* Remove old entries */
11000   unsigned int old_start_even=tlb_e[Random&0x3F].start_even;
11001   unsigned int old_end_even=tlb_e[Random&0x3F].end_even;
11002   unsigned int old_start_odd=tlb_e[Random&0x3F].start_odd;
11003   unsigned int old_end_odd=tlb_e[Random&0x3F].end_odd;
11004   for (i=old_start_even>>12; i<=old_end_even>>12; i++)
11005   {
11006     if(i<0x80000||i>0xBFFFF)
11007     {
11008       invalidate_block(i);
11009       memory_map[i]=-1;
11010     }
11011   }
11012   for (i=old_start_odd>>12; i<=old_end_odd>>12; i++)
11013   {
11014     if(i<0x80000||i>0xBFFFF)
11015     {
11016       invalidate_block(i);
11017       memory_map[i]=-1;
11018     }
11019   }
11020   cached_interpreter_table.TLBWR();
11021   /* Combine tlb_LUT_r, tlb_LUT_w, and invalid_code into a single table
11022      for fast look up. */
11023   for (i=tlb_e[Random&0x3F].start_even>>12; i<=tlb_e[Random&0x3F].end_even>>12; i++)
11024   {
11025     //DebugMessage(M64MSG_VERBOSE, "%x: r:%8x w:%8x",i,tlb_LUT_r[i],tlb_LUT_w[i]);
11026     if(i<0x80000||i>0xBFFFF)
11027     {
11028       if(tlb_LUT_r[i]) {
11029         memory_map[i]=((tlb_LUT_r[i]&0xFFFFF000)-(i<<12)+(unsigned int)rdram-0x80000000)>>2;
11030         // FIXME: should make sure the physical page is invalid too
11031         if(!tlb_LUT_w[i]||!invalid_code[i]) {
11032           memory_map[i]|=0x40000000; // Write protect
11033         }else{
11034           assert(tlb_LUT_r[i]==tlb_LUT_w[i]);
11035         }
11036         if(!using_tlb) DebugMessage(M64MSG_VERBOSE, "Enabled TLB");
11037         // Tell the dynamic recompiler to generate tlb lookup code
11038         using_tlb=1;
11039       }
11040       else memory_map[i]=-1;
11041     }
11042     //DebugMessage(M64MSG_VERBOSE, "memory_map[%x]: %8x (+%8x)",i,memory_map[i],memory_map[i]<<2);
11043   }
11044   for (i=tlb_e[Random&0x3F].start_odd>>12; i<=tlb_e[Random&0x3F].end_odd>>12; i++)
11045   {
11046     //DebugMessage(M64MSG_VERBOSE, "%x: r:%8x w:%8x",i,tlb_LUT_r[i],tlb_LUT_w[i]);
11047     if(i<0x80000||i>0xBFFFF)
11048     {
11049       if(tlb_LUT_r[i]) {
11050         memory_map[i]=((tlb_LUT_r[i]&0xFFFFF000)-(i<<12)+(unsigned int)rdram-0x80000000)>>2;
11051         // FIXME: should make sure the physical page is invalid too
11052         if(!tlb_LUT_w[i]||!invalid_code[i]) {
11053           memory_map[i]|=0x40000000; // Write protect
11054         }else{
11055           assert(tlb_LUT_r[i]==tlb_LUT_w[i]);
11056         }
11057         if(!using_tlb) DebugMessage(M64MSG_VERBOSE, "Enabled TLB");
11058         // Tell the dynamic recompiler to generate tlb lookup code
11059         using_tlb=1;
11060       }
11061       else memory_map[i]=-1;
11062     }
11063     //DebugMessage(M64MSG_VERBOSE, "memory_map[%x]: %8x (+%8x)",i,memory_map[i],memory_map[i]<<2);
11064   }
11065 }